target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32
  33 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  34 {
  35     ARMCPU *cpu = ARM_CPU(cs);
  36
  37     cpu->env.regs[15] = value;
  38 }
  39
  40 static bool arm_cpu_has_work(CPUState *cs)
  41 {
  42     return cs->interrupt_request &
  43         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
  44 }
  45
  46 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  47 {
  48     /* Reset a single ARMCPRegInfo register */
  49     ARMCPRegInfo *ri = value;
  50     ARMCPU *cpu = opaque;
  51
  52     if (ri->type & ARM_CP_SPECIAL) {
  53         return;
  54     }
  55
  56     if (ri->resetfn) {
  57         ri->resetfn(&cpu->env, ri);
  58         return;
  59     }
  60
  61     /* A zero offset is never possible as it would be regs[0]
  62      * so we use it to indicate that reset is being handled elsewhere.
  63      * This is basically only used for fields in non-core coprocessors
  64      * (like the pxa2xx ones).
  65      */
  66     if (!ri->fieldoffset) {
  67         return;
  68     }
  69
  70     if (cpreg_field_is_64bit(ri)) {
  71         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  72     } else {
  73         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  74     }
  75 }
  76
  77 /* CPUClass::reset() */
  78 static void arm_cpu_reset(CPUState *s)
  79 {
  80     ARMCPU *cpu = ARM_CPU(s);
  81     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  82     CPUARMState *env = &cpu->env;
  83
  84     acc->parent_reset(s);
  85
  86     memset(env, 0, offsetof(CPUARMState, features));
  87     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  88     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  89     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  90     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  91
  92     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  93         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  94     }
  95
  96     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  97         /* 64 bit CPUs always start in 64 bit mode */
  98         env->aarch64 = 1;
  99 #if defined(CONFIG_USER_ONLY)
 100         env->pstate = PSTATE_MODE_EL0t;
 101         /* Userspace expects access to CTL_EL0 and the cache ops */
 102         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 103 #else
 104         env->pstate = PSTATE_MODE_EL1h;
 105 #endif
 106     }
 107
 108 #if defined(CONFIG_USER_ONLY)
 109     env->uncached_cpsr = ARM_CPU_MODE_USR;
 110     /* For user mode we must enable access to coprocessors */
 111     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 112     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 113         env->cp15.c15_cpar = 3;
 114     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 115         env->cp15.c15_cpar = 1;
 116     }
 117 #else
 118     /* SVC mode with interrupts disabled.  */
 119     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 120     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 121     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 122        clear at reset.  Initial SP and PC are loaded from ROM.  */
 123     if (IS_M(env)) {
 124         uint32_t pc;
 125         uint8_t *rom;
 126         env->daif &= ~PSTATE_I;
 127         rom = rom_ptr(0);
 128         if (rom) {
 129             /* We should really use ldl_phys here, in case the guest
 130                modified flash and reset itself.  However images
 131                loaded via -kernel have not been copied yet, so load the
 132                values directly from there.  */
 133             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 134             pc = ldl_p(rom + 4);
 135             env->thumb = pc & 1;
 136             env->regs[15] = pc & ~1;
 137         }
 138     }
 139
 140     if (env->cp15.c1_sys & SCTLR_V) {
 141             env->regs[15] = 0xFFFF0000;
 142     }
 143
 144     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 145 #endif
 146     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 147     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 148     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 149     set_float_detect_tininess(float_tininess_before_rounding,
 150                               &env->vfp.fp_status);
 151     set_float_detect_tininess(float_tininess_before_rounding,
 152                               &env->vfp.standard_fp_status);
 153     tlb_flush(s, 1);
 154     /* Reset is a state change for some CPUARMState fields which we
 155      * bake assumptions about into translated code, so we need to
 156      * tb_flush().
 157      */
 158     tb_flush(env);
 159 }
 160
 161 #ifndef CONFIG_USER_ONLY
 162 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 163 {
 164     ARMCPU *cpu = opaque;
 165     CPUState *cs = CPU(cpu);
 166
 167     switch (irq) {
 168     case ARM_CPU_IRQ:
 169         if (level) {
 170             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 171         } else {
 172             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 173         }
 174         break;
 175     case ARM_CPU_FIQ:
 176         if (level) {
 177             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 178         } else {
 179             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 180         }
 181         break;
 182     default:
 183         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 184     }
 185 }
 186
 187 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 188 {
 189 #ifdef CONFIG_KVM
 190     ARMCPU *cpu = opaque;
 191     CPUState *cs = CPU(cpu);
 192     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 193
 194     switch (irq) {
 195     case ARM_CPU_IRQ:
 196         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 197         break;
 198     case ARM_CPU_FIQ:
 199         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 200         break;
 201     default:
 202         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 203     }
 204     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 205     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 206 #endif
 207 }
 208 #endif
 209
 210 static inline void set_feature(CPUARMState *env, int feature)
 211 {
 212     env->features |= 1ULL << feature;
 213 }
 214
 215 static void arm_cpu_initfn(Object *obj)
 216 {
 217     CPUState *cs = CPU(obj);
 218     ARMCPU *cpu = ARM_CPU(obj);
 219     static bool inited;
 220
 221     cs->env_ptr = &cpu->env;
 222     cpu_exec_init(&cpu->env);
 223     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 224                                          g_free, g_free);
 225
 226 #ifndef CONFIG_USER_ONLY
 227     /* Our inbound IRQ and FIQ lines */
 228     if (kvm_enabled()) {
 229         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 230     } else {
 231         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 232     }
 233
 234     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 235                                                 arm_gt_ptimer_cb, cpu);
 236     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 237                                                 arm_gt_vtimer_cb, cpu);
 238     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 239                        ARRAY_SIZE(cpu->gt_timer_outputs));
 240 #endif
 241
 242     /* DTB consumers generally don't in fact care what the 'compatible'
 243      * string is, so always provide some string and trust that a hypothetical
 244      * picky DTB consumer will also provide a helpful error message.
 245      */
 246     cpu->dtb_compatible = "qemu,unknown";
 247     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 248
 249     if (tcg_enabled() && !inited) {
 250         inited = true;
 251         arm_translate_init();
 252     }
 253 }
 254
 255 static Property arm_cpu_reset_cbar_property =
 256             DEFINE_PROP_UINT32("reset-cbar", ARMCPU, reset_cbar, 0);
 257
 258 static Property arm_cpu_reset_hivecs_property =
 259             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 260
 261 static void arm_cpu_post_init(Object *obj)
 262 {
 263     ARMCPU *cpu = ARM_CPU(obj);
 264
 265     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR)) {
 266         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 267                                  &error_abort);
 268     }
 269
 270     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 271         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 272                                  &error_abort);
 273     }
 274 }
 275
 276 static void arm_cpu_finalizefn(Object *obj)
 277 {
 278     ARMCPU *cpu = ARM_CPU(obj);
 279     g_hash_table_destroy(cpu->cp_regs);
 280 }
 281
 282 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 283 {
 284     CPUState *cs = CPU(dev);
 285     ARMCPU *cpu = ARM_CPU(dev);
 286     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 287     CPUARMState *env = &cpu->env;
 288
 289     /* Some features automatically imply others: */
 290     if (arm_feature(env, ARM_FEATURE_V8)) {
 291         set_feature(env, ARM_FEATURE_V7);
 292         set_feature(env, ARM_FEATURE_ARM_DIV);
 293         set_feature(env, ARM_FEATURE_LPAE);
 294         set_feature(env, ARM_FEATURE_V8_AES);
 295     }
 296     if (arm_feature(env, ARM_FEATURE_V7)) {
 297         set_feature(env, ARM_FEATURE_VAPA);
 298         set_feature(env, ARM_FEATURE_THUMB2);
 299         set_feature(env, ARM_FEATURE_MPIDR);
 300         if (!arm_feature(env, ARM_FEATURE_M)) {
 301             set_feature(env, ARM_FEATURE_V6K);
 302         } else {
 303             set_feature(env, ARM_FEATURE_V6);
 304         }
 305     }
 306     if (arm_feature(env, ARM_FEATURE_V6K)) {
 307         set_feature(env, ARM_FEATURE_V6);
 308         set_feature(env, ARM_FEATURE_MVFR);
 309     }
 310     if (arm_feature(env, ARM_FEATURE_V6)) {
 311         set_feature(env, ARM_FEATURE_V5);
 312         if (!arm_feature(env, ARM_FEATURE_M)) {
 313             set_feature(env, ARM_FEATURE_AUXCR);
 314         }
 315     }
 316     if (arm_feature(env, ARM_FEATURE_V5)) {
 317         set_feature(env, ARM_FEATURE_V4T);
 318     }
 319     if (arm_feature(env, ARM_FEATURE_M)) {
 320         set_feature(env, ARM_FEATURE_THUMB_DIV);
 321     }
 322     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 323         set_feature(env, ARM_FEATURE_THUMB_DIV);
 324     }
 325     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 326         set_feature(env, ARM_FEATURE_VFP3);
 327     }
 328     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 329         set_feature(env, ARM_FEATURE_VFP);
 330     }
 331     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 332         set_feature(env, ARM_FEATURE_V7MP);
 333         set_feature(env, ARM_FEATURE_PXN);
 334     }
 335
 336     if (cpu->reset_hivecs) {
 337             cpu->reset_sctlr |= (1 << 13);
 338     }
 339
 340     register_cp_regs_for_features(cpu);
 341     arm_cpu_register_gdb_regs_for_features(cpu);
 342
 343     init_cpreg_list(cpu);
 344
 345     cpu_reset(cs);
 346     qemu_init_vcpu(cs);
 347
 348     acc->parent_realize(dev, errp);
 349 }
 350
 351 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 352 {
 353     ObjectClass *oc;
 354     char *typename;
 355
 356     if (!cpu_model) {
 357         return NULL;
 358     }
 359
 360     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 361     oc = object_class_by_name(typename);
 362     g_free(typename);
 363     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 364         object_class_is_abstract(oc)) {
 365         return NULL;
 366     }
 367     return oc;
 368 }
 369
 370 /* CPU models. These are not needed for the AArch64 linux-user build. */
 371 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 372
 373 static void arm926_initfn(Object *obj)
 374 {
 375     ARMCPU *cpu = ARM_CPU(obj);
 376
 377     cpu->dtb_compatible = "arm,arm926";
 378     set_feature(&cpu->env, ARM_FEATURE_V5);
 379     set_feature(&cpu->env, ARM_FEATURE_VFP);
 380     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 381     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 382     cpu->midr = 0x41069265;
 383     cpu->reset_fpsid = 0x41011090;
 384     cpu->ctr = 0x1dd20d2;
 385     cpu->reset_sctlr = 0x00090078;
 386 }
 387
 388 static void arm946_initfn(Object *obj)
 389 {
 390     ARMCPU *cpu = ARM_CPU(obj);
 391
 392     cpu->dtb_compatible = "arm,arm946";
 393     set_feature(&cpu->env, ARM_FEATURE_V5);
 394     set_feature(&cpu->env, ARM_FEATURE_MPU);
 395     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 396     cpu->midr = 0x41059461;
 397     cpu->ctr = 0x0f004006;
 398     cpu->reset_sctlr = 0x00000078;
 399 }
 400
 401 static void arm1026_initfn(Object *obj)
 402 {
 403     ARMCPU *cpu = ARM_CPU(obj);
 404
 405     cpu->dtb_compatible = "arm,arm1026";
 406     set_feature(&cpu->env, ARM_FEATURE_V5);
 407     set_feature(&cpu->env, ARM_FEATURE_VFP);
 408     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 409     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 410     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 411     cpu->midr = 0x4106a262;
 412     cpu->reset_fpsid = 0x410110a0;
 413     cpu->ctr = 0x1dd20d2;
 414     cpu->reset_sctlr = 0x00090078;
 415     cpu->reset_auxcr = 1;
 416     {
 417         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 418         ARMCPRegInfo ifar = {
 419             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 420             .access = PL1_RW,
 421             .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
 422             .resetvalue = 0
 423         };
 424         define_one_arm_cp_reg(cpu, &ifar);
 425     }
 426 }
 427
 428 static void arm1136_r2_initfn(Object *obj)
 429 {
 430     ARMCPU *cpu = ARM_CPU(obj);
 431     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 432      * older core than plain "arm1136". In particular this does not
 433      * have the v6K features.
 434      * These ID register values are correct for 1136 but may be wrong
 435      * for 1136_r2 (in particular r0p2 does not actually implement most
 436      * of the ID registers).
 437      */
 438
 439     cpu->dtb_compatible = "arm,arm1136";
 440     set_feature(&cpu->env, ARM_FEATURE_V6);
 441     set_feature(&cpu->env, ARM_FEATURE_VFP);
 442     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 443     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 444     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 445     cpu->midr = 0x4107b362;
 446     cpu->reset_fpsid = 0x410120b4;
 447     cpu->mvfr0 = 0x11111111;
 448     cpu->mvfr1 = 0x00000000;
 449     cpu->ctr = 0x1dd20d2;
 450     cpu->reset_sctlr = 0x00050078;
 451     cpu->id_pfr0 = 0x111;
 452     cpu->id_pfr1 = 0x1;
 453     cpu->id_dfr0 = 0x2;
 454     cpu->id_afr0 = 0x3;
 455     cpu->id_mmfr0 = 0x01130003;
 456     cpu->id_mmfr1 = 0x10030302;
 457     cpu->id_mmfr2 = 0x01222110;
 458     cpu->id_isar0 = 0x00140011;
 459     cpu->id_isar1 = 0x12002111;
 460     cpu->id_isar2 = 0x11231111;
 461     cpu->id_isar3 = 0x01102131;
 462     cpu->id_isar4 = 0x141;
 463     cpu->reset_auxcr = 7;
 464 }
 465
 466 static void arm1136_initfn(Object *obj)
 467 {
 468     ARMCPU *cpu = ARM_CPU(obj);
 469
 470     cpu->dtb_compatible = "arm,arm1136";
 471     set_feature(&cpu->env, ARM_FEATURE_V6K);
 472     set_feature(&cpu->env, ARM_FEATURE_V6);
 473     set_feature(&cpu->env, ARM_FEATURE_VFP);
 474     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 475     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 476     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 477     cpu->midr = 0x4117b363;
 478     cpu->reset_fpsid = 0x410120b4;
 479     cpu->mvfr0 = 0x11111111;
 480     cpu->mvfr1 = 0x00000000;
 481     cpu->ctr = 0x1dd20d2;
 482     cpu->reset_sctlr = 0x00050078;
 483     cpu->id_pfr0 = 0x111;
 484     cpu->id_pfr1 = 0x1;
 485     cpu->id_dfr0 = 0x2;
 486     cpu->id_afr0 = 0x3;
 487     cpu->id_mmfr0 = 0x01130003;
 488     cpu->id_mmfr1 = 0x10030302;
 489     cpu->id_mmfr2 = 0x01222110;
 490     cpu->id_isar0 = 0x00140011;
 491     cpu->id_isar1 = 0x12002111;
 492     cpu->id_isar2 = 0x11231111;
 493     cpu->id_isar3 = 0x01102131;
 494     cpu->id_isar4 = 0x141;
 495     cpu->reset_auxcr = 7;
 496 }
 497
 498 static void arm1176_initfn(Object *obj)
 499 {
 500     ARMCPU *cpu = ARM_CPU(obj);
 501
 502     cpu->dtb_compatible = "arm,arm1176";
 503     set_feature(&cpu->env, ARM_FEATURE_V6K);
 504     set_feature(&cpu->env, ARM_FEATURE_VFP);
 505     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 506     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 507     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 508     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 509     cpu->midr = 0x410fb767;
 510     cpu->reset_fpsid = 0x410120b5;
 511     cpu->mvfr0 = 0x11111111;
 512     cpu->mvfr1 = 0x00000000;
 513     cpu->ctr = 0x1dd20d2;
 514     cpu->reset_sctlr = 0x00050078;
 515     cpu->id_pfr0 = 0x111;
 516     cpu->id_pfr1 = 0x11;
 517     cpu->id_dfr0 = 0x33;
 518     cpu->id_afr0 = 0;
 519     cpu->id_mmfr0 = 0x01130003;
 520     cpu->id_mmfr1 = 0x10030302;
 521     cpu->id_mmfr2 = 0x01222100;
 522     cpu->id_isar0 = 0x0140011;
 523     cpu->id_isar1 = 0x12002111;
 524     cpu->id_isar2 = 0x11231121;
 525     cpu->id_isar3 = 0x01102131;
 526     cpu->id_isar4 = 0x01141;
 527     cpu->reset_auxcr = 7;
 528 }
 529
 530 static void arm11mpcore_initfn(Object *obj)
 531 {
 532     ARMCPU *cpu = ARM_CPU(obj);
 533
 534     cpu->dtb_compatible = "arm,arm11mpcore";
 535     set_feature(&cpu->env, ARM_FEATURE_V6K);
 536     set_feature(&cpu->env, ARM_FEATURE_VFP);
 537     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 538     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 539     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 540     cpu->midr = 0x410fb022;
 541     cpu->reset_fpsid = 0x410120b4;
 542     cpu->mvfr0 = 0x11111111;
 543     cpu->mvfr1 = 0x00000000;
 544     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 545     cpu->id_pfr0 = 0x111;
 546     cpu->id_pfr1 = 0x1;
 547     cpu->id_dfr0 = 0;
 548     cpu->id_afr0 = 0x2;
 549     cpu->id_mmfr0 = 0x01100103;
 550     cpu->id_mmfr1 = 0x10020302;
 551     cpu->id_mmfr2 = 0x01222000;
 552     cpu->id_isar0 = 0x00100011;
 553     cpu->id_isar1 = 0x12002111;
 554     cpu->id_isar2 = 0x11221011;
 555     cpu->id_isar3 = 0x01102131;
 556     cpu->id_isar4 = 0x141;
 557     cpu->reset_auxcr = 1;
 558 }
 559
 560 static void cortex_m3_initfn(Object *obj)
 561 {
 562     ARMCPU *cpu = ARM_CPU(obj);
 563     set_feature(&cpu->env, ARM_FEATURE_V7);
 564     set_feature(&cpu->env, ARM_FEATURE_M);
 565     cpu->midr = 0x410fc231;
 566 }
 567
 568 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 569 {
 570 #ifndef CONFIG_USER_ONLY
 571     CPUClass *cc = CPU_CLASS(oc);
 572
 573     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 574 #endif
 575 }
 576
 577 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 578     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 579       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 580     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 581       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 582     REGINFO_SENTINEL
 583 };
 584
 585 static void cortex_a8_initfn(Object *obj)
 586 {
 587     ARMCPU *cpu = ARM_CPU(obj);
 588
 589     cpu->dtb_compatible = "arm,cortex-a8";
 590     set_feature(&cpu->env, ARM_FEATURE_V7);
 591     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 592     set_feature(&cpu->env, ARM_FEATURE_NEON);
 593     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 594     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 595     cpu->midr = 0x410fc080;
 596     cpu->reset_fpsid = 0x410330c0;
 597     cpu->mvfr0 = 0x11110222;
 598     cpu->mvfr1 = 0x00011100;
 599     cpu->ctr = 0x82048004;
 600     cpu->reset_sctlr = 0x00c50078;
 601     cpu->id_pfr0 = 0x1031;
 602     cpu->id_pfr1 = 0x11;
 603     cpu->id_dfr0 = 0x400;
 604     cpu->id_afr0 = 0;
 605     cpu->id_mmfr0 = 0x31100003;
 606     cpu->id_mmfr1 = 0x20000000;
 607     cpu->id_mmfr2 = 0x01202000;
 608     cpu->id_mmfr3 = 0x11;
 609     cpu->id_isar0 = 0x00101111;
 610     cpu->id_isar1 = 0x12112111;
 611     cpu->id_isar2 = 0x21232031;
 612     cpu->id_isar3 = 0x11112131;
 613     cpu->id_isar4 = 0x00111142;
 614     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 615     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 616     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 617     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 618     cpu->reset_auxcr = 2;
 619     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 620 }
 621
 622 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 623     /* power_control should be set to maximum latency. Again,
 624      * default to 0 and set by private hook
 625      */
 626     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 627       .access = PL1_RW, .resetvalue = 0,
 628       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 629     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 630       .access = PL1_RW, .resetvalue = 0,
 631       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 632     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 633       .access = PL1_RW, .resetvalue = 0,
 634       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 635     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 636       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 637     /* TLB lockdown control */
 638     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 639       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 640     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 641       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 642     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 643       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 644     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 645       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 646     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 647       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 648     REGINFO_SENTINEL
 649 };
 650
 651 static void cortex_a9_initfn(Object *obj)
 652 {
 653     ARMCPU *cpu = ARM_CPU(obj);
 654
 655     cpu->dtb_compatible = "arm,cortex-a9";
 656     set_feature(&cpu->env, ARM_FEATURE_V7);
 657     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 658     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 659     set_feature(&cpu->env, ARM_FEATURE_NEON);
 660     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 661     /* Note that A9 supports the MP extensions even for
 662      * A9UP and single-core A9MP (which are both different
 663      * and valid configurations; we don't model A9UP).
 664      */
 665     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 666     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 667     cpu->midr = 0x410fc090;
 668     cpu->reset_fpsid = 0x41033090;
 669     cpu->mvfr0 = 0x11110222;
 670     cpu->mvfr1 = 0x01111111;
 671     cpu->ctr = 0x80038003;
 672     cpu->reset_sctlr = 0x00c50078;
 673     cpu->id_pfr0 = 0x1031;
 674     cpu->id_pfr1 = 0x11;
 675     cpu->id_dfr0 = 0x000;
 676     cpu->id_afr0 = 0;
 677     cpu->id_mmfr0 = 0x00100103;
 678     cpu->id_mmfr1 = 0x20000000;
 679     cpu->id_mmfr2 = 0x01230000;
 680     cpu->id_mmfr3 = 0x00002111;
 681     cpu->id_isar0 = 0x00101111;
 682     cpu->id_isar1 = 0x13112111;
 683     cpu->id_isar2 = 0x21232041;
 684     cpu->id_isar3 = 0x11112131;
 685     cpu->id_isar4 = 0x00111142;
 686     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 687     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 688     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 689     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 690 }
 691
 692 #ifndef CONFIG_USER_ONLY
 693 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 694 {
 695     /* Linux wants the number of processors from here.
 696      * Might as well set the interrupt-controller bit too.
 697      */
 698     return ((smp_cpus - 1) << 24) | (1 << 23);
 699 }
 700 #endif
 701
 702 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 703 #ifndef CONFIG_USER_ONLY
 704     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 705       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 706       .writefn = arm_cp_write_ignore, },
 707 #endif
 708     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 709       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 710     REGINFO_SENTINEL
 711 };
 712
 713 static void cortex_a15_initfn(Object *obj)
 714 {
 715     ARMCPU *cpu = ARM_CPU(obj);
 716
 717     cpu->dtb_compatible = "arm,cortex-a15";
 718     set_feature(&cpu->env, ARM_FEATURE_V7);
 719     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 720     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 721     set_feature(&cpu->env, ARM_FEATURE_NEON);
 722     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 723     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 724     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 725     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 726     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 727     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 728     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 729     cpu->midr = 0x412fc0f1;
 730     cpu->reset_fpsid = 0x410430f0;
 731     cpu->mvfr0 = 0x10110222;
 732     cpu->mvfr1 = 0x11111111;
 733     cpu->ctr = 0x8444c004;
 734     cpu->reset_sctlr = 0x00c50078;
 735     cpu->id_pfr0 = 0x00001131;
 736     cpu->id_pfr1 = 0x00011011;
 737     cpu->id_dfr0 = 0x02010555;
 738     cpu->id_afr0 = 0x00000000;
 739     cpu->id_mmfr0 = 0x10201105;
 740     cpu->id_mmfr1 = 0x20000000;
 741     cpu->id_mmfr2 = 0x01240000;
 742     cpu->id_mmfr3 = 0x02102211;
 743     cpu->id_isar0 = 0x02101110;
 744     cpu->id_isar1 = 0x13112111;
 745     cpu->id_isar2 = 0x21232041;
 746     cpu->id_isar3 = 0x11112131;
 747     cpu->id_isar4 = 0x10011142;
 748     cpu->clidr = 0x0a200023;
 749     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 750     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 751     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 752     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 753 }
 754
 755 static void ti925t_initfn(Object *obj)
 756 {
 757     ARMCPU *cpu = ARM_CPU(obj);
 758     set_feature(&cpu->env, ARM_FEATURE_V4T);
 759     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 760     cpu->midr = ARM_CPUID_TI925T;
 761     cpu->ctr = 0x5109149;
 762     cpu->reset_sctlr = 0x00000070;
 763 }
 764
 765 static void sa1100_initfn(Object *obj)
 766 {
 767     ARMCPU *cpu = ARM_CPU(obj);
 768
 769     cpu->dtb_compatible = "intel,sa1100";
 770     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 771     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 772     cpu->midr = 0x4401A11B;
 773     cpu->reset_sctlr = 0x00000070;
 774 }
 775
 776 static void sa1110_initfn(Object *obj)
 777 {
 778     ARMCPU *cpu = ARM_CPU(obj);
 779     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 780     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 781     cpu->midr = 0x6901B119;
 782     cpu->reset_sctlr = 0x00000070;
 783 }
 784
 785 static void pxa250_initfn(Object *obj)
 786 {
 787     ARMCPU *cpu = ARM_CPU(obj);
 788
 789     cpu->dtb_compatible = "marvell,xscale";
 790     set_feature(&cpu->env, ARM_FEATURE_V5);
 791     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 792     cpu->midr = 0x69052100;
 793     cpu->ctr = 0xd172172;
 794     cpu->reset_sctlr = 0x00000078;
 795 }
 796
 797 static void pxa255_initfn(Object *obj)
 798 {
 799     ARMCPU *cpu = ARM_CPU(obj);
 800
 801     cpu->dtb_compatible = "marvell,xscale";
 802     set_feature(&cpu->env, ARM_FEATURE_V5);
 803     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 804     cpu->midr = 0x69052d00;
 805     cpu->ctr = 0xd172172;
 806     cpu->reset_sctlr = 0x00000078;
 807 }
 808
 809 static void pxa260_initfn(Object *obj)
 810 {
 811     ARMCPU *cpu = ARM_CPU(obj);
 812
 813     cpu->dtb_compatible = "marvell,xscale";
 814     set_feature(&cpu->env, ARM_FEATURE_V5);
 815     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 816     cpu->midr = 0x69052903;
 817     cpu->ctr = 0xd172172;
 818     cpu->reset_sctlr = 0x00000078;
 819 }
 820
 821 static void pxa261_initfn(Object *obj)
 822 {
 823     ARMCPU *cpu = ARM_CPU(obj);
 824
 825     cpu->dtb_compatible = "marvell,xscale";
 826     set_feature(&cpu->env, ARM_FEATURE_V5);
 827     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 828     cpu->midr = 0x69052d05;
 829     cpu->ctr = 0xd172172;
 830     cpu->reset_sctlr = 0x00000078;
 831 }
 832
 833 static void pxa262_initfn(Object *obj)
 834 {
 835     ARMCPU *cpu = ARM_CPU(obj);
 836
 837     cpu->dtb_compatible = "marvell,xscale";
 838     set_feature(&cpu->env, ARM_FEATURE_V5);
 839     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 840     cpu->midr = 0x69052d06;
 841     cpu->ctr = 0xd172172;
 842     cpu->reset_sctlr = 0x00000078;
 843 }
 844
 845 static void pxa270a0_initfn(Object *obj)
 846 {
 847     ARMCPU *cpu = ARM_CPU(obj);
 848
 849     cpu->dtb_compatible = "marvell,xscale";
 850     set_feature(&cpu->env, ARM_FEATURE_V5);
 851     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 852     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 853     cpu->midr = 0x69054110;
 854     cpu->ctr = 0xd172172;
 855     cpu->reset_sctlr = 0x00000078;
 856 }
 857
 858 static void pxa270a1_initfn(Object *obj)
 859 {
 860     ARMCPU *cpu = ARM_CPU(obj);
 861
 862     cpu->dtb_compatible = "marvell,xscale";
 863     set_feature(&cpu->env, ARM_FEATURE_V5);
 864     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 865     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 866     cpu->midr = 0x69054111;
 867     cpu->ctr = 0xd172172;
 868     cpu->reset_sctlr = 0x00000078;
 869 }
 870
 871 static void pxa270b0_initfn(Object *obj)
 872 {
 873     ARMCPU *cpu = ARM_CPU(obj);
 874
 875     cpu->dtb_compatible = "marvell,xscale";
 876     set_feature(&cpu->env, ARM_FEATURE_V5);
 877     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 878     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 879     cpu->midr = 0x69054112;
 880     cpu->ctr = 0xd172172;
 881     cpu->reset_sctlr = 0x00000078;
 882 }
 883
 884 static void pxa270b1_initfn(Object *obj)
 885 {
 886     ARMCPU *cpu = ARM_CPU(obj);
 887
 888     cpu->dtb_compatible = "marvell,xscale";
 889     set_feature(&cpu->env, ARM_FEATURE_V5);
 890     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 891     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 892     cpu->midr = 0x69054113;
 893     cpu->ctr = 0xd172172;
 894     cpu->reset_sctlr = 0x00000078;
 895 }
 896
 897 static void pxa270c0_initfn(Object *obj)
 898 {
 899     ARMCPU *cpu = ARM_CPU(obj);
 900
 901     cpu->dtb_compatible = "marvell,xscale";
 902     set_feature(&cpu->env, ARM_FEATURE_V5);
 903     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 904     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 905     cpu->midr = 0x69054114;
 906     cpu->ctr = 0xd172172;
 907     cpu->reset_sctlr = 0x00000078;
 908 }
 909
 910 static void pxa270c5_initfn(Object *obj)
 911 {
 912     ARMCPU *cpu = ARM_CPU(obj);
 913
 914     cpu->dtb_compatible = "marvell,xscale";
 915     set_feature(&cpu->env, ARM_FEATURE_V5);
 916     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 917     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 918     cpu->midr = 0x69054117;
 919     cpu->ctr = 0xd172172;
 920     cpu->reset_sctlr = 0x00000078;
 921 }
 922
 923 #ifdef CONFIG_USER_ONLY
 924 static void arm_any_initfn(Object *obj)
 925 {
 926     ARMCPU *cpu = ARM_CPU(obj);
 927     set_feature(&cpu->env, ARM_FEATURE_V8);
 928     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 929     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 930     set_feature(&cpu->env, ARM_FEATURE_NEON);
 931     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 932     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 933     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 934     set_feature(&cpu->env, ARM_FEATURE_CRC);
 935 #ifdef TARGET_AARCH64
 936     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 937 #endif
 938     cpu->midr = 0xffffffff;
 939 }
 940 #endif
 941
 942 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 943
 944 typedef struct ARMCPUInfo {
 945     const char *name;
 946     void (*initfn)(Object *obj);
 947     void (*class_init)(ObjectClass *oc, void *data);
 948 } ARMCPUInfo;
 949
 950 static const ARMCPUInfo arm_cpus[] = {
 951 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 952     { .name = "arm926",      .initfn = arm926_initfn },
 953     { .name = "arm946",      .initfn = arm946_initfn },
 954     { .name = "arm1026",     .initfn = arm1026_initfn },
 955     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 956      * older core than plain "arm1136". In particular this does not
 957      * have the v6K features.
 958      */
 959     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 960     { .name = "arm1136",     .initfn = arm1136_initfn },
 961     { .name = "arm1176",     .initfn = arm1176_initfn },
 962     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 963     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 964                              .class_init = arm_v7m_class_init },
 965     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 966     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 967     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 968     { .name = "ti925t",      .initfn = ti925t_initfn },
 969     { .name = "sa1100",      .initfn = sa1100_initfn },
 970     { .name = "sa1110",      .initfn = sa1110_initfn },
 971     { .name = "pxa250",      .initfn = pxa250_initfn },
 972     { .name = "pxa255",      .initfn = pxa255_initfn },
 973     { .name = "pxa260",      .initfn = pxa260_initfn },
 974     { .name = "pxa261",      .initfn = pxa261_initfn },
 975     { .name = "pxa262",      .initfn = pxa262_initfn },
 976     /* "pxa270" is an alias for "pxa270-a0" */
 977     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 978     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 979     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 980     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 981     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 982     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 983     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 984 #ifdef CONFIG_USER_ONLY
 985     { .name = "any",         .initfn = arm_any_initfn },
 986 #endif
 987 #endif
 988     { .name = NULL }
 989 };
 990
 991 static Property arm_cpu_properties[] = {
 992     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
 993     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
 994     DEFINE_PROP_END_OF_LIST()
 995 };
 996
 997 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 998 {
 999     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1000     CPUClass *cc = CPU_CLASS(acc);
1001     DeviceClass *dc = DEVICE_CLASS(oc);
1002
1003     acc->parent_realize = dc->realize;
1004     dc->realize = arm_cpu_realizefn;
1005     dc->props = arm_cpu_properties;
1006
1007     acc->parent_reset = cc->reset;
1008     cc->reset = arm_cpu_reset;
1009
1010     cc->class_by_name = arm_cpu_class_by_name;
1011     cc->has_work = arm_cpu_has_work;
1012     cc->do_interrupt = arm_cpu_do_interrupt;
1013     cc->dump_state = arm_cpu_dump_state;
1014     cc->set_pc = arm_cpu_set_pc;
1015     cc->gdb_read_register = arm_cpu_gdb_read_register;
1016     cc->gdb_write_register = arm_cpu_gdb_write_register;
1017 #ifdef CONFIG_USER_ONLY
1018     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1019 #else
1020     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1021     cc->vmsd = &vmstate_arm_cpu;
1022 #endif
1023     cc->gdb_num_core_regs = 26;
1024     cc->gdb_core_xml_file = "arm-core.xml";
1025 }
1026
1027 static void cpu_register(const ARMCPUInfo *info)
1028 {
1029     TypeInfo type_info = {
1030         .parent = TYPE_ARM_CPU,
1031         .instance_size = sizeof(ARMCPU),
1032         .instance_init = info->initfn,
1033         .class_size = sizeof(ARMCPUClass),
1034         .class_init = info->class_init,
1035     };
1036
1037     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1038     type_register(&type_info);
1039     g_free((void *)type_info.name);
1040 }
1041
1042 static const TypeInfo arm_cpu_type_info = {
1043     .name = TYPE_ARM_CPU,
1044     .parent = TYPE_CPU,
1045     .instance_size = sizeof(ARMCPU),
1046     .instance_init = arm_cpu_initfn,
1047     .instance_post_init = arm_cpu_post_init,
1048     .instance_finalize = arm_cpu_finalizefn,
1049     .abstract = true,
1050     .class_size = sizeof(ARMCPUClass),
1051     .class_init = arm_cpu_class_init,
1052 };
1053
1054 static void arm_cpu_register_types(void)
1055 {
1056     const ARMCPUInfo *info = arm_cpus;
1057
1058     type_register_static(&arm_cpu_type_info);
1059
1060     while (info->name) {
1061         cpu_register(info);
1062         info++;
1063     }
1064 }
1065
1066 type_init(arm_cpu_register_types)