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msi: Invoke msi/msix_reset from PCI core
[qemu.git] / hw / pci_bridge_dev.c
1 /*
2  * Standard PCI Bridge Device
3  *
4  * Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <[email protected]>
5  *
6  * http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, see <http://www.gnu.org/licenses/>.
20  */
21
22 #include "pci_bridge.h"
23 #include "pci_ids.h"
24 #include "msi.h"
25 #include "shpc.h"
26 #include "slotid_cap.h"
27 #include "memory.h"
28 #include "pci_internals.h"
29
30 #define REDHAT_PCI_VENDOR_ID 0x1b36
31 #define PCI_BRIDGE_DEV_VENDOR_ID REDHAT_PCI_VENDOR_ID
32 #define PCI_BRIDGE_DEV_DEVICE_ID 0x1
33
34 struct PCIBridgeDev {
35     PCIBridge bridge;
36     MemoryRegion bar;
37     uint8_t chassis_nr;
38 #define PCI_BRIDGE_DEV_F_MSI_REQ 0
39     uint32_t flags;
40 };
41 typedef struct PCIBridgeDev PCIBridgeDev;
42
43 /* Mapping mandated by PCI-to-PCI Bridge architecture specification,
44  * revision 1.2 */
45 /* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
46 static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
47 {
48     return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
49 }
50
51 static int pci_bridge_dev_initfn(PCIDevice *dev)
52 {
53     PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
54     PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
55     int err;
56     pci_bridge_map_irq(br, NULL, pci_bridge_dev_map_irq_fn);
57     err = pci_bridge_initfn(dev);
58     if (err) {
59         goto bridge_error;
60     }
61     memory_region_init(&bridge_dev->bar, "shpc-bar", shpc_bar_size(dev));
62     err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
63     if (err) {
64         goto shpc_error;
65     }
66     err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0);
67     if (err) {
68         goto slotid_error;
69     }
70     if ((bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_MSI_REQ)) &&
71         msi_supported) {
72         err = msi_init(dev, 0, 1, true, true);
73         if (err < 0) {
74             goto msi_error;
75         }
76     }
77     /* TODO: spec recommends using 64 bit prefetcheable BAR.
78      * Check whether that works well. */
79     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
80                      PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
81     dev->config[PCI_INTERRUPT_PIN] = 0x1;
82     return 0;
83 msi_error:
84     slotid_cap_cleanup(dev);
85 slotid_error:
86     shpc_cleanup(dev, &bridge_dev->bar);
87 shpc_error:
88     memory_region_destroy(&bridge_dev->bar);
89 bridge_error:
90     return err;
91 }
92
93 static int pci_bridge_dev_exitfn(PCIDevice *dev)
94 {
95     PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
96     PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
97     int ret;
98     if (msi_present(dev)) {
99         msi_uninit(dev);
100     }
101     slotid_cap_cleanup(dev);
102     shpc_cleanup(dev, &bridge_dev->bar);
103     memory_region_destroy(&bridge_dev->bar);
104     ret = pci_bridge_exitfn(dev);
105     assert(!ret);
106     return 0;
107 }
108
109 static void pci_bridge_dev_write_config(PCIDevice *d,
110                                         uint32_t address, uint32_t val, int len)
111 {
112     pci_bridge_write_config(d, address, val, len);
113     if (msi_present(d)) {
114         msi_write_config(d, address, val, len);
115     }
116     shpc_cap_write_config(d, address, val, len);
117 }
118
119 static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
120 {
121     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
122
123     pci_bridge_reset(qdev);
124     shpc_reset(dev);
125 }
126
127 static Property pci_bridge_dev_properties[] = {
128                     /* Note: 0 is not a legal chassis number. */
129     DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0),
130     DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true),
131     DEFINE_PROP_END_OF_LIST(),
132 };
133
134 static const VMStateDescription pci_bridge_dev_vmstate = {
135     .name = "pci_bridge",
136     .fields = (VMStateField[]) {
137         VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev),
138         SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev),
139         VMSTATE_END_OF_LIST()
140     }
141 };
142
143 static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
144 {
145     DeviceClass *dc = DEVICE_CLASS(klass);
146     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
147     k->init = pci_bridge_dev_initfn;
148     k->exit = pci_bridge_dev_exitfn;
149     k->config_write = pci_bridge_dev_write_config;
150     k->vendor_id = PCI_BRIDGE_DEV_VENDOR_ID;
151     k->device_id = PCI_BRIDGE_DEV_DEVICE_ID;
152     k->class_id = PCI_CLASS_BRIDGE_PCI;
153     k->is_bridge = 1,
154     dc->desc = "Standard PCI Bridge";
155     dc->reset = qdev_pci_bridge_dev_reset;
156     dc->props = pci_bridge_dev_properties;
157     dc->vmsd = &pci_bridge_dev_vmstate;
158 }
159
160 static TypeInfo pci_bridge_dev_info = {
161     .name = "pci-bridge",
162     .parent        = TYPE_PCI_DEVICE,
163     .instance_size = sizeof(PCIBridgeDev),
164     .class_init = pci_bridge_dev_class_init,
165 };
166
167 static void pci_bridge_dev_register(void)
168 {
169     type_register_static(&pci_bridge_dev_info);
170 }
171
172 type_init(pci_bridge_dev_register);
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