target-tricore/tricore-opcodes.h

   1 /*
   2  *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   3  *
   4  * This library is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU Lesser General Public
   6  * License as published by the Free Software Foundation; either
   7  * version 2 of the License, or (at your option) any later version.
   8  *
   9  * This library is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * Lesser General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU Lesser General Public
  15  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 /*
  19  * Opcode Masks for Tricore
  20  * Format MASK_OP_InstrFormatName_Field
  21  */
  22
  23 /* This creates a mask with bits start .. end set to 1 and applies it to op */
  24 #define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
  25                                         (end) - (start) + 1))
  26 #define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
  27                                              (end) - (start) + 1))
  28
  29 /* new opcode masks */
  30
  31 #define MASK_OP_MAJOR(op)      MASK_BITS_SHIFT(op, 0, 7)
  32
  33 /* 16-Bit Formats */
  34 #define MASK_OP_SB_DISP8(op)   MASK_BITS_SHIFT(op, 8, 15)
  35 #define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
  36
  37 #define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
  38 #define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
  39 #define MASK_OP_SBC_DISP4(op)  MASK_BITS_SHIFT(op, 8, 11)
  40
  41 #define MASK_OP_SBR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
  42 #define MASK_OP_SBR_DISP4(op)  MASK_BITS_SHIFT(op, 8, 11)
  43
  44 #define MASK_OP_SBRN_N(op)     MASK_BITS_SHIFT(op, 12, 15)
  45 #define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
  46
  47 #define MASK_OP_SC_CONST8(op)  MASK_BITS_SHIFT(op, 8, 15)
  48
  49 #define MASK_OP_SLR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
  50 #define MASK_OP_SLR_D(op)      MASK_BITS_SHIFT(op, 8, 11)
  51
  52 #define MASK_OP_SLRO_OFF4(op)  MASK_BITS_SHIFT(op, 12, 15)
  53 #define MASK_OP_SLRO_D(op)     MASK_BITS_SHIFT(op, 8, 11)
  54
  55 #define MASK_OP_SR_OP2(op)     MASK_BITS_SHIFT(op, 12, 15)
  56 #define MASK_OP_SR_S1D(op)     MASK_BITS_SHIFT(op, 8, 11)
  57
  58 #define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
  59 #define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
  60 #define MASK_OP_SRC_S1D(op)    MASK_BITS_SHIFT(op, 8, 11)
  61
  62 #define MASK_OP_SRO_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
  63 #define MASK_OP_SRO_OFF4(op)   MASK_BITS_SHIFT(op, 8, 11)
  64
  65 #define MASK_OP_SRR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
  66 #define MASK_OP_SRR_S1D(op)    MASK_BITS_SHIFT(op, 8, 11)
  67
  68 #define MASK_OP_SRRS_S2(op)    MASK_BITS_SHIFT(op, 12, 15)
  69 #define MASK_OP_SRRS_S1D(op)   MASK_BITS_SHIFT(op, 8, 11)
  70 #define MASK_OP_SRRS_N(op)     MASK_BITS_SHIFT(op, 6, 7)
  71
  72 #define MASK_OP_SSR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
  73 #define MASK_OP_SSR_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
  74
  75 #define MASK_OP_SSRO_OFF4(op)  MASK_BITS_SHIFT(op, 12, 15)
  76 #define MASK_OP_SSRO_S1(op)    MASK_BITS_SHIFT(op, 8, 11)
  77
  78 /* 32-Bit Formats */
  79
  80 /* ABS Format */
  81 #define MASK_OP_ABS_OFF18(op)  (MASK_BITS_SHIFT(op, 16, 21) +       \
  82                                (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
  83                                (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
  84                                (MASK_BITS_SHIFT(op, 12, 15) << 14))
  85 #define MASK_OP_ABS_OP2(op)    MASK_BITS_SHIFT(op, 26, 27)
  86 #define MASK_OP_ABS_S1D(op)    MASK_BITS_SHIFT(op, 8, 11)
  87
  88 /* ABSB Format */
  89 #define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
  90 #define MASK_OP_ABSB_OP2(op)   MASK_BITS_SHIFT(op, 26, 27)
  91 #define MASK_OP_ABSB_B(op)     MASK_BITS_SHIFT(op, 11, 11)
  92 #define MASK_OP_ABSB_BPOS(op)  MASK_BITS_SHIFT(op, 8, 10)
  93
  94 /* B Format   */
  95 #define MASK_OP_B_DISP24(op)   (MASK_BITS_SHIFT(op, 16, 31) + \
  96                                (MASK_BITS_SHIFT(op, 8, 15) << 16))
  97 #define MASK_OP_B_DISP24_SEXT(op)   (MASK_BITS_SHIFT(op, 16, 31) + \
  98                                     (MASK_BITS_SHIFT_SEXT(op, 8, 15) << 16))
  99 /* BIT Format */
 100 #define MASK_OP_BIT_D(op)      MASK_BITS_SHIFT(op, 28, 31)
 101 #define MASK_OP_BIT_POS2(op)   MASK_BITS_SHIFT(op, 23, 27)
 102 #define MASK_OP_BIT_OP2(op)    MASK_BITS_SHIFT(op, 21, 22)
 103 #define MASK_OP_BIT_POS1(op)   MASK_BITS_SHIFT(op, 16, 20)
 104 #define MASK_OP_BIT_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
 105 #define MASK_OP_BIT_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
 106
 107 /* BO Format */
 108 #define MASK_OP_BO_OFF10(op)   (MASK_BITS_SHIFT(op, 16, 21) + \
 109                                (MASK_BITS_SHIFT(op, 28, 31) << 6))
 110 #define MASK_OP_BO_OFF10_SEXT(op)   (MASK_BITS_SHIFT_SEXT(op, 16, 21) + \
 111                                     (MASK_BITS_SHIFT_SEXT(op, 28, 31) << 6))
 112 #define MASK_OP_BO_OP2(op)     MASK_BITS_SHIFT(op, 22, 27)
 113 #define MASK_OP_BO_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
 114 #define MASK_OP_BO_S1D(op)     MASK_BITS_SHIFT(op, 8, 11)
 115
 116 /* BOL Format */
 117 #define MASK_OP_BOL_OFF16(op)  ((MASK_BITS_SHIFT(op, 16, 21) +        \
 118                                (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
 119                                (MASK_BITS_SHIFT(op, 22, 27) << 10))
 120 #define MASK_OP_BOL_OFF16_SEXT(op)  ((MASK_BITS_SHIFT(op, 16, 21) +        \
 121                                     (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
 122                                     (MASK_BITS_SHIFT_SEXT(op, 22, 27) << 10))
 123 #define MASK_OP_BOL_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
 124 #define MASK_OP_BOL_S1D(op)    MASK_BITS_SHIFT(op, 8, 11)
 125
 126 /* BRC Format */
 127 #define MASK_OP_BRC_OP2(op)    MASK_BITS_SHIFT(op, 31, 31)
 128 #define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
 129 #define MASK_OP_BRC_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
 130 #define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
 131 #define MASK_OP_BRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
 132 #define MASK_OP_BRC_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
 133
 134 /* BRN Format */
 135 #define MASK_OP_BRN_OP2(op)    MASK_BITS_SHIFT(op, 31, 31)
 136 #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
 137 #define MASK_OP_BRN_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
 138 #define MASK_OP_BRN_N(op)      (MASK_BITS_SHIFT(op, 12, 15) + \
 139                                (MASK_BITS_SHIFT(op, 7, 7) << 4))
 140 #define MASK_OP_BRN_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
 141 /* BRR Format */
 142 #define MASK_OP_BRR_OP2(op)    MASK_BITS_SHIFT(op, 31, 31)
 143 #define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
 144 #define MASK_OP_BRR_DISP15_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 16, 30)
 145 #define MASK_OP_BRR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
 146 #define MASK_OP_BRR_S1(op)     MASK_BITS_SHIFT(op, 8, 11)
 147
 148 /* META MASK for similar instr Formats */
 149 #define MASK_OP_META_D(op)     MASK_BITS_SHIFT(op, 28, 31)
 150 #define MASK_OP_META_S1(op)    MASK_BITS_SHIFT(op, 8, 11)
 151
 152 /* RC Format */
 153 #define MASK_OP_RC_D(op)       MASK_OP_META_D(op)
 154 #define MASK_OP_RC_OP2(op)     MASK_BITS_SHIFT(op, 21, 27)
 155 #define MASK_OP_RC_CONST9(op)  MASK_BITS_SHIFT(op, 12, 20)
 156 #define MASK_OP_RC_CONST9_SEXT(op)  MASK_BITS_SHIFT_SEXT(op, 12, 20)
 157 #define MASK_OP_RC_S1(op)      MASK_OP_META_S1(op)
 158
 159 /* RCPW Format */
 160
 161 #define MASK_OP_RCPW_D(op)      MASK_OP_META_D(op)
 162 #define MASK_OP_RCPW_POS(op)    MASK_BITS_SHIFT(op, 23, 27)
 163 #define MASK_OP_RCPW_OP2(op)    MASK_BITS_SHIFT(op, 21, 22)
 164 #define MASK_OP_RCPW_WIDTH(op)  MASK_BITS_SHIFT(op, 16, 20)
 165 #define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
 166 #define MASK_OP_RCPW_S1(op)     MASK_OP_META_S1(op)
 167
 168 /* RCR Format */
 169
 170 #define MASK_OP_RCR_D(op)      MASK_OP_META_D(op)
 171 #define MASK_OP_RCR_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
 172 #define MASK_OP_RCR_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
 173 #define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
 174 #define MASK_OP_RCR_CONST9_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 20)
 175 #define MASK_OP_RCR_S1(op)     MASK_OP_META_S1(op)
 176
 177 /* RCRR Format */
 178
 179 #define MASK_OP_RCRR_D(op)      MASK_OP_META_D(op)
 180 #define MASK_OP_RCRR_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
 181 #define MASK_OP_RCRR_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
 182 #define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
 183 #define MASK_OP_RCRR_S1(op)     MASK_OP_META_S1(op)
 184
 185 /* RCRW Format */
 186
 187 #define MASK_OP_RCRW_D(op)      MASK_OP_META_D(op)
 188 #define MASK_OP_RCRW_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
 189 #define MASK_OP_RCRW_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
 190 #define MASK_OP_RCRW_WIDTH(op)  MASK_BITS_SHIFT(op, 16, 20)
 191 #define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
 192 #define MASK_OP_RCRW_S1(op)     MASK_OP_META_S1(op)
 193
 194 /* RLC Format */
 195
 196 #define MASK_OP_RLC_D(op)       MASK_OP_META_D(op)
 197 #define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
 198 #define MASK_OP_RLC_CONST16_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 27)
 199 #define MASK_OP_RLC_S1(op)      MASK_OP_META_S1(op)
 200
 201 /* RR  Format */
 202 #define MASK_OP_RR_D(op)        MASK_OP_META_D(op)
 203 #define MASK_OP_RR_OP2(op)      MASK_BITS_SHIFT(op, 20, 27)
 204 #define MASK_OP_RR_N(op)        MASK_BITS_SHIFT(op, 16, 17)
 205 #define MASK_OP_RR_S2(op)       MASK_BITS_SHIFT(op, 12, 15)
 206 #define MASK_OP_RR_S1(op)       MASK_OP_META_S1(op)
 207
 208 /* RR1  Format */
 209 #define MASK_OP_RR1_D(op)       MASK_OP_META_D(op)
 210 #define MASK_OP_RR1_OP2(op)     MASK_BITS_SHIFT(op, 18, 27)
 211 #define MASK_OP_RR1_N(op)       MASK_BITS_SHIFT(op, 16, 17)
 212 #define MASK_OP_RR1_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
 213 #define MASK_OP_RR1_S1(op)      MASK_OP_META_S1(op)
 214
 215 /* RR2  Format */
 216 #define MASK_OP_RR2_D(op)       MASK_OP_META_D(op)
 217 #define MASK_OP_RR2_OP2(op)     MASK_BITS_SHIFT(op, 16, 27)
 218 #define MASK_OP_RR2_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
 219 #define MASK_OP_RR2_S1(op)      MASK_OP_META_S1(op)
 220
 221 /* RRPW  Format */
 222 #define MASK_OP_RRPW_D(op)      MASK_OP_META_D(op)
 223 #define MASK_OP_RRPW_POS(op)    MASK_BITS_SHIFT(op, 23, 27)
 224 #define MASK_OP_RRPW_OP2(op)    MASK_BITS_SHIFT(op, 21, 22)
 225 #define MASK_OP_RRPW_WIDTH(op)  MASK_BITS_SHIFT(op, 16, 20)
 226 #define MASK_OP_RRPW_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
 227 #define MASK_OP_RRPW_S1(op)     MASK_OP_META_S1(op)
 228
 229 /* RRR  Format */
 230 #define MASK_OP_RRR_D(op)       MASK_OP_META_D(op)
 231 #define MASK_OP_RRR_S3(op)      MASK_BITS_SHIFT(op, 24, 27)
 232 #define MASK_OP_RRR_OP2(op)     MASK_BITS_SHIFT(op, 20, 23)
 233 #define MASK_OP_RRR_N(op)       MASK_BITS_SHIFT(op, 16, 17)
 234 #define MASK_OP_RRR_S2(op)      MASK_BITS_SHIFT(op, 12, 15)
 235 #define MASK_OP_RRR_S1(op)      MASK_OP_META_S1(op)
 236
 237 /* RRR1  Format */
 238 #define MASK_OP_RRR1_D(op)      MASK_OP_META_D(op)
 239 #define MASK_OP_RRR1_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
 240 #define MASK_OP_RRR1_OP2(op)    MASK_BITS_SHIFT(op, 18, 23)
 241 #define MASK_OP_RRR1_N(op)      MASK_BITS_SHIFT(op, 16, 17)
 242 #define MASK_OP_RRR1_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
 243 #define MASK_OP_RRR1_S1(op)     MASK_OP_META_S1(op)
 244
 245 /* RRR2  Format */
 246 #define MASK_OP_RRR2_D(op)      MASK_OP_META_D(op)
 247 #define MASK_OP_RRR2_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
 248 #define MASK_OP_RRR2_OP2(op)    MASK_BITS_SHIFT(op, 16, 23)
 249 #define MASK_OP_RRR2_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
 250 #define MASK_OP_RRR2_S1(op)     MASK_OP_META_S1(op)
 251
 252 /* RRRR  Format */
 253 #define MASK_OP_RRRR_D(op)      MASK_OP_META_D(op)
 254 #define MASK_OP_RRRR_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
 255 #define MASK_OP_RRRR_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
 256 #define MASK_OP_RRRR_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
 257 #define MASK_OP_RRRR_S1(op)     MASK_OP_META_S1(op)
 258
 259 /* RRRW  Format */
 260 #define MASK_OP_RRRW_D(op)      MASK_OP_META_D(op)
 261 #define MASK_OP_RRRW_S3(op)     MASK_BITS_SHIFT(op, 24, 27)
 262 #define MASK_OP_RRRW_OP2(op)    MASK_BITS_SHIFT(op, 21, 23)
 263 #define MASK_OP_RRRW_WIDTH(op)  MASK_BITS_SHIFT(op, 16, 20)
 264 #define MASK_OP_RRRW_S2(op)     MASK_BITS_SHIFT(op, 12, 15)
 265 #define MASK_OP_RRRW_S1(op)     MASK_OP_META_S1(op)
 266
 267 /* SYS Format */
 268 #define MASK_OP_SYS_OP2(op)     MASK_BITS_SHIFT(op, 22, 27)
 269 #define MASK_OP_SYS_S1D(op)     MASK_OP_META_S1(op)
 270
 271
 272
 273 /*
 274  * Tricore Opcodes Enums
 275  *
 276  * Format: OPC(1|2|M)_InstrLen_Name
 277  * OPC1 = only op1 field is used
 278  * OPC2 = op1 and op2 field used part of OPCM
 279  * OPCM = op1 field used to group Instr
 280  * InstrLen = 16|32
 281  * Name = Name of Instr
 282  */
 283
 284 /* 16-Bit */
 285 enum {
 286
 287     OPCM_16_SR_SYSTEM                                = 0x00,
 288     OPCM_16_SR_ACCU                                  = 0x32,
 289
 290     OPC1_16_SRC_ADD                                  = 0xc2,
 291     OPC1_16_SRC_ADD_A15                              = 0x92,
 292     OPC1_16_SRC_ADD_15A                              = 0x9a,
 293     OPC1_16_SRR_ADD                                  = 0x42,
 294     OPC1_16_SRR_ADD_A15                              = 0x12,
 295     OPC1_16_SRR_ADD_15A                              = 0x1a,
 296     OPC1_16_SRC_ADD_A                                = 0xb0,
 297     OPC1_16_SRR_ADD_A                                = 0x30,
 298     OPC1_16_SRR_ADDS                                 = 0x22,
 299     OPC1_16_SRRS_ADDSC_A                             = 0x10,
 300     OPC1_16_SC_AND                                   = 0x16,
 301     OPC1_16_SRR_AND                                  = 0x26,
 302     OPC1_16_SC_BISR                                  = 0xe0,
 303     OPC1_16_SRC_CADD                                 = 0x8a,
 304     OPC1_16_SRC_CADDN                                = 0xca,
 305     OPC1_16_SB_CALL                                  = 0x5c,
 306     OPC1_16_SRC_CMOV                                 = 0xaa,
 307     OPC1_16_SRR_CMOV                                 = 0x2a,
 308     OPC1_16_SRC_CMOVN                                = 0xea,
 309     OPC1_16_SRR_CMOVN                                = 0x6a,
 310     OPC1_16_SRC_EQ                                   = 0xba,
 311     OPC1_16_SRR_EQ                                   = 0x3a,
 312     OPC1_16_SB_J                                     = 0x3c,
 313     OPC1_16_SBC_JEQ                                  = 0x1e,
 314     OPC1_16_SBR_JEQ                                  = 0x3e,
 315     OPC1_16_SBR_JGEZ                                 = 0xce,
 316     OPC1_16_SBR_JGTZ                                 = 0x4e,
 317     OPC1_16_SR_JI                                    = 0xdc,
 318     OPC1_16_SBR_JLEZ                                 = 0x8e,
 319     OPC1_16_SBR_JLTZ                                 = 0x0e,
 320     OPC1_16_SBC_JNE                                  = 0x5e,
 321     OPC1_16_SBR_JNE                                  = 0x7e,
 322     OPC1_16_SB_JNZ                                   = 0xee,
 323     OPC1_16_SBR_JNZ                                  = 0xf6,
 324     OPC1_16_SBR_JNZ_A                                = 0x7c,
 325     OPC1_16_SBRN_JNZ_T                               = 0xae,
 326     OPC1_16_SB_JZ                                    = 0x6e,
 327     OPC1_16_SBR_JZ                                   = 0x76,
 328     OPC1_16_SBR_JZ_A                                 = 0xbc,
 329     OPC1_16_SBRN_JZ_T                                = 0x2e,
 330     OPC1_16_SC_LD_A                                  = 0xd8,
 331     OPC1_16_SLR_LD_A                                 = 0xd4,
 332     OPC1_16_SLR_LD_A_POSTINC                         = 0xc4,
 333     OPC1_16_SLRO_LD_A                                = 0xc8,
 334     OPC1_16_SRO_LD_A                                 = 0xcc,
 335     OPC1_16_SLR_LD_BU                                = 0x14,
 336     OPC1_16_SLR_LD_BU_POSTINC                        = 0x04,
 337     OPC1_16_SLRO_LD_BU                               = 0x08,
 338     OPC1_16_SRO_LD_BU                                = 0x0c,
 339     OPC1_16_SLR_LD_H                                 = 0x94,
 340     OPC1_16_SLR_LD_H_POSTINC                         = 0x84,
 341     OPC1_16_SLRO_LD_H                                = 0x88,
 342     OPC1_16_SRO_LD_H                                 = 0x8c,
 343     OPC1_16_SC_LD_W                                  = 0x58,
 344     OPC1_16_SLR_LD_W                                 = 0x54,
 345     OPC1_16_SLR_LD_W_POSTINC                         = 0x44,
 346     OPC1_16_SLRO_LD_W                                = 0x48,
 347     OPC1_16_SRO_LD_W                                 = 0x4c,
 348     OPC1_16_SBR_LOOP                                 = 0xfc,
 349     OPC1_16_SRC_LT                                   = 0xfa,
 350     OPC1_16_SRR_LT                                   = 0x7a,
 351     OPC1_16_SC_MOV                                   = 0xda,
 352     OPC1_16_SRC_MOV                                  = 0x82,
 353     OPC1_16_SRR_MOV                                  = 0x02,
 354     OPC1_16_SRC_MOV_E                                = 0xd2,/* 1.6 only */
 355     OPC1_16_SRC_MOV_A                                = 0xa0,
 356     OPC1_16_SRR_MOV_A                                = 0x60,
 357     OPC1_16_SRR_MOV_AA                               = 0x40,
 358     OPC1_16_SRR_MOV_D                                = 0x80,
 359     OPC1_16_SRR_MUL                                  = 0xe2,
 360     OPC1_16_SR_NOT                                   = 0x46,
 361     OPC1_16_SC_OR                                    = 0x96,
 362     OPC1_16_SRR_OR                                   = 0xa6,
 363     OPC1_16_SRC_SH                                   = 0x06,
 364     OPC1_16_SRC_SHA                                  = 0x86,
 365     OPC1_16_SC_ST_A                                  = 0xf8,
 366     OPC1_16_SRO_ST_A                                 = 0xec,
 367     OPC1_16_SSR_ST_A                                 = 0xf4,
 368     OPC1_16_SSR_ST_A_POSTINC                         = 0xe4,
 369     OPC1_16_SSRO_ST_A                                = 0xe8,
 370     OPC1_16_SRO_ST_B                                 = 0x2c,
 371     OPC1_16_SSR_ST_B                                 = 0x34,
 372     OPC1_16_SSR_ST_B_POSTINC                         = 0x24,
 373     OPC1_16_SSRO_ST_B                                = 0x28,
 374     OPC1_16_SRO_ST_H                                 = 0xac,
 375     OPC1_16_SSR_ST_H                                 = 0xb4,
 376     OPC1_16_SSR_ST_H_POSTINC                         = 0xa4,
 377     OPC1_16_SSRO_ST_H                                = 0xa8,
 378     OPC1_16_SC_ST_W                                  = 0x78,
 379     OPC1_16_SRO_ST_W                                 = 0x6c,
 380     OPC1_16_SSR_ST_W                                 = 0x74,
 381     OPC1_16_SSR_ST_W_POSTINC                         = 0x64,
 382     OPC1_16_SSRO_ST_W                                = 0x68,
 383     OPC1_16_SRR_SUB                                  = 0xa2,
 384     OPC1_16_SRR_SUB_A15B                             = 0x52,
 385     OPC1_16_SRR_SUB_15AB                             = 0x5a,
 386     OPC1_16_SC_SUB_A                                 = 0x20,
 387     OPC1_16_SRR_SUBS                                 = 0x62,
 388     OPC1_16_SRR_XOR                                  = 0xc6,
 389
 390 };
 391
 392 /*
 393  * SR Format
 394  */
 395 /* OPCM_16_SR_SYSTEM                                 */
 396 enum {
 397
 398     OPC2_16_SR_NOP                                   = 0x00,
 399     OPC2_16_SR_RET                                   = 0x09,
 400     OPC2_16_SR_RFE                                   = 0x08,
 401     OPC2_16_SR_DEBUG                                 = 0x0a,
 402 };
 403 /* OPCM_16_SR_ACCU                                   */
 404 enum {
 405     OPC2_16_SR_RSUB                                  = 0x05,
 406     OPC2_16_SR_SAT_B                                 = 0x00,
 407     OPC2_16_SR_SAT_BU                                = 0x01,
 408     OPC2_16_SR_SAT_H                                 = 0x02,
 409     OPC2_16_SR_SAT_HU                                = 0x03,
 410
 411 };
 412
 413 /* 32-Bit */
 414
 415 enum {
 416 /* ABS Format 1, M */
 417     OPCM_32_ABS_LDW                                  = 0x85,
 418     OPCM_32_ABS_LDB                                  = 0x05,
 419     OPCM_32_ABS_LDMST_SWAP                           = 0xe5,
 420     OPCM_32_ABS_LDST_CONTEXT                         = 0x15,
 421     OPCM_32_ABS_STORE                                = 0xa5,
 422     OPCM_32_ABS_STOREB_H                             = 0x25,
 423     OPC1_32_ABS_STOREQ                               = 0x65,
 424     OPC1_32_ABS_LD_Q                                 = 0x45,
 425     OPC1_32_ABS_LEA                                  = 0xc5,
 426 /* ABSB Format */
 427     OPC1_32_ABSB_ST_T                                = 0xd5,
 428 /* B Format */
 429     OPC1_32_B_CALL                                   = 0x6d,
 430     OPC1_32_B_CALLA                                  = 0xed,
 431     OPC1_32_B_J                                      = 0x1d,
 432     OPC1_32_B_JA                                     = 0x9d,
 433     OPC1_32_B_JL                                     = 0x5d,
 434     OPC1_32_B_JLA                                    = 0xdd,
 435 /* Bit Format */
 436     OPCM_32_BIT_ANDACC                               = 0x47,
 437     OPCM_32_BIT_LOGICAL_T1                           = 0x87,
 438     OPCM_32_BIT_INSERT                               = 0x67,
 439     OPCM_32_BIT_LOGICAL_T2                           = 0x07,
 440     OPCM_32_BIT_ORAND                                = 0xc7,
 441     OPCM_32_BIT_SH_LOGIC1                            = 0x27,
 442     OPCM_32_BIT_SH_LOGIC2                            = 0xa7,
 443 /* BO Format */
 444     OPCM_32_BO_ADDRMODE_POST_PRE_BASE                = 0x89,
 445     OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR          = 0xa9,
 446     OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE             = 0x09,
 447     OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR       = 0x29,
 448     OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE          = 0x49,
 449     OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR    = 0x69,
 450 /* BOL Format */
 451     OPC1_32_BOL_LD_A_LONGOFF                         = 0x99,
 452     OPC1_32_BOL_LD_W_LONGOFF                         = 0x19,
 453     OPC1_32_BOL_LEA_LONGOFF                          = 0xd9,
 454     OPC1_32_BOL_ST_W_LONGOFF                         = 0x59,
 455     OPC1_32_BOL_ST_A_LONGOFF                         = 0xb5, /* 1.6 only */
 456     OPC1_32_BOL_LD_B_LONGOFF                         = 0x79, /* 1.6 only */
 457     OPC1_32_BOL_LD_BU_LONGOFF                        = 0x39, /* 1.6 only */
 458     OPC1_32_BOL_LD_H_LONGOFF                         = 0xc9, /* 1.6 only */
 459     OPC1_32_BOL_LD_HU_LONGOFF                        = 0xb9, /* 1.6 only */
 460     OPC1_32_BOL_ST_B_LONGOFF                         = 0xe9, /* 1.6 only */
 461     OPC1_32_BOL_ST_H_LONGOFF                         = 0xf9, /* 1.6 only */
 462 /* BRC Format */
 463     OPCM_32_BRC_EQ_NEQ                               = 0xdf,
 464     OPCM_32_BRC_GE                                   = 0xff,
 465     OPCM_32_BRC_JLT                                  = 0xbf,
 466     OPCM_32_BRC_JNE                                  = 0x9f,
 467 /* BRN Format */
 468     OPCM_32_BRN_JTT                                  = 0x6f,
 469 /* BRR Format */
 470     OPCM_32_BRR_EQ_NEQ                               = 0x5f,
 471     OPCM_32_BRR_ADDR_EQ_NEQ                          = 0x7d,
 472     OPCM_32_BRR_GE                                   = 0x7f,
 473     OPCM_32_BRR_JLT                                  = 0x3f,
 474     OPCM_32_BRR_JNE                                  = 0x1f,
 475     OPCM_32_BRR_JNZ                                  = 0xbd,
 476     OPCM_32_BRR_LOOP                                 = 0xfd,
 477 /* RC Format */
 478     OPCM_32_RC_LOGICAL_SHIFT                         = 0x8f,
 479     OPCM_32_RC_ACCUMULATOR                           = 0x8b,
 480     OPCM_32_RC_SERVICEROUTINE                        = 0xad,
 481     OPCM_32_RC_MUL                                   = 0x53,
 482 /* RCPW Format */
 483     OPCM_32_RCPW_MASK_INSERT                         = 0xb7,
 484 /* RCR Format */
 485     OPCM_32_RCR_COND_SELECT                          = 0xab,
 486     OPCM_32_RCR_MADD                                 = 0x13,
 487     OPCM_32_RCR_MSUB                                 = 0x33,
 488 /* RCRR Format */
 489     OPC1_32_RCRR_INSERT                              = 0x97,
 490 /* RCRW Format */
 491     OPCM_32_RCRW_MASK_INSERT                         = 0xd7,
 492 /* RLC Format */
 493     OPC1_32_RLC_ADDI                                 = 0x1b,
 494     OPC1_32_RLC_ADDIH                                = 0x9b,
 495     OPC1_32_RLC_ADDIH_A                              = 0x11,
 496     OPC1_32_RLC_MFCR                                 = 0x4d,
 497     OPC1_32_RLC_MOV                                  = 0x3b,
 498     OPC1_32_RLC_MOV_64                               = 0xfb, /* 1.6 only */
 499     OPC1_32_RLC_MOV_U                                = 0xbb,
 500     OPC1_32_RLC_MOV_H                                = 0x7b,
 501     OPC1_32_RLC_MOVH_A                               = 0x91,
 502     OPC1_32_RLC_MTCR                                 = 0xcd,
 503 /* RR Format */
 504     OPCM_32_RR_LOGICAL_SHIFT                         = 0x0f,
 505     OPCM_32_RR_ACCUMULATOR                           = 0x0b,
 506     OPCM_32_RR_ADRESS                                = 0x01,
 507     OPCM_32_RR_DIVIDE                                = 0x4b,
 508     OPCM_32_RR_IDIRECT                               = 0x2d,
 509 /* RR1 Format */
 510     OPCM_32_RR1_MUL                                  = 0xb3,
 511     OPCM_32_RR1_MULQ                                 = 0x93,
 512 /* RR2 Format */
 513     OPCM_32_RR2_MUL                                  = 0x73,
 514 /* RRPW Format */
 515     OPCM_32_RRPW_EXTRACT_INSERT                      = 0x37,
 516     OPC1_32_RRPW_DEXTR                               = 0x77,
 517 /* RRR Format */
 518     OPCM_32_RRR_COND_SELECT                          = 0x2b,
 519     OPCM_32_RRR_FLOAT                                = 0x6b,
 520 /* RRR1 Format */
 521     OPCM_32_RRR1_MADD                                = 0x83,
 522     OPCM_32_RRR1_MADDQ_H                             = 0x43,
 523     OPCM_32_RRR1_MADDSU_H                            = 0xc3,
 524     OPCM_32_RRR1_MSUB_H                              = 0xa3,
 525     OPCM_32_RRR1_MSUB_Q                              = 0x63,
 526     OPCM_32_RRR1_MSUBADS_H                           = 0xe3,
 527 /* RRR2 Format */
 528     OPCM_32_RRR2_MADD                                = 0x03,
 529     OPCM_32_RRR2_MSUB                                = 0x23,
 530 /* RRRR Format */
 531     OPCM_32_RRRR_EXTRACT_INSERT                      = 0x17,
 532 /* RRRW Format */
 533     OPCM_32_RRRW_EXTRACT_INSERT                      = 0x57,
 534 /* SYS Format */
 535     OPCM_32_SYS_INTERRUPTS                           = 0x0d,
 536     OPC1_32_SYS_RSTV                                 = 0x2f,
 537 };
 538
 539
 540
 541 /*
 542  * ABS Format
 543  */
 544
 545 /* OPCM_32_ABS_LDW  */
 546 enum {
 547
 548     OPC2_32_ABS_LD_A                             = 0x02,
 549     OPC2_32_ABS_LD_D                             = 0x01,
 550     OPC2_32_ABS_LD_DA                            = 0x03,
 551     OPC2_32_ABS_LD_W                             = 0x00,
 552 };
 553
 554 /* OPCM_32_ABS_LDB */
 555 enum {
 556     OPC2_32_ABS_LD_B                             = 0x00,
 557     OPC2_32_ABS_LD_BU                            = 0x01,
 558     OPC2_32_ABS_LD_H                             = 0x02,
 559     OPC2_32_ABS_LD_HU                            = 0x03,
 560 };
 561 /* OPCM_32_ABS_LDMST_SWAP       */
 562 enum {
 563     OPC2_32_ABS_LDMST                            = 0x01,
 564     OPC2_32_ABS_SWAP_W                           = 0x00,
 565 };
 566 /* OPCM_32_ABS_LDST_CONTEXT     */
 567 enum {
 568     OPC2_32_ABS_LDLCX                            = 0x02,
 569     OPC2_32_ABS_LDUCX                            = 0x03,
 570     OPC2_32_ABS_STLCX                            = 0x00,
 571     OPC2_32_ABS_STUCX                            = 0x01,
 572 };
 573 /* OPCM_32_ABS_STORE            */
 574 enum {
 575     OPC2_32_ABS_ST_A                             = 0x02,
 576     OPC2_32_ABS_ST_D                             = 0x01,
 577     OPC2_32_ABS_ST_DA                            = 0x03,
 578     OPC2_32_ABS_ST_W                             = 0x00,
 579 };
 580 /* OPCM_32_ABS_STOREB_H */
 581 enum {
 582     OPC2_32_ABS_ST_B                             = 0x00,
 583     OPC2_32_ABS_ST_H                             = 0x02,
 584 };
 585 /*
 586  * Bit Format
 587  */
 588 /* OPCM_32_BIT_ANDACC              */
 589 enum {
 590     OPC2_32_BIT_AND_AND_T                        = 0x00,
 591     OPC2_32_BIT_AND_ANDN_T                       = 0x03,
 592     OPC2_32_BIT_AND_NOR_T                        = 0x02,
 593     OPC2_32_BIT_AND_OR_T                         = 0x01,
 594 };
 595 /* OPCM_32_BIT_LOGICAL_T                       */
 596 enum {
 597     OPC2_32_BIT_AND_T                            = 0x00,
 598     OPC2_32_BIT_ANDN_T                           = 0x03,
 599     OPC2_32_BIT_NOR_T                            = 0x02,
 600     OPC2_32_BIT_OR_T                             = 0x01,
 601 };
 602 /* OPCM_32_BIT_INSERT                   */
 603 enum {
 604     OPC2_32_BIT_INS_T                            = 0x00,
 605     OPC2_32_BIT_INSN_T                           = 0x01,
 606 };
 607 /* OPCM_32_BIT_LOGICAL_T2              */
 608 enum {
 609     OPC2_32_BIT_NAND_T                           = 0x00,
 610     OPC2_32_BIT_ORN_T                            = 0x01,
 611     OPC2_32_BIT_XNOR_T                           = 0x02,
 612     OPC2_32_BIT_XOR_T                            = 0x03,
 613 };
 614 /* OPCM_32_BIT_ORAND                    */
 615 enum {
 616     OPC2_32_BIT_OR_AND_T                         = 0x00,
 617     OPC2_32_BIT_OR_ANDN_T                        = 0x03,
 618     OPC2_32_BIT_OR_NOR_T                         = 0x02,
 619     OPC2_32_BIT_OR_OR_T                          = 0x01,
 620 };
 621 /*OPCM_32_BIT_SH_LOGIC1                 */
 622 enum {
 623     OPC2_32_BIT_SH_AND_T                         = 0x00,
 624     OPC2_32_BIT_SH_ANDN_T                        = 0x03,
 625     OPC2_32_BIT_SH_NOR_T                         = 0x02,
 626     OPC2_32_BIT_SH_OR_T                          = 0x01,
 627 };
 628 /* OPCM_32_BIT_SH_LOGIC2              */
 629 enum {
 630     OPC2_32_BIT_SH_NAND_T                        = 0x00,
 631     OPC2_32_BIT_SH_ORN_T                         = 0x01,
 632     OPC2_32_BIT_SH_XNOR_T                        = 0x02,
 633     OPC2_32_BIT_SH_XOR_T                         = 0x03,
 634 };
 635 /*
 636  * BO Format
 637  */
 638 /* OPCM_32_BO_ADDRMODE_POST_PRE_BASE     */
 639 enum {
 640     OPC2_32_BO_CACHEA_I_SHORTOFF                 = 0x2e,
 641     OPC2_32_BO_CACHEA_I_POSTINC                  = 0x0e,
 642     OPC2_32_BO_CACHEA_I_PREINC                   = 0x1e,
 643     OPC2_32_BO_CACHEA_W_SHORTOFF                 = 0x2c,
 644     OPC2_32_BO_CACHEA_W_POSTINC                  = 0x0c,
 645     OPC2_32_BO_CACHEA_W_PREINC                   = 0x1c,
 646     OPC2_32_BO_CACHEA_WI_SHORTOFF                = 0x2d,
 647     OPC2_32_BO_CACHEA_WI_POSTINC                 = 0x0d,
 648     OPC2_32_BO_CACHEA_WI_PREINC                  = 0x1d,
 649     /* 1.3.1 only */
 650     OPC2_32_BO_CACHEI_W_SHORTOFF                 = 0x2b,
 651     OPC2_32_BO_CACHEI_W_POSTINC                  = 0x0b,
 652     OPC2_32_BO_CACHEI_W_PREINC                   = 0x1b,
 653     OPC2_32_BO_CACHEI_WI_SHORTOFF                = 0x2f,
 654     OPC2_32_BO_CACHEI_WI_POSTINC                 = 0x0f,
 655     OPC2_32_BO_CACHEI_WI_PREINC                  = 0x1f,
 656     /* end 1.3.1 only */
 657     OPC2_32_BO_ST_A_SHORTOFF                     = 0x26,
 658     OPC2_32_BO_ST_A_POSTINC                      = 0x06,
 659     OPC2_32_BO_ST_A_PREINC                       = 0x16,
 660     OPC2_32_BO_ST_B_SHORTOFF                     = 0x20,
 661     OPC2_32_BO_ST_B_POSTINC                      = 0x00,
 662     OPC2_32_BO_ST_B_PREINC                       = 0x10,
 663     OPC2_32_BO_ST_D_SHORTOFF                     = 0x25,
 664     OPC2_32_BO_ST_D_POSTINC                      = 0x05,
 665     OPC2_32_BO_ST_D_PREINC                       = 0x15,
 666     OPC2_32_BO_ST_DA_SHORTOFF                    = 0x27,
 667     OPC2_32_BO_ST_DA_POSTINC                     = 0x07,
 668     OPC2_32_BO_ST_DA_PREINC                      = 0x17,
 669     OPC2_32_BO_ST_H_SHORTOFF                     = 0x22,
 670     OPC2_32_BO_ST_H_POSTINC                      = 0x02,
 671     OPC2_32_BO_ST_H_PREINC                       = 0x12,
 672     OPC2_32_BO_ST_Q_SHORTOFF                     = 0x28,
 673     OPC2_32_BO_ST_Q_POSTINC                      = 0x08,
 674     OPC2_32_BO_ST_Q_PREINC                       = 0x18,
 675     OPC2_32_BO_ST_W_SHORTOFF                     = 0x24,
 676     OPC2_32_BO_ST_W_POSTINC                      = 0x04,
 677     OPC2_32_BO_ST_W_PREINC                       = 0x14,
 678 };
 679 /* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR   */
 680 enum {
 681     OPC2_32_BO_CACHEA_I_BR                       = 0x0e,
 682     OPC2_32_BO_CACHEA_I_CIRC                     = 0x1e,
 683     OPC2_32_BO_CACHEA_W_BR                       = 0x0c,
 684     OPC2_32_BO_CACHEA_W_CIRC                     = 0x1c,
 685     OPC2_32_BO_CACHEA_WI_BR                      = 0x0d,
 686     OPC2_32_BO_CACHEA_WI_CIRC                    = 0x1d,
 687     OPC2_32_BO_ST_A_BR                           = 0x06,
 688     OPC2_32_BO_ST_A_CIRC                         = 0x16,
 689     OPC2_32_BO_ST_B_BR                           = 0x00,
 690     OPC2_32_BO_ST_B_CIRC                         = 0x10,
 691     OPC2_32_BO_ST_D_BR                           = 0x05,
 692     OPC2_32_BO_ST_D_CIRC                         = 0x15,
 693     OPC2_32_BO_ST_DA_BR                          = 0x07,
 694     OPC2_32_BO_ST_DA_CIRC                        = 0x17,
 695     OPC2_32_BO_ST_H_BR                           = 0x02,
 696     OPC2_32_BO_ST_H_CIRC                         = 0x12,
 697     OPC2_32_BO_ST_Q_BR                           = 0x08,
 698     OPC2_32_BO_ST_Q_CIRC                         = 0x18,
 699     OPC2_32_BO_ST_W_BR                           = 0x04,
 700     OPC2_32_BO_ST_W_CIRC                         = 0x14,
 701 };
 702 /*    OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE   */
 703 enum {
 704     OPC2_32_BO_LD_A_SHORTOFF                     = 0x26,
 705     OPC2_32_BO_LD_A_POSTINC                      = 0x06,
 706     OPC2_32_BO_LD_A_PREINC                       = 0x16,
 707     OPC2_32_BO_LD_B_SHORTOFF                     = 0x20,
 708     OPC2_32_BO_LD_B_POSTINC                      = 0x00,
 709     OPC2_32_BO_LD_B_PREINC                       = 0x10,
 710     OPC2_32_BO_LD_BU_SHORTOFF                    = 0x21,
 711     OPC2_32_BO_LD_BU_POSTINC                     = 0x01,
 712     OPC2_32_BO_LD_BU_PREINC                      = 0x11,
 713     OPC2_32_BO_LD_D_SHORTOFF                     = 0x25,
 714     OPC2_32_BO_LD_D_POSTINC                      = 0x05,
 715     OPC2_32_BO_LD_D_PREINC                       = 0x15,
 716     OPC2_32_BO_LD_DA_SHORTOFF                    = 0x27,
 717     OPC2_32_BO_LD_DA_POSTINC                     = 0x07,
 718     OPC2_32_BO_LD_DA_PREINC                      = 0x17,
 719     OPC2_32_BO_LD_H_SHORTOFF                     = 0x22,
 720     OPC2_32_BO_LD_H_POSTINC                      = 0x02,
 721     OPC2_32_BO_LD_H_PREINC                       = 0x12,
 722     OPC2_32_BO_LD_HU_SHORTOFF                    = 0x23,
 723     OPC2_32_BO_LD_HU_POSTINC                     = 0x03,
 724     OPC2_32_BO_LD_HU_PREINC                      = 0x13,
 725     OPC2_32_BO_LD_Q_SHORTOFF                     = 0x28,
 726     OPC2_32_BO_LD_Q_POSTINC                      = 0x08,
 727     OPC2_32_BO_LD_Q_PREINC                       = 0x18,
 728     OPC2_32_BO_LD_W_SHORTOFF                     = 0x24,
 729     OPC2_32_BO_LD_W_POSTINC                      = 0x04,
 730     OPC2_32_BO_LD_W_PREINC                       = 0x14,
 731 };
 732 /* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR  */
 733 enum {
 734     OPC2_32_BO_LD_A_BR                           = 0x06,
 735     OPC2_32_BO_LD_A_CIRC                         = 0x16,
 736     OPC2_32_BO_LD_B_BR                           = 0x00,
 737     OPC2_32_BO_LD_B_CIRC                         = 0x10,
 738     OPC2_32_BO_LD_BU_BR                          = 0x01,
 739     OPC2_32_BO_LD_BU_CIRC                        = 0x11,
 740     OPC2_32_BO_LD_D_BR                           = 0x05,
 741     OPC2_32_BO_LD_D_CIRC                         = 0x15,
 742     OPC2_32_BO_LD_DA_BR                          = 0x07,
 743     OPC2_32_BO_LD_DA_CIRC                        = 0x17,
 744     OPC2_32_BO_LD_H_BR                           = 0x02,
 745     OPC2_32_BO_LD_H_CIRC                         = 0x12,
 746     OPC2_32_BO_LD_HU_BR                          = 0x03,
 747     OPC2_32_BO_LD_HU_CIRC                        = 0x13,
 748     OPC2_32_BO_LD_Q_BR                           = 0x08,
 749     OPC2_32_BO_LD_Q_CIRC                         = 0x18,
 750     OPC2_32_BO_LD_W_BR                           = 0x04,
 751     OPC2_32_BO_LD_W_CIRC                         = 0x14,
 752 };
 753 /* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE    */
 754 enum {
 755     OPC2_32_BO_LDLCX_SHORTOFF                    = 0x24,
 756     OPC2_32_BO_LDMST_SHORTOFF                    = 0x21,
 757     OPC2_32_BO_LDMST_POSTINC                     = 0x01,
 758     OPC2_32_BO_LDMST_PREINC                      = 0x11,
 759     OPC2_32_BO_LDUCX_SHORTOFF                    = 0x25,
 760     OPC2_32_BO_LEA_SHORTOFF                      = 0x28,
 761     OPC2_32_BO_STLCX_SHORTOFF                    = 0x26,
 762     OPC2_32_BO_STUCX_SHORTOFF                    = 0x27,
 763     OPC2_32_BO_SWAP_W_SHORTOFF                   = 0x20,
 764     OPC2_32_BO_SWAP_W_POSTINC                    = 0x00,
 765     OPC2_32_BO_SWAP_W_PREINC                     = 0x10,
 766 };
 767 /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR  */
 768 enum {
 769     OPC2_32_BO_LDMST_BR                          = 0x01,
 770     OPC2_32_BO_LDMST_CIRC                        = 0x11,
 771     OPC2_32_BO_SWAP_W_BR                         = 0x00,
 772     OPC2_32_BO_SWAP_W_CIRC                       = 0x10,
 773 };
 774 /*
 775  * BRC Format
 776  */
 777 /*OPCM_32_BRC_EQ_NEQ                             */
 778 enum {
 779     OPC2_32_BRC_JEQ                              = 0x00,
 780     OPC2_32_BRC_JNE                              = 0x01,
 781 };
 782 /* OPCM_32_BRC_GE                                   */
 783 enum {
 784     OP2_32_BRC_JGE                               = 0x00,
 785     OPC_32_BRC_JGE_U                             = 0x01,
 786 };
 787 /* OPCM_32_BRC_JLT                                  */
 788 enum {
 789     OPC2_32_BRC_JLT                              = 0x00,
 790     OPC2_32_BRC_JLT_U                            = 0x01,
 791 };
 792 /* OPCM_32_BRC_JNE                                  */
 793 enum {
 794     OPC2_32_BRC_JNED                             = 0x01,
 795     OPC2_32_BRC_JNEI                             = 0x00,
 796 };
 797 /*
 798  * BRN Format
 799  */
 800 /* OPCM_32_BRN_JTT                                  */
 801 enum {
 802     OPC2_32_BRN_JNZ_T                            = 0x01,
 803     OPC2_32_BRN_JZ_T                             = 0x00,
 804 };
 805 /*
 806  * BRR Format
 807  */
 808 /* OPCM_32_BRR_EQ_NEQ                               */
 809 enum {
 810     OPC2_32_BRR_JEQ                              = 0x00,
 811     OPC2_32_BRR_JNE                              = 0x01,
 812 };
 813 /* OPCM_32_BRR_ADDR_EQ_NEQ                        */
 814 enum {
 815     OPC2_32_BRR_JEQ_A                            = 0x00,
 816     OPC2_32_BRR_JNE_A                            = 0x01,
 817 };
 818 /*OPCM_32_BRR_GE                                   */
 819 enum {
 820     OPC2_32_BRR_JGE                              = 0x00,
 821     OPC2_32_BRR_JGE_U                            = 0x01,
 822 };
 823 /* OPCM_32_BRR_JLT                                  */
 824 enum {
 825     OPC2_32_BRR_JLT                              = 0x00,
 826     OPC2_32_BRR_JLT_U                            = 0x01,
 827 };
 828 /* OPCM_32_BRR_JNE                                  */
 829 enum {
 830     OPC2_32_BRR_JNED                             = 0x01,
 831     OPC2_32_BRR_JNEI                             = 0x00,
 832 };
 833 /* OPCM_32_BRR_JNZ                                  */
 834 enum {
 835     OPC2_32_BRR_JNZ_A                            = 0x01,
 836     OPC2_32_BRR_JZ_A                             = 0x00,
 837 };
 838 /* OPCM_32_BRR_LOOP                                 */
 839 enum {
 840     OPC2_32_BRR_LOOP                             = 0x00,
 841     OPC2_32_BRR_LOOPU                            = 0x01,
 842 };
 843 /*
 844  * RC Format
 845  */
 846 /* OPCM_32_RC_LOGICAL_SHIFT                         */
 847 enum {
 848     OPC2_32_RC_AND                               = 0x08,
 849     OPC2_32_RC_ANDN                              = 0x0e,
 850     OPC2_32_RC_NAND                              = 0x09,
 851     OPC2_32_RC_NOR                               = 0x0b,
 852     OPC2_32_RC_OR                                = 0x0a,
 853     OPC2_32_RC_ORN                               = 0x0f,
 854     OPC2_32_RC_SH                                = 0x00,
 855     OPC2_32_RC_SH_H                              = 0x40,
 856     OPC2_32_RC_SHA                               = 0x01,
 857     OPC2_32_RC_SHA_H                             = 0x41,
 858     OPC2_32_RC_SHAS                              = 0x02,
 859     OPC2_32_RC_XNOR                              = 0x0d,
 860     OPC2_32_RC_XOR                               = 0x0c,
 861 };
 862 /* OPCM_32_RC_ACCUMULATOR                           */
 863 enum {
 864     OPC2_32_RC_ABSDIF                            = 0x0e,
 865     OPC2_32_RC_ABSDIFS                           = 0x0f,
 866     OPC2_32_RC_ADD                               = 0x00,
 867     OPC2_32_RC_ADDC                              = 0x05,
 868     OPC2_32_RC_ADDS                              = 0x02,
 869     OPC2_32_RC_ADDS_U                            = 0x03,
 870     OPC2_32_RC_ADDX                              = 0x04,
 871     OPC2_32_RC_AND_EQ                            = 0x20,
 872     OPC2_32_RC_AND_GE                            = 0x24,
 873     OPC2_32_RC_AND_GE_U                          = 0x25,
 874     OPC2_32_RC_AND_LT                            = 0x22,
 875     OPC2_32_RC_AND_LT_U                          = 0x23,
 876     OPC2_32_RC_AND_NE                            = 0x21,
 877     OPC2_32_RC_EQ                                = 0x10,
 878     OPC2_32_RC_EQANY_B                           = 0x56,
 879     OPC2_32_RC_EQANY_H                           = 0x76,
 880     OPC2_32_RC_GE                                = 0x14,
 881     OPC2_32_RC_GE_U                              = 0x15,
 882     OPC2_32_RC_LT                                = 0x12,
 883     OPC2_32_RC_LT_U                              = 0x13,
 884     OPC2_32_RC_MAX                               = 0x1a,
 885     OPC2_32_RC_MAX_U                             = 0x1b,
 886     OPC2_32_RC_MIN                               = 0x18,
 887     OPC2_32_RC_MIN_U                             = 0x19,
 888     OPC2_32_RC_NE                                = 0x11,
 889     OPC2_32_RC_OR_EQ                             = 0x27,
 890     OPC2_32_RC_OR_GE                             = 0x2b,
 891     OPC2_32_RC_OR_GE_U                           = 0x2c,
 892     OPC2_32_RC_OR_LT                             = 0x29,
 893     OPC2_32_RC_OR_LT_U                           = 0x2a,
 894     OPC2_32_RC_OR_NE                             = 0x28,
 895     OPC2_32_RC_RSUB                              = 0x08,
 896     OPC2_32_RC_RSUBS                             = 0x0a,
 897     OPC2_32_RC_RSUBS_U                           = 0x0b,
 898     OPC2_32_RC_SH_EQ                             = 0x37,
 899     OPC2_32_RC_SH_GE                             = 0x3b,
 900     OPC2_32_RC_SH_GE_U                           = 0x3c,
 901     OPC2_32_RC_SH_LT                             = 0x39,
 902     OPC2_32_RC_SH_LT_U                           = 0x3a,
 903     OPC2_32_RC_SH_NE                             = 0x38,
 904     OPC2_32_RC_XOR_EQ                            = 0x2f,
 905     OPC2_32_RC_XOR_GE                            = 0x33,
 906     OPC2_32_RC_XOR_GE_U                          = 0x34,
 907     OPC2_32_RC_XOR_LT                            = 0x31,
 908     OPC2_32_RC_XOR_LT_U                          = 0x32,
 909     OPC2_32_RC_XOR_NE                            = 0x30,
 910 };
 911 /* OPCM_32_RC_SERVICEROUTINE                        */
 912 enum {
 913     OPC2_32_RC_BISR                              = 0x00,
 914     OPC2_32_RC_SYSCALL                           = 0x04,
 915 };
 916 /* OPCM_32_RC_MUL                                   */
 917 enum {
 918     OPC2_32_RC_MUL_32                            = 0x01,
 919     OPC2_32_RC_MUL_64                            = 0x03,
 920     OPC2_32_RC_MULS_32                           = 0x05,
 921     OPC2_32_RC_MUL_U_64                          = 0x02,
 922     OPC2_32_RC_MULS_U_32                         = 0x04,
 923 };
 924 /*
 925  * RCPW Format
 926  */
 927 /* OPCM_32_RCPW_MASK_INSERT                         */
 928 enum {
 929     OPC2_32_RCPW_IMASK                           = 0x01,
 930     OPC2_32_RCPW_INSERT                          = 0x00,
 931 };
 932 /*
 933  * RCR Format
 934  */
 935 /* OPCM_32_RCR_COND_SELECT                          */
 936 enum {
 937     OPC2_32_RCR_CADD                             = 0x00,
 938     OPC2_32_RCR_CADDN                            = 0x01,
 939     OPC2_32_RCR_SEL                              = 0x04,
 940     OPC2_32_RCR_SELN                             = 0x05,
 941 };
 942 /* OPCM_32_RCR_MADD                                 */
 943 enum {
 944     OPC2_32_RCR_MADD_32                          = 0x01,
 945     OPC2_32_RCR_MADD_64                          = 0x03,
 946     OPC2_32_RCR_MADDS_32                         = 0x05,
 947     OPC2_32_RCR_MADDS_64                         = 0x07,
 948     OPC2_32_RCR_MADD_U_64                        = 0x02,
 949     OPC2_32_RCR_MADDS_U_32                       = 0x04,
 950     OPC2_32_RCR_MADDS_U_64                       = 0x06,
 951 };
 952 /* OPCM_32_RCR_MSUB                                 */
 953 enum {
 954     OPC2_32_RCR_MSUB_32                          = 0x01,
 955     OPC2_32_RCR_MSUB_64                          = 0x03,
 956     OPC2_32_RCR_MSUBS_32                         = 0x05,
 957     OPC2_32_RCR_MSUBS_64                         = 0x07,
 958     OPC2_32_RCR_MSUB_U_64                        = 0x02,
 959     OPC2_32_RCR_MSUBS_U_32                       = 0x04,
 960     OPC2_32_RCR_MSUBS_U_64                       = 0x06,
 961 };
 962 /*
 963  * RCRW Format
 964  */
 965 /* OPCM_32_RCRW_MASK_INSERT                         */
 966 enum {
 967     OPC2_32_RCRW_IMASK                           = 0x01,
 968     OPC2_32_RCRW_INSERT                          = 0x00,
 969 };
 970
 971 /*
 972  * RR Format
 973  */
 974 /* OPCM_32_RR_LOGICAL_SHIFT                         */
 975 enum {
 976     OPC2_32_RR_AND                               = 0x08,
 977     OPC2_32_RR_ANDN                              = 0x0e,
 978     OPC2_32_RR_CLO                               = 0x1c,
 979     OPC2_32_RR_CLO_H                             = 0x7d,
 980     OPC2_32_RR_CLS                               = 0x1d,
 981     OPC2_32_RR_CLS_H                             = 0x7e,
 982     OPC2_32_RR_CLZ                               = 0x1b,
 983     OPC2_32_RR_CLZ_H                             = 0x7c,
 984     OPC2_32_RR_NAND                              = 0x09,
 985     OPC2_32_RR_NOR                               = 0x0b,
 986     OPC2_32_RR_OR                                = 0x0a,
 987     OPC2_32_RR_ORN                               = 0x0f,
 988     OPC2_32_RR_SH                                = 0x00,
 989     OPC2_32_RR_SH_H                              = 0x40,
 990     OPC2_32_RR_SHA                               = 0x01,
 991     OPC2_32_RR_SHA_H                             = 0x41,
 992     OPC2_32_RR_SHAS                              = 0x02,
 993     OPC2_32_RR_XNOR                              = 0x0d,
 994     OPC2_32_RR_XOR                               = 0x0c,
 995 };
 996 /* OPCM_32_RR_ACCUMULATOR                           */
 997 enum {
 998     OPC2_32_RR_ABS                               = 0x1c,
 999     OPC2_32_RR_ABS_B                             = 0x5c,
1000     OPC2_32_RR_ABS_H                             = 0x7c,
1001     OPC2_32_RR_ABSDIF                            = 0x0e,
1002     OPC2_32_RR_ABSDIF_B                          = 0x4e,
1003     OPC2_32_RR_ABSDIF_H                          = 0x6e,
1004     OPC2_32_RR_ABSDIFS                           = 0x0f,
1005     OPC2_32_RR_ABSDIFS_H                         = 0x6f,
1006     OPC2_32_RR_ABSS                              = 0x1d,
1007     OPC2_32_RR_ABSS_H                            = 0x7d,
1008     OPC2_32_RR_ADD                               = 0x00,
1009     OPC2_32_RR_ADD_B                             = 0x40,
1010     OPC2_32_RR_ADD_H                             = 0x60,
1011     OPC2_32_RR_ADDC                              = 0x05,
1012     OPC2_32_RR_ADDS                              = 0x02,
1013     OPC2_32_RR_ADDS_H                            = 0x62,
1014     OPC2_32_RR_ADDS_HU                           = 0x63,
1015     OPC2_32_RR_ADDS_U                            = 0x03,
1016     OPC2_32_RR_ADDX                              = 0x04,
1017     OPC2_32_RR_AND_EQ                            = 0x20,
1018     OPC2_32_RR_AND_GE                            = 0x24,
1019     OPC2_32_RR_AND_GE_U                          = 0x25,
1020     OPC2_32_RR_AND_LT                            = 0x22,
1021     OPC2_32_RR_AND_LT_U                          = 0x23,
1022     OPC2_32_RR_AND_NE                            = 0x21,
1023     OPC2_32_RR_EQ                                = 0x10,
1024     OPC2_32_RR_EQ_B                              = 0x50,
1025     OPC2_32_RR_EQ_H                              = 0x70,
1026     OPC2_32_RR_EQ_W                              = 0x90,
1027     OPC2_32_RR_EQANY_B                           = 0x56,
1028     OPC2_32_RR_EQANY_H                           = 0x76,
1029     OPC2_32_RR_GE                                = 0x14,
1030     OPC2_32_RR_GE_U                              = 0x15,
1031     OPC2_32_RR_LT                                = 0x12,
1032     OPC2_32_RR_LT_U                              = 0x13,
1033     OPC2_32_RR_LT_B                              = 0x52,
1034     OPC2_32_RR_LT_BU                             = 0x53,
1035     OPC2_32_RR_LT_H                              = 0x72,
1036     OPC2_32_RR_LT_HU                             = 0x73,
1037     OPC2_32_RR_LT_W                              = 0x92,
1038     OPC2_32_RR_LT_WU                             = 0x93,
1039     OPC2_32_RR_MAX                               = 0x1a,
1040     OPC2_32_RR_MAX_U                             = 0x1b,
1041     OPC2_32_RR_MAX_B                             = 0x5a,
1042     OPC2_32_RR_MAX_BU                            = 0x5b,
1043     OPC2_32_RR_MAX_H                             = 0x7a,
1044     OPC2_32_RR_MAX_HU                            = 0x7b,
1045     OPC2_32_RR_MIN                               = 0x18,
1046     OPC2_32_RR_MIN_U                             = 0x19,
1047     OPC2_32_RR_MIN_B                             = 0x58,
1048     OPC2_32_RR_MIN_BU                            = 0x59,
1049     OPC2_32_RR_MIN_H                             = 0x78,
1050     OPC2_32_RR_MIN_HU                            = 0x79,
1051     OPC2_32_RR_MOV                               = 0x1f,
1052     OPC2_32_RR_NE                                = 0x11,
1053     OPC2_32_RR_OR_EQ                             = 0x27,
1054     OPC2_32_RR_OR_GE                             = 0x2b,
1055     OPC2_32_RR_OR_GE_U                           = 0x2c,
1056     OPC2_32_RR_OR_LT                             = 0x29,
1057     OPC2_32_RR_OR_LT_U                           = 0x2a,
1058     OPC2_32_RR_OR_NE                             = 0x28,
1059     OPC2_32_RR_SAT_B                             = 0x5e,
1060     OPC2_32_RR_SAT_BU                            = 0x5f,
1061     OPC2_32_RR_SAT_H                             = 0x7e,
1062     OPC2_32_RR_SAT_HU                            = 0x7f,
1063     OPC2_32_RR_SH_EQ                             = 0x37,
1064     OPC2_32_RR_SH_GE                             = 0x3b,
1065     OPC2_32_RR_SH_GE_U                           = 0x3c,
1066     OPC2_32_RR_SH_LT                             = 0x39,
1067     OPC2_32_RR_SH_LT_U                           = 0x3a,
1068     OPC2_32_RR_SH_NE                             = 0x38,
1069     OPC2_32_RR_SUB                               = 0x08,
1070     OPC2_32_RR_SUB_B                             = 0x48,
1071     OPC2_32_RR_SUB_H                             = 0x68,
1072     OPC2_32_RR_SUBC                              = 0x0d,
1073     OPC2_32_RR_SUBS                              = 0x0a,
1074     OPC2_32_RR_SUBS_U                            = 0x0b,
1075     OPC2_32_RR_SUBS_H                            = 0x6a,
1076     OPC2_32_RR_SUBS_HU                           = 0x6b,
1077     OPC2_32_RR_SUBX                              = 0x0c,
1078     OPC2_32_RR_XOR_EQ                            = 0x2f,
1079     OPC2_32_RR_XOR_GE                            = 0x33,
1080     OPC2_32_RR_XOR_GE_U                          = 0x34,
1081     OPC2_32_RR_XOR_LT                            = 0x31,
1082     OPC2_32_RR_XOR_LT_U                          = 0x32,
1083     OPC2_32_RR_XOR_NE                            = 0x30,
1084 };
1085 /* OPCM_32_RR_ADRESS                                */
1086 enum {
1087     OPC2_32_RR_ADD_A                             = 0x01,
1088     OPC2_32_RR_ADDSC_A                           = 0x60,
1089     OPC2_32_RR_ADDSC_AT                          = 0x62,
1090     OPC2_32_RR_EQ_A                              = 0x40,
1091     OPC2_32_RR_EQZ                               = 0x48,
1092     OPC2_32_RR_GE_A                              = 0x43,
1093     OPC2_32_RR_LT_A                              = 0x42,
1094     OPC2_32_RR_MOV_A                             = 0x63,
1095     OPC2_32_RR_MOV_AA                            = 0x00,
1096     OPC2_32_RR_MOV_D                             = 0x4c,
1097     OPC2_32_RR_NE_A                              = 0x41,
1098     OPC2_32_RR_NEZ_A                             = 0x49,
1099     OPC2_32_RR_SUB_A                             = 0x02,
1100 };
1101 /* OPCM_32_RR_FLOAT                                 */
1102 enum {
1103     OPC2_32_RR_BMERGE                            = 0x01,
1104     OPC2_32_RR_BSPLIT                            = 0x09,
1105     OPC2_32_RR_DVINIT_B                          = 0x5a,
1106     OPC2_32_RR_DVINIT_BU                         = 0x4a,
1107     OPC2_32_RR_DVINIT_H                          = 0x3a,
1108     OPC2_32_RR_DVINIT_HU                         = 0x2a,
1109     OPC2_32_RR_DVINIT                            = 0x1a,
1110     OPC2_32_RR_DVINIT_U                          = 0x0a,
1111     OPC2_32_RR_PARITY                            = 0x02,
1112     OPC2_32_RR_UNPACK                            = 0x08,
1113 };
1114 /* OPCM_32_RR_IDIRECT                               */
1115 enum {
1116     OPC2_32_RR_JI                                = 0x03,
1117     OPC2_32_RR_JLI                               = 0x02,
1118     OPC2_32_RR_CALLI                             = 0x00,
1119 };
1120 /*
1121  * RR1 Format
1122  */
1123 /* OPCM_32_RR1_MUL                                  */
1124 enum {
1125     OPC2_32_RR1_MUL_H_32_LL                      = 0x1a,
1126     OPC2_32_RR1_MUL_H_32_LU                      = 0x19,
1127     OPC2_32_RR1_MUL_H_32_UL                      = 0x18,
1128     OPC2_32_RR1_MUL_H_32_UU                      = 0x1b,
1129     OPC2_32_RR1_MULM_H_64_LL                     = 0x1e,
1130     OPC2_32_RR1_MULM_H_64_LU                     = 0x1d,
1131     OPC2_32_RR1_MULM_H_64_UL                     = 0x1c,
1132     OPC2_32_RR1_MULM_H_64_UU                     = 0x1f,
1133     OPC2_32_RR1_MULR_H_16_LL                     = 0x0e,
1134     OPC2_32_RR1_MULR_H_16_LU                     = 0x0d,
1135     OPC2_32_RR1_MULR_H_16_UL                     = 0x0c,
1136     OPC2_32_RR1_MULR_H_16_UU                     = 0x0f,
1137 };
1138 /* OPCM_32_RR1_MULQ                                 */
1139 enum {
1140     OPC2_32_RR1_MUL_Q_32                         = 0x02,
1141     OPC2_32_RR1_MUL_Q_64                         = 0x1b,
1142     OPC2_32_RR1_MUL_Q_32_L                       = 0x01,
1143     OPC2_32_RR1_MUL_Q_64_L                       = 0x19,
1144     OPC2_32_RR1_MUL_Q_32_U                       = 0x00,
1145     OPC2_32_RR1_MUL_Q_64_U                       = 0x18,
1146     OPC2_32_RR1_MUL_Q_32_LL                      = 0x05,
1147     OPC2_32_RR1_MUL_Q_32_UU                      = 0x04,
1148     OPC2_32_RR1_MULR_Q_32_L                      = 0x07,
1149     OPC2_32_RR1_MULR_Q_32_U                      = 0x06,
1150 };
1151 /*
1152  * RR2 Format
1153  */
1154 /* OPCM_32_RR2_MUL                                  */
1155 enum {
1156     OPC2_32_RR2_MUL_32                           = 0x0a,
1157     OPC2_32_RR2_MUL_64                           = 0x6a,
1158     OPC2_32_RR2_MULS_32                          = 0x8a,
1159     OPC2_32_RR2_MUL_U_64                         = 0x68,
1160     OPC2_32_RR2_MULS_U_32                        = 0x88,
1161 };
1162 /*
1163  * RRPW Format
1164  */
1165 /* OPCM_32_RRPW_EXTRACT_INSERT                      */
1166 enum {
1167
1168     OPC2_32_RRPW_EXTR                            = 0x02,
1169     OPC2_32_RRPW_EXTR_U                          = 0x03,
1170     OPC2_32_RRPW_IMASK                           = 0x01,
1171     OPC2_32_RRPW_INSERT                          = 0x00,
1172 };
1173 /*
1174  * RRR Format
1175  */
1176 /* OPCM_32_RRR_COND_SELECT                          */
1177 enum {
1178     OPC2_32_RRR_CADD                             = 0x00,
1179     OPC2_32_RRR_CADDN                            = 0x01,
1180     OPC2_32_RRR_CSUB                             = 0x02,
1181     OPC2_32_RRR_CSUBN                            = 0x03,
1182     OPC2_32_RRR_SEL                              = 0x04,
1183     OPC2_32_RRR_SELN                             = 0x05,
1184 };
1185 /* OPCM_32_RRR_FLOAT                                */
1186 enum {
1187     OPC2_32_RRR_DVADJ                            = 0x0d,
1188     OPC2_32_RRR_DVSTEP                           = 0x0f,
1189     OPC2_32_RRR_DVSTEP_U                         = 0x0e,
1190     OPC2_32_RRR_IXMAX                            = 0x0a,
1191     OPC2_32_RRR_IXMAX_U                          = 0x0b,
1192     OPC2_32_RRR_IXMIN                            = 0x08,
1193     OPC2_32_RRR_IXMIN_U                          = 0x09,
1194     OPC2_32_RRR_PACK                             = 0x00,
1195 };
1196 /*
1197  * RRR1 Format
1198  */
1199 /* OPCM_32_RRR1_MADD                                */
1200 enum {
1201     OPC2_32_RRR1_MADD_H_LL                       = 0x1a,
1202     OPC2_32_RRR1_MADD_H_LU                       = 0x19,
1203     OPC2_32_RRR1_MADD_H_UL                       = 0x18,
1204     OPC2_32_RRR1_MADD_H_UU                       = 0x1b,
1205     OPC2_32_RRR1_MADDS_H_LL                      = 0x3a,
1206     OPC2_32_RRR1_MADDS_H_LU                      = 0x39,
1207     OPC2_32_RRR1_MADDS_H_UL                      = 0x38,
1208     OPC2_32_RRR1_MADDS_H_UU                      = 0x3b,
1209     OPC2_32_RRR1_MADDM_H_LL                      = 0x1e,
1210     OPC2_32_RRR1_MADDM_H_LU                      = 0x1d,
1211     OPC2_32_RRR1_MADDM_H_UL                      = 0x1c,
1212     OPC2_32_RRR1_MADDM_H_UU                      = 0x1f,
1213     OPC2_32_RRR1_MADDMS_H_LL                     = 0x3e,
1214     OPC2_32_RRR1_MADDMS_H_LU                     = 0x3d,
1215     OPC2_32_RRR1_MADDMS_H_UL                     = 0x3c,
1216     OPC2_32_RRR1_MADDMS_H_UU                     = 0x3f,
1217     OPC2_32_RRR1_MADDR_H_LL                      = 0x0e,
1218     OPC2_32_RRR1_MADDR_H_LU                      = 0x0d,
1219     OPC2_32_RRR1_MADDR_H_UL                      = 0x0c,
1220     OPC2_32_RRR1_MADDR_H_UU                      = 0x0f,
1221     OPC2_32_RRR1_MADDRS_H_LL                     = 0x2e,
1222     OPC2_32_RRR1_MADDRS_H_LU                     = 0x2d,
1223     OPC2_32_RRR1_MADDRS_H_UL                     = 0x2c,
1224     OPC2_32_RRR1_MADDRS_H_UU                     = 0x2f,
1225 };
1226 /* OPCM_32_RRR1_MADDQ_H                             */
1227 enum {
1228     OPC2_32_RRR1_MADD_Q_32                       = 0x02,
1229     OPC2_32_RRR1_MADD_Q_64                       = 0x1b,
1230     OPC2_32_RRR1_MADD_Q_32_L                     = 0x01,
1231     OPC2_32_RRR1_MADD_Q_64_L                     = 0x19,
1232     OPC2_32_RRR1_MADD_Q_32_U                     = 0x00,
1233     OPC2_32_RRR1_MADD_Q_64_U                     = 0x18,
1234     OPC2_32_RRR1_MADD_Q_32_LL                    = 0x05,
1235     OPC2_32_RRR1_MADD_Q_64_LL                    = 0x1d,
1236     OPC2_32_RRR1_MADD_Q_32_UU                    = 0x04,
1237     OPC2_32_RRR1_MADD_Q_64_UU                    = 0x1c,
1238     OPC2_32_RRR1_MADDS_Q_32                      = 0x22,
1239     OPC2_32_RRR1_MADDS_Q_64                      = 0x3b,
1240     OPC2_32_RRR1_MADDS_Q_32_L                    = 0x21,
1241     OPC2_32_RRR1_MADDS_Q_64_L                    = 0x39,
1242     OPC2_32_RRR1_MADDS_Q_32_U                    = 0x20,
1243     OPC2_32_RRR1_MADDS_Q_64_U                    = 0x38,
1244     OPC2_32_RRR1_MADDS_Q_32_LL                   = 0x25,
1245     OPC2_32_RRR1_MADDS_Q_64_LL                   = 0x3d,
1246     OPC2_32_RRR1_MADDS_Q_32_UU                   = 0x24,
1247     OPC2_32_RRR1_MADDS_Q_64_UU                   = 0x3c,
1248     OPC2_32_RRR1_MADDR_H_16_UL                   = 0x1e,
1249     OPC2_32_RRR1_MADDRS_H_16_UL                  = 0x3e,
1250     OPC2_32_RRR1_MADDR_Q_32_L                    = 0x07,
1251     OPC2_32_RRR1_MADDR_Q_32_U                    = 0x06,
1252     OPC2_32_RRR1_MADDRS_Q_32_LL                  = 0x27,
1253     OPC2_32_RRR1_MADDRS_Q_32_UU                  = 0x26,
1254 };
1255 /* OPCM_32_RRR1_MADDSU_H                            */
1256 enum {
1257     OPC2_32_RRR1_MADDSU_H_32_LL                  = 0x1a,
1258     OPC2_32_RRR1_MADDSU_H_32_LU                  = 0x19,
1259     OPC2_32_RRR1_MADDSU_H_32_UL                  = 0x18,
1260     OPC2_32_RRR1_MADDSU_H_32_UU                  = 0x1b,
1261     OPC2_32_RRR1_MADDSUS_H_32_LL                 = 0x3a,
1262     OPC2_32_RRR1_MADDSUS_H_32_LU                 = 0x39,
1263     OPC2_32_RRR1_MADDSUS_H_32_UL                 = 0x38,
1264     OPC2_32_RRR1_MADDSUS_H_32_UU                 = 0x3b,
1265     OPC2_32_RRR1_MADDSUM_H_64_LL                 = 0x1e,
1266     OPC2_32_RRR1_MADDSUM_H_64_LU                 = 0x1d,
1267     OPC2_32_RRR1_MADDSUM_H_64_UL                 = 0x1c,
1268     OPC2_32_RRR1_MADDSUM_H_64_UU                 = 0x1f,
1269     OPC2_32_RRR1_MADDSUMS_H_64_LL                = 0x3e,
1270     OPC2_32_RRR1_MADDSUMS_H_64_LU                = 0x3d,
1271     OPC2_32_RRR1_MADDSUMS_H_64_UL                = 0x3c,
1272     OPC2_32_RRR1_MADDSUMS_H_64_UU                = 0x3f,
1273     OPC2_32_RRR1_MADDSUR_H_16_LL                 = 0x0e,
1274     OPC2_32_RRR1_MADDSUR_H_16_LU                 = 0x0d,
1275     OPC2_32_RRR1_MADDSUR_H_16_UL                 = 0x0c,
1276     OPC2_32_RRR1_MADDSUR_H_16_UU                 = 0x0f,
1277     OPC2_32_RRR1_MADDSURS_H_16_LL                = 0x2e,
1278     OPC2_32_RRR1_MADDSURS_H_16_LU                = 0x2d,
1279     OPC2_32_RRR1_MADDSURS_H_16_UL                = 0x2c,
1280     OPC2_32_RRR1_MADDSURS_H_16_UU                = 0x2f,
1281 };
1282 /* OPCM_32_RRR1_MSUB_H                              */
1283 enum {
1284     OPC2_32_RRR1_MSUB_H_32_LL                    = 0x1a,
1285     OPC2_32_RRR1_MSUB_H_32_LU                    = 0x19,
1286     OPC2_32_RRR1_MSUB_H_32_UL                    = 0x18,
1287     OPC2_32_RRR1_MSUB_H_32_UU                    = 0x1b,
1288     OPC2_32_RRR1_MSUBS_H_32_LL                   = 0x3a,
1289     OPC2_32_RRR1_MSUBS_H_32_LU                   = 0x39,
1290     OPC2_32_RRR1_MSUBS_H_32_UL                   = 0x38,
1291     OPC2_32_RRR1_MSUBS_H_32_UU                   = 0x3b,
1292     OPC2_32_RRR1_MSUBM_H_64_LL                   = 0x1e,
1293     OPC2_32_RRR1_MSUBM_H_64_LU                   = 0x1d,
1294     OPC2_32_RRR1_MSUBM_H_64_UL                   = 0x1c,
1295     OPC2_32_RRR1_MSUBM_H_64_UU                   = 0x1f,
1296     OPC2_32_RRR1_MSUBMS_H_64_LL                  = 0x3e,
1297     OPC2_32_RRR1_MSUBMS_H_64_LU                  = 0x3d,
1298     OPC2_32_RRR1_MSUBMS_H_64_UL                  = 0x3c,
1299     OPC2_32_RRR1_MSUBMS_H_64_UU                  = 0x3f,
1300     OPC2_32_RRR1_MSUBR_H_16_LL                   = 0x0e,
1301     OPC2_32_RRR1_MSUBR_H_16_LU                   = 0x0d,
1302     OPC2_32_RRR1_MSUBR_H_16_UL                   = 0x0c,
1303     OPC2_32_RRR1_MSUBR_H_16_UU                   = 0x0f,
1304     OPC2_32_RRR1_MSUBRS_H_16_LL                  = 0x2e,
1305     OPC2_32_RRR1_MSUBRS_H_16_LU                  = 0x2d,
1306     OPC2_32_RRR1_MSUBRS_H_16_UL                  = 0x2c,
1307     OPC2_32_RRR1_MSUBRS_H_16_UU                  = 0x2f,
1308 };
1309 /* OPCM_32_RRR1_MSUB_Q                              */
1310 enum {
1311     OPC2_32_RRR1_MSUB_Q_32                       = 0x02,
1312     OPC2_32_RRR1_MSUB_Q_64                       = 0x1b,
1313     OPC2_32_RRR1_MSUB_Q_32_L                     = 0x01,
1314     OPC2_32_RRR1_MSUB_Q_64_L                     = 0x19,
1315     OPC2_32_RRR1_MSUB_Q_32_U                     = 0x00,
1316     OPC2_32_RRR1_MSUB_Q_64_U                     = 0x18,
1317     OPC2_32_RRR1_MSUB_Q_32_LL                    = 0x05,
1318     OPC2_32_RRR1_MSUB_Q_64_LL                    = 0x1d,
1319     OPC2_32_RRR1_MSUB_Q_32_UU                    = 0x04,
1320     OPC2_32_RRR1_MSUB_Q_64_UU                    = 0x1c,
1321     OPC2_32_RRR1_MSUBS_Q_32                      = 0x22,
1322     OPC2_32_RRR1_MSUBS_Q_64                      = 0x3b,
1323     OPC2_32_RRR1_MSUBS_Q_32_L                    = 0x21,
1324     OPC2_32_RRR1_MSUBS_Q_64_L                    = 0x39,
1325     OPC2_32_RRR1_MSUBS_Q_32_U                    = 0x20,
1326     OPC2_32_RRR1_MSUBS_Q_64_U                    = 0x38,
1327     OPC2_32_RRR1_MSUBS_Q_32_LL                   = 0x25,
1328     OPC2_32_RRR1_MSUBS_Q_64_LL                   = 0x3d,
1329     OPC2_32_RRR1_MSUBS_Q_32_UU                   = 0x24,
1330     OPC2_32_RRR1_MSUBS_Q_64_UU                   = 0x3c,
1331     OPC2_32_RRR1_MSUBR_H_32_UL                   = 0x1e,
1332     OPC2_32_RRR1_MSUBRS_H_32_UL                  = 0x3e,
1333     OPC2_32_RRR1_MSUBR_Q_32_LL                   = 0x07,
1334     OPC2_32_RRR1_MSUBR_Q_32_UU                   = 0x06,
1335     OPC2_32_RRR1_MSUBRS_Q_32_LL                  = 0x27,
1336     OPC2_32_RRR1_MSUBRS_Q_32_UU                  = 0x26,
1337 };
1338 /* OPCM_32_RRR1_MSUBADS_H                           */
1339 enum {
1340     OPC2_32_RRR1_MSUBAD_H_32_LL                  = 0x1a,
1341     OPC2_32_RRR1_MSUBAD_H_32_LU                  = 0x19,
1342     OPC2_32_RRR1_MSUBAD_H_32_UL                  = 0x18,
1343     OPC2_32_RRR1_MSUBAD_H_32_UU                  = 0x1b,
1344     OPC2_32_RRR1_MSUBADS_H_32_LL                 = 0x3a,
1345     OPC2_32_RRR1_MSUBADS_H_32_LU                 = 0x39,
1346     OPC2_32_RRR1_MSUBADS_H_32_UL                 = 0x38,
1347     OPC2_32_RRR1_MSUBADS_H_32_UU                 = 0x3b,
1348     OPC2_32_RRR1_MSUBADM_H_64_LL                 = 0x1e,
1349     OPC2_32_RRR1_MSUBADM_H_64_LU                 = 0x1d,
1350     OPC2_32_RRR1_MSUBADM_H_64_UL                 = 0x1c,
1351     OPC2_32_RRR1_MSUBADM_H_64_UU                 = 0x1f,
1352     OPC2_32_RRR1_MSUBADMS_H_64_LL                = 0x3e,
1353     OPC2_32_RRR1_MSUBADMS_H_64_LU                = 0x3d,
1354     OPC2_32_RRR1_MSUBADMS_H_64_UL                = 0x3c,
1355     OPC2_32_RRR1_MSUBADMS_H_16_UU                = 0x3f,
1356     OPC2_32_RRR1_MSUBADR_H_16_LL                 = 0x0e,
1357     OPC2_32_RRR1_MSUBADR_H_16_LU                 = 0x0d,
1358     OPC2_32_RRR1_MSUBADR_H_16_UL                 = 0x0c,
1359     OPC2_32_RRR1_MSUBADR_H_16_UU                 = 0x0f,
1360     OPC2_32_RRR1_MSUBADRS_H_16_LL                = 0x2e,
1361     OPC2_32_RRR1_MSUBADRS_H_16_LU                = 0x2d,
1362     OPC2_32_RRR1_MSUBADRS_H_16_UL                = 0x2c,
1363     OPC2_32_RRR1_MSUBADRS_H_16_UU                = 0x2f,
1364 };
1365 /*
1366  * RRR2 Format
1367  */
1368 /* OPCM_32_RRR2_MADD                                */
1369 enum {
1370     OPC2_32_RRR2_MADD_32                         = 0x0a,
1371     OPC2_32_RRR2_MADD_64                         = 0x6a,
1372     OPC2_32_RRR2_MADDS_32                        = 0x8a,
1373     OPC2_32_RRR2_MADDS_64                        = 0xea,
1374     OPC2_32_RRR2_MADD_U_32                       = 0x68,
1375     OPC2_32_RRR2_MADDS_U_32                      = 0x88,
1376     OPC2_32_RRR2_MADDS_U_64                      = 0xe8,
1377 };
1378 /* OPCM_32_RRR2_MSUB                                */
1379 enum {
1380     OPC2_32_RRR2_MSUB_32                         = 0x0a,
1381     OPC2_32_RRR2_MSUB_64                         = 0x6a,
1382     OPC2_32_RRR2_MSUBS_32                        = 0x8a,
1383     OPC2_32_RRR2_MSUBS_64                        = 0xea,
1384     OPC2_32_RRR2_MSUB_U_64                       = 0x68,
1385     OPC2_32_RRR2_MSUBS_U_32                      = 0x88,
1386     OPC2_32_RRR2_MSUBS_U_64                      = 0xe8,
1387 };
1388 /*
1389  * RRRR Format
1390  */
1391 /* OPCM_32_RRRR_EXTRACT_INSERT                      */
1392 enum {
1393     OPC2_32_RRRR_DEXTR                           = 0x04,
1394     OPC2_32_RRRR_EXTR                            = 0x02,
1395     OPC2_32_RRRR_EXTR_U                          = 0x03,
1396     OPC2_32_RRRR_INSERT                          = 0x00,
1397 };
1398 /*
1399  * RRRW Format
1400  */
1401 /* OPCM_32_RRRW_EXTRACT_INSERT                      */
1402 enum {
1403     OPC2_32_RRRW_EXTR                            = 0x02,
1404     OPC2_32_RRRW_EXTR_U                          = 0x03,
1405     OPC2_32_RRRW_IMASK                           = 0x01,
1406     OPC2_32_RRRW_INSERT                          = 0x00,
1407 };
1408 /*
1409  * SYS Format
1410  */
1411 /* OPCM_32_SYS_INTERRUPTS                           */
1412 enum {
1413     OPC2_32_SYS_DEBUG                            = 0x04,
1414     OPC2_32_SYS_DISABLE                          = 0x0d,
1415     OPC2_32_SYS_DSYNC                            = 0x12,
1416     OPC2_32_SYS_ENABLE                           = 0x0c,
1417     OPC2_32_SYS_ISYNC                            = 0x13,
1418     OPC2_32_SYS_NOP                              = 0x00,
1419     OPC2_32_SYS_RET                              = 0x06,
1420     OPC2_32_SYS_RFE                              = 0x07,
1421     OPC2_32_SYS_RFM                              = 0x05,
1422     OPC2_32_SYS_RSLCX                            = 0x09,
1423     OPC2_32_SYS_SVLCX                            = 0x08,
1424     OPC2_32_SYS_TRAPSV                           = 0x15,
1425     OPC2_32_SYS_TRAPV                            = 0x14,
1426 };