hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "pci_host.h"
  29 #include "isa.h"
  30 #include "sysbus.h"
  31 #include "range.h"
  32 #include "xen.h"
  33
  34 /*
  35  * I440FX chipset data sheet.
  36  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  37  */
  38
  39 typedef struct I440FXState {
  40     PCIHostState parent_obj;
  41 } I440FXState;
  42
  43 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  44 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  45 #define XEN_PIIX_NUM_PIRQS      128ULL
  46 #define PIIX_PIRQC              0x60
  47
  48 typedef struct PIIX3State {
  49     PCIDevice dev;
  50
  51     /*
  52      * bitmap to track pic levels.
  53      * The pic level is the logical OR of all the PCI irqs mapped to it
  54      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  55      *
  56      * PIRQ is mapped to PIC pins, we track it by
  57      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  58      * pic_irq * PIIX_NUM_PIRQS + pirq
  59      */
  60 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  61 #error "unable to encode pic state in 64bit in pic_levels."
  62 #endif
  63     uint64_t pic_levels;
  64
  65     qemu_irq *pic;
  66
  67     /* This member isn't used. Just for save/load compatibility */
  68     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  69 } PIIX3State;
  70
  71 typedef struct PAMMemoryRegion {
  72     MemoryRegion alias[4];  /* index = PAM value */
  73     unsigned current;
  74 } PAMMemoryRegion;
  75
  76 struct PCII440FXState {
  77     PCIDevice dev;
  78     MemoryRegion *system_memory;
  79     MemoryRegion *pci_address_space;
  80     MemoryRegion *ram_memory;
  81     MemoryRegion pci_hole;
  82     MemoryRegion pci_hole_64bit;
  83     PAMMemoryRegion pam_regions[13];
  84     MemoryRegion smram_region;
  85     uint8_t smm_enabled;
  86 };
  87
  88
  89 #define I440FX_PAM      0x59
  90 #define I440FX_PAM_SIZE 7
  91 #define I440FX_SMRAM    0x72
  92
  93 static void piix3_set_irq(void *opaque, int pirq, int level);
  94 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
  95 static void piix3_write_config_xen(PCIDevice *dev,
  96                                uint32_t address, uint32_t val, int len);
  97
  98 /* return the global irq number corresponding to a given device irq
  99    pin. We could also use the bus number to have a more precise
 100    mapping. */
 101 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 102 {
 103     int slot_addend;
 104     slot_addend = (pci_dev->devfn >> 3) - 1;
 105     return (pci_intx + slot_addend) & 3;
 106 }
 107
 108 static void init_pam(PCII440FXState *d, PAMMemoryRegion *mem,
 109                      uint32_t start, uint32_t size)
 110 {
 111     int i;
 112
 113     /* RAM */
 114     memory_region_init_alias(&mem->alias[3], "pam-ram", d->ram_memory, start, size);
 115     /* ROM (XXX: not quite correct) */
 116     memory_region_init_alias(&mem->alias[1], "pam-rom", d->ram_memory, start, size);
 117     memory_region_set_readonly(&mem->alias[1], true);
 118
 119     /* XXX: should distinguish read/write cases */
 120     memory_region_init_alias(&mem->alias[0], "pam-pci", d->pci_address_space,
 121                              start, size);
 122     memory_region_init_alias(&mem->alias[2], "pam-pci", d->pci_address_space,
 123                              start, size);
 124
 125     for (i = 0; i < 4; ++i) {
 126         memory_region_set_enabled(&mem->alias[i], false);
 127         memory_region_add_subregion_overlap(d->system_memory, start, &mem->alias[i], 1);
 128     }
 129     mem->current = 0;
 130 }
 131
 132 static void update_pam(PAMMemoryRegion *pam, unsigned r)
 133 {
 134     memory_region_set_enabled(&pam->alias[pam->current], false);
 135     pam->current = r;
 136     memory_region_set_enabled(&pam->alias[pam->current], true);
 137 }
 138
 139 static void i440fx_update_memory_mappings(PCII440FXState *d)
 140 {
 141     int i, r;
 142     uint32_t smram;
 143     bool smram_enabled;
 144
 145     memory_region_transaction_begin();
 146     update_pam(&d->pam_regions[0], (d->dev.config[I440FX_PAM] >> 4) & 3);
 147     for(i = 0; i < 12; i++) {
 148         r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
 149         update_pam(&d->pam_regions[i+1], r);
 150     }
 151     smram = d->dev.config[I440FX_SMRAM];
 152     smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
 153     memory_region_set_enabled(&d->smram_region, !smram_enabled);
 154     memory_region_transaction_commit();
 155 }
 156
 157 static void i440fx_set_smm(int val, void *arg)
 158 {
 159     PCII440FXState *d = arg;
 160
 161     val = (val != 0);
 162     if (d->smm_enabled != val) {
 163         d->smm_enabled = val;
 164         i440fx_update_memory_mappings(d);
 165     }
 166 }
 167
 168
 169 static void i440fx_write_config(PCIDevice *dev,
 170                                 uint32_t address, uint32_t val, int len)
 171 {
 172     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 173
 174     /* XXX: implement SMRAM.D_LOCK */
 175     pci_default_write_config(dev, address, val, len);
 176     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 177         range_covers_byte(address, len, I440FX_SMRAM)) {
 178         i440fx_update_memory_mappings(d);
 179     }
 180 }
 181
 182 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 183 {
 184     PCII440FXState *d = opaque;
 185     int ret, i;
 186
 187     ret = pci_device_load(&d->dev, f);
 188     if (ret < 0)
 189         return ret;
 190     i440fx_update_memory_mappings(d);
 191     qemu_get_8s(f, &d->smm_enabled);
 192
 193     if (version_id == 2) {
 194         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 195             qemu_get_be32(f); /* dummy load for compatibility */
 196         }
 197     }
 198
 199     return 0;
 200 }
 201
 202 static int i440fx_post_load(void *opaque, int version_id)
 203 {
 204     PCII440FXState *d = opaque;
 205
 206     i440fx_update_memory_mappings(d);
 207     return 0;
 208 }
 209
 210 static const VMStateDescription vmstate_i440fx = {
 211     .name = "I440FX",
 212     .version_id = 3,
 213     .minimum_version_id = 3,
 214     .minimum_version_id_old = 1,
 215     .load_state_old = i440fx_load_old,
 216     .post_load = i440fx_post_load,
 217     .fields      = (VMStateField []) {
 218         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 219         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 220         VMSTATE_END_OF_LIST()
 221     }
 222 };
 223
 224 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 225 {
 226     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 227
 228     memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
 229                           "pci-conf-idx", 4);
 230     sysbus_add_io(dev, 0xcf8, &s->conf_mem);
 231     sysbus_init_ioports(&s->busdev, 0xcf8, 4);
 232
 233     memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
 234                           "pci-conf-data", 4);
 235     sysbus_add_io(dev, 0xcfc, &s->data_mem);
 236     sysbus_init_ioports(&s->busdev, 0xcfc, 4);
 237
 238     return 0;
 239 }
 240
 241 static int i440fx_initfn(PCIDevice *dev)
 242 {
 243     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 244
 245     d->dev.config[I440FX_SMRAM] = 0x02;
 246
 247     cpu_smm_register(&i440fx_set_smm, d);
 248     return 0;
 249 }
 250
 251 static PCIBus *i440fx_common_init(const char *device_name,
 252                                   PCII440FXState **pi440fx_state,
 253                                   int *piix3_devfn,
 254                                   ISABus **isa_bus, qemu_irq *pic,
 255                                   MemoryRegion *address_space_mem,
 256                                   MemoryRegion *address_space_io,
 257                                   ram_addr_t ram_size,
 258                                   hwaddr pci_hole_start,
 259                                   hwaddr pci_hole_size,
 260                                   hwaddr pci_hole64_start,
 261                                   hwaddr pci_hole64_size,
 262                                   MemoryRegion *pci_address_space,
 263                                   MemoryRegion *ram_memory)
 264 {
 265     DeviceState *dev;
 266     PCIBus *b;
 267     PCIDevice *d;
 268     PCIHostState *s;
 269     PIIX3State *piix3;
 270     PCII440FXState *f;
 271     unsigned i;
 272
 273     dev = qdev_create(NULL, "i440FX-pcihost");
 274     s = PCI_HOST_BRIDGE(dev);
 275     s->address_space = address_space_mem;
 276     b = pci_bus_new(dev, NULL, pci_address_space,
 277                     address_space_io, 0);
 278     s->bus = b;
 279     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 280     qdev_init_nofail(dev);
 281
 282     d = pci_create_simple(b, 0, device_name);
 283     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 284     f = *pi440fx_state;
 285     f->system_memory = address_space_mem;
 286     f->pci_address_space = pci_address_space;
 287     f->ram_memory = ram_memory;
 288     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
 289                              pci_hole_start, pci_hole_size);
 290     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 291     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
 292                              f->pci_address_space,
 293                              pci_hole64_start, pci_hole64_size);
 294     if (pci_hole64_size) {
 295         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 296                                     &f->pci_hole_64bit);
 297     }
 298     memory_region_init_alias(&f->smram_region, "smram-region",
 299                              f->pci_address_space, 0xa0000, 0x20000);
 300     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 301                                         &f->smram_region, 1);
 302     memory_region_set_enabled(&f->smram_region, false);
 303     init_pam(f, &f->pam_regions[0], 0xf0000, 0x10000);
 304     for (i = 0; i < 12; ++i) {
 305         init_pam(f, &f->pam_regions[i+1], 0xc0000 + i * 0x4000, 0x4000);
 306     }
 307
 308     /* Xen supports additional interrupt routes from the PCI devices to
 309      * the IOAPIC: the four pins of each PCI device on the bus are also
 310      * connected to the IOAPIC directly.
 311      * These additional routes can be discovered through ACPI. */
 312     if (xen_enabled()) {
 313         piix3 = DO_UPCAST(PIIX3State, dev,
 314                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 315         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 316                 piix3, XEN_PIIX_NUM_PIRQS);
 317     } else {
 318         piix3 = DO_UPCAST(PIIX3State, dev,
 319                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 320         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 321                 PIIX_NUM_PIRQS);
 322         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 323     }
 324     piix3->pic = pic;
 325     *isa_bus = DO_UPCAST(ISABus, qbus,
 326                          qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
 327
 328     *piix3_devfn = piix3->dev.devfn;
 329
 330     ram_size = ram_size / 8 / 1024 / 1024;
 331     if (ram_size > 255)
 332         ram_size = 255;
 333     (*pi440fx_state)->dev.config[0x57]=ram_size;
 334
 335     i440fx_update_memory_mappings(f);
 336
 337     return b;
 338 }
 339
 340 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 341                     ISABus **isa_bus, qemu_irq *pic,
 342                     MemoryRegion *address_space_mem,
 343                     MemoryRegion *address_space_io,
 344                     ram_addr_t ram_size,
 345                     hwaddr pci_hole_start,
 346                     hwaddr pci_hole_size,
 347                     hwaddr pci_hole64_start,
 348                     hwaddr pci_hole64_size,
 349                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 350
 351 {
 352     PCIBus *b;
 353
 354     b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
 355                            address_space_mem, address_space_io, ram_size,
 356                            pci_hole_start, pci_hole_size,
 357                            pci_hole64_start, pci_hole64_size,
 358                            pci_memory, ram_memory);
 359     return b;
 360 }
 361
 362 /* PIIX3 PCI to ISA bridge */
 363 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 364 {
 365     qemu_set_irq(piix3->pic[pic_irq],
 366                  !!(piix3->pic_levels &
 367                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 368                      (pic_irq * PIIX_NUM_PIRQS))));
 369 }
 370
 371 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 372 {
 373     int pic_irq;
 374     uint64_t mask;
 375
 376     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 377     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 378         return;
 379     }
 380
 381     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 382     piix3->pic_levels &= ~mask;
 383     piix3->pic_levels |= mask * !!level;
 384
 385     piix3_set_irq_pic(piix3, pic_irq);
 386 }
 387
 388 static void piix3_set_irq(void *opaque, int pirq, int level)
 389 {
 390     PIIX3State *piix3 = opaque;
 391     piix3_set_irq_level(piix3, pirq, level);
 392 }
 393
 394 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 395 {
 396     PIIX3State *piix3 = opaque;
 397     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 398     PCIINTxRoute route;
 399
 400     if (irq < PIIX_NUM_PIC_IRQS) {
 401         route.mode = PCI_INTX_ENABLED;
 402         route.irq = irq;
 403     } else {
 404         route.mode = PCI_INTX_DISABLED;
 405         route.irq = -1;
 406     }
 407     return route;
 408 }
 409
 410 /* irq routing is changed. so rebuild bitmap */
 411 static void piix3_update_irq_levels(PIIX3State *piix3)
 412 {
 413     int pirq;
 414
 415     piix3->pic_levels = 0;
 416     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 417         piix3_set_irq_level(piix3, pirq,
 418                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 419     }
 420 }
 421
 422 static void piix3_write_config(PCIDevice *dev,
 423                                uint32_t address, uint32_t val, int len)
 424 {
 425     pci_default_write_config(dev, address, val, len);
 426     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 427         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 428         int pic_irq;
 429
 430         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 431         piix3_update_irq_levels(piix3);
 432         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 433             piix3_set_irq_pic(piix3, pic_irq);
 434         }
 435     }
 436 }
 437
 438 static void piix3_write_config_xen(PCIDevice *dev,
 439                                uint32_t address, uint32_t val, int len)
 440 {
 441     xen_piix_pci_write_config_client(address, val, len);
 442     piix3_write_config(dev, address, val, len);
 443 }
 444
 445 static void piix3_reset(void *opaque)
 446 {
 447     PIIX3State *d = opaque;
 448     uint8_t *pci_conf = d->dev.config;
 449
 450     pci_conf[0x04] = 0x07; // master, memory and I/O
 451     pci_conf[0x05] = 0x00;
 452     pci_conf[0x06] = 0x00;
 453     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 454     pci_conf[0x4c] = 0x4d;
 455     pci_conf[0x4e] = 0x03;
 456     pci_conf[0x4f] = 0x00;
 457     pci_conf[0x60] = 0x80;
 458     pci_conf[0x61] = 0x80;
 459     pci_conf[0x62] = 0x80;
 460     pci_conf[0x63] = 0x80;
 461     pci_conf[0x69] = 0x02;
 462     pci_conf[0x70] = 0x80;
 463     pci_conf[0x76] = 0x0c;
 464     pci_conf[0x77] = 0x0c;
 465     pci_conf[0x78] = 0x02;
 466     pci_conf[0x79] = 0x00;
 467     pci_conf[0x80] = 0x00;
 468     pci_conf[0x82] = 0x00;
 469     pci_conf[0xa0] = 0x08;
 470     pci_conf[0xa2] = 0x00;
 471     pci_conf[0xa3] = 0x00;
 472     pci_conf[0xa4] = 0x00;
 473     pci_conf[0xa5] = 0x00;
 474     pci_conf[0xa6] = 0x00;
 475     pci_conf[0xa7] = 0x00;
 476     pci_conf[0xa8] = 0x0f;
 477     pci_conf[0xaa] = 0x00;
 478     pci_conf[0xab] = 0x00;
 479     pci_conf[0xac] = 0x00;
 480     pci_conf[0xae] = 0x00;
 481
 482     d->pic_levels = 0;
 483 }
 484
 485 static int piix3_post_load(void *opaque, int version_id)
 486 {
 487     PIIX3State *piix3 = opaque;
 488     piix3_update_irq_levels(piix3);
 489     return 0;
 490 }
 491
 492 static void piix3_pre_save(void *opaque)
 493 {
 494     int i;
 495     PIIX3State *piix3 = opaque;
 496
 497     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 498         piix3->pci_irq_levels_vmstate[i] =
 499             pci_bus_get_irq_level(piix3->dev.bus, i);
 500     }
 501 }
 502
 503 static const VMStateDescription vmstate_piix3 = {
 504     .name = "PIIX3",
 505     .version_id = 3,
 506     .minimum_version_id = 2,
 507     .minimum_version_id_old = 2,
 508     .post_load = piix3_post_load,
 509     .pre_save = piix3_pre_save,
 510     .fields      = (VMStateField []) {
 511         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 512         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 513                               PIIX_NUM_PIRQS, 3),
 514         VMSTATE_END_OF_LIST()
 515     }
 516 };
 517
 518 static int piix3_initfn(PCIDevice *dev)
 519 {
 520     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 521
 522     isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
 523     qemu_register_reset(piix3_reset, d);
 524     return 0;
 525 }
 526
 527 static void piix3_class_init(ObjectClass *klass, void *data)
 528 {
 529     DeviceClass *dc = DEVICE_CLASS(klass);
 530     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 531
 532     dc->desc        = "ISA bridge";
 533     dc->vmsd        = &vmstate_piix3;
 534     dc->no_user     = 1,
 535     k->no_hotplug   = 1;
 536     k->init         = piix3_initfn;
 537     k->config_write = piix3_write_config;
 538     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 539     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 540     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 541 }
 542
 543 static const TypeInfo piix3_info = {
 544     .name          = "PIIX3",
 545     .parent        = TYPE_PCI_DEVICE,
 546     .instance_size = sizeof(PIIX3State),
 547     .class_init    = piix3_class_init,
 548 };
 549
 550 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 551 {
 552     DeviceClass *dc = DEVICE_CLASS(klass);
 553     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 554
 555     dc->desc        = "ISA bridge";
 556     dc->vmsd        = &vmstate_piix3;
 557     dc->no_user     = 1;
 558     k->no_hotplug   = 1;
 559     k->init         = piix3_initfn;
 560     k->config_write = piix3_write_config_xen;
 561     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 562     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 563     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 564 };
 565
 566 static const TypeInfo piix3_xen_info = {
 567     .name          = "PIIX3-xen",
 568     .parent        = TYPE_PCI_DEVICE,
 569     .instance_size = sizeof(PIIX3State),
 570     .class_init    = piix3_xen_class_init,
 571 };
 572
 573 static void i440fx_class_init(ObjectClass *klass, void *data)
 574 {
 575     DeviceClass *dc = DEVICE_CLASS(klass);
 576     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 577
 578     k->no_hotplug = 1;
 579     k->init = i440fx_initfn;
 580     k->config_write = i440fx_write_config;
 581     k->vendor_id = PCI_VENDOR_ID_INTEL;
 582     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 583     k->revision = 0x02;
 584     k->class_id = PCI_CLASS_BRIDGE_HOST;
 585     dc->desc = "Host bridge";
 586     dc->no_user = 1;
 587     dc->vmsd = &vmstate_i440fx;
 588 }
 589
 590 static const TypeInfo i440fx_info = {
 591     .name          = "i440FX",
 592     .parent        = TYPE_PCI_DEVICE,
 593     .instance_size = sizeof(PCII440FXState),
 594     .class_init    = i440fx_class_init,
 595 };
 596
 597 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 598 {
 599     DeviceClass *dc = DEVICE_CLASS(klass);
 600     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 601
 602     k->init = i440fx_pcihost_initfn;
 603     dc->fw_name = "pci";
 604     dc->no_user = 1;
 605 }
 606
 607 static const TypeInfo i440fx_pcihost_info = {
 608     .name          = "i440FX-pcihost",
 609     .parent        = TYPE_PCI_HOST_BRIDGE,
 610     .instance_size = sizeof(I440FXState),
 611     .class_init    = i440fx_pcihost_class_init,
 612 };
 613
 614 static void i440fx_register_types(void)
 615 {
 616     type_register_static(&i440fx_info);
 617     type_register_static(&piix3_info);
 618     type_register_static(&piix3_xen_info);
 619     type_register_static(&i440fx_pcihost_info);
 620 }
 621
 622 type_init(i440fx_register_types)