hw/pci-host/q35.c

   1 /*
   2  * QEMU MCH/ICH9 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009, 2010, 2011
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <[email protected]>
   9  *
  10  * This is based on piix_pci.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/pci-host/q35.h"
  32 #include "qapi/visitor.h"
  33
  34 /****************************************************************************
  35  * Q35 host
  36  */
  37
  38 static void q35_host_realize(DeviceState *dev, Error **errp)
  39 {
  40     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
  41     Q35PCIHost *s = Q35_HOST_DEVICE(dev);
  42     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  43
  44     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
  45     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
  46
  47     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
  48     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
  49
  50     if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) {
  51         error_setg(errp, "failed to initialize pcie host");
  52         return;
  53     }
  54     pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
  55                            s->mch.pci_address_space, s->mch.address_space_io,
  56                            0, TYPE_PCIE_BUS);
  57     qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
  58     qdev_init_nofail(DEVICE(&s->mch));
  59 }
  60
  61 static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
  62                                           PCIBus *rootbus)
  63 {
  64     /* For backwards compat with old device paths */
  65     return "0000";
  66 }
  67
  68 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
  69                                         void *opaque, const char *name,
  70                                         Error **errp)
  71 {
  72     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  73     uint32_t value = s->mch.pci_info.w32.begin;
  74
  75     visit_type_uint32(v, &value, name, errp);
  76 }
  77
  78 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
  79                                       void *opaque, const char *name,
  80                                       Error **errp)
  81 {
  82     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  83     uint32_t value = s->mch.pci_info.w32.end;
  84
  85     visit_type_uint32(v, &value, name, errp);
  86 }
  87
  88 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
  89                                           void *opaque, const char *name,
  90                                           Error **errp)
  91 {
  92     PCIHostState *h = PCI_HOST_BRIDGE(obj);
  93     Range w64;
  94
  95     pci_bus_get_w64_range(h->bus, &w64);
  96
  97     visit_type_uint64(v, &w64.begin, name, errp);
  98 }
  99
 100 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
 101                                         void *opaque, const char *name,
 102                                         Error **errp)
 103 {
 104     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 105     Range w64;
 106
 107     pci_bus_get_w64_range(h->bus, &w64);
 108
 109     visit_type_uint64(v, &w64.end, name, errp);
 110 }
 111
 112 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
 113                                     void *opaque, const char *name,
 114                                     Error **errp)
 115 {
 116     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
 117     uint32_t value = e->size;
 118
 119     visit_type_uint32(v, &value, name, errp);
 120 }
 121
 122 static Property mch_props[] = {
 123     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
 124                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
 125     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
 126                      mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
 127     DEFINE_PROP_END_OF_LIST(),
 128 };
 129
 130 static void q35_host_class_init(ObjectClass *klass, void *data)
 131 {
 132     DeviceClass *dc = DEVICE_CLASS(klass);
 133     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 134
 135     hc->root_bus_path = q35_host_root_bus_path;
 136     dc->realize = q35_host_realize;
 137     dc->props = mch_props;
 138     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 139     dc->fw_name = "pci";
 140 }
 141
 142 static void q35_host_initfn(Object *obj)
 143 {
 144     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
 145     PCIHostState *phb = PCI_HOST_BRIDGE(obj);
 146
 147     memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
 148                           "pci-conf-idx", 4);
 149     memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
 150                           "pci-conf-data", 4);
 151
 152     object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
 153     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
 154     qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
 155     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
 156
 157     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
 158                         q35_host_get_pci_hole_start,
 159                         NULL, NULL, NULL, NULL);
 160
 161     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
 162                         q35_host_get_pci_hole_end,
 163                         NULL, NULL, NULL, NULL);
 164
 165     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
 166                         q35_host_get_pci_hole64_start,
 167                         NULL, NULL, NULL, NULL);
 168
 169     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
 170                         q35_host_get_pci_hole64_end,
 171                         NULL, NULL, NULL, NULL);
 172
 173     object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
 174                         q35_host_get_mmcfg_size,
 175                         NULL, NULL, NULL, NULL);
 176
 177     /* Leave enough space for the biggest MCFG BAR */
 178     /* TODO: this matches current bios behaviour, but
 179      * it's not a power of two, which means an MTRR
 180      * can't cover it exactly.
 181      */
 182     s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
 183         MCH_HOST_BRIDGE_PCIEXBAR_MAX;
 184     s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
 185 }
 186
 187 static const TypeInfo q35_host_info = {
 188     .name       = TYPE_Q35_HOST_DEVICE,
 189     .parent     = TYPE_PCIE_HOST_BRIDGE,
 190     .instance_size = sizeof(Q35PCIHost),
 191     .instance_init = q35_host_initfn,
 192     .class_init = q35_host_class_init,
 193 };
 194
 195 /****************************************************************************
 196  * MCH D0:F0
 197  */
 198
 199 /* PCIe MMCFG */
 200 static void mch_update_pciexbar(MCHPCIState *mch)
 201 {
 202     PCIDevice *pci_dev = PCI_DEVICE(mch);
 203     BusState *bus = qdev_get_parent_bus(DEVICE(mch));
 204     PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
 205
 206     uint64_t pciexbar;
 207     int enable;
 208     uint64_t addr;
 209     uint64_t addr_mask;
 210     uint32_t length;
 211
 212     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
 213     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
 214     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
 215     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
 216     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
 217         length = 256 * 1024 * 1024;
 218         break;
 219     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
 220         length = 128 * 1024 * 1024;
 221         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
 222             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 223         break;
 224     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
 225         length = 64 * 1024 * 1024;
 226         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 227         break;
 228     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
 229     default:
 230         enable = 0;
 231         length = 0;
 232         abort();
 233         break;
 234     }
 235     addr = pciexbar & addr_mask;
 236     pcie_host_mmcfg_update(pehb, enable, addr, length);
 237     /* Leave enough space for the MCFG BAR */
 238     /*
 239      * TODO: this matches current bios behaviour, but it's not a power of two,
 240      * which means an MTRR can't cover it exactly.
 241      */
 242     if (enable) {
 243         mch->pci_info.w32.begin = addr + length;
 244     } else {
 245         mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
 246     }
 247 }
 248
 249 /* PAM */
 250 static void mch_update_pam(MCHPCIState *mch)
 251 {
 252     PCIDevice *pd = PCI_DEVICE(mch);
 253     int i;
 254
 255     memory_region_transaction_begin();
 256     for (i = 0; i < 13; i++) {
 257         pam_update(&mch->pam_regions[i], i,
 258                    pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
 259     }
 260     memory_region_transaction_commit();
 261 }
 262
 263 /* SMRAM */
 264 static void mch_update_smram(MCHPCIState *mch)
 265 {
 266     PCIDevice *pd = PCI_DEVICE(mch);
 267
 268     memory_region_transaction_begin();
 269     smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
 270                     mch->smm_enabled);
 271     memory_region_transaction_commit();
 272 }
 273
 274 static void mch_set_smm(int smm, void *arg)
 275 {
 276     MCHPCIState *mch = arg;
 277     PCIDevice *pd = PCI_DEVICE(mch);
 278
 279     memory_region_transaction_begin();
 280     smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
 281                     &mch->smram_region);
 282     memory_region_transaction_commit();
 283 }
 284
 285 static void mch_write_config(PCIDevice *d,
 286                               uint32_t address, uint32_t val, int len)
 287 {
 288     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 289
 290     /* XXX: implement SMRAM.D_LOCK */
 291     pci_default_write_config(d, address, val, len);
 292
 293     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
 294                        MCH_HOST_BRIDGE_PAM_SIZE)) {
 295         mch_update_pam(mch);
 296     }
 297
 298     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
 299                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
 300         mch_update_pciexbar(mch);
 301     }
 302
 303     if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
 304                        MCH_HOST_BRDIGE_SMRAM_SIZE)) {
 305         mch_update_smram(mch);
 306     }
 307 }
 308
 309 static void mch_update(MCHPCIState *mch)
 310 {
 311     mch_update_pciexbar(mch);
 312     mch_update_pam(mch);
 313     mch_update_smram(mch);
 314 }
 315
 316 static int mch_post_load(void *opaque, int version_id)
 317 {
 318     MCHPCIState *mch = opaque;
 319     mch_update(mch);
 320     return 0;
 321 }
 322
 323 static const VMStateDescription vmstate_mch = {
 324     .name = "mch",
 325     .version_id = 1,
 326     .minimum_version_id = 1,
 327     .minimum_version_id_old = 1,
 328     .post_load = mch_post_load,
 329     .fields = (VMStateField []) {
 330         VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
 331         VMSTATE_UINT8(smm_enabled, MCHPCIState),
 332         VMSTATE_END_OF_LIST()
 333     }
 334 };
 335
 336 static void mch_reset(DeviceState *qdev)
 337 {
 338     PCIDevice *d = PCI_DEVICE(qdev);
 339     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 340
 341     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
 342                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
 343
 344     d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
 345
 346     mch_update(mch);
 347 }
 348
 349 static int mch_init(PCIDevice *d)
 350 {
 351     int i;
 352     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 353     uint64_t pci_hole64_size;
 354
 355     /* setup pci memory regions */
 356     memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole",
 357                              mch->pci_address_space,
 358                              mch->below_4g_mem_size,
 359                              0x100000000ULL - mch->below_4g_mem_size);
 360     memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
 361                                 &mch->pci_hole);
 362
 363     pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size);
 364     pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size,
 365                        pci_hole64_size);
 366     memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64",
 367                              mch->pci_address_space,
 368                              mch->pci_info.w64.begin,
 369                              pci_hole64_size);
 370     if (pci_hole64_size) {
 371         memory_region_add_subregion(mch->system_memory,
 372                                     mch->pci_info.w64.begin,
 373                                     &mch->pci_hole_64bit);
 374     }
 375     /* smram */
 376     cpu_smm_register(&mch_set_smm, mch);
 377     memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
 378                              mch->pci_address_space, 0xa0000, 0x20000);
 379     memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
 380                                         &mch->smram_region, 1);
 381     memory_region_set_enabled(&mch->smram_region, false);
 382     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
 383              &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 384     for (i = 0; i < 12; ++i) {
 385         init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space,
 386                  &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 387                  PAM_EXPAN_SIZE);
 388     }
 389     return 0;
 390 }
 391
 392 uint64_t mch_mcfg_base(void)
 393 {
 394     bool ambiguous;
 395     Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
 396     if (!o) {
 397         return 0;
 398     }
 399     return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
 400 }
 401
 402 static void mch_class_init(ObjectClass *klass, void *data)
 403 {
 404     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 405     DeviceClass *dc = DEVICE_CLASS(klass);
 406
 407     k->init = mch_init;
 408     k->config_write = mch_write_config;
 409     dc->reset = mch_reset;
 410     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 411     dc->desc = "Host bridge";
 412     dc->vmsd = &vmstate_mch;
 413     k->vendor_id = PCI_VENDOR_ID_INTEL;
 414     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
 415     k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
 416     k->class_id = PCI_CLASS_BRIDGE_HOST;
 417 }
 418
 419 static const TypeInfo mch_info = {
 420     .name = TYPE_MCH_PCI_DEVICE,
 421     .parent = TYPE_PCI_DEVICE,
 422     .instance_size = sizeof(MCHPCIState),
 423     .class_init = mch_class_init,
 424 };
 425
 426 static void q35_register(void)
 427 {
 428     type_register_static(&mch_info);
 429     type_register_static(&q35_host_info);
 430 }
 431
 432 type_init(q35_register);