hw/etraxfs_eth.c

   1 /*
   2  * QEMU ETRAX Ethernet Controller.
   3  *
   4  * Copyright (c) 2008 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include "hw.h"
  27 #include "net.h"
  28
  29 #include "etraxfs_dma.h"
  30
  31 #define D(x)
  32
  33 /* Advertisement control register. */
  34 #define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
  35 #define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
  36 #define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
  37 #define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
  38
  39 /*
  40  * The MDIO extensions in the TDK PHY model were reversed engineered from the
  41  * linux driver (PHYID and Diagnostics reg).
  42  * TODO: Add friendly names for the register nums.
  43  */
  44 struct qemu_phy
  45 {
  46         uint32_t regs[32];
  47
  48         unsigned int (*read)(struct qemu_phy *phy, unsigned int req);
  49         void (*write)(struct qemu_phy *phy, unsigned int req,
  50                       unsigned int data);
  51 };
  52
  53 static unsigned int tdk_read(struct qemu_phy *phy, unsigned int req)
  54 {
  55         int regnum;
  56         unsigned r = 0;
  57
  58         regnum = req & 0x1f;
  59
  60         switch (regnum) {
  61                 case 1:
  62                         /* MR1.  */
  63                         /* Speeds and modes.  */
  64                         r |= (1 << 13) | (1 << 14);
  65                         r |= (1 << 11) | (1 << 12);
  66                         r |= (1 << 5); /* Autoneg complete.  */
  67                         r |= (1 << 3); /* Autoneg able.  */
  68                         r |= (1 << 2); /* Link.  */
  69                         break;
  70                 case 5:
  71                         /* Link partner ability.
  72                            We are kind; always agree with whatever best mode
  73                            the guest advertises.  */
  74                         r = 1 << 14; /* Success.  */
  75                         /* Copy advertised modes.  */
  76                         r |= phy->regs[4] & (15 << 5);
  77                         /* Autoneg support.  */
  78                         r |= 1;
  79                         break;
  80                 case 18:
  81                 {
  82                         /* Diagnostics reg.  */
  83                         int duplex = 0;
  84                         int speed_100 = 0;
  85
  86                         /* Are we advertising 100 half or 100 duplex ? */
  87                         speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
  88                         speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
  89
  90                         /* Are we advertising 10 duplex or 100 duplex ? */
  91                         duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
  92                         duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
  93                         r = (speed_100 << 10) | (duplex << 11);
  94                 }
  95                 break;
  96
  97                 default:
  98                         r = phy->regs[regnum];
  99                         break;
 100         }
 101         D(printf("\n%s %x = reg[%d]\n", __func__, r, regnum));
 102         return r;
 103 }
 104
 105 static void
 106 tdk_write(struct qemu_phy *phy, unsigned int req, unsigned int data)
 107 {
 108         int regnum;
 109
 110         regnum = req & 0x1f;
 111         D(printf("%s reg[%d] = %x\n", __func__, regnum, data));
 112         switch (regnum) {
 113                 default:
 114                         phy->regs[regnum] = data;
 115                         break;
 116         }
 117 }
 118
 119 static void
 120 tdk_init(struct qemu_phy *phy)
 121 {
 122         phy->regs[0] = 0x3100;
 123         /* PHY Id.  */
 124         phy->regs[2] = 0x0300;
 125         phy->regs[3] = 0xe400;
 126         /* Autonegotiation advertisement reg.  */
 127         phy->regs[4] = 0x01E1;
 128
 129         phy->read = tdk_read;
 130         phy->write = tdk_write;
 131 }
 132
 133 struct qemu_mdio
 134 {
 135         /* bus.  */
 136         int mdc;
 137         int mdio;
 138
 139         /* decoder.  */
 140         enum {
 141                 PREAMBLE,
 142                 SOF,
 143                 OPC,
 144                 ADDR,
 145                 REQ,
 146                 TURNAROUND,
 147                 DATA
 148         } state;
 149         unsigned int drive;
 150
 151         unsigned int cnt;
 152         unsigned int addr;
 153         unsigned int opc;
 154         unsigned int req;
 155         unsigned int data;
 156
 157         struct qemu_phy *devs[32];
 158 };
 159
 160 static void
 161 mdio_attach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
 162 {
 163         bus->devs[addr & 0x1f] = phy;
 164 }
 165
 166 #ifdef USE_THIS_DEAD_CODE
 167 static void
 168 mdio_detach(struct qemu_mdio *bus, struct qemu_phy *phy, unsigned int addr)
 169 {
 170         bus->devs[addr & 0x1f] = NULL;
 171 }
 172 #endif
 173
 174 static void mdio_read_req(struct qemu_mdio *bus)
 175 {
 176         struct qemu_phy *phy;
 177
 178         phy = bus->devs[bus->addr];
 179         if (phy && phy->read)
 180                 bus->data = phy->read(phy, bus->req);
 181         else
 182                 bus->data = 0xffff;
 183 }
 184
 185 static void mdio_write_req(struct qemu_mdio *bus)
 186 {
 187         struct qemu_phy *phy;
 188
 189         phy = bus->devs[bus->addr];
 190         if (phy && phy->write)
 191                 phy->write(phy, bus->req, bus->data);
 192 }
 193
 194 static void mdio_cycle(struct qemu_mdio *bus)
 195 {
 196         bus->cnt++;
 197
 198         D(printf("mdc=%d mdio=%d state=%d cnt=%d drv=%d\n",
 199                 bus->mdc, bus->mdio, bus->state, bus->cnt, bus->drive));
 200 #if 0
 201         if (bus->mdc)
 202                 printf("%d", bus->mdio);
 203 #endif
 204         switch (bus->state)
 205         {
 206                 case PREAMBLE:
 207                         if (bus->mdc) {
 208                                 if (bus->cnt >= (32 * 2) && !bus->mdio) {
 209                                         bus->cnt = 0;
 210                                         bus->state = SOF;
 211                                         bus->data = 0;
 212                                 }
 213                         }
 214                         break;
 215                 case SOF:
 216                         if (bus->mdc) {
 217                                 if (bus->mdio != 1)
 218                                         printf("WARNING: no SOF\n");
 219                                 if (bus->cnt == 1*2) {
 220                                         bus->cnt = 0;
 221                                         bus->opc = 0;
 222                                         bus->state = OPC;
 223                                 }
 224                         }
 225                         break;
 226                 case OPC:
 227                         if (bus->mdc) {
 228                                 bus->opc <<= 1;
 229                                 bus->opc |= bus->mdio & 1;
 230                                 if (bus->cnt == 2*2) {
 231                                         bus->cnt = 0;
 232                                         bus->addr = 0;
 233                                         bus->state = ADDR;
 234                                 }
 235                         }
 236                         break;
 237                 case ADDR:
 238                         if (bus->mdc) {
 239                                 bus->addr <<= 1;
 240                                 bus->addr |= bus->mdio & 1;
 241
 242                                 if (bus->cnt == 5*2) {
 243                                         bus->cnt = 0;
 244                                         bus->req = 0;
 245                                         bus->state = REQ;
 246                                 }
 247                         }
 248                         break;
 249                 case REQ:
 250                         if (bus->mdc) {
 251                                 bus->req <<= 1;
 252                                 bus->req |= bus->mdio & 1;
 253                                 if (bus->cnt == 5*2) {
 254                                         bus->cnt = 0;
 255                                         bus->state = TURNAROUND;
 256                                 }
 257                         }
 258                         break;
 259                 case TURNAROUND:
 260                         if (bus->mdc && bus->cnt == 2*2) {
 261                                 bus->mdio = 0;
 262                                 bus->cnt = 0;
 263
 264                                 if (bus->opc == 2) {
 265                                         bus->drive = 1;
 266                                         mdio_read_req(bus);
 267                                         bus->mdio = bus->data & 1;
 268                                 }
 269                                 bus->state = DATA;
 270                         }
 271                         break;
 272                 case DATA:
 273                         if (!bus->mdc) {
 274                                 if (bus->drive) {
 275                                         bus->mdio = !!(bus->data & (1 << 15));
 276                                         bus->data <<= 1;
 277                                 }
 278                         } else {
 279                                 if (!bus->drive) {
 280                                         bus->data <<= 1;
 281                                         bus->data |= bus->mdio;
 282                                 }
 283                                 if (bus->cnt == 16 * 2) {
 284                                         bus->cnt = 0;
 285                                         bus->state = PREAMBLE;
 286                                         if (!bus->drive)
 287                                                 mdio_write_req(bus);
 288                                         bus->drive = 0;
 289                                 }
 290                         }
 291                         break;
 292                 default:
 293                         break;
 294         }
 295 }
 296
 297 /* ETRAX-FS Ethernet MAC block starts here.  */
 298
 299 #define RW_MA0_LO         0x00
 300 #define RW_MA0_HI         0x01
 301 #define RW_MA1_LO         0x02
 302 #define RW_MA1_HI         0x03
 303 #define RW_GA_LO          0x04
 304 #define RW_GA_HI          0x05
 305 #define RW_GEN_CTRL       0x06
 306 #define RW_REC_CTRL       0x07
 307 #define RW_TR_CTRL        0x08
 308 #define RW_CLR_ERR        0x09
 309 #define RW_MGM_CTRL       0x0a
 310 #define R_STAT            0x0b
 311 #define FS_ETH_MAX_REGS   0x17
 312
 313 struct fs_eth
 314 {
 315         CPUState *env;
 316         qemu_irq *irq;
 317         VLANClientState *vc;
 318         int ethregs;
 319
 320         /* Two addrs in the filter.  */
 321         uint8_t macaddr[2][6];
 322         uint32_t regs[FS_ETH_MAX_REGS];
 323
 324         struct etraxfs_dma_client *dma_out;
 325         struct etraxfs_dma_client *dma_in;
 326
 327         /* MDIO bus.  */
 328         struct qemu_mdio mdio_bus;
 329         unsigned int phyaddr;
 330         int duplex_mismatch;
 331
 332         /* PHY.  */
 333         struct qemu_phy phy;
 334 };
 335
 336 static void eth_validate_duplex(struct fs_eth *eth)
 337 {
 338         struct qemu_phy *phy;
 339         unsigned int phy_duplex;
 340         unsigned int mac_duplex;
 341         int new_mm = 0;
 342
 343         phy = eth->mdio_bus.devs[eth->phyaddr];
 344         phy_duplex = !!(phy->read(phy, 18) & (1 << 11));
 345         mac_duplex = !!(eth->regs[RW_REC_CTRL] & 128);
 346
 347         if (mac_duplex != phy_duplex)
 348                 new_mm = 1;
 349
 350         if (eth->regs[RW_GEN_CTRL] & 1) {
 351                 if (new_mm != eth->duplex_mismatch) {
 352                         if (new_mm)
 353                                 printf("HW: WARNING "
 354                                        "ETH duplex mismatch MAC=%d PHY=%d\n",
 355                                        mac_duplex, phy_duplex);
 356                         else
 357                                 printf("HW: ETH duplex ok.\n");
 358                 }
 359                 eth->duplex_mismatch = new_mm;
 360         }
 361 }
 362
 363 static uint32_t eth_readl (void *opaque, target_phys_addr_t addr)
 364 {
 365         struct fs_eth *eth = opaque;
 366         uint32_t r = 0;
 367
 368         addr >>= 2;
 369
 370         switch (addr) {
 371                 case R_STAT:
 372                         r = eth->mdio_bus.mdio & 1;
 373                         break;
 374         default:
 375                 r = eth->regs[addr];
 376                 D(printf ("%s %x\n", __func__, addr * 4));
 377                 break;
 378         }
 379         return r;
 380 }
 381
 382 static void eth_update_ma(struct fs_eth *eth, int ma)
 383 {
 384         int reg;
 385         int i = 0;
 386
 387         ma &= 1;
 388
 389         reg = RW_MA0_LO;
 390         if (ma)
 391                 reg = RW_MA1_LO;
 392
 393         eth->macaddr[ma][i++] = eth->regs[reg];
 394         eth->macaddr[ma][i++] = eth->regs[reg] >> 8;
 395         eth->macaddr[ma][i++] = eth->regs[reg] >> 16;
 396         eth->macaddr[ma][i++] = eth->regs[reg] >> 24;
 397         eth->macaddr[ma][i++] = eth->regs[reg + 4];
 398         eth->macaddr[ma][i++] = eth->regs[reg + 4] >> 8;
 399
 400         D(printf("set mac%d=%x.%x.%x.%x.%x.%x\n", ma,
 401                  eth->macaddr[ma][0], eth->macaddr[ma][1],
 402                  eth->macaddr[ma][2], eth->macaddr[ma][3],
 403                  eth->macaddr[ma][4], eth->macaddr[ma][5]));
 404 }
 405
 406 static void
 407 eth_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 408 {
 409         struct fs_eth *eth = opaque;
 410
 411         addr >>= 2;
 412         switch (addr)
 413         {
 414                 case RW_MA0_LO:
 415                 case RW_MA0_HI:
 416                         eth->regs[addr] = value;
 417                         eth_update_ma(eth, 0);
 418                         break;
 419                 case RW_MA1_LO:
 420                 case RW_MA1_HI:
 421                         eth->regs[addr] = value;
 422                         eth_update_ma(eth, 1);
 423                         break;
 424
 425                 case RW_MGM_CTRL:
 426                         /* Attach an MDIO/PHY abstraction.  */
 427                         if (value & 2)
 428                                 eth->mdio_bus.mdio = value & 1;
 429                         if (eth->mdio_bus.mdc != (value & 4)) {
 430                                 mdio_cycle(&eth->mdio_bus);
 431                                 eth_validate_duplex(eth);
 432                         }
 433                         eth->mdio_bus.mdc = !!(value & 4);
 434                         break;
 435
 436                 case RW_REC_CTRL:
 437                         eth->regs[addr] = value;
 438                         eth_validate_duplex(eth);
 439                         break;
 440
 441                 default:
 442                         eth->regs[addr] = value;
 443                         D(printf ("%s %x %x\n",
 444                                   __func__, addr, value));
 445                         break;
 446         }
 447 }
 448
 449 /* The ETRAX FS has a groupt address table (GAT) which works like a k=1 bloom
 450    filter dropping group addresses we have not joined.  The filter has 64
 451    bits (m). The has function is a simple nible xor of the group addr.  */
 452 static int eth_match_groupaddr(struct fs_eth *eth, const unsigned char *sa)
 453 {
 454         unsigned int hsh;
 455         int m_individual = eth->regs[RW_REC_CTRL] & 4;
 456         int match;
 457
 458         /* First bit on the wire of a MAC address signals multicast or
 459            physical address.  */
 460         if (!m_individual && !sa[0] & 1)
 461                 return 0;
 462
 463         /* Calculate the hash index for the GA registers. */
 464         hsh = 0;
 465         hsh ^= (*sa) & 0x3f;
 466         hsh ^= ((*sa) >> 6) & 0x03;
 467         ++sa;
 468         hsh ^= ((*sa) << 2) & 0x03c;
 469         hsh ^= ((*sa) >> 4) & 0xf;
 470         ++sa;
 471         hsh ^= ((*sa) << 4) & 0x30;
 472         hsh ^= ((*sa) >> 2) & 0x3f;
 473         ++sa;
 474         hsh ^= (*sa) & 0x3f;
 475         hsh ^= ((*sa) >> 6) & 0x03;
 476         ++sa;
 477         hsh ^= ((*sa) << 2) & 0x03c;
 478         hsh ^= ((*sa) >> 4) & 0xf;
 479         ++sa;
 480         hsh ^= ((*sa) << 4) & 0x30;
 481         hsh ^= ((*sa) >> 2) & 0x3f;
 482
 483         hsh &= 63;
 484         if (hsh > 31)
 485                 match = eth->regs[RW_GA_HI] & (1 << (hsh - 32));
 486         else
 487                 match = eth->regs[RW_GA_LO] & (1 << hsh);
 488         D(printf("hsh=%x ga=%x.%x mtch=%d\n", hsh,
 489                  eth->regs[RW_GA_HI], eth->regs[RW_GA_LO], match));
 490         return match;
 491 }
 492
 493 static int eth_can_receive(void *opaque)
 494 {
 495         return 1;
 496 }
 497
 498 static void eth_receive(void *opaque, const uint8_t *buf, int size)
 499 {
 500         unsigned char sa_bcast[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 501         struct fs_eth *eth = opaque;
 502         int use_ma0 = eth->regs[RW_REC_CTRL] & 1;
 503         int use_ma1 = eth->regs[RW_REC_CTRL] & 2;
 504         int r_bcast = eth->regs[RW_REC_CTRL] & 8;
 505
 506         if (size < 12)
 507                 return;
 508
 509         D(printf("%x.%x.%x.%x.%x.%x ma=%d %d bc=%d\n",
 510                  buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
 511                  use_ma0, use_ma1, r_bcast));
 512
 513         /* Does the frame get through the address filters?  */
 514         if ((!use_ma0 || memcmp(buf, eth->macaddr[0], 6))
 515             && (!use_ma1 || memcmp(buf, eth->macaddr[1], 6))
 516             && (!r_bcast || memcmp(buf, sa_bcast, 6))
 517             && !eth_match_groupaddr(eth, buf))
 518                 return;
 519
 520         /* FIXME: Find another way to pass on the fake csum.  */
 521         etraxfs_dmac_input(eth->dma_in, (void *)buf, size + 4, 1);
 522 }
 523
 524 static int eth_tx_push(void *opaque, unsigned char *buf, int len)
 525 {
 526         struct fs_eth *eth = opaque;
 527
 528         D(printf("%s buf=%p len=%d\n", __func__, buf, len));
 529         qemu_send_packet(eth->vc, buf, len);
 530         return len;
 531 }
 532
 533 static CPUReadMemoryFunc *eth_read[] = {
 534         NULL, NULL,
 535         &eth_readl,
 536 };
 537
 538 static CPUWriteMemoryFunc *eth_write[] = {
 539         NULL, NULL,
 540         &eth_writel,
 541 };
 542
 543 void *etraxfs_eth_init(NICInfo *nd, CPUState *env,
 544                        qemu_irq *irq, target_phys_addr_t base)
 545 {
 546         struct etraxfs_dma_client *dma = NULL;
 547         struct fs_eth *eth = NULL;
 548
 549         dma = qemu_mallocz(sizeof *dma * 2);
 550         if (!dma)
 551                 return NULL;
 552
 553         eth = qemu_mallocz(sizeof *eth);
 554         if (!eth)
 555                 goto err;
 556
 557         dma[0].client.push = eth_tx_push;
 558         dma[0].client.opaque = eth;
 559         dma[1].client.opaque = eth;
 560         dma[1].client.pull = NULL;
 561
 562         eth->env = env;
 563         eth->irq = irq;
 564         eth->dma_out = dma;
 565         eth->dma_in = dma + 1;
 566
 567         /* Connect the phy.  */
 568         eth->phyaddr = 1;
 569         tdk_init(&eth->phy);
 570         mdio_attach(&eth->mdio_bus, &eth->phy, eth->phyaddr);
 571
 572         eth->ethregs = cpu_register_io_memory(0, eth_read, eth_write, eth);
 573         cpu_register_physical_memory (base, 0x5c, eth->ethregs);
 574
 575         eth->vc = qemu_new_vlan_client(nd->vlan, nd->model,
 576                                        eth_receive, eth_can_receive, eth);
 577
 578         return dma;
 579   err:
 580         qemu_free(eth);
 581         qemu_free(dma);
 582         return NULL;
 583 }