target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "sysemu/kvm.h"
  26 #include "sysemu/cpus.h"
  27 #include "kvm_i386.h"
  28 #include "topology.h"
  29
  30 #include "qemu/option.h"
  31 #include "qemu/config-file.h"
  32 #include "qapi/qmp/qerror.h"
  33
  34 #include "qapi-types.h"
  35 #include "qapi-visit.h"
  36 #include "qapi/visitor.h"
  37 #include "sysemu/arch_init.h"
  38
  39 #include "hw/hw.h"
  40 #if defined(CONFIG_KVM)
  41 #include <linux/kvm_para.h>
  42 #endif
  43
  44 #include "sysemu/sysemu.h"
  45 #include "hw/qdev-properties.h"
  46 #include "hw/cpu/icc_bus.h"
  47 #ifndef CONFIG_USER_ONLY
  48 #include "hw/xen/xen.h"
  49 #include "hw/i386/apic_internal.h"
  50 #endif
  51
  52
  53 /* Cache topology CPUID constants: */
  54
  55 /* CPUID Leaf 2 Descriptors */
  56
  57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
  58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
  59 #define CPUID_2_L2_2MB_8WAY_64B   0x7d
  60
  61
  62 /* CPUID Leaf 4 constants: */
  63
  64 /* EAX: */
  65 #define CPUID_4_TYPE_DCACHE  1
  66 #define CPUID_4_TYPE_ICACHE  2
  67 #define CPUID_4_TYPE_UNIFIED 3
  68
  69 #define CPUID_4_LEVEL(l)          ((l) << 5)
  70
  71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
  72 #define CPUID_4_FULLY_ASSOC     (1 << 9)
  73
  74 /* EDX: */
  75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
  76 #define CPUID_4_INCLUSIVE       (1 << 1)
  77 #define CPUID_4_COMPLEX_IDX     (1 << 2)
  78
  79 #define ASSOC_FULL 0xFF
  80
  81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
  82 #define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
  83                           a ==   2 ? 0x2 : \
  84                           a ==   4 ? 0x4 : \
  85                           a ==   8 ? 0x6 : \
  86                           a ==  16 ? 0x8 : \
  87                           a ==  32 ? 0xA : \
  88                           a ==  48 ? 0xB : \
  89                           a ==  64 ? 0xC : \
  90                           a ==  96 ? 0xD : \
  91                           a == 128 ? 0xE : \
  92                           a == ASSOC_FULL ? 0xF : \
  93                           0 /* invalid value */)
  94
  95
  96 /* Definitions of the hardcoded cache entries we expose: */
  97
  98 /* L1 data cache: */
  99 #define L1D_LINE_SIZE         64
 100 #define L1D_ASSOCIATIVITY      8
 101 #define L1D_SETS              64
 102 #define L1D_PARTITIONS         1
 103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
 105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 106 #define L1D_LINES_PER_TAG      1
 107 #define L1D_SIZE_KB_AMD       64
 108 #define L1D_ASSOCIATIVITY_AMD  2
 109
 110 /* L1 instruction cache: */
 111 #define L1I_LINE_SIZE         64
 112 #define L1I_ASSOCIATIVITY      8
 113 #define L1I_SETS              64
 114 #define L1I_PARTITIONS         1
 115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
 117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 118 #define L1I_LINES_PER_TAG      1
 119 #define L1I_SIZE_KB_AMD       64
 120 #define L1I_ASSOCIATIVITY_AMD  2
 121
 122 /* Level 2 unified cache: */
 123 #define L2_LINE_SIZE          64
 124 #define L2_ASSOCIATIVITY      16
 125 #define L2_SETS             4096
 126 #define L2_PARTITIONS          1
 127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
 128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
 129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
 130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
 131 #define L2_LINES_PER_TAG       1
 132 #define L2_SIZE_KB_AMD       512
 133
 134 /* No L3 cache: */
 135 #define L3_SIZE_KB             0 /* disabled */
 136 #define L3_ASSOCIATIVITY       0 /* disabled */
 137 #define L3_LINES_PER_TAG       0 /* disabled */
 138 #define L3_LINE_SIZE           0 /* disabled */
 139
 140 /* TLB definitions: */
 141
 142 #define L1_DTLB_2M_ASSOC       1
 143 #define L1_DTLB_2M_ENTRIES   255
 144 #define L1_DTLB_4K_ASSOC       1
 145 #define L1_DTLB_4K_ENTRIES   255
 146
 147 #define L1_ITLB_2M_ASSOC       1
 148 #define L1_ITLB_2M_ENTRIES   255
 149 #define L1_ITLB_4K_ASSOC       1
 150 #define L1_ITLB_4K_ENTRIES   255
 151
 152 #define L2_DTLB_2M_ASSOC       0 /* disabled */
 153 #define L2_DTLB_2M_ENTRIES     0 /* disabled */
 154 #define L2_DTLB_4K_ASSOC       4
 155 #define L2_DTLB_4K_ENTRIES   512
 156
 157 #define L2_ITLB_2M_ASSOC       0 /* disabled */
 158 #define L2_ITLB_2M_ENTRIES     0 /* disabled */
 159 #define L2_ITLB_4K_ASSOC       4
 160 #define L2_ITLB_4K_ENTRIES   512
 161
 162
 163
 164 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 165                                      uint32_t vendor2, uint32_t vendor3)
 166 {
 167     int i;
 168     for (i = 0; i < 4; i++) {
 169         dst[i] = vendor1 >> (8 * i);
 170         dst[i + 4] = vendor2 >> (8 * i);
 171         dst[i + 8] = vendor3 >> (8 * i);
 172     }
 173     dst[CPUID_VENDOR_SZ] = '\0';
 174 }
 175
 176 /* feature flags taken from "Intel Processor Identification and the CPUID
 177  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
 178  * between feature naming conventions, aliases may be added.
 179  */
 180 static const char *feature_name[] = {
 181     "fpu", "vme", "de", "pse",
 182     "tsc", "msr", "pae", "mce",
 183     "cx8", "apic", NULL, "sep",
 184     "mtrr", "pge", "mca", "cmov",
 185     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
 186     NULL, "ds" /* Intel dts */, "acpi", "mmx",
 187     "fxsr", "sse", "sse2", "ss",
 188     "ht" /* Intel htt */, "tm", "ia64", "pbe",
 189 };
 190 static const char *ext_feature_name[] = {
 191     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
 192     "ds_cpl", "vmx", "smx", "est",
 193     "tm2", "ssse3", "cid", NULL,
 194     "fma", "cx16", "xtpr", "pdcm",
 195     NULL, "pcid", "dca", "sse4.1|sse4_1",
 196     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
 197     "tsc-deadline", "aes", "xsave", "osxsave",
 198     "avx", "f16c", "rdrand", "hypervisor",
 199 };
 200 /* Feature names that are already defined on feature_name[] but are set on
 201  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
 202  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
 203  * if and only if CPU vendor is AMD.
 204  */
 205 static const char *ext2_feature_name[] = {
 206     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
 207     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
 208     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
 209     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
 210     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
 211     "nx|xd", NULL, "mmxext", NULL /* mmx */,
 212     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
 213     NULL, "lm|i64", "3dnowext", "3dnow",
 214 };
 215 static const char *ext3_feature_name[] = {
 216     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
 217     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
 218     "3dnowprefetch", "osvw", "ibs", "xop",
 219     "skinit", "wdt", NULL, "lwp",
 220     "fma4", "tce", NULL, "nodeid_msr",
 221     NULL, "tbm", "topoext", "perfctr_core",
 222     "perfctr_nb", NULL, NULL, NULL,
 223     NULL, NULL, NULL, NULL,
 224 };
 225
 226 static const char *ext4_feature_name[] = {
 227     NULL, NULL, "xstore", "xstore-en",
 228     NULL, NULL, "xcrypt", "xcrypt-en",
 229     "ace2", "ace2-en", "phe", "phe-en",
 230     "pmm", "pmm-en", NULL, NULL,
 231     NULL, NULL, NULL, NULL,
 232     NULL, NULL, NULL, NULL,
 233     NULL, NULL, NULL, NULL,
 234     NULL, NULL, NULL, NULL,
 235 };
 236
 237 static const char *kvm_feature_name[] = {
 238     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 239     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
 240     NULL, NULL, NULL, NULL,
 241     NULL, NULL, NULL, NULL,
 242     NULL, NULL, NULL, NULL,
 243     NULL, NULL, NULL, NULL,
 244     NULL, NULL, NULL, NULL,
 245     NULL, NULL, NULL, NULL,
 246 };
 247
 248 static const char *svm_feature_name[] = {
 249     "npt", "lbrv", "svm_lock", "nrip_save",
 250     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 251     NULL, NULL, "pause_filter", NULL,
 252     "pfthreshold", NULL, NULL, NULL,
 253     NULL, NULL, NULL, NULL,
 254     NULL, NULL, NULL, NULL,
 255     NULL, NULL, NULL, NULL,
 256     NULL, NULL, NULL, NULL,
 257 };
 258
 259 static const char *cpuid_7_0_ebx_feature_name[] = {
 260     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
 261     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
 262     NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
 263     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 264 };
 265
 266 typedef struct FeatureWordInfo {
 267     const char **feat_names;
 268     uint32_t cpuid_eax;   /* Input EAX for CPUID */
 269     bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
 270     uint32_t cpuid_ecx;   /* Input ECX value for CPUID */
 271     int cpuid_reg;        /* output register (R_* constant) */
 272 } FeatureWordInfo;
 273
 274 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 275     [FEAT_1_EDX] = {
 276         .feat_names = feature_name,
 277         .cpuid_eax = 1, .cpuid_reg = R_EDX,
 278     },
 279     [FEAT_1_ECX] = {
 280         .feat_names = ext_feature_name,
 281         .cpuid_eax = 1, .cpuid_reg = R_ECX,
 282     },
 283     [FEAT_8000_0001_EDX] = {
 284         .feat_names = ext2_feature_name,
 285         .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
 286     },
 287     [FEAT_8000_0001_ECX] = {
 288         .feat_names = ext3_feature_name,
 289         .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
 290     },
 291     [FEAT_C000_0001_EDX] = {
 292         .feat_names = ext4_feature_name,
 293         .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
 294     },
 295     [FEAT_KVM] = {
 296         .feat_names = kvm_feature_name,
 297         .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
 298     },
 299     [FEAT_SVM] = {
 300         .feat_names = svm_feature_name,
 301         .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
 302     },
 303     [FEAT_7_0_EBX] = {
 304         .feat_names = cpuid_7_0_ebx_feature_name,
 305         .cpuid_eax = 7,
 306         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
 307         .cpuid_reg = R_EBX,
 308     },
 309 };
 310
 311 typedef struct X86RegisterInfo32 {
 312     /* Name of register */
 313     const char *name;
 314     /* QAPI enum value register */
 315     X86CPURegister32 qapi_enum;
 316 } X86RegisterInfo32;
 317
 318 #define REGISTER(reg) \
 319     [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
 320 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
 321     REGISTER(EAX),
 322     REGISTER(ECX),
 323     REGISTER(EDX),
 324     REGISTER(EBX),
 325     REGISTER(ESP),
 326     REGISTER(EBP),
 327     REGISTER(ESI),
 328     REGISTER(EDI),
 329 };
 330 #undef REGISTER
 331
 332 typedef struct ExtSaveArea {
 333     uint32_t feature, bits;
 334     uint32_t offset, size;
 335 } ExtSaveArea;
 336
 337 static const ExtSaveArea ext_save_areas[] = {
 338     [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
 339             .offset = 0x240, .size = 0x100 },
 340     [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 341             .offset = 0x3c0, .size = 0x40  },
 342     [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 343             .offset = 0x400, .size = 0x40  },
 344 };
 345
 346 const char *get_register_name_32(unsigned int reg)
 347 {
 348     if (reg >= CPU_NB_REGS32) {
 349         return NULL;
 350     }
 351     return x86_reg_info_32[reg].name;
 352 }
 353
 354 /* collects per-function cpuid data
 355  */
 356 typedef struct model_features_t {
 357     uint32_t *guest_feat;
 358     uint32_t *host_feat;
 359     FeatureWord feat_word;
 360 } model_features_t;
 361
 362 /* KVM-specific features that are automatically added to all CPU models
 363  * when KVM is enabled.
 364  */
 365 static uint32_t kvm_default_features[FEATURE_WORDS] = {
 366     [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
 367         (1 << KVM_FEATURE_NOP_IO_DELAY) |
 368         (1 << KVM_FEATURE_CLOCKSOURCE2) |
 369         (1 << KVM_FEATURE_ASYNC_PF) |
 370         (1 << KVM_FEATURE_STEAL_TIME) |
 371         (1 << KVM_FEATURE_PV_EOI) |
 372         (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
 373     [FEAT_1_ECX] = CPUID_EXT_X2APIC,
 374 };
 375
 376 void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
 377 {
 378     kvm_default_features[w] &= ~features;
 379 }
 380
 381 void host_cpuid(uint32_t function, uint32_t count,
 382                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 383 {
 384     uint32_t vec[4];
 385
 386 #ifdef __x86_64__
 387     asm volatile("cpuid"
 388                  : "=a"(vec[0]), "=b"(vec[1]),
 389                    "=c"(vec[2]), "=d"(vec[3])
 390                  : "0"(function), "c"(count) : "cc");
 391 #elif defined(__i386__)
 392     asm volatile("pusha \n\t"
 393                  "cpuid \n\t"
 394                  "mov %%eax, 0(%2) \n\t"
 395                  "mov %%ebx, 4(%2) \n\t"
 396                  "mov %%ecx, 8(%2) \n\t"
 397                  "mov %%edx, 12(%2) \n\t"
 398                  "popa"
 399                  : : "a"(function), "c"(count), "S"(vec)
 400                  : "memory", "cc");
 401 #else
 402     abort();
 403 #endif
 404
 405     if (eax)
 406         *eax = vec[0];
 407     if (ebx)
 408         *ebx = vec[1];
 409     if (ecx)
 410         *ecx = vec[2];
 411     if (edx)
 412         *edx = vec[3];
 413 }
 414
 415 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 416
 417 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 418  * a substring.  ex if !NULL points to the first char after a substring,
 419  * otherwise the string is assumed to sized by a terminating nul.
 420  * Return lexical ordering of *s1:*s2.
 421  */
 422 static int sstrcmp(const char *s1, const char *e1, const char *s2,
 423     const char *e2)
 424 {
 425     for (;;) {
 426         if (!*s1 || !*s2 || *s1 != *s2)
 427             return (*s1 - *s2);
 428         ++s1, ++s2;
 429         if (s1 == e1 && s2 == e2)
 430             return (0);
 431         else if (s1 == e1)
 432             return (*s2);
 433         else if (s2 == e2)
 434             return (*s1);
 435     }
 436 }
 437
 438 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 439  * '|' delimited (possibly empty) strings in which case search for a match
 440  * within the alternatives proceeds left to right.  Return 0 for success,
 441  * non-zero otherwise.
 442  */
 443 static int altcmp(const char *s, const char *e, const char *altstr)
 444 {
 445     const char *p, *q;
 446
 447     for (q = p = altstr; ; ) {
 448         while (*p && *p != '|')
 449             ++p;
 450         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 451             return (0);
 452         if (!*p)
 453             return (1);
 454         else
 455             q = ++p;
 456     }
 457 }
 458
 459 /* search featureset for flag *[s..e), if found set corresponding bit in
 460  * *pval and return true, otherwise return false
 461  */
 462 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 463                            const char **featureset)
 464 {
 465     uint32_t mask;
 466     const char **ppc;
 467     bool found = false;
 468
 469     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 470         if (*ppc && !altcmp(s, e, *ppc)) {
 471             *pval |= mask;
 472             found = true;
 473         }
 474     }
 475     return found;
 476 }
 477
 478 static void add_flagname_to_bitmaps(const char *flagname,
 479                                     FeatureWordArray words)
 480 {
 481     FeatureWord w;
 482     for (w = 0; w < FEATURE_WORDS; w++) {
 483         FeatureWordInfo *wi = &feature_word_info[w];
 484         if (wi->feat_names &&
 485             lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
 486             break;
 487         }
 488     }
 489     if (w == FEATURE_WORDS) {
 490         fprintf(stderr, "CPU feature %s not found\n", flagname);
 491     }
 492 }
 493
 494 /* CPU class name definitions: */
 495
 496 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
 497 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 498
 499 /* Return type name for a given CPU model name
 500  * Caller is responsible for freeing the returned string.
 501  */
 502 static char *x86_cpu_type_name(const char *model_name)
 503 {
 504     return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
 505 }
 506
 507 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
 508 {
 509     ObjectClass *oc;
 510     char *typename;
 511
 512     if (cpu_model == NULL) {
 513         return NULL;
 514     }
 515
 516     typename = x86_cpu_type_name(cpu_model);
 517     oc = object_class_by_name(typename);
 518     g_free(typename);
 519     return oc;
 520 }
 521
 522 struct X86CPUDefinition {
 523     const char *name;
 524     uint32_t level;
 525     uint32_t xlevel;
 526     uint32_t xlevel2;
 527     /* vendor is zero-terminated, 12 character ASCII string */
 528     char vendor[CPUID_VENDOR_SZ + 1];
 529     int family;
 530     int model;
 531     int stepping;
 532     FeatureWordArray features;
 533     char model_id[48];
 534     bool cache_info_passthrough;
 535 };
 536
 537 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 538 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 539           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 540 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 541           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 542           CPUID_PSE36 | CPUID_FXSR)
 543 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 544 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 545           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 546           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 547           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 548
 549 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 550           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 551           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 552           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 553           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
 554           /* partly implemented:
 555           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
 556           CPUID_PSE36 (needed for Solaris) */
 557           /* missing:
 558           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 559 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 560           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 561           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 562           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
 563           /* missing:
 564           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 565           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 566           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 567           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
 568           CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
 569           CPUID_EXT_RDRAND */
 570 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 571           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 572           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
 573           /* missing:
 574           CPUID_EXT2_PDPE1GB */
 575 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 576           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 577 #define TCG_SVM_FEATURES 0
 578 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
 579           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
 580           /* missing:
 581           CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 582           CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 583           CPUID_7_0_EBX_RDSEED */
 584
 585 static X86CPUDefinition builtin_x86_defs[] = {
 586     {
 587         .name = "qemu64",
 588         .level = 4,
 589         .vendor = CPUID_VENDOR_AMD,
 590         .family = 6,
 591         .model = 6,
 592         .stepping = 3,
 593         .features[FEAT_1_EDX] =
 594             PPRO_FEATURES |
 595             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 596             CPUID_PSE36,
 597         .features[FEAT_1_ECX] =
 598             CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
 599         .features[FEAT_8000_0001_EDX] =
 600             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 601             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 602         .features[FEAT_8000_0001_ECX] =
 603             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 604             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 605         .xlevel = 0x8000000A,
 606     },
 607     {
 608         .name = "phenom",
 609         .level = 5,
 610         .vendor = CPUID_VENDOR_AMD,
 611         .family = 16,
 612         .model = 2,
 613         .stepping = 3,
 614         .features[FEAT_1_EDX] =
 615             PPRO_FEATURES |
 616             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 617             CPUID_PSE36 | CPUID_VME | CPUID_HT,
 618         .features[FEAT_1_ECX] =
 619             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 620             CPUID_EXT_POPCNT,
 621         .features[FEAT_8000_0001_EDX] =
 622             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 623             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 624             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 625             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 626         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 627                     CPUID_EXT3_CR8LEG,
 628                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 629                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 630         .features[FEAT_8000_0001_ECX] =
 631             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 632             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 633         .features[FEAT_SVM] =
 634             CPUID_SVM_NPT | CPUID_SVM_LBRV,
 635         .xlevel = 0x8000001A,
 636         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 637     },
 638     {
 639         .name = "core2duo",
 640         .level = 10,
 641         .vendor = CPUID_VENDOR_INTEL,
 642         .family = 6,
 643         .model = 15,
 644         .stepping = 11,
 645         .features[FEAT_1_EDX] =
 646             PPRO_FEATURES |
 647             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 648             CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
 649             CPUID_HT | CPUID_TM | CPUID_PBE,
 650         .features[FEAT_1_ECX] =
 651             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 652             CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
 653             CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 654         .features[FEAT_8000_0001_EDX] =
 655             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 656         .features[FEAT_8000_0001_ECX] =
 657             CPUID_EXT3_LAHF_LM,
 658         .xlevel = 0x80000008,
 659         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 660     },
 661     {
 662         .name = "kvm64",
 663         .level = 5,
 664         .vendor = CPUID_VENDOR_INTEL,
 665         .family = 15,
 666         .model = 6,
 667         .stepping = 1,
 668         /* Missing: CPUID_VME, CPUID_HT */
 669         .features[FEAT_1_EDX] =
 670             PPRO_FEATURES |
 671             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 672             CPUID_PSE36,
 673         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 674         .features[FEAT_1_ECX] =
 675             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 676         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 677         .features[FEAT_8000_0001_EDX] =
 678             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 679             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 680         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 681                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 682                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 683                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 684         .features[FEAT_8000_0001_ECX] =
 685             0,
 686         .xlevel = 0x80000008,
 687         .model_id = "Common KVM processor"
 688     },
 689     {
 690         .name = "qemu32",
 691         .level = 4,
 692         .vendor = CPUID_VENDOR_INTEL,
 693         .family = 6,
 694         .model = 6,
 695         .stepping = 3,
 696         .features[FEAT_1_EDX] =
 697             PPRO_FEATURES,
 698         .features[FEAT_1_ECX] =
 699             CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
 700         .xlevel = 0x80000004,
 701     },
 702     {
 703         .name = "kvm32",
 704         .level = 5,
 705         .vendor = CPUID_VENDOR_INTEL,
 706         .family = 15,
 707         .model = 6,
 708         .stepping = 1,
 709         .features[FEAT_1_EDX] =
 710             PPRO_FEATURES |
 711             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 712         .features[FEAT_1_ECX] =
 713             CPUID_EXT_SSE3,
 714         .features[FEAT_8000_0001_EDX] =
 715             PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
 716         .features[FEAT_8000_0001_ECX] =
 717             0,
 718         .xlevel = 0x80000008,
 719         .model_id = "Common 32-bit KVM processor"
 720     },
 721     {
 722         .name = "coreduo",
 723         .level = 10,
 724         .vendor = CPUID_VENDOR_INTEL,
 725         .family = 6,
 726         .model = 14,
 727         .stepping = 8,
 728         .features[FEAT_1_EDX] =
 729             PPRO_FEATURES | CPUID_VME |
 730             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
 731             CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 732         .features[FEAT_1_ECX] =
 733             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
 734             CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 735         .features[FEAT_8000_0001_EDX] =
 736             CPUID_EXT2_NX,
 737         .xlevel = 0x80000008,
 738         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 739     },
 740     {
 741         .name = "486",
 742         .level = 1,
 743         .vendor = CPUID_VENDOR_INTEL,
 744         .family = 4,
 745         .model = 8,
 746         .stepping = 0,
 747         .features[FEAT_1_EDX] =
 748             I486_FEATURES,
 749         .xlevel = 0,
 750     },
 751     {
 752         .name = "pentium",
 753         .level = 1,
 754         .vendor = CPUID_VENDOR_INTEL,
 755         .family = 5,
 756         .model = 4,
 757         .stepping = 3,
 758         .features[FEAT_1_EDX] =
 759             PENTIUM_FEATURES,
 760         .xlevel = 0,
 761     },
 762     {
 763         .name = "pentium2",
 764         .level = 2,
 765         .vendor = CPUID_VENDOR_INTEL,
 766         .family = 6,
 767         .model = 5,
 768         .stepping = 2,
 769         .features[FEAT_1_EDX] =
 770             PENTIUM2_FEATURES,
 771         .xlevel = 0,
 772     },
 773     {
 774         .name = "pentium3",
 775         .level = 2,
 776         .vendor = CPUID_VENDOR_INTEL,
 777         .family = 6,
 778         .model = 7,
 779         .stepping = 3,
 780         .features[FEAT_1_EDX] =
 781             PENTIUM3_FEATURES,
 782         .xlevel = 0,
 783     },
 784     {
 785         .name = "athlon",
 786         .level = 2,
 787         .vendor = CPUID_VENDOR_AMD,
 788         .family = 6,
 789         .model = 2,
 790         .stepping = 3,
 791         .features[FEAT_1_EDX] =
 792             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 793             CPUID_MCA,
 794         .features[FEAT_8000_0001_EDX] =
 795             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 796             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 797         .xlevel = 0x80000008,
 798     },
 799     {
 800         .name = "n270",
 801         /* original is on level 10 */
 802         .level = 5,
 803         .vendor = CPUID_VENDOR_INTEL,
 804         .family = 6,
 805         .model = 28,
 806         .stepping = 2,
 807         .features[FEAT_1_EDX] =
 808             PPRO_FEATURES |
 809             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
 810             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 811             /* Some CPUs got no CPUID_SEP */
 812         .features[FEAT_1_ECX] =
 813             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 814             CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
 815             CPUID_EXT_MOVBE,
 816         .features[FEAT_8000_0001_EDX] =
 817             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 818             CPUID_EXT2_NX,
 819         .features[FEAT_8000_0001_ECX] =
 820             CPUID_EXT3_LAHF_LM,
 821         .xlevel = 0x8000000A,
 822         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 823     },
 824     {
 825         .name = "Conroe",
 826         .level = 4,
 827         .vendor = CPUID_VENDOR_INTEL,
 828         .family = 6,
 829         .model = 15,
 830         .stepping = 3,
 831         .features[FEAT_1_EDX] =
 832             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 833              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 834              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 835              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 836              CPUID_DE | CPUID_FP87,
 837         .features[FEAT_1_ECX] =
 838             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 839         .features[FEAT_8000_0001_EDX] =
 840             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 841         .features[FEAT_8000_0001_ECX] =
 842             CPUID_EXT3_LAHF_LM,
 843         .xlevel = 0x8000000A,
 844         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 845     },
 846     {
 847         .name = "Penryn",
 848         .level = 4,
 849         .vendor = CPUID_VENDOR_INTEL,
 850         .family = 6,
 851         .model = 23,
 852         .stepping = 3,
 853         .features[FEAT_1_EDX] =
 854             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 855              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 856              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 857              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 858              CPUID_DE | CPUID_FP87,
 859         .features[FEAT_1_ECX] =
 860             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 861              CPUID_EXT_SSE3,
 862         .features[FEAT_8000_0001_EDX] =
 863             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 864         .features[FEAT_8000_0001_ECX] =
 865             CPUID_EXT3_LAHF_LM,
 866         .xlevel = 0x8000000A,
 867         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 868     },
 869     {
 870         .name = "Nehalem",
 871         .level = 4,
 872         .vendor = CPUID_VENDOR_INTEL,
 873         .family = 6,
 874         .model = 26,
 875         .stepping = 3,
 876         .features[FEAT_1_EDX] =
 877             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 878              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 879              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 880              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 881              CPUID_DE | CPUID_FP87,
 882         .features[FEAT_1_ECX] =
 883             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 884              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 885         .features[FEAT_8000_0001_EDX] =
 886             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 887         .features[FEAT_8000_0001_ECX] =
 888             CPUID_EXT3_LAHF_LM,
 889         .xlevel = 0x8000000A,
 890         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 891     },
 892     {
 893         .name = "Westmere",
 894         .level = 11,
 895         .vendor = CPUID_VENDOR_INTEL,
 896         .family = 6,
 897         .model = 44,
 898         .stepping = 1,
 899         .features[FEAT_1_EDX] =
 900             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 901              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 902              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 903              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 904              CPUID_DE | CPUID_FP87,
 905         .features[FEAT_1_ECX] =
 906             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 907              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 908              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 909         .features[FEAT_8000_0001_EDX] =
 910             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 911         .features[FEAT_8000_0001_ECX] =
 912             CPUID_EXT3_LAHF_LM,
 913         .xlevel = 0x8000000A,
 914         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 915     },
 916     {
 917         .name = "SandyBridge",
 918         .level = 0xd,
 919         .vendor = CPUID_VENDOR_INTEL,
 920         .family = 6,
 921         .model = 42,
 922         .stepping = 1,
 923         .features[FEAT_1_EDX] =
 924             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 925              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 926              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 927              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 928              CPUID_DE | CPUID_FP87,
 929         .features[FEAT_1_ECX] =
 930             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 931              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
 932              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 933              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 934              CPUID_EXT_SSE3,
 935         .features[FEAT_8000_0001_EDX] =
 936             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 937              CPUID_EXT2_SYSCALL,
 938         .features[FEAT_8000_0001_ECX] =
 939             CPUID_EXT3_LAHF_LM,
 940         .xlevel = 0x8000000A,
 941         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
 942     },
 943     {
 944         .name = "Haswell",
 945         .level = 0xd,
 946         .vendor = CPUID_VENDOR_INTEL,
 947         .family = 6,
 948         .model = 60,
 949         .stepping = 1,
 950         .features[FEAT_1_EDX] =
 951             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 952              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 953              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 954              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 955              CPUID_DE | CPUID_FP87,
 956         .features[FEAT_1_ECX] =
 957             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 958              CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
 959              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 960              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
 961              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
 962              CPUID_EXT_PCID,
 963         .features[FEAT_8000_0001_EDX] =
 964             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 965              CPUID_EXT2_SYSCALL,
 966         .features[FEAT_8000_0001_ECX] =
 967             CPUID_EXT3_LAHF_LM,
 968         .features[FEAT_7_0_EBX] =
 969             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
 970             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
 971             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
 972             CPUID_7_0_EBX_RTM,
 973         .xlevel = 0x8000000A,
 974         .model_id = "Intel Core Processor (Haswell)",
 975     },
 976     {
 977         .name = "Opteron_G1",
 978         .level = 5,
 979         .vendor = CPUID_VENDOR_AMD,
 980         .family = 15,
 981         .model = 6,
 982         .stepping = 1,
 983         .features[FEAT_1_EDX] =
 984             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 985              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 986              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 987              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 988              CPUID_DE | CPUID_FP87,
 989         .features[FEAT_1_ECX] =
 990             CPUID_EXT_SSE3,
 991         .features[FEAT_8000_0001_EDX] =
 992             CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 993              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 994              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 995              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 996              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 997              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 998         .xlevel = 0x80000008,
 999         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1000     },
1001     {
1002         .name = "Opteron_G2",
1003         .level = 5,
1004         .vendor = CPUID_VENDOR_AMD,
1005         .family = 15,
1006         .model = 6,
1007         .stepping = 1,
1008         .features[FEAT_1_EDX] =
1009             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1010              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1011              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1012              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1013              CPUID_DE | CPUID_FP87,
1014         .features[FEAT_1_ECX] =
1015             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1016         .features[FEAT_8000_0001_EDX] =
1017             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1018              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1019              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1020              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1021              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1022              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1023              CPUID_EXT2_DE | CPUID_EXT2_FPU,
1024         .features[FEAT_8000_0001_ECX] =
1025             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1026         .xlevel = 0x80000008,
1027         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1028     },
1029     {
1030         .name = "Opteron_G3",
1031         .level = 5,
1032         .vendor = CPUID_VENDOR_AMD,
1033         .family = 15,
1034         .model = 6,
1035         .stepping = 1,
1036         .features[FEAT_1_EDX] =
1037             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1038              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1039              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1040              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1041              CPUID_DE | CPUID_FP87,
1042         .features[FEAT_1_ECX] =
1043             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1044              CPUID_EXT_SSE3,
1045         .features[FEAT_8000_0001_EDX] =
1046             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1047              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1048              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1049              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1050              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1051              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1052              CPUID_EXT2_DE | CPUID_EXT2_FPU,
1053         .features[FEAT_8000_0001_ECX] =
1054             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1055              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1056         .xlevel = 0x80000008,
1057         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1058     },
1059     {
1060         .name = "Opteron_G4",
1061         .level = 0xd,
1062         .vendor = CPUID_VENDOR_AMD,
1063         .family = 21,
1064         .model = 1,
1065         .stepping = 2,
1066         .features[FEAT_1_EDX] =
1067             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1068              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1069              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1070              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1071              CPUID_DE | CPUID_FP87,
1072         .features[FEAT_1_ECX] =
1073             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1074              CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1075              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1076              CPUID_EXT_SSE3,
1077         .features[FEAT_8000_0001_EDX] =
1078             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1079              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1080              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1081              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1082              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1083              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1084              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1085         .features[FEAT_8000_0001_ECX] =
1086             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1087              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1088              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1089              CPUID_EXT3_LAHF_LM,
1090         .xlevel = 0x8000001A,
1091         .model_id = "AMD Opteron 62xx class CPU",
1092     },
1093     {
1094         .name = "Opteron_G5",
1095         .level = 0xd,
1096         .vendor = CPUID_VENDOR_AMD,
1097         .family = 21,
1098         .model = 2,
1099         .stepping = 0,
1100         .features[FEAT_1_EDX] =
1101             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1102              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1103              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1104              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1105              CPUID_DE | CPUID_FP87,
1106         .features[FEAT_1_ECX] =
1107             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1108              CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1109              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1110              CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1111         .features[FEAT_8000_0001_EDX] =
1112             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1113              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1114              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1115              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1116              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1117              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1118              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1119         .features[FEAT_8000_0001_ECX] =
1120             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1121              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1122              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1123              CPUID_EXT3_LAHF_LM,
1124         .xlevel = 0x8000001A,
1125         .model_id = "AMD Opteron 63xx class CPU",
1126     },
1127 };
1128
1129 /**
1130  * x86_cpu_compat_set_features:
1131  * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1132  * @w: Identifies the feature word to be changed.
1133  * @feat_add: Feature bits to be added to feature word
1134  * @feat_remove: Feature bits to be removed from feature word
1135  *
1136  * Change CPU model feature bits for compatibility.
1137  *
1138  * This function may be used by machine-type compatibility functions
1139  * to enable or disable feature bits on specific CPU models.
1140  */
1141 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1142                                  uint32_t feat_add, uint32_t feat_remove)
1143 {
1144     X86CPUDefinition *def;
1145     int i;
1146     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1147         def = &builtin_x86_defs[i];
1148         if (!cpu_model || !strcmp(cpu_model, def->name)) {
1149             def->features[w] |= feat_add;
1150             def->features[w] &= ~feat_remove;
1151         }
1152     }
1153 }
1154
1155 #ifdef CONFIG_KVM
1156
1157 static int cpu_x86_fill_model_id(char *str)
1158 {
1159     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1160     int i;
1161
1162     for (i = 0; i < 3; i++) {
1163         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1164         memcpy(str + i * 16 +  0, &eax, 4);
1165         memcpy(str + i * 16 +  4, &ebx, 4);
1166         memcpy(str + i * 16 +  8, &ecx, 4);
1167         memcpy(str + i * 16 + 12, &edx, 4);
1168     }
1169     return 0;
1170 }
1171
1172 static X86CPUDefinition host_cpudef;
1173
1174 /* class_init for the "host" CPU model
1175  *
1176  * This function may be called before KVM is initialized.
1177  */
1178 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1179 {
1180     X86CPUClass *xcc = X86_CPU_CLASS(oc);
1181     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1182
1183     xcc->kvm_required = true;
1184
1185     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1186     x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1187
1188     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1189     host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1190     host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1191     host_cpudef.stepping = eax & 0x0F;
1192
1193     cpu_x86_fill_model_id(host_cpudef.model_id);
1194
1195     xcc->cpu_def = &host_cpudef;
1196     host_cpudef.cache_info_passthrough = true;
1197
1198     /* level, xlevel, xlevel2, and the feature words are initialized on
1199      * instance_init, because they require KVM to be initialized.
1200      */
1201 }
1202
1203 static void host_x86_cpu_initfn(Object *obj)
1204 {
1205     X86CPU *cpu = X86_CPU(obj);
1206     CPUX86State *env = &cpu->env;
1207     KVMState *s = kvm_state;
1208     FeatureWord w;
1209
1210     assert(kvm_enabled());
1211
1212     env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1213     env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1214     env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1215
1216     for (w = 0; w < FEATURE_WORDS; w++) {
1217         FeatureWordInfo *wi = &feature_word_info[w];
1218         env->features[w] =
1219             kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1220                                          wi->cpuid_reg);
1221     }
1222     object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1223 }
1224
1225 static const TypeInfo host_x86_cpu_type_info = {
1226     .name = X86_CPU_TYPE_NAME("host"),
1227     .parent = TYPE_X86_CPU,
1228     .instance_init = host_x86_cpu_initfn,
1229     .class_init = host_x86_cpu_class_init,
1230 };
1231
1232 #endif
1233
1234 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1235 {
1236     int i;
1237
1238     for (i = 0; i < 32; ++i)
1239         if (1 << i & mask) {
1240             const char *reg = get_register_name_32(f->cpuid_reg);
1241             assert(reg);
1242             fprintf(stderr, "warning: host doesn't support requested feature: "
1243                 "CPUID.%02XH:%s%s%s [bit %d]\n",
1244                 f->cpuid_eax, reg,
1245                 f->feat_names[i] ? "." : "",
1246                 f->feat_names[i] ? f->feat_names[i] : "", i);
1247             break;
1248         }
1249     return 0;
1250 }
1251
1252 /* Check if all requested cpu flags are making their way to the guest
1253  *
1254  * Returns 0 if all flags are supported by the host, non-zero otherwise.
1255  *
1256  * This function may be called only if KVM is enabled.
1257  */
1258 static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
1259 {
1260     CPUX86State *env = &cpu->env;
1261     int rv = 0;
1262     FeatureWord w;
1263
1264     assert(kvm_enabled());
1265
1266     for (w = 0; w < FEATURE_WORDS; w++) {
1267         FeatureWordInfo *wi = &feature_word_info[w];
1268         uint32_t guest_feat = env->features[w];
1269         uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1270                                                              wi->cpuid_ecx,
1271                                                              wi->cpuid_reg);
1272         uint32_t mask;
1273         for (mask = 1; mask; mask <<= 1) {
1274             if (guest_feat & mask && !(host_feat & mask)) {
1275                 unavailable_host_feature(wi, mask);
1276                 rv = 1;
1277             }
1278         }
1279     }
1280     return rv;
1281 }
1282
1283 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1284                                          const char *name, Error **errp)
1285 {
1286     X86CPU *cpu = X86_CPU(obj);
1287     CPUX86State *env = &cpu->env;
1288     int64_t value;
1289
1290     value = (env->cpuid_version >> 8) & 0xf;
1291     if (value == 0xf) {
1292         value += (env->cpuid_version >> 20) & 0xff;
1293     }
1294     visit_type_int(v, &value, name, errp);
1295 }
1296
1297 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1298                                          const char *name, Error **errp)
1299 {
1300     X86CPU *cpu = X86_CPU(obj);
1301     CPUX86State *env = &cpu->env;
1302     const int64_t min = 0;
1303     const int64_t max = 0xff + 0xf;
1304     Error *local_err = NULL;
1305     int64_t value;
1306
1307     visit_type_int(v, &value, name, &local_err);
1308     if (local_err) {
1309         error_propagate(errp, local_err);
1310         return;
1311     }
1312     if (value < min || value > max) {
1313         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1314                   name ? name : "null", value, min, max);
1315         return;
1316     }
1317
1318     env->cpuid_version &= ~0xff00f00;
1319     if (value > 0x0f) {
1320         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1321     } else {
1322         env->cpuid_version |= value << 8;
1323     }
1324 }
1325
1326 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1327                                         const char *name, Error **errp)
1328 {
1329     X86CPU *cpu = X86_CPU(obj);
1330     CPUX86State *env = &cpu->env;
1331     int64_t value;
1332
1333     value = (env->cpuid_version >> 4) & 0xf;
1334     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1335     visit_type_int(v, &value, name, errp);
1336 }
1337
1338 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1339                                         const char *name, Error **errp)
1340 {
1341     X86CPU *cpu = X86_CPU(obj);
1342     CPUX86State *env = &cpu->env;
1343     const int64_t min = 0;
1344     const int64_t max = 0xff;
1345     Error *local_err = NULL;
1346     int64_t value;
1347
1348     visit_type_int(v, &value, name, &local_err);
1349     if (local_err) {
1350         error_propagate(errp, local_err);
1351         return;
1352     }
1353     if (value < min || value > max) {
1354         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1355                   name ? name : "null", value, min, max);
1356         return;
1357     }
1358
1359     env->cpuid_version &= ~0xf00f0;
1360     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1361 }
1362
1363 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1364                                            void *opaque, const char *name,
1365                                            Error **errp)
1366 {
1367     X86CPU *cpu = X86_CPU(obj);
1368     CPUX86State *env = &cpu->env;
1369     int64_t value;
1370
1371     value = env->cpuid_version & 0xf;
1372     visit_type_int(v, &value, name, errp);
1373 }
1374
1375 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1376                                            void *opaque, const char *name,
1377                                            Error **errp)
1378 {
1379     X86CPU *cpu = X86_CPU(obj);
1380     CPUX86State *env = &cpu->env;
1381     const int64_t min = 0;
1382     const int64_t max = 0xf;
1383     Error *local_err = NULL;
1384     int64_t value;
1385
1386     visit_type_int(v, &value, name, &local_err);
1387     if (local_err) {
1388         error_propagate(errp, local_err);
1389         return;
1390     }
1391     if (value < min || value > max) {
1392         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1393                   name ? name : "null", value, min, max);
1394         return;
1395     }
1396
1397     env->cpuid_version &= ~0xf;
1398     env->cpuid_version |= value & 0xf;
1399 }
1400
1401 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1402                                 const char *name, Error **errp)
1403 {
1404     X86CPU *cpu = X86_CPU(obj);
1405
1406     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1407 }
1408
1409 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1410                                 const char *name, Error **errp)
1411 {
1412     X86CPU *cpu = X86_CPU(obj);
1413
1414     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1415 }
1416
1417 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1418                                  const char *name, Error **errp)
1419 {
1420     X86CPU *cpu = X86_CPU(obj);
1421
1422     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1423 }
1424
1425 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1426                                  const char *name, Error **errp)
1427 {
1428     X86CPU *cpu = X86_CPU(obj);
1429
1430     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1431 }
1432
1433 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1434 {
1435     X86CPU *cpu = X86_CPU(obj);
1436     CPUX86State *env = &cpu->env;
1437     char *value;
1438
1439     value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1440     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1441                              env->cpuid_vendor3);
1442     return value;
1443 }
1444
1445 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1446                                  Error **errp)
1447 {
1448     X86CPU *cpu = X86_CPU(obj);
1449     CPUX86State *env = &cpu->env;
1450     int i;
1451
1452     if (strlen(value) != CPUID_VENDOR_SZ) {
1453         error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1454                   "vendor", value);
1455         return;
1456     }
1457
1458     env->cpuid_vendor1 = 0;
1459     env->cpuid_vendor2 = 0;
1460     env->cpuid_vendor3 = 0;
1461     for (i = 0; i < 4; i++) {
1462         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1463         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1464         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1465     }
1466 }
1467
1468 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1469 {
1470     X86CPU *cpu = X86_CPU(obj);
1471     CPUX86State *env = &cpu->env;
1472     char *value;
1473     int i;
1474
1475     value = g_malloc(48 + 1);
1476     for (i = 0; i < 48; i++) {
1477         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1478     }
1479     value[48] = '\0';
1480     return value;
1481 }
1482
1483 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1484                                    Error **errp)
1485 {
1486     X86CPU *cpu = X86_CPU(obj);
1487     CPUX86State *env = &cpu->env;
1488     int c, len, i;
1489
1490     if (model_id == NULL) {
1491         model_id = "";
1492     }
1493     len = strlen(model_id);
1494     memset(env->cpuid_model, 0, 48);
1495     for (i = 0; i < 48; i++) {
1496         if (i >= len) {
1497             c = '\0';
1498         } else {
1499             c = (uint8_t)model_id[i];
1500         }
1501         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1502     }
1503 }
1504
1505 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1506                                    const char *name, Error **errp)
1507 {
1508     X86CPU *cpu = X86_CPU(obj);
1509     int64_t value;
1510
1511     value = cpu->env.tsc_khz * 1000;
1512     visit_type_int(v, &value, name, errp);
1513 }
1514
1515 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1516                                    const char *name, Error **errp)
1517 {
1518     X86CPU *cpu = X86_CPU(obj);
1519     const int64_t min = 0;
1520     const int64_t max = INT64_MAX;
1521     Error *local_err = NULL;
1522     int64_t value;
1523
1524     visit_type_int(v, &value, name, &local_err);
1525     if (local_err) {
1526         error_propagate(errp, local_err);
1527         return;
1528     }
1529     if (value < min || value > max) {
1530         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1531                   name ? name : "null", value, min, max);
1532         return;
1533     }
1534
1535     cpu->env.tsc_khz = value / 1000;
1536 }
1537
1538 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1539                                   const char *name, Error **errp)
1540 {
1541     X86CPU *cpu = X86_CPU(obj);
1542     int64_t value = cpu->env.cpuid_apic_id;
1543
1544     visit_type_int(v, &value, name, errp);
1545 }
1546
1547 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1548                                   const char *name, Error **errp)
1549 {
1550     X86CPU *cpu = X86_CPU(obj);
1551     DeviceState *dev = DEVICE(obj);
1552     const int64_t min = 0;
1553     const int64_t max = UINT32_MAX;
1554     Error *error = NULL;
1555     int64_t value;
1556
1557     if (dev->realized) {
1558         error_setg(errp, "Attempt to set property '%s' on '%s' after "
1559                    "it was realized", name, object_get_typename(obj));
1560         return;
1561     }
1562
1563     visit_type_int(v, &value, name, &error);
1564     if (error) {
1565         error_propagate(errp, error);
1566         return;
1567     }
1568     if (value < min || value > max) {
1569         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1570                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1571                    object_get_typename(obj), name, value, min, max);
1572         return;
1573     }
1574
1575     if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1576         error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1577         return;
1578     }
1579     cpu->env.cpuid_apic_id = value;
1580 }
1581
1582 /* Generic getter for "feature-words" and "filtered-features" properties */
1583 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1584                                       const char *name, Error **errp)
1585 {
1586     uint32_t *array = (uint32_t *)opaque;
1587     FeatureWord w;
1588     Error *err = NULL;
1589     X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1590     X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1591     X86CPUFeatureWordInfoList *list = NULL;
1592
1593     for (w = 0; w < FEATURE_WORDS; w++) {
1594         FeatureWordInfo *wi = &feature_word_info[w];
1595         X86CPUFeatureWordInfo *qwi = &word_infos[w];
1596         qwi->cpuid_input_eax = wi->cpuid_eax;
1597         qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1598         qwi->cpuid_input_ecx = wi->cpuid_ecx;
1599         qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1600         qwi->features = array[w];
1601
1602         /* List will be in reverse order, but order shouldn't matter */
1603         list_entries[w].next = list;
1604         list_entries[w].value = &word_infos[w];
1605         list = &list_entries[w];
1606     }
1607
1608     visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1609     error_propagate(errp, err);
1610 }
1611
1612 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1613                                  const char *name, Error **errp)
1614 {
1615     X86CPU *cpu = X86_CPU(obj);
1616     int64_t value = cpu->hyperv_spinlock_attempts;
1617
1618     visit_type_int(v, &value, name, errp);
1619 }
1620
1621 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1622                                  const char *name, Error **errp)
1623 {
1624     const int64_t min = 0xFFF;
1625     const int64_t max = UINT_MAX;
1626     X86CPU *cpu = X86_CPU(obj);
1627     Error *err = NULL;
1628     int64_t value;
1629
1630     visit_type_int(v, &value, name, &err);
1631     if (err) {
1632         error_propagate(errp, err);
1633         return;
1634     }
1635
1636     if (value < min || value > max) {
1637         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1638                   " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1639                   object_get_typename(obj), name ? name : "null",
1640                   value, min, max);
1641         return;
1642     }
1643     cpu->hyperv_spinlock_attempts = value;
1644 }
1645
1646 static PropertyInfo qdev_prop_spinlocks = {
1647     .name  = "int",
1648     .get   = x86_get_hv_spinlocks,
1649     .set   = x86_set_hv_spinlocks,
1650 };
1651
1652 /* Convert all '_' in a feature string option name to '-', to make feature
1653  * name conform to QOM property naming rule, which uses '-' instead of '_'.
1654  */
1655 static inline void feat2prop(char *s)
1656 {
1657     while ((s = strchr(s, '_'))) {
1658         *s = '-';
1659     }
1660 }
1661
1662 /* Parse "+feature,-feature,feature=foo" CPU feature string
1663  */
1664 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1665                                      Error **errp)
1666 {
1667     X86CPU *cpu = X86_CPU(cs);
1668     char *featurestr; /* Single 'key=value" string being parsed */
1669     /* Features to be added */
1670     FeatureWordArray plus_features = { 0 };
1671     /* Features to be removed */
1672     FeatureWordArray minus_features = { 0 };
1673     uint32_t numvalue;
1674     CPUX86State *env = &cpu->env;
1675     Error *local_err = NULL;
1676
1677     featurestr = features ? strtok(features, ",") : NULL;
1678
1679     while (featurestr) {
1680         char *val;
1681         if (featurestr[0] == '+') {
1682             add_flagname_to_bitmaps(featurestr + 1, plus_features);
1683         } else if (featurestr[0] == '-') {
1684             add_flagname_to_bitmaps(featurestr + 1, minus_features);
1685         } else if ((val = strchr(featurestr, '='))) {
1686             *val = 0; val++;
1687             feat2prop(featurestr);
1688             if (!strcmp(featurestr, "xlevel")) {
1689                 char *err;
1690                 char num[32];
1691
1692                 numvalue = strtoul(val, &err, 0);
1693                 if (!*val || *err) {
1694                     error_setg(&local_err, "bad numerical value %s", val);
1695                     goto out;
1696                 }
1697                 if (numvalue < 0x80000000) {
1698                     error_report("xlevel value shall always be >= 0x80000000"
1699                                  ", fixup will be removed in future versions");
1700                     numvalue += 0x80000000;
1701                 }
1702                 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1703                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1704             } else if (!strcmp(featurestr, "tsc-freq")) {
1705                 int64_t tsc_freq;
1706                 char *err;
1707                 char num[32];
1708
1709                 tsc_freq = strtosz_suffix_unit(val, &err,
1710                                                STRTOSZ_DEFSUFFIX_B, 1000);
1711                 if (tsc_freq < 0 || *err) {
1712                     error_setg(&local_err, "bad numerical value %s", val);
1713                     goto out;
1714                 }
1715                 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1716                 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1717                                       &local_err);
1718             } else if (!strcmp(featurestr, "hv-spinlocks")) {
1719                 char *err;
1720                 const int min = 0xFFF;
1721                 char num[32];
1722                 numvalue = strtoul(val, &err, 0);
1723                 if (!*val || *err) {
1724                     error_setg(&local_err, "bad numerical value %s", val);
1725                     goto out;
1726                 }
1727                 if (numvalue < min) {
1728                     error_report("hv-spinlocks value shall always be >= 0x%x"
1729                             ", fixup will be removed in future versions",
1730                             min);
1731                     numvalue = min;
1732                 }
1733                 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1734                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1735             } else {
1736                 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1737             }
1738         } else {
1739             feat2prop(featurestr);
1740             object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1741         }
1742         if (local_err) {
1743             error_propagate(errp, local_err);
1744             goto out;
1745         }
1746         featurestr = strtok(NULL, ",");
1747     }
1748     env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1749     env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1750     env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1751     env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1752     env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1753     env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1754     env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1755     env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1756     env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1757     env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1758     env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1759     env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1760     env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1761     env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1762     env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1763     env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1764
1765 out:
1766     return;
1767 }
1768
1769 /* generate a composite string into buf of all cpuid names in featureset
1770  * selected by fbits.  indicate truncation at bufsize in the event of overflow.
1771  * if flags, suppress names undefined in featureset.
1772  */
1773 static void listflags(char *buf, int bufsize, uint32_t fbits,
1774     const char **featureset, uint32_t flags)
1775 {
1776     const char **p = &featureset[31];
1777     char *q, *b, bit;
1778     int nc;
1779
1780     b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1781     *buf = '\0';
1782     for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1783         if (fbits & 1 << bit && (*p || !flags)) {
1784             if (*p)
1785                 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1786             else
1787                 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1788             if (bufsize <= nc) {
1789                 if (b) {
1790                     memcpy(b, "...", sizeof("..."));
1791                 }
1792                 return;
1793             }
1794             q += nc;
1795             bufsize -= nc;
1796         }
1797 }
1798
1799 /* generate CPU information. */
1800 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1801 {
1802     X86CPUDefinition *def;
1803     char buf[256];
1804     int i;
1805
1806     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1807         def = &builtin_x86_defs[i];
1808         snprintf(buf, sizeof(buf), "%s", def->name);
1809         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1810     }
1811 #ifdef CONFIG_KVM
1812     (*cpu_fprintf)(f, "x86 %16s  %-48s\n", "host",
1813                    "KVM processor with all supported host features "
1814                    "(only available in KVM mode)");
1815 #endif
1816
1817     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1818     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1819         FeatureWordInfo *fw = &feature_word_info[i];
1820
1821         listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1822         (*cpu_fprintf)(f, "  %s\n", buf);
1823     }
1824 }
1825
1826 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1827 {
1828     CpuDefinitionInfoList *cpu_list = NULL;
1829     X86CPUDefinition *def;
1830     int i;
1831
1832     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1833         CpuDefinitionInfoList *entry;
1834         CpuDefinitionInfo *info;
1835
1836         def = &builtin_x86_defs[i];
1837         info = g_malloc0(sizeof(*info));
1838         info->name = g_strdup(def->name);
1839
1840         entry = g_malloc0(sizeof(*entry));
1841         entry->value = info;
1842         entry->next = cpu_list;
1843         cpu_list = entry;
1844     }
1845
1846     return cpu_list;
1847 }
1848
1849 static void filter_features_for_kvm(X86CPU *cpu)
1850 {
1851     CPUX86State *env = &cpu->env;
1852     KVMState *s = kvm_state;
1853     FeatureWord w;
1854
1855     for (w = 0; w < FEATURE_WORDS; w++) {
1856         FeatureWordInfo *wi = &feature_word_info[w];
1857         uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1858                                                              wi->cpuid_ecx,
1859                                                              wi->cpuid_reg);
1860         uint32_t requested_features = env->features[w];
1861         env->features[w] &= host_feat;
1862         cpu->filtered_features[w] = requested_features & ~env->features[w];
1863     }
1864 }
1865
1866 /* Load data from X86CPUDefinition
1867  */
1868 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1869 {
1870     CPUX86State *env = &cpu->env;
1871     const char *vendor;
1872     char host_vendor[CPUID_VENDOR_SZ + 1];
1873
1874     object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1875     object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1876     object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1877     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1878     env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1879     env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1880     env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1881     env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1882     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1883     env->features[FEAT_KVM] = def->features[FEAT_KVM];
1884     env->features[FEAT_SVM] = def->features[FEAT_SVM];
1885     env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1886     env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1887     env->cpuid_xlevel2 = def->xlevel2;
1888     cpu->cache_info_passthrough = def->cache_info_passthrough;
1889
1890     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1891
1892     /* Special cases not set in the X86CPUDefinition structs: */
1893     if (kvm_enabled()) {
1894         FeatureWord w;
1895         for (w = 0; w < FEATURE_WORDS; w++) {
1896             env->features[w] |= kvm_default_features[w];
1897         }
1898     }
1899
1900     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1901
1902     /* sysenter isn't supported in compatibility mode on AMD,
1903      * syscall isn't supported in compatibility mode on Intel.
1904      * Normally we advertise the actual CPU vendor, but you can
1905      * override this using the 'vendor' property if you want to use
1906      * KVM's sysenter/syscall emulation in compatibility mode and
1907      * when doing cross vendor migration
1908      */
1909     vendor = def->vendor;
1910     if (kvm_enabled()) {
1911         uint32_t  ebx = 0, ecx = 0, edx = 0;
1912         host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1913         x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1914         vendor = host_vendor;
1915     }
1916
1917     object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1918
1919 }
1920
1921 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1922                        Error **errp)
1923 {
1924     X86CPU *cpu = NULL;
1925     X86CPUClass *xcc;
1926     ObjectClass *oc;
1927     gchar **model_pieces;
1928     char *name, *features;
1929     Error *error = NULL;
1930
1931     model_pieces = g_strsplit(cpu_model, ",", 2);
1932     if (!model_pieces[0]) {
1933         error_setg(&error, "Invalid/empty CPU model name");
1934         goto out;
1935     }
1936     name = model_pieces[0];
1937     features = model_pieces[1];
1938
1939     oc = x86_cpu_class_by_name(name);
1940     if (oc == NULL) {
1941         error_setg(&error, "Unable to find CPU definition: %s", name);
1942         goto out;
1943     }
1944     xcc = X86_CPU_CLASS(oc);
1945
1946     if (xcc->kvm_required && !kvm_enabled()) {
1947         error_setg(&error, "CPU model '%s' requires KVM", name);
1948         goto out;
1949     }
1950
1951     cpu = X86_CPU(object_new(object_class_get_name(oc)));
1952
1953 #ifndef CONFIG_USER_ONLY
1954     if (icc_bridge == NULL) {
1955         error_setg(&error, "Invalid icc-bridge value");
1956         goto out;
1957     }
1958     qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1959     object_unref(OBJECT(cpu));
1960 #endif
1961
1962     x86_cpu_parse_featurestr(CPU(cpu), features, &error);
1963     if (error) {
1964         goto out;
1965     }
1966
1967 out:
1968     if (error != NULL) {
1969         error_propagate(errp, error);
1970         if (cpu) {
1971             object_unref(OBJECT(cpu));
1972             cpu = NULL;
1973         }
1974     }
1975     g_strfreev(model_pieces);
1976     return cpu;
1977 }
1978
1979 X86CPU *cpu_x86_init(const char *cpu_model)
1980 {
1981     Error *error = NULL;
1982     X86CPU *cpu;
1983
1984     cpu = cpu_x86_create(cpu_model, NULL, &error);
1985     if (error) {
1986         goto out;
1987     }
1988
1989     object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1990
1991 out:
1992     if (error) {
1993         error_report("%s", error_get_pretty(error));
1994         error_free(error);
1995         if (cpu != NULL) {
1996             object_unref(OBJECT(cpu));
1997             cpu = NULL;
1998         }
1999     }
2000     return cpu;
2001 }
2002
2003 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2004 {
2005     X86CPUDefinition *cpudef = data;
2006     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2007
2008     xcc->cpu_def = cpudef;
2009 }
2010
2011 static void x86_register_cpudef_type(X86CPUDefinition *def)
2012 {
2013     char *typename = x86_cpu_type_name(def->name);
2014     TypeInfo ti = {
2015         .name = typename,
2016         .parent = TYPE_X86_CPU,
2017         .class_init = x86_cpu_cpudef_class_init,
2018         .class_data = def,
2019     };
2020
2021     type_register(&ti);
2022     g_free(typename);
2023 }
2024
2025 #if !defined(CONFIG_USER_ONLY)
2026
2027 void cpu_clear_apic_feature(CPUX86State *env)
2028 {
2029     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2030 }
2031
2032 #endif /* !CONFIG_USER_ONLY */
2033
2034 /* Initialize list of CPU models, filling some non-static fields if necessary
2035  */
2036 void x86_cpudef_setup(void)
2037 {
2038     int i, j;
2039     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2040
2041     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2042         X86CPUDefinition *def = &builtin_x86_defs[i];
2043
2044         /* Look for specific "cpudef" models that */
2045         /* have the QEMU version in .model_id */
2046         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2047             if (strcmp(model_with_versions[j], def->name) == 0) {
2048                 pstrcpy(def->model_id, sizeof(def->model_id),
2049                         "QEMU Virtual CPU version ");
2050                 pstrcat(def->model_id, sizeof(def->model_id),
2051                         qemu_get_version());
2052                 break;
2053             }
2054         }
2055     }
2056 }
2057
2058 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2059                              uint32_t *ecx, uint32_t *edx)
2060 {
2061     *ebx = env->cpuid_vendor1;
2062     *edx = env->cpuid_vendor2;
2063     *ecx = env->cpuid_vendor3;
2064 }
2065
2066 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2067                    uint32_t *eax, uint32_t *ebx,
2068                    uint32_t *ecx, uint32_t *edx)
2069 {
2070     X86CPU *cpu = x86_env_get_cpu(env);
2071     CPUState *cs = CPU(cpu);
2072
2073     /* test if maximum index reached */
2074     if (index & 0x80000000) {
2075         if (index > env->cpuid_xlevel) {
2076             if (env->cpuid_xlevel2 > 0) {
2077                 /* Handle the Centaur's CPUID instruction. */
2078                 if (index > env->cpuid_xlevel2) {
2079                     index = env->cpuid_xlevel2;
2080                 } else if (index < 0xC0000000) {
2081                     index = env->cpuid_xlevel;
2082                 }
2083             } else {
2084                 /* Intel documentation states that invalid EAX input will
2085                  * return the same information as EAX=cpuid_level
2086                  * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2087                  */
2088                 index =  env->cpuid_level;
2089             }
2090         }
2091     } else {
2092         if (index > env->cpuid_level)
2093             index = env->cpuid_level;
2094     }
2095
2096     switch(index) {
2097     case 0:
2098         *eax = env->cpuid_level;
2099         get_cpuid_vendor(env, ebx, ecx, edx);
2100         break;
2101     case 1:
2102         *eax = env->cpuid_version;
2103         *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2104         *ecx = env->features[FEAT_1_ECX];
2105         *edx = env->features[FEAT_1_EDX];
2106         if (cs->nr_cores * cs->nr_threads > 1) {
2107             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2108             *edx |= 1 << 28;    /* HTT bit */
2109         }
2110         break;
2111     case 2:
2112         /* cache info: needed for Pentium Pro compatibility */
2113         if (cpu->cache_info_passthrough) {
2114             host_cpuid(index, 0, eax, ebx, ecx, edx);
2115             break;
2116         }
2117         *eax = 1; /* Number of CPUID[EAX=2] calls required */
2118         *ebx = 0;
2119         *ecx = 0;
2120         *edx = (L1D_DESCRIPTOR << 16) | \
2121                (L1I_DESCRIPTOR <<  8) | \
2122                (L2_DESCRIPTOR);
2123         break;
2124     case 4:
2125         /* cache info: needed for Core compatibility */
2126         if (cpu->cache_info_passthrough) {
2127             host_cpuid(index, count, eax, ebx, ecx, edx);
2128             *eax &= ~0xFC000000;
2129         } else {
2130             *eax = 0;
2131             switch (count) {
2132             case 0: /* L1 dcache info */
2133                 *eax |= CPUID_4_TYPE_DCACHE | \
2134                         CPUID_4_LEVEL(1) | \
2135                         CPUID_4_SELF_INIT_LEVEL;
2136                 *ebx = (L1D_LINE_SIZE - 1) | \
2137                        ((L1D_PARTITIONS - 1) << 12) | \
2138                        ((L1D_ASSOCIATIVITY - 1) << 22);
2139                 *ecx = L1D_SETS - 1;
2140                 *edx = CPUID_4_NO_INVD_SHARING;
2141                 break;
2142             case 1: /* L1 icache info */
2143                 *eax |= CPUID_4_TYPE_ICACHE | \
2144                         CPUID_4_LEVEL(1) | \
2145                         CPUID_4_SELF_INIT_LEVEL;
2146                 *ebx = (L1I_LINE_SIZE - 1) | \
2147                        ((L1I_PARTITIONS - 1) << 12) | \
2148                        ((L1I_ASSOCIATIVITY - 1) << 22);
2149                 *ecx = L1I_SETS - 1;
2150                 *edx = CPUID_4_NO_INVD_SHARING;
2151                 break;
2152             case 2: /* L2 cache info */
2153                 *eax |= CPUID_4_TYPE_UNIFIED | \
2154                         CPUID_4_LEVEL(2) | \
2155                         CPUID_4_SELF_INIT_LEVEL;
2156                 if (cs->nr_threads > 1) {
2157                     *eax |= (cs->nr_threads - 1) << 14;
2158                 }
2159                 *ebx = (L2_LINE_SIZE - 1) | \
2160                        ((L2_PARTITIONS - 1) << 12) | \
2161                        ((L2_ASSOCIATIVITY - 1) << 22);
2162                 *ecx = L2_SETS - 1;
2163                 *edx = CPUID_4_NO_INVD_SHARING;
2164                 break;
2165             default: /* end of info */
2166                 *eax = 0;
2167                 *ebx = 0;
2168                 *ecx = 0;
2169                 *edx = 0;
2170                 break;
2171             }
2172         }
2173
2174         /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  */
2175         if ((*eax & 31) && cs->nr_cores > 1) {
2176             *eax |= (cs->nr_cores - 1) << 26;
2177         }
2178         break;
2179     case 5:
2180         /* mwait info: needed for Core compatibility */
2181         *eax = 0; /* Smallest monitor-line size in bytes */
2182         *ebx = 0; /* Largest monitor-line size in bytes */
2183         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2184         *edx = 0;
2185         break;
2186     case 6:
2187         /* Thermal and Power Leaf */
2188         *eax = 0;
2189         *ebx = 0;
2190         *ecx = 0;
2191         *edx = 0;
2192         break;
2193     case 7:
2194         /* Structured Extended Feature Flags Enumeration Leaf */
2195         if (count == 0) {
2196             *eax = 0; /* Maximum ECX value for sub-leaves */
2197             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2198             *ecx = 0; /* Reserved */
2199             *edx = 0; /* Reserved */
2200         } else {
2201             *eax = 0;
2202             *ebx = 0;
2203             *ecx = 0;
2204             *edx = 0;
2205         }
2206         break;
2207     case 9:
2208         /* Direct Cache Access Information Leaf */
2209         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2210         *ebx = 0;
2211         *ecx = 0;
2212         *edx = 0;
2213         break;
2214     case 0xA:
2215         /* Architectural Performance Monitoring Leaf */
2216         if (kvm_enabled() && cpu->enable_pmu) {
2217             KVMState *s = cs->kvm_state;
2218
2219             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2220             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2221             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2222             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2223         } else {
2224             *eax = 0;
2225             *ebx = 0;
2226             *ecx = 0;
2227             *edx = 0;
2228         }
2229         break;
2230     case 0xD: {
2231         KVMState *s = cs->kvm_state;
2232         uint64_t kvm_mask;
2233         int i;
2234
2235         /* Processor Extended State */
2236         *eax = 0;
2237         *ebx = 0;
2238         *ecx = 0;
2239         *edx = 0;
2240         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2241             break;
2242         }
2243         kvm_mask =
2244             kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2245             ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2246
2247         if (count == 0) {
2248             *ecx = 0x240;
2249             for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2250                 const ExtSaveArea *esa = &ext_save_areas[i];
2251                 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2252                     (kvm_mask & (1 << i)) != 0) {
2253                     if (i < 32) {
2254                         *eax |= 1 << i;
2255                     } else {
2256                         *edx |= 1 << (i - 32);
2257                     }
2258                     *ecx = MAX(*ecx, esa->offset + esa->size);
2259                 }
2260             }
2261             *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2262             *ebx = *ecx;
2263         } else if (count == 1) {
2264             *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2265         } else if (count < ARRAY_SIZE(ext_save_areas)) {
2266             const ExtSaveArea *esa = &ext_save_areas[count];
2267             if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2268                 (kvm_mask & (1 << count)) != 0) {
2269                 *eax = esa->size;
2270                 *ebx = esa->offset;
2271             }
2272         }
2273         break;
2274     }
2275     case 0x80000000:
2276         *eax = env->cpuid_xlevel;
2277         *ebx = env->cpuid_vendor1;
2278         *edx = env->cpuid_vendor2;
2279         *ecx = env->cpuid_vendor3;
2280         break;
2281     case 0x80000001:
2282         *eax = env->cpuid_version;
2283         *ebx = 0;
2284         *ecx = env->features[FEAT_8000_0001_ECX];
2285         *edx = env->features[FEAT_8000_0001_EDX];
2286
2287         /* The Linux kernel checks for the CMPLegacy bit and
2288          * discards multiple thread information if it is set.
2289          * So dont set it here for Intel to make Linux guests happy.
2290          */
2291         if (cs->nr_cores * cs->nr_threads > 1) {
2292             uint32_t tebx, tecx, tedx;
2293             get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2294             if (tebx != CPUID_VENDOR_INTEL_1 ||
2295                 tedx != CPUID_VENDOR_INTEL_2 ||
2296                 tecx != CPUID_VENDOR_INTEL_3) {
2297                 *ecx |= 1 << 1;    /* CmpLegacy bit */
2298             }
2299         }
2300         break;
2301     case 0x80000002:
2302     case 0x80000003:
2303     case 0x80000004:
2304         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2305         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2306         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2307         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2308         break;
2309     case 0x80000005:
2310         /* cache info (L1 cache) */
2311         if (cpu->cache_info_passthrough) {
2312             host_cpuid(index, 0, eax, ebx, ecx, edx);
2313             break;
2314         }
2315         *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2316                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
2317         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2318                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
2319         *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2320                (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2321         *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2322                (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2323         break;
2324     case 0x80000006:
2325         /* cache info (L2 cache) */
2326         if (cpu->cache_info_passthrough) {
2327             host_cpuid(index, 0, eax, ebx, ecx, edx);
2328             break;
2329         }
2330         *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2331                (L2_DTLB_2M_ENTRIES << 16) | \
2332                (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2333                (L2_ITLB_2M_ENTRIES);
2334         *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2335                (L2_DTLB_4K_ENTRIES << 16) | \
2336                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2337                (L2_ITLB_4K_ENTRIES);
2338         *ecx = (L2_SIZE_KB_AMD << 16) | \
2339                (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2340                (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2341         *edx = ((L3_SIZE_KB/512) << 18) | \
2342                (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2343                (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2344         break;
2345     case 0x80000008:
2346         /* virtual & phys address size in low 2 bytes. */
2347 /* XXX: This value must match the one used in the MMU code. */
2348         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2349             /* 64 bit processor */
2350 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2351             *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2352         } else {
2353             if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2354                 *eax = 0x00000024; /* 36 bits physical */
2355             } else {
2356                 *eax = 0x00000020; /* 32 bits physical */
2357             }
2358         }
2359         *ebx = 0;
2360         *ecx = 0;
2361         *edx = 0;
2362         if (cs->nr_cores * cs->nr_threads > 1) {
2363             *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2364         }
2365         break;
2366     case 0x8000000A:
2367         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2368             *eax = 0x00000001; /* SVM Revision */
2369             *ebx = 0x00000010; /* nr of ASIDs */
2370             *ecx = 0;
2371             *edx = env->features[FEAT_SVM]; /* optional features */
2372         } else {
2373             *eax = 0;
2374             *ebx = 0;
2375             *ecx = 0;
2376             *edx = 0;
2377         }
2378         break;
2379     case 0xC0000000:
2380         *eax = env->cpuid_xlevel2;
2381         *ebx = 0;
2382         *ecx = 0;
2383         *edx = 0;
2384         break;
2385     case 0xC0000001:
2386         /* Support for VIA CPU's CPUID instruction */
2387         *eax = env->cpuid_version;
2388         *ebx = 0;
2389         *ecx = 0;
2390         *edx = env->features[FEAT_C000_0001_EDX];
2391         break;
2392     case 0xC0000002:
2393     case 0xC0000003:
2394     case 0xC0000004:
2395         /* Reserved for the future, and now filled with zero */
2396         *eax = 0;
2397         *ebx = 0;
2398         *ecx = 0;
2399         *edx = 0;
2400         break;
2401     default:
2402         /* reserved values: zero */
2403         *eax = 0;
2404         *ebx = 0;
2405         *ecx = 0;
2406         *edx = 0;
2407         break;
2408     }
2409 }
2410
2411 /* CPUClass::reset() */
2412 static void x86_cpu_reset(CPUState *s)
2413 {
2414     X86CPU *cpu = X86_CPU(s);
2415     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2416     CPUX86State *env = &cpu->env;
2417     int i;
2418
2419     xcc->parent_reset(s);
2420
2421     memset(env, 0, offsetof(CPUX86State, cpuid_level));
2422
2423     tlb_flush(s, 1);
2424
2425     env->old_exception = -1;
2426
2427     /* init to reset state */
2428
2429 #ifdef CONFIG_SOFTMMU
2430     env->hflags |= HF_SOFTMMU_MASK;
2431 #endif
2432     env->hflags2 |= HF2_GIF_MASK;
2433
2434     cpu_x86_update_cr0(env, 0x60000010);
2435     env->a20_mask = ~0x0;
2436     env->smbase = 0x30000;
2437
2438     env->idt.limit = 0xffff;
2439     env->gdt.limit = 0xffff;
2440     env->ldt.limit = 0xffff;
2441     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2442     env->tr.limit = 0xffff;
2443     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2444
2445     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2446                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2447                            DESC_R_MASK | DESC_A_MASK);
2448     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2449                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2450                            DESC_A_MASK);
2451     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2452                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2453                            DESC_A_MASK);
2454     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2455                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2456                            DESC_A_MASK);
2457     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2458                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2459                            DESC_A_MASK);
2460     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2461                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2462                            DESC_A_MASK);
2463
2464     env->eip = 0xfff0;
2465     env->regs[R_EDX] = env->cpuid_version;
2466
2467     env->eflags = 0x2;
2468
2469     /* FPU init */
2470     for (i = 0; i < 8; i++) {
2471         env->fptags[i] = 1;
2472     }
2473     env->fpuc = 0x37f;
2474
2475     env->mxcsr = 0x1f80;
2476     env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2477
2478     env->pat = 0x0007040600070406ULL;
2479     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2480
2481     memset(env->dr, 0, sizeof(env->dr));
2482     env->dr[6] = DR6_FIXED_1;
2483     env->dr[7] = DR7_FIXED_1;
2484     cpu_breakpoint_remove_all(s, BP_CPU);
2485     cpu_watchpoint_remove_all(s, BP_CPU);
2486
2487     env->xcr0 = 1;
2488
2489 #if !defined(CONFIG_USER_ONLY)
2490     /* We hard-wire the BSP to the first CPU. */
2491     if (s->cpu_index == 0) {
2492         apic_designate_bsp(cpu->apic_state);
2493     }
2494
2495     s->halted = !cpu_is_bsp(cpu);
2496
2497     if (kvm_enabled()) {
2498         kvm_arch_reset_vcpu(cpu);
2499     }
2500 #endif
2501 }
2502
2503 #ifndef CONFIG_USER_ONLY
2504 bool cpu_is_bsp(X86CPU *cpu)
2505 {
2506     return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2507 }
2508
2509 /* TODO: remove me, when reset over QOM tree is implemented */
2510 static void x86_cpu_machine_reset_cb(void *opaque)
2511 {
2512     X86CPU *cpu = opaque;
2513     cpu_reset(CPU(cpu));
2514 }
2515 #endif
2516
2517 static void mce_init(X86CPU *cpu)
2518 {
2519     CPUX86State *cenv = &cpu->env;
2520     unsigned int bank;
2521
2522     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2523         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2524             (CPUID_MCE | CPUID_MCA)) {
2525         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2526         cenv->mcg_ctl = ~(uint64_t)0;
2527         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2528             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2529         }
2530     }
2531 }
2532
2533 #ifndef CONFIG_USER_ONLY
2534 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2535 {
2536     CPUX86State *env = &cpu->env;
2537     DeviceState *dev = DEVICE(cpu);
2538     APICCommonState *apic;
2539     const char *apic_type = "apic";
2540
2541     if (kvm_irqchip_in_kernel()) {
2542         apic_type = "kvm-apic";
2543     } else if (xen_enabled()) {
2544         apic_type = "xen-apic";
2545     }
2546
2547     cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2548     if (cpu->apic_state == NULL) {
2549         error_setg(errp, "APIC device '%s' could not be created", apic_type);
2550         return;
2551     }
2552
2553     object_property_add_child(OBJECT(cpu), "apic",
2554                               OBJECT(cpu->apic_state), NULL);
2555     qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2556     /* TODO: convert to link<> */
2557     apic = APIC_COMMON(cpu->apic_state);
2558     apic->cpu = cpu;
2559 }
2560
2561 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2562 {
2563     if (cpu->apic_state == NULL) {
2564         return;
2565     }
2566
2567     if (qdev_init(cpu->apic_state)) {
2568         error_setg(errp, "APIC device '%s' could not be initialized",
2569                    object_get_typename(OBJECT(cpu->apic_state)));
2570         return;
2571     }
2572 }
2573 #else
2574 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2575 {
2576 }
2577 #endif
2578
2579 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2580 {
2581     CPUState *cs = CPU(dev);
2582     X86CPU *cpu = X86_CPU(dev);
2583     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2584     CPUX86State *env = &cpu->env;
2585     Error *local_err = NULL;
2586
2587     if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2588         env->cpuid_level = 7;
2589     }
2590
2591     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2592      * CPUID[1].EDX.
2593      */
2594     if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2595         env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2596         env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2597         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2598         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2599            & CPUID_EXT2_AMD_ALIASES);
2600     }
2601
2602     if (!kvm_enabled()) {
2603         env->features[FEAT_1_EDX] &= TCG_FEATURES;
2604         env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2605         env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2606 #ifdef TARGET_X86_64
2607             | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2608 #endif
2609             );
2610         env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2611         env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2612     } else {
2613         KVMState *s = kvm_state;
2614         if ((cpu->check_cpuid || cpu->enforce_cpuid)
2615             && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
2616             error_setg(&local_err,
2617                        "Host's CPU doesn't support requested features");
2618             goto out;
2619         }
2620         filter_features_for_kvm(cpu);
2621     }
2622
2623 #ifndef CONFIG_USER_ONLY
2624     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2625
2626     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2627         x86_cpu_apic_create(cpu, &local_err);
2628         if (local_err != NULL) {
2629             goto out;
2630         }
2631     }
2632 #endif
2633
2634     mce_init(cpu);
2635     qemu_init_vcpu(cs);
2636
2637     x86_cpu_apic_realize(cpu, &local_err);
2638     if (local_err != NULL) {
2639         goto out;
2640     }
2641     cpu_reset(cs);
2642
2643     xcc->parent_realize(dev, &local_err);
2644 out:
2645     if (local_err != NULL) {
2646         error_propagate(errp, local_err);
2647         return;
2648     }
2649 }
2650
2651 /* Enables contiguous-apic-ID mode, for compatibility */
2652 static bool compat_apic_id_mode;
2653
2654 void enable_compat_apic_id_mode(void)
2655 {
2656     compat_apic_id_mode = true;
2657 }
2658
2659 /* Calculates initial APIC ID for a specific CPU index
2660  *
2661  * Currently we need to be able to calculate the APIC ID from the CPU index
2662  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2663  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2664  * all CPUs up to max_cpus.
2665  */
2666 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2667 {
2668     uint32_t correct_id;
2669     static bool warned;
2670
2671     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2672     if (compat_apic_id_mode) {
2673         if (cpu_index != correct_id && !warned) {
2674             error_report("APIC IDs set in compatibility mode, "
2675                          "CPU topology won't match the configuration");
2676             warned = true;
2677         }
2678         return cpu_index;
2679     } else {
2680         return correct_id;
2681     }
2682 }
2683
2684 static void x86_cpu_initfn(Object *obj)
2685 {
2686     CPUState *cs = CPU(obj);
2687     X86CPU *cpu = X86_CPU(obj);
2688     X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2689     CPUX86State *env = &cpu->env;
2690     static int inited;
2691
2692     cs->env_ptr = env;
2693     cpu_exec_init(env);
2694
2695     object_property_add(obj, "family", "int",
2696                         x86_cpuid_version_get_family,
2697                         x86_cpuid_version_set_family, NULL, NULL, NULL);
2698     object_property_add(obj, "model", "int",
2699                         x86_cpuid_version_get_model,
2700                         x86_cpuid_version_set_model, NULL, NULL, NULL);
2701     object_property_add(obj, "stepping", "int",
2702                         x86_cpuid_version_get_stepping,
2703                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2704     object_property_add(obj, "level", "int",
2705                         x86_cpuid_get_level,
2706                         x86_cpuid_set_level, NULL, NULL, NULL);
2707     object_property_add(obj, "xlevel", "int",
2708                         x86_cpuid_get_xlevel,
2709                         x86_cpuid_set_xlevel, NULL, NULL, NULL);
2710     object_property_add_str(obj, "vendor",
2711                             x86_cpuid_get_vendor,
2712                             x86_cpuid_set_vendor, NULL);
2713     object_property_add_str(obj, "model-id",
2714                             x86_cpuid_get_model_id,
2715                             x86_cpuid_set_model_id, NULL);
2716     object_property_add(obj, "tsc-frequency", "int",
2717                         x86_cpuid_get_tsc_freq,
2718                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2719     object_property_add(obj, "apic-id", "int",
2720                         x86_cpuid_get_apic_id,
2721                         x86_cpuid_set_apic_id, NULL, NULL, NULL);
2722     object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2723                         x86_cpu_get_feature_words,
2724                         NULL, NULL, (void *)env->features, NULL);
2725     object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2726                         x86_cpu_get_feature_words,
2727                         NULL, NULL, (void *)cpu->filtered_features, NULL);
2728
2729     cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2730     env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2731
2732     x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2733
2734     /* init various static tables used in TCG mode */
2735     if (tcg_enabled() && !inited) {
2736         inited = 1;
2737         optimize_flags_init();
2738 #ifndef CONFIG_USER_ONLY
2739         cpu_set_debug_excp_handler(breakpoint_handler);
2740 #endif
2741     }
2742 }
2743
2744 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2745 {
2746     X86CPU *cpu = X86_CPU(cs);
2747     CPUX86State *env = &cpu->env;
2748
2749     return env->cpuid_apic_id;
2750 }
2751
2752 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2753 {
2754     X86CPU *cpu = X86_CPU(cs);
2755
2756     return cpu->env.cr[0] & CR0_PG_MASK;
2757 }
2758
2759 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2760 {
2761     X86CPU *cpu = X86_CPU(cs);
2762
2763     cpu->env.eip = value;
2764 }
2765
2766 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2767 {
2768     X86CPU *cpu = X86_CPU(cs);
2769
2770     cpu->env.eip = tb->pc - tb->cs_base;
2771 }
2772
2773 static bool x86_cpu_has_work(CPUState *cs)
2774 {
2775     X86CPU *cpu = X86_CPU(cs);
2776     CPUX86State *env = &cpu->env;
2777
2778     return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2779                                       CPU_INTERRUPT_POLL)) &&
2780             (env->eflags & IF_MASK)) ||
2781            (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2782                                      CPU_INTERRUPT_INIT |
2783                                      CPU_INTERRUPT_SIPI |
2784                                      CPU_INTERRUPT_MCE));
2785 }
2786
2787 static Property x86_cpu_properties[] = {
2788     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2789     { .name  = "hv-spinlocks", .info  = &qdev_prop_spinlocks },
2790     DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2791     DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2792     DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2793     DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2794     DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2795     DEFINE_PROP_END_OF_LIST()
2796 };
2797
2798 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2799 {
2800     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2801     CPUClass *cc = CPU_CLASS(oc);
2802     DeviceClass *dc = DEVICE_CLASS(oc);
2803
2804     xcc->parent_realize = dc->realize;
2805     dc->realize = x86_cpu_realizefn;
2806     dc->bus_type = TYPE_ICC_BUS;
2807     dc->props = x86_cpu_properties;
2808
2809     xcc->parent_reset = cc->reset;
2810     cc->reset = x86_cpu_reset;
2811     cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2812
2813     cc->class_by_name = x86_cpu_class_by_name;
2814     cc->parse_features = x86_cpu_parse_featurestr;
2815     cc->has_work = x86_cpu_has_work;
2816     cc->do_interrupt = x86_cpu_do_interrupt;
2817     cc->dump_state = x86_cpu_dump_state;
2818     cc->set_pc = x86_cpu_set_pc;
2819     cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2820     cc->gdb_read_register = x86_cpu_gdb_read_register;
2821     cc->gdb_write_register = x86_cpu_gdb_write_register;
2822     cc->get_arch_id = x86_cpu_get_arch_id;
2823     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2824 #ifdef CONFIG_USER_ONLY
2825     cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2826 #else
2827     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2828     cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2829     cc->write_elf64_note = x86_cpu_write_elf64_note;
2830     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2831     cc->write_elf32_note = x86_cpu_write_elf32_note;
2832     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2833     cc->vmsd = &vmstate_x86_cpu;
2834 #endif
2835     cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2836 }
2837
2838 static const TypeInfo x86_cpu_type_info = {
2839     .name = TYPE_X86_CPU,
2840     .parent = TYPE_CPU,
2841     .instance_size = sizeof(X86CPU),
2842     .instance_init = x86_cpu_initfn,
2843     .abstract = true,
2844     .class_size = sizeof(X86CPUClass),
2845     .class_init = x86_cpu_common_class_init,
2846 };
2847
2848 static void x86_cpu_register_types(void)
2849 {
2850     int i;
2851
2852     type_register_static(&x86_cpu_type_info);
2853     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2854         x86_register_cpudef_type(&builtin_x86_defs[i]);
2855     }
2856 #ifdef CONFIG_KVM
2857     type_register_static(&host_x86_cpu_type_info);
2858 #endif
2859 }
2860
2861 type_init(x86_cpu_register_types)