target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & ARM_CP_SPECIAL) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 112         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 115 #else
 116         /* Reset into the highest available EL */
 117         if (arm_feature(env, ARM_FEATURE_EL3)) {
 118             env->pstate = PSTATE_MODE_EL3h;
 119         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 120             env->pstate = PSTATE_MODE_EL2h;
 121         } else {
 122             env->pstate = PSTATE_MODE_EL1h;
 123         }
 124         env->pc = cpu->rvbar;
 125 #endif
 126     } else {
 127 #if defined(CONFIG_USER_ONLY)
 128         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 129         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 130 #endif
 131     }
 132
 133 #if defined(CONFIG_USER_ONLY)
 134     env->uncached_cpsr = ARM_CPU_MODE_USR;
 135     /* For user mode we must enable access to coprocessors */
 136     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 137     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 138         env->cp15.c15_cpar = 3;
 139     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 140         env->cp15.c15_cpar = 1;
 141     }
 142 #else
 143     /* SVC mode with interrupts disabled.  */
 144     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 145     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 146     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 147      * clear at reset. Initial SP and PC are loaded from ROM.
 148      */
 149     if (IS_M(env)) {
 150         uint32_t initial_msp; /* Loaded from 0x0 */
 151         uint32_t initial_pc; /* Loaded from 0x4 */
 152         uint8_t *rom;
 153
 154         env->daif &= ~PSTATE_I;
 155         rom = rom_ptr(0);
 156         if (rom) {
 157             /* Address zero is covered by ROM which hasn't yet been
 158              * copied into physical memory.
 159              */
 160             initial_msp = ldl_p(rom);
 161             initial_pc = ldl_p(rom + 4);
 162         } else {
 163             /* Address zero not covered by a ROM blob, or the ROM blob
 164              * is in non-modifiable memory and this is a second reset after
 165              * it got copied into memory. In the latter case, rom_ptr
 166              * will return a NULL pointer and we should use ldl_phys instead.
 167              */
 168             initial_msp = ldl_phys(s->as, 0);
 169             initial_pc = ldl_phys(s->as, 4);
 170         }
 171
 172         env->regs[13] = initial_msp & 0xFFFFFFFC;
 173         env->regs[15] = initial_pc & ~1;
 174         env->thumb = initial_pc & 1;
 175     }
 176
 177     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 178      * executing as AArch32 then check if highvecs are enabled and
 179      * adjust the PC accordingly.
 180      */
 181     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 182         env->regs[15] = 0xFFFF0000;
 183     }
 184
 185     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 186 #endif
 187     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 188     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 189     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 190     set_float_detect_tininess(float_tininess_before_rounding,
 191                               &env->vfp.fp_status);
 192     set_float_detect_tininess(float_tininess_before_rounding,
 193                               &env->vfp.standard_fp_status);
 194     tlb_flush(s, 1);
 195
 196 #ifndef CONFIG_USER_ONLY
 197     if (kvm_enabled()) {
 198         kvm_arm_reset_vcpu(cpu);
 199     }
 200 #endif
 201
 202     hw_breakpoint_update_all(cpu);
 203     hw_watchpoint_update_all(cpu);
 204 }
 205
 206 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 207 {
 208     CPUClass *cc = CPU_GET_CLASS(cs);
 209     bool ret = false;
 210
 211     if (interrupt_request & CPU_INTERRUPT_FIQ
 212         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 213         cs->exception_index = EXCP_FIQ;
 214         cc->do_interrupt(cs);
 215         ret = true;
 216     }
 217     if (interrupt_request & CPU_INTERRUPT_HARD
 218         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 219         cs->exception_index = EXCP_IRQ;
 220         cc->do_interrupt(cs);
 221         ret = true;
 222     }
 223     if (interrupt_request & CPU_INTERRUPT_VIRQ
 224         && arm_excp_unmasked(cs, EXCP_VIRQ)) {
 225         cs->exception_index = EXCP_VIRQ;
 226         cc->do_interrupt(cs);
 227         ret = true;
 228     }
 229     if (interrupt_request & CPU_INTERRUPT_VFIQ
 230         && arm_excp_unmasked(cs, EXCP_VFIQ)) {
 231         cs->exception_index = EXCP_VFIQ;
 232         cc->do_interrupt(cs);
 233         ret = true;
 234     }
 235
 236     return ret;
 237 }
 238
 239 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 240 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 241 {
 242     CPUClass *cc = CPU_GET_CLASS(cs);
 243     ARMCPU *cpu = ARM_CPU(cs);
 244     CPUARMState *env = &cpu->env;
 245     bool ret = false;
 246
 247
 248     if (interrupt_request & CPU_INTERRUPT_FIQ
 249         && !(env->daif & PSTATE_F)) {
 250         cs->exception_index = EXCP_FIQ;
 251         cc->do_interrupt(cs);
 252         ret = true;
 253     }
 254     /* ARMv7-M interrupt return works by loading a magic value
 255      * into the PC.  On real hardware the load causes the
 256      * return to occur.  The qemu implementation performs the
 257      * jump normally, then does the exception return when the
 258      * CPU tries to execute code at the magic address.
 259      * This will cause the magic PC value to be pushed to
 260      * the stack if an interrupt occurred at the wrong time.
 261      * We avoid this by disabling interrupts when
 262      * pc contains a magic address.
 263      */
 264     if (interrupt_request & CPU_INTERRUPT_HARD
 265         && !(env->daif & PSTATE_I)
 266         && (env->regs[15] < 0xfffffff0)) {
 267         cs->exception_index = EXCP_IRQ;
 268         cc->do_interrupt(cs);
 269         ret = true;
 270     }
 271     return ret;
 272 }
 273 #endif
 274
 275 #ifndef CONFIG_USER_ONLY
 276 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 277 {
 278     ARMCPU *cpu = opaque;
 279     CPUARMState *env = &cpu->env;
 280     CPUState *cs = CPU(cpu);
 281     static const int mask[] = {
 282         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 283         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 284         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 285         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 286     };
 287
 288     switch (irq) {
 289     case ARM_CPU_VIRQ:
 290     case ARM_CPU_VFIQ:
 291         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 292             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 293                      __func__, irq);
 294         }
 295         /* fall through */
 296     case ARM_CPU_IRQ:
 297     case ARM_CPU_FIQ:
 298         if (level) {
 299             cpu_interrupt(cs, mask[irq]);
 300         } else {
 301             cpu_reset_interrupt(cs, mask[irq]);
 302         }
 303         break;
 304     default:
 305         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 306     }
 307 }
 308
 309 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 310 {
 311 #ifdef CONFIG_KVM
 312     ARMCPU *cpu = opaque;
 313     CPUState *cs = CPU(cpu);
 314     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 315
 316     switch (irq) {
 317     case ARM_CPU_IRQ:
 318         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 319         break;
 320     case ARM_CPU_FIQ:
 321         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 322         break;
 323     default:
 324         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 325     }
 326     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 327     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 328 #endif
 329 }
 330
 331 static bool arm_cpu_is_big_endian(CPUState *cs)
 332 {
 333     ARMCPU *cpu = ARM_CPU(cs);
 334     CPUARMState *env = &cpu->env;
 335     int cur_el;
 336
 337     cpu_synchronize_state(cs);
 338
 339     /* In 32bit guest endianness is determined by looking at CPSR's E bit */
 340     if (!is_a64(env)) {
 341         return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
 342     }
 343
 344     cur_el = arm_current_el(env);
 345
 346     if (cur_el == 0) {
 347         return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
 348     }
 349
 350     return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
 351 }
 352
 353 #endif
 354
 355 static inline void set_feature(CPUARMState *env, int feature)
 356 {
 357     env->features |= 1ULL << feature;
 358 }
 359
 360 static inline void unset_feature(CPUARMState *env, int feature)
 361 {
 362     env->features &= ~(1ULL << feature);
 363 }
 364
 365 static void arm_cpu_initfn(Object *obj)
 366 {
 367     CPUState *cs = CPU(obj);
 368     ARMCPU *cpu = ARM_CPU(obj);
 369     static bool inited;
 370
 371     cs->env_ptr = &cpu->env;
 372     cpu_exec_init(&cpu->env);
 373     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 374                                          g_free, g_free);
 375
 376 #ifndef CONFIG_USER_ONLY
 377     /* Our inbound IRQ and FIQ lines */
 378     if (kvm_enabled()) {
 379         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 380          * the same interface as non-KVM CPUs.
 381          */
 382         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 383     } else {
 384         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 385     }
 386
 387     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 388                                                 arm_gt_ptimer_cb, cpu);
 389     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 390                                                 arm_gt_vtimer_cb, cpu);
 391     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 392                        ARRAY_SIZE(cpu->gt_timer_outputs));
 393 #endif
 394
 395     /* DTB consumers generally don't in fact care what the 'compatible'
 396      * string is, so always provide some string and trust that a hypothetical
 397      * picky DTB consumer will also provide a helpful error message.
 398      */
 399     cpu->dtb_compatible = "qemu,unknown";
 400     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 401     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 402
 403     if (tcg_enabled()) {
 404         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 405         if (!inited) {
 406             inited = true;
 407             arm_translate_init();
 408         }
 409     }
 410 }
 411
 412 static Property arm_cpu_reset_cbar_property =
 413             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 414
 415 static Property arm_cpu_reset_hivecs_property =
 416             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 417
 418 static Property arm_cpu_rvbar_property =
 419             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 420
 421 static Property arm_cpu_has_el3_property =
 422             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 423
 424 static void arm_cpu_post_init(Object *obj)
 425 {
 426     ARMCPU *cpu = ARM_CPU(obj);
 427
 428     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 429         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 430         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 431                                  &error_abort);
 432     }
 433
 434     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 435         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 436                                  &error_abort);
 437     }
 438
 439     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 440         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 441                                  &error_abort);
 442     }
 443
 444     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 445         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 446          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 447          */
 448         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 449                                  &error_abort);
 450     }
 451 }
 452
 453 static void arm_cpu_finalizefn(Object *obj)
 454 {
 455     ARMCPU *cpu = ARM_CPU(obj);
 456     g_hash_table_destroy(cpu->cp_regs);
 457 }
 458
 459 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 460 {
 461     CPUState *cs = CPU(dev);
 462     ARMCPU *cpu = ARM_CPU(dev);
 463     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 464     CPUARMState *env = &cpu->env;
 465
 466     /* Some features automatically imply others: */
 467     if (arm_feature(env, ARM_FEATURE_V8)) {
 468         set_feature(env, ARM_FEATURE_V7);
 469         set_feature(env, ARM_FEATURE_ARM_DIV);
 470         set_feature(env, ARM_FEATURE_LPAE);
 471     }
 472     if (arm_feature(env, ARM_FEATURE_V7)) {
 473         set_feature(env, ARM_FEATURE_VAPA);
 474         set_feature(env, ARM_FEATURE_THUMB2);
 475         set_feature(env, ARM_FEATURE_MPIDR);
 476         if (!arm_feature(env, ARM_FEATURE_M)) {
 477             set_feature(env, ARM_FEATURE_V6K);
 478         } else {
 479             set_feature(env, ARM_FEATURE_V6);
 480         }
 481     }
 482     if (arm_feature(env, ARM_FEATURE_V6K)) {
 483         set_feature(env, ARM_FEATURE_V6);
 484         set_feature(env, ARM_FEATURE_MVFR);
 485     }
 486     if (arm_feature(env, ARM_FEATURE_V6)) {
 487         set_feature(env, ARM_FEATURE_V5);
 488         if (!arm_feature(env, ARM_FEATURE_M)) {
 489             set_feature(env, ARM_FEATURE_AUXCR);
 490         }
 491     }
 492     if (arm_feature(env, ARM_FEATURE_V5)) {
 493         set_feature(env, ARM_FEATURE_V4T);
 494     }
 495     if (arm_feature(env, ARM_FEATURE_M)) {
 496         set_feature(env, ARM_FEATURE_THUMB_DIV);
 497     }
 498     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 499         set_feature(env, ARM_FEATURE_THUMB_DIV);
 500     }
 501     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 502         set_feature(env, ARM_FEATURE_VFP3);
 503         set_feature(env, ARM_FEATURE_VFP_FP16);
 504     }
 505     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 506         set_feature(env, ARM_FEATURE_VFP);
 507     }
 508     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 509         set_feature(env, ARM_FEATURE_V7MP);
 510         set_feature(env, ARM_FEATURE_PXN);
 511     }
 512     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 513         set_feature(env, ARM_FEATURE_CBAR);
 514     }
 515
 516     if (cpu->reset_hivecs) {
 517             cpu->reset_sctlr |= (1 << 13);
 518     }
 519
 520     if (!cpu->has_el3) {
 521         /* If the has_el3 CPU property is disabled then we need to disable the
 522          * feature.
 523          */
 524         unset_feature(env, ARM_FEATURE_EL3);
 525
 526         /* Disable the security extension feature bits in the processor feature
 527          * register as well.  This is id_pfr1[7:4].
 528          */
 529         cpu->id_pfr1 &= ~0xf0;
 530     }
 531
 532     register_cp_regs_for_features(cpu);
 533     arm_cpu_register_gdb_regs_for_features(cpu);
 534
 535     init_cpreg_list(cpu);
 536
 537     qemu_init_vcpu(cs);
 538     cpu_reset(cs);
 539
 540     acc->parent_realize(dev, errp);
 541 }
 542
 543 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 544 {
 545     ObjectClass *oc;
 546     char *typename;
 547
 548     if (!cpu_model) {
 549         return NULL;
 550     }
 551
 552     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 553     oc = object_class_by_name(typename);
 554     g_free(typename);
 555     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 556         object_class_is_abstract(oc)) {
 557         return NULL;
 558     }
 559     return oc;
 560 }
 561
 562 /* CPU models. These are not needed for the AArch64 linux-user build. */
 563 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 564
 565 static void arm926_initfn(Object *obj)
 566 {
 567     ARMCPU *cpu = ARM_CPU(obj);
 568
 569     cpu->dtb_compatible = "arm,arm926";
 570     set_feature(&cpu->env, ARM_FEATURE_V5);
 571     set_feature(&cpu->env, ARM_FEATURE_VFP);
 572     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 573     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 574     cpu->midr = 0x41069265;
 575     cpu->reset_fpsid = 0x41011090;
 576     cpu->ctr = 0x1dd20d2;
 577     cpu->reset_sctlr = 0x00090078;
 578 }
 579
 580 static void arm946_initfn(Object *obj)
 581 {
 582     ARMCPU *cpu = ARM_CPU(obj);
 583
 584     cpu->dtb_compatible = "arm,arm946";
 585     set_feature(&cpu->env, ARM_FEATURE_V5);
 586     set_feature(&cpu->env, ARM_FEATURE_MPU);
 587     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 588     cpu->midr = 0x41059461;
 589     cpu->ctr = 0x0f004006;
 590     cpu->reset_sctlr = 0x00000078;
 591 }
 592
 593 static void arm1026_initfn(Object *obj)
 594 {
 595     ARMCPU *cpu = ARM_CPU(obj);
 596
 597     cpu->dtb_compatible = "arm,arm1026";
 598     set_feature(&cpu->env, ARM_FEATURE_V5);
 599     set_feature(&cpu->env, ARM_FEATURE_VFP);
 600     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 601     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 602     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 603     cpu->midr = 0x4106a262;
 604     cpu->reset_fpsid = 0x410110a0;
 605     cpu->ctr = 0x1dd20d2;
 606     cpu->reset_sctlr = 0x00090078;
 607     cpu->reset_auxcr = 1;
 608     {
 609         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 610         ARMCPRegInfo ifar = {
 611             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 612             .access = PL1_RW,
 613             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 614             .resetvalue = 0
 615         };
 616         define_one_arm_cp_reg(cpu, &ifar);
 617     }
 618 }
 619
 620 static void arm1136_r2_initfn(Object *obj)
 621 {
 622     ARMCPU *cpu = ARM_CPU(obj);
 623     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 624      * older core than plain "arm1136". In particular this does not
 625      * have the v6K features.
 626      * These ID register values are correct for 1136 but may be wrong
 627      * for 1136_r2 (in particular r0p2 does not actually implement most
 628      * of the ID registers).
 629      */
 630
 631     cpu->dtb_compatible = "arm,arm1136";
 632     set_feature(&cpu->env, ARM_FEATURE_V6);
 633     set_feature(&cpu->env, ARM_FEATURE_VFP);
 634     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 635     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 636     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 637     cpu->midr = 0x4107b362;
 638     cpu->reset_fpsid = 0x410120b4;
 639     cpu->mvfr0 = 0x11111111;
 640     cpu->mvfr1 = 0x00000000;
 641     cpu->ctr = 0x1dd20d2;
 642     cpu->reset_sctlr = 0x00050078;
 643     cpu->id_pfr0 = 0x111;
 644     cpu->id_pfr1 = 0x1;
 645     cpu->id_dfr0 = 0x2;
 646     cpu->id_afr0 = 0x3;
 647     cpu->id_mmfr0 = 0x01130003;
 648     cpu->id_mmfr1 = 0x10030302;
 649     cpu->id_mmfr2 = 0x01222110;
 650     cpu->id_isar0 = 0x00140011;
 651     cpu->id_isar1 = 0x12002111;
 652     cpu->id_isar2 = 0x11231111;
 653     cpu->id_isar3 = 0x01102131;
 654     cpu->id_isar4 = 0x141;
 655     cpu->reset_auxcr = 7;
 656 }
 657
 658 static void arm1136_initfn(Object *obj)
 659 {
 660     ARMCPU *cpu = ARM_CPU(obj);
 661
 662     cpu->dtb_compatible = "arm,arm1136";
 663     set_feature(&cpu->env, ARM_FEATURE_V6K);
 664     set_feature(&cpu->env, ARM_FEATURE_V6);
 665     set_feature(&cpu->env, ARM_FEATURE_VFP);
 666     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 667     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 668     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 669     cpu->midr = 0x4117b363;
 670     cpu->reset_fpsid = 0x410120b4;
 671     cpu->mvfr0 = 0x11111111;
 672     cpu->mvfr1 = 0x00000000;
 673     cpu->ctr = 0x1dd20d2;
 674     cpu->reset_sctlr = 0x00050078;
 675     cpu->id_pfr0 = 0x111;
 676     cpu->id_pfr1 = 0x1;
 677     cpu->id_dfr0 = 0x2;
 678     cpu->id_afr0 = 0x3;
 679     cpu->id_mmfr0 = 0x01130003;
 680     cpu->id_mmfr1 = 0x10030302;
 681     cpu->id_mmfr2 = 0x01222110;
 682     cpu->id_isar0 = 0x00140011;
 683     cpu->id_isar1 = 0x12002111;
 684     cpu->id_isar2 = 0x11231111;
 685     cpu->id_isar3 = 0x01102131;
 686     cpu->id_isar4 = 0x141;
 687     cpu->reset_auxcr = 7;
 688 }
 689
 690 static void arm1176_initfn(Object *obj)
 691 {
 692     ARMCPU *cpu = ARM_CPU(obj);
 693
 694     cpu->dtb_compatible = "arm,arm1176";
 695     set_feature(&cpu->env, ARM_FEATURE_V6K);
 696     set_feature(&cpu->env, ARM_FEATURE_VFP);
 697     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 698     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 699     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 700     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 701     set_feature(&cpu->env, ARM_FEATURE_EL3);
 702     cpu->midr = 0x410fb767;
 703     cpu->reset_fpsid = 0x410120b5;
 704     cpu->mvfr0 = 0x11111111;
 705     cpu->mvfr1 = 0x00000000;
 706     cpu->ctr = 0x1dd20d2;
 707     cpu->reset_sctlr = 0x00050078;
 708     cpu->id_pfr0 = 0x111;
 709     cpu->id_pfr1 = 0x11;
 710     cpu->id_dfr0 = 0x33;
 711     cpu->id_afr0 = 0;
 712     cpu->id_mmfr0 = 0x01130003;
 713     cpu->id_mmfr1 = 0x10030302;
 714     cpu->id_mmfr2 = 0x01222100;
 715     cpu->id_isar0 = 0x0140011;
 716     cpu->id_isar1 = 0x12002111;
 717     cpu->id_isar2 = 0x11231121;
 718     cpu->id_isar3 = 0x01102131;
 719     cpu->id_isar4 = 0x01141;
 720     cpu->reset_auxcr = 7;
 721 }
 722
 723 static void arm11mpcore_initfn(Object *obj)
 724 {
 725     ARMCPU *cpu = ARM_CPU(obj);
 726
 727     cpu->dtb_compatible = "arm,arm11mpcore";
 728     set_feature(&cpu->env, ARM_FEATURE_V6K);
 729     set_feature(&cpu->env, ARM_FEATURE_VFP);
 730     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 731     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 732     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 733     cpu->midr = 0x410fb022;
 734     cpu->reset_fpsid = 0x410120b4;
 735     cpu->mvfr0 = 0x11111111;
 736     cpu->mvfr1 = 0x00000000;
 737     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 738     cpu->id_pfr0 = 0x111;
 739     cpu->id_pfr1 = 0x1;
 740     cpu->id_dfr0 = 0;
 741     cpu->id_afr0 = 0x2;
 742     cpu->id_mmfr0 = 0x01100103;
 743     cpu->id_mmfr1 = 0x10020302;
 744     cpu->id_mmfr2 = 0x01222000;
 745     cpu->id_isar0 = 0x00100011;
 746     cpu->id_isar1 = 0x12002111;
 747     cpu->id_isar2 = 0x11221011;
 748     cpu->id_isar3 = 0x01102131;
 749     cpu->id_isar4 = 0x141;
 750     cpu->reset_auxcr = 1;
 751 }
 752
 753 static void cortex_m3_initfn(Object *obj)
 754 {
 755     ARMCPU *cpu = ARM_CPU(obj);
 756     set_feature(&cpu->env, ARM_FEATURE_V7);
 757     set_feature(&cpu->env, ARM_FEATURE_M);
 758     cpu->midr = 0x410fc231;
 759 }
 760
 761 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 762 {
 763     CPUClass *cc = CPU_CLASS(oc);
 764
 765 #ifndef CONFIG_USER_ONLY
 766     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 767 #endif
 768
 769     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 770 }
 771
 772 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 773     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 774       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 775     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 776       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 777     REGINFO_SENTINEL
 778 };
 779
 780 static void cortex_a8_initfn(Object *obj)
 781 {
 782     ARMCPU *cpu = ARM_CPU(obj);
 783
 784     cpu->dtb_compatible = "arm,cortex-a8";
 785     set_feature(&cpu->env, ARM_FEATURE_V7);
 786     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 787     set_feature(&cpu->env, ARM_FEATURE_NEON);
 788     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 789     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 790     set_feature(&cpu->env, ARM_FEATURE_EL3);
 791     cpu->midr = 0x410fc080;
 792     cpu->reset_fpsid = 0x410330c0;
 793     cpu->mvfr0 = 0x11110222;
 794     cpu->mvfr1 = 0x00011100;
 795     cpu->ctr = 0x82048004;
 796     cpu->reset_sctlr = 0x00c50078;
 797     cpu->id_pfr0 = 0x1031;
 798     cpu->id_pfr1 = 0x11;
 799     cpu->id_dfr0 = 0x400;
 800     cpu->id_afr0 = 0;
 801     cpu->id_mmfr0 = 0x31100003;
 802     cpu->id_mmfr1 = 0x20000000;
 803     cpu->id_mmfr2 = 0x01202000;
 804     cpu->id_mmfr3 = 0x11;
 805     cpu->id_isar0 = 0x00101111;
 806     cpu->id_isar1 = 0x12112111;
 807     cpu->id_isar2 = 0x21232031;
 808     cpu->id_isar3 = 0x11112131;
 809     cpu->id_isar4 = 0x00111142;
 810     cpu->dbgdidr = 0x15141000;
 811     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 812     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 813     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 814     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 815     cpu->reset_auxcr = 2;
 816     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 817 }
 818
 819 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 820     /* power_control should be set to maximum latency. Again,
 821      * default to 0 and set by private hook
 822      */
 823     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 824       .access = PL1_RW, .resetvalue = 0,
 825       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 826     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 827       .access = PL1_RW, .resetvalue = 0,
 828       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 829     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 830       .access = PL1_RW, .resetvalue = 0,
 831       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 832     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 833       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 834     /* TLB lockdown control */
 835     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 836       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 837     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 838       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 839     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 840       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 841     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 842       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 843     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 844       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 845     REGINFO_SENTINEL
 846 };
 847
 848 static void cortex_a9_initfn(Object *obj)
 849 {
 850     ARMCPU *cpu = ARM_CPU(obj);
 851
 852     cpu->dtb_compatible = "arm,cortex-a9";
 853     set_feature(&cpu->env, ARM_FEATURE_V7);
 854     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 855     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 856     set_feature(&cpu->env, ARM_FEATURE_NEON);
 857     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 858     set_feature(&cpu->env, ARM_FEATURE_EL3);
 859     /* Note that A9 supports the MP extensions even for
 860      * A9UP and single-core A9MP (which are both different
 861      * and valid configurations; we don't model A9UP).
 862      */
 863     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 864     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 865     cpu->midr = 0x410fc090;
 866     cpu->reset_fpsid = 0x41033090;
 867     cpu->mvfr0 = 0x11110222;
 868     cpu->mvfr1 = 0x01111111;
 869     cpu->ctr = 0x80038003;
 870     cpu->reset_sctlr = 0x00c50078;
 871     cpu->id_pfr0 = 0x1031;
 872     cpu->id_pfr1 = 0x11;
 873     cpu->id_dfr0 = 0x000;
 874     cpu->id_afr0 = 0;
 875     cpu->id_mmfr0 = 0x00100103;
 876     cpu->id_mmfr1 = 0x20000000;
 877     cpu->id_mmfr2 = 0x01230000;
 878     cpu->id_mmfr3 = 0x00002111;
 879     cpu->id_isar0 = 0x00101111;
 880     cpu->id_isar1 = 0x13112111;
 881     cpu->id_isar2 = 0x21232041;
 882     cpu->id_isar3 = 0x11112131;
 883     cpu->id_isar4 = 0x00111142;
 884     cpu->dbgdidr = 0x35141000;
 885     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 886     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 887     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 888     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 889 }
 890
 891 #ifndef CONFIG_USER_ONLY
 892 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 893 {
 894     /* Linux wants the number of processors from here.
 895      * Might as well set the interrupt-controller bit too.
 896      */
 897     return ((smp_cpus - 1) << 24) | (1 << 23);
 898 }
 899 #endif
 900
 901 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 902 #ifndef CONFIG_USER_ONLY
 903     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 904       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 905       .writefn = arm_cp_write_ignore, },
 906 #endif
 907     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 908       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 909     REGINFO_SENTINEL
 910 };
 911
 912 static void cortex_a15_initfn(Object *obj)
 913 {
 914     ARMCPU *cpu = ARM_CPU(obj);
 915
 916     cpu->dtb_compatible = "arm,cortex-a15";
 917     set_feature(&cpu->env, ARM_FEATURE_V7);
 918     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 919     set_feature(&cpu->env, ARM_FEATURE_NEON);
 920     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 921     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 922     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 923     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 924     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 925     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 926     set_feature(&cpu->env, ARM_FEATURE_EL3);
 927     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 928     cpu->midr = 0x412fc0f1;
 929     cpu->reset_fpsid = 0x410430f0;
 930     cpu->mvfr0 = 0x10110222;
 931     cpu->mvfr1 = 0x11111111;
 932     cpu->ctr = 0x8444c004;
 933     cpu->reset_sctlr = 0x00c50078;
 934     cpu->id_pfr0 = 0x00001131;
 935     cpu->id_pfr1 = 0x00011011;
 936     cpu->id_dfr0 = 0x02010555;
 937     cpu->id_afr0 = 0x00000000;
 938     cpu->id_mmfr0 = 0x10201105;
 939     cpu->id_mmfr1 = 0x20000000;
 940     cpu->id_mmfr2 = 0x01240000;
 941     cpu->id_mmfr3 = 0x02102211;
 942     cpu->id_isar0 = 0x02101110;
 943     cpu->id_isar1 = 0x13112111;
 944     cpu->id_isar2 = 0x21232041;
 945     cpu->id_isar3 = 0x11112131;
 946     cpu->id_isar4 = 0x10011142;
 947     cpu->dbgdidr = 0x3515f021;
 948     cpu->clidr = 0x0a200023;
 949     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 950     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 951     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 952     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 953 }
 954
 955 static void ti925t_initfn(Object *obj)
 956 {
 957     ARMCPU *cpu = ARM_CPU(obj);
 958     set_feature(&cpu->env, ARM_FEATURE_V4T);
 959     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 960     cpu->midr = ARM_CPUID_TI925T;
 961     cpu->ctr = 0x5109149;
 962     cpu->reset_sctlr = 0x00000070;
 963 }
 964
 965 static void sa1100_initfn(Object *obj)
 966 {
 967     ARMCPU *cpu = ARM_CPU(obj);
 968
 969     cpu->dtb_compatible = "intel,sa1100";
 970     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 971     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 972     cpu->midr = 0x4401A11B;
 973     cpu->reset_sctlr = 0x00000070;
 974 }
 975
 976 static void sa1110_initfn(Object *obj)
 977 {
 978     ARMCPU *cpu = ARM_CPU(obj);
 979     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 980     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 981     cpu->midr = 0x6901B119;
 982     cpu->reset_sctlr = 0x00000070;
 983 }
 984
 985 static void pxa250_initfn(Object *obj)
 986 {
 987     ARMCPU *cpu = ARM_CPU(obj);
 988
 989     cpu->dtb_compatible = "marvell,xscale";
 990     set_feature(&cpu->env, ARM_FEATURE_V5);
 991     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 992     cpu->midr = 0x69052100;
 993     cpu->ctr = 0xd172172;
 994     cpu->reset_sctlr = 0x00000078;
 995 }
 996
 997 static void pxa255_initfn(Object *obj)
 998 {
 999     ARMCPU *cpu = ARM_CPU(obj);
1000
1001     cpu->dtb_compatible = "marvell,xscale";
1002     set_feature(&cpu->env, ARM_FEATURE_V5);
1003     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1004     cpu->midr = 0x69052d00;
1005     cpu->ctr = 0xd172172;
1006     cpu->reset_sctlr = 0x00000078;
1007 }
1008
1009 static void pxa260_initfn(Object *obj)
1010 {
1011     ARMCPU *cpu = ARM_CPU(obj);
1012
1013     cpu->dtb_compatible = "marvell,xscale";
1014     set_feature(&cpu->env, ARM_FEATURE_V5);
1015     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1016     cpu->midr = 0x69052903;
1017     cpu->ctr = 0xd172172;
1018     cpu->reset_sctlr = 0x00000078;
1019 }
1020
1021 static void pxa261_initfn(Object *obj)
1022 {
1023     ARMCPU *cpu = ARM_CPU(obj);
1024
1025     cpu->dtb_compatible = "marvell,xscale";
1026     set_feature(&cpu->env, ARM_FEATURE_V5);
1027     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1028     cpu->midr = 0x69052d05;
1029     cpu->ctr = 0xd172172;
1030     cpu->reset_sctlr = 0x00000078;
1031 }
1032
1033 static void pxa262_initfn(Object *obj)
1034 {
1035     ARMCPU *cpu = ARM_CPU(obj);
1036
1037     cpu->dtb_compatible = "marvell,xscale";
1038     set_feature(&cpu->env, ARM_FEATURE_V5);
1039     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1040     cpu->midr = 0x69052d06;
1041     cpu->ctr = 0xd172172;
1042     cpu->reset_sctlr = 0x00000078;
1043 }
1044
1045 static void pxa270a0_initfn(Object *obj)
1046 {
1047     ARMCPU *cpu = ARM_CPU(obj);
1048
1049     cpu->dtb_compatible = "marvell,xscale";
1050     set_feature(&cpu->env, ARM_FEATURE_V5);
1051     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1052     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1053     cpu->midr = 0x69054110;
1054     cpu->ctr = 0xd172172;
1055     cpu->reset_sctlr = 0x00000078;
1056 }
1057
1058 static void pxa270a1_initfn(Object *obj)
1059 {
1060     ARMCPU *cpu = ARM_CPU(obj);
1061
1062     cpu->dtb_compatible = "marvell,xscale";
1063     set_feature(&cpu->env, ARM_FEATURE_V5);
1064     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1065     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1066     cpu->midr = 0x69054111;
1067     cpu->ctr = 0xd172172;
1068     cpu->reset_sctlr = 0x00000078;
1069 }
1070
1071 static void pxa270b0_initfn(Object *obj)
1072 {
1073     ARMCPU *cpu = ARM_CPU(obj);
1074
1075     cpu->dtb_compatible = "marvell,xscale";
1076     set_feature(&cpu->env, ARM_FEATURE_V5);
1077     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1078     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1079     cpu->midr = 0x69054112;
1080     cpu->ctr = 0xd172172;
1081     cpu->reset_sctlr = 0x00000078;
1082 }
1083
1084 static void pxa270b1_initfn(Object *obj)
1085 {
1086     ARMCPU *cpu = ARM_CPU(obj);
1087
1088     cpu->dtb_compatible = "marvell,xscale";
1089     set_feature(&cpu->env, ARM_FEATURE_V5);
1090     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1091     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1092     cpu->midr = 0x69054113;
1093     cpu->ctr = 0xd172172;
1094     cpu->reset_sctlr = 0x00000078;
1095 }
1096
1097 static void pxa270c0_initfn(Object *obj)
1098 {
1099     ARMCPU *cpu = ARM_CPU(obj);
1100
1101     cpu->dtb_compatible = "marvell,xscale";
1102     set_feature(&cpu->env, ARM_FEATURE_V5);
1103     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1104     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1105     cpu->midr = 0x69054114;
1106     cpu->ctr = 0xd172172;
1107     cpu->reset_sctlr = 0x00000078;
1108 }
1109
1110 static void pxa270c5_initfn(Object *obj)
1111 {
1112     ARMCPU *cpu = ARM_CPU(obj);
1113
1114     cpu->dtb_compatible = "marvell,xscale";
1115     set_feature(&cpu->env, ARM_FEATURE_V5);
1116     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1117     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1118     cpu->midr = 0x69054117;
1119     cpu->ctr = 0xd172172;
1120     cpu->reset_sctlr = 0x00000078;
1121 }
1122
1123 #ifdef CONFIG_USER_ONLY
1124 static void arm_any_initfn(Object *obj)
1125 {
1126     ARMCPU *cpu = ARM_CPU(obj);
1127     set_feature(&cpu->env, ARM_FEATURE_V8);
1128     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1129     set_feature(&cpu->env, ARM_FEATURE_NEON);
1130     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1131     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1132     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1133     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1134     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1135     set_feature(&cpu->env, ARM_FEATURE_CRC);
1136     cpu->midr = 0xffffffff;
1137 }
1138 #endif
1139
1140 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1141
1142 typedef struct ARMCPUInfo {
1143     const char *name;
1144     void (*initfn)(Object *obj);
1145     void (*class_init)(ObjectClass *oc, void *data);
1146 } ARMCPUInfo;
1147
1148 static const ARMCPUInfo arm_cpus[] = {
1149 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1150     { .name = "arm926",      .initfn = arm926_initfn },
1151     { .name = "arm946",      .initfn = arm946_initfn },
1152     { .name = "arm1026",     .initfn = arm1026_initfn },
1153     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1154      * older core than plain "arm1136". In particular this does not
1155      * have the v6K features.
1156      */
1157     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1158     { .name = "arm1136",     .initfn = arm1136_initfn },
1159     { .name = "arm1176",     .initfn = arm1176_initfn },
1160     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1161     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1162                              .class_init = arm_v7m_class_init },
1163     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1164     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1165     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1166     { .name = "ti925t",      .initfn = ti925t_initfn },
1167     { .name = "sa1100",      .initfn = sa1100_initfn },
1168     { .name = "sa1110",      .initfn = sa1110_initfn },
1169     { .name = "pxa250",      .initfn = pxa250_initfn },
1170     { .name = "pxa255",      .initfn = pxa255_initfn },
1171     { .name = "pxa260",      .initfn = pxa260_initfn },
1172     { .name = "pxa261",      .initfn = pxa261_initfn },
1173     { .name = "pxa262",      .initfn = pxa262_initfn },
1174     /* "pxa270" is an alias for "pxa270-a0" */
1175     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1176     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1177     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1178     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1179     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1180     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1181     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1182 #ifdef CONFIG_USER_ONLY
1183     { .name = "any",         .initfn = arm_any_initfn },
1184 #endif
1185 #endif
1186     { .name = NULL }
1187 };
1188
1189 static Property arm_cpu_properties[] = {
1190     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1191     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1192     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1193     DEFINE_PROP_END_OF_LIST()
1194 };
1195
1196 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1197 {
1198     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1199     CPUClass *cc = CPU_CLASS(acc);
1200     DeviceClass *dc = DEVICE_CLASS(oc);
1201
1202     acc->parent_realize = dc->realize;
1203     dc->realize = arm_cpu_realizefn;
1204     dc->props = arm_cpu_properties;
1205
1206     acc->parent_reset = cc->reset;
1207     cc->reset = arm_cpu_reset;
1208
1209     cc->class_by_name = arm_cpu_class_by_name;
1210     cc->has_work = arm_cpu_has_work;
1211     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1212     cc->dump_state = arm_cpu_dump_state;
1213     cc->set_pc = arm_cpu_set_pc;
1214     cc->gdb_read_register = arm_cpu_gdb_read_register;
1215     cc->gdb_write_register = arm_cpu_gdb_write_register;
1216 #ifdef CONFIG_USER_ONLY
1217     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1218 #else
1219     cc->do_interrupt = arm_cpu_do_interrupt;
1220     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1221     cc->vmsd = &vmstate_arm_cpu;
1222     cc->virtio_is_big_endian = arm_cpu_is_big_endian;
1223 #endif
1224     cc->gdb_num_core_regs = 26;
1225     cc->gdb_core_xml_file = "arm-core.xml";
1226     cc->gdb_stop_before_watchpoint = true;
1227     cc->debug_excp_handler = arm_debug_excp_handler;
1228 }
1229
1230 static void cpu_register(const ARMCPUInfo *info)
1231 {
1232     TypeInfo type_info = {
1233         .parent = TYPE_ARM_CPU,
1234         .instance_size = sizeof(ARMCPU),
1235         .instance_init = info->initfn,
1236         .class_size = sizeof(ARMCPUClass),
1237         .class_init = info->class_init,
1238     };
1239
1240     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1241     type_register(&type_info);
1242     g_free((void *)type_info.name);
1243 }
1244
1245 static const TypeInfo arm_cpu_type_info = {
1246     .name = TYPE_ARM_CPU,
1247     .parent = TYPE_CPU,
1248     .instance_size = sizeof(ARMCPU),
1249     .instance_init = arm_cpu_initfn,
1250     .instance_post_init = arm_cpu_post_init,
1251     .instance_finalize = arm_cpu_finalizefn,
1252     .abstract = true,
1253     .class_size = sizeof(ARMCPUClass),
1254     .class_init = arm_cpu_class_init,
1255 };
1256
1257 static void arm_cpu_register_types(void)
1258 {
1259     const ARMCPUInfo *info = arm_cpus;
1260
1261     type_register_static(&arm_cpu_type_info);
1262
1263     while (info->name) {
1264         cpu_register(info);
1265         info++;
1266     }
1267 }
1268
1269 type_init(arm_cpu_register_types)