hw/riscv/sifive_u.c

   1 /*
   2  * QEMU RISC-V Board Compatible with SiFive Freedom U SDK
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, [email protected]
   5  * Copyright (c) 2017 SiFive, Inc.
   6  *
   7  * Provides a board compatible with the SiFive Freedom U SDK:
   8  *
   9  * 0) UART
  10  * 1) CLINT (Core Level Interruptor)
  11  * 2) PLIC (Platform Level Interrupt Controller)
  12  *
  13  * This board currently uses a hardcoded devicetree that indicates one hart.
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms and conditions of the GNU General Public License,
  17  * version 2 or later, as published by the Free Software Foundation.
  18  *
  19  * This program is distributed in the hope it will be useful, but WITHOUT
  20  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  22  * more details.
  23  *
  24  * You should have received a copy of the GNU General Public License along with
  25  * this program.  If not, see <http://www.gnu.org/licenses/>.
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qemu/log.h"
  30 #include "qemu/error-report.h"
  31 #include "qapi/error.h"
  32 #include "hw/hw.h"
  33 #include "hw/boards.h"
  34 #include "hw/loader.h"
  35 #include "hw/sysbus.h"
  36 #include "hw/char/serial.h"
  37 #include "target/riscv/cpu.h"
  38 #include "hw/riscv/riscv_hart.h"
  39 #include "hw/riscv/sifive_plic.h"
  40 #include "hw/riscv/sifive_clint.h"
  41 #include "hw/riscv/sifive_uart.h"
  42 #include "hw/riscv/sifive_prci.h"
  43 #include "hw/riscv/sifive_u.h"
  44 #include "chardev/char.h"
  45 #include "sysemu/arch_init.h"
  46 #include "sysemu/device_tree.h"
  47 #include "exec/address-spaces.h"
  48 #include "elf.h"
  49
  50 static const struct MemmapEntry {
  51     hwaddr base;
  52     hwaddr size;
  53 } sifive_u_memmap[] = {
  54     [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
  55     [SIFIVE_U_MROM] =     {     0x1000,     0x2000 },
  56     [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
  57     [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
  58     [SIFIVE_U_UART0] =    { 0x10013000,     0x1000 },
  59     [SIFIVE_U_UART1] =    { 0x10023000,     0x1000 },
  60     [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
  61 };
  62
  63 static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len)
  64 {
  65     int i;
  66     for (i = 0; i < (len >> 2); i++) {
  67         stl_phys(&address_space_memory, pa + (i << 2), rom[i]);
  68     }
  69 }
  70
  71 static uint64_t load_kernel(const char *kernel_filename)
  72 {
  73     uint64_t kernel_entry, kernel_high;
  74
  75     if (load_elf(kernel_filename, NULL, NULL,
  76                  &kernel_entry, NULL, &kernel_high,
  77                  0, ELF_MACHINE, 1, 0) < 0) {
  78         error_report("qemu: could not load kernel '%s'", kernel_filename);
  79         exit(1);
  80     }
  81     return kernel_entry;
  82 }
  83
  84 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
  85     uint64_t mem_size, const char *cmdline)
  86 {
  87     void *fdt;
  88     int cpu;
  89     uint32_t *cells;
  90     char *nodename;
  91     uint32_t plic_phandle;
  92
  93     fdt = s->fdt = create_device_tree(&s->fdt_size);
  94     if (!fdt) {
  95         error_report("create_device_tree() failed");
  96         exit(1);
  97     }
  98
  99     qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu");
 100     qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev");
 101     qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
 102     qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
 103
 104     qemu_fdt_add_subnode(fdt, "/soc");
 105     qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
 106     qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc");
 107     qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2);
 108     qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
 109
 110     nodename = g_strdup_printf("/memory@%lx",
 111         (long)memmap[SIFIVE_U_DRAM].base);
 112     qemu_fdt_add_subnode(fdt, nodename);
 113     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 114         memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
 115         mem_size >> 32, mem_size);
 116     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
 117     g_free(nodename);
 118
 119     qemu_fdt_add_subnode(fdt, "/cpus");
 120     qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency",
 121         SIFIVE_CLINT_TIMEBASE_FREQ);
 122     qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0);
 123     qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1);
 124
 125     for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
 126         nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
 127         char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 128         char *isa = riscv_isa_string(&s->soc.harts[cpu]);
 129         qemu_fdt_add_subnode(fdt, nodename);
 130         qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
 131                               SIFIVE_U_CLOCK_FREQ);
 132         qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
 133         qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
 134         qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
 135         qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
 136         qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
 137         qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
 138         qemu_fdt_add_subnode(fdt, intc);
 139         qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
 140         qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
 141         qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
 142         qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
 143         qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
 144         g_free(isa);
 145         g_free(intc);
 146         g_free(nodename);
 147     }
 148
 149     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 150     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 151         nodename =
 152             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 153         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 154         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 155         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT);
 156         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 157         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER);
 158         g_free(nodename);
 159     }
 160     nodename = g_strdup_printf("/soc/clint@%lx",
 161         (long)memmap[SIFIVE_U_CLINT].base);
 162     qemu_fdt_add_subnode(fdt, nodename);
 163     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
 164     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 165         0x0, memmap[SIFIVE_U_CLINT].base,
 166         0x0, memmap[SIFIVE_U_CLINT].size);
 167     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 168         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 169     g_free(cells);
 170     g_free(nodename);
 171
 172     cells =  g_new0(uint32_t, s->soc.num_harts * 4);
 173     for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
 174         nodename =
 175             g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
 176         uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename);
 177         cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle);
 178         cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT);
 179         cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle);
 180         cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT);
 181         g_free(nodename);
 182     }
 183     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
 184         (long)memmap[SIFIVE_U_PLIC].base);
 185     qemu_fdt_add_subnode(fdt, nodename);
 186     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
 187     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
 188     qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0);
 189     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
 190         cells, s->soc.num_harts * sizeof(uint32_t) * 4);
 191     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 192         0x0, memmap[SIFIVE_U_PLIC].base,
 193         0x0, memmap[SIFIVE_U_PLIC].size);
 194     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
 195     qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
 196     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
 197     qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
 198     qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
 199     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
 200     g_free(cells);
 201     g_free(nodename);
 202
 203     nodename = g_strdup_printf("/uart@%lx",
 204         (long)memmap[SIFIVE_U_UART0].base);
 205     qemu_fdt_add_subnode(fdt, nodename);
 206     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
 207     qemu_fdt_setprop_cells(fdt, nodename, "reg",
 208         0x0, memmap[SIFIVE_U_UART0].base,
 209         0x0, memmap[SIFIVE_U_UART0].size);
 210     qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle);
 211     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1);
 212
 213     qemu_fdt_add_subnode(fdt, "/chosen");
 214     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
 215     qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
 216     g_free(nodename);
 217 }
 218
 219 static void riscv_sifive_u_init(MachineState *machine)
 220 {
 221     const struct MemmapEntry *memmap = sifive_u_memmap;
 222
 223     SiFiveUState *s = g_new0(SiFiveUState, 1);
 224     MemoryRegion *sys_memory = get_system_memory();
 225     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
 226     MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
 227
 228     /* Initialize SOC */
 229     object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY);
 230     object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
 231                               &error_abort);
 232     object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type",
 233                             &error_abort);
 234     object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
 235                             &error_abort);
 236     object_property_set_bool(OBJECT(&s->soc), true, "realized",
 237                             &error_abort);
 238
 239     /* register RAM */
 240     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
 241                            machine->ram_size, &error_fatal);
 242     memory_region_add_subregion(sys_memory, memmap[SIFIVE_U_DRAM].base,
 243         main_mem);
 244
 245     /* create device tree */
 246     create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
 247
 248     /* boot rom */
 249     memory_region_init_ram(boot_rom, NULL, "riscv.sifive.u.mrom",
 250                            memmap[SIFIVE_U_MROM].base, &error_fatal);
 251     memory_region_set_readonly(boot_rom, true);
 252     memory_region_add_subregion(sys_memory, 0x0, boot_rom);
 253
 254     if (machine->kernel_filename) {
 255         load_kernel(machine->kernel_filename);
 256     }
 257
 258     /* reset vector */
 259     uint32_t reset_vec[8] = {
 260         0x00000297,                    /* 1:  auipc  t0, %pcrel_hi(dtb) */
 261         0x02028593,                    /*     addi   a1, t0, %pcrel_lo(1b) */
 262         0xf1402573,                    /*     csrr   a0, mhartid  */
 263 #if defined(TARGET_RISCV32)
 264         0x0182a283,                    /*     lw     t0, 24(t0) */
 265 #elif defined(TARGET_RISCV64)
 266         0x0182b283,                    /*     ld     t0, 24(t0) */
 267 #endif
 268         0x00028067,                    /*     jr     t0 */
 269         0x00000000,
 270         memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */
 271         0x00000000,
 272                                        /* dtb: */
 273     };
 274
 275     /* copy in the reset vector */
 276     copy_le32_to_phys(memmap[SIFIVE_U_MROM].base, reset_vec, sizeof(reset_vec));
 277
 278     /* copy in the device tree */
 279     qemu_fdt_dumpdtb(s->fdt, s->fdt_size);
 280     cpu_physical_memory_write(memmap[SIFIVE_U_MROM].base +
 281         sizeof(reset_vec), s->fdt, s->fdt_size);
 282
 283     /* MMIO */
 284     s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
 285         (char *)SIFIVE_U_PLIC_HART_CONFIG,
 286         SIFIVE_U_PLIC_NUM_SOURCES,
 287         SIFIVE_U_PLIC_NUM_PRIORITIES,
 288         SIFIVE_U_PLIC_PRIORITY_BASE,
 289         SIFIVE_U_PLIC_PENDING_BASE,
 290         SIFIVE_U_PLIC_ENABLE_BASE,
 291         SIFIVE_U_PLIC_ENABLE_STRIDE,
 292         SIFIVE_U_PLIC_CONTEXT_BASE,
 293         SIFIVE_U_PLIC_CONTEXT_STRIDE,
 294         memmap[SIFIVE_U_PLIC].size);
 295     sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART0].base,
 296         serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART0_IRQ]);
 297     /* sifive_uart_create(sys_memory, memmap[SIFIVE_U_UART1].base,
 298         serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_U_UART1_IRQ]); */
 299     sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
 300         memmap[SIFIVE_U_CLINT].size, smp_cpus,
 301         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
 302 }
 303
 304 static int riscv_sifive_u_sysbus_device_init(SysBusDevice *sysbusdev)
 305 {
 306     return 0;
 307 }
 308
 309 static void riscv_sifive_u_class_init(ObjectClass *klass, void *data)
 310 {
 311     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 312     k->init = riscv_sifive_u_sysbus_device_init;
 313 }
 314
 315 static const TypeInfo riscv_sifive_u_device = {
 316     .name          = TYPE_SIFIVE_U,
 317     .parent        = TYPE_SYS_BUS_DEVICE,
 318     .instance_size = sizeof(SiFiveUState),
 319     .class_init    = riscv_sifive_u_class_init,
 320 };
 321
 322 static void riscv_sifive_u_register_types(void)
 323 {
 324     type_register_static(&riscv_sifive_u_device);
 325 }
 326
 327 type_init(riscv_sifive_u_register_types);
 328
 329 static void riscv_sifive_u_machine_init(MachineClass *mc)
 330 {
 331     mc->desc = "RISC-V Board compatible with SiFive U SDK";
 332     mc->init = riscv_sifive_u_init;
 333     mc->max_cpus = 1;
 334 }
 335
 336 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init)