target-mips/dsp_helper.c

   1 /*
   2  * MIPS ASE DSP Instruction emulation helpers for QEMU.
   3  *
   4  * Copyright (c) 2012  Jia Liu <[email protected]>
   5  *                     Dongxue Zhang <[email protected]>
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "cpu.h"
  21 #include "helper.h"
  22
  23 /* As the byte ordering doesn't matter, i.e. all columns are treated
  24    identically, these unions can be used directly.  */
  25 typedef union {
  26     uint8_t  ub[4];
  27     int8_t   sb[4];
  28     uint16_t uh[2];
  29     int16_t  sh[2];
  30     uint32_t uw[1];
  31     int32_t  sw[1];
  32 } DSP32Value;
  33
  34 typedef union {
  35     uint8_t  ub[8];
  36     int8_t   sb[8];
  37     uint16_t uh[4];
  38     int16_t  sh[4];
  39     uint32_t uw[2];
  40     int32_t  sw[2];
  41     uint64_t ul[1];
  42     int64_t  sl[1];
  43 } DSP64Value;
  44
  45 /*** MIPS DSP internal functions begin ***/
  46 #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
  47 #define MIPSDSP_OVERFLOW_ADD(a, b, c, d) (~(a ^ b) & (a ^ c) & d)
  48 #define MIPSDSP_OVERFLOW_SUB(a, b, c, d) ((a ^ b) & (a ^ c) & d)
  49
  50 static inline void set_DSPControl_overflow_flag(uint32_t flag, int position,
  51                                                 CPUMIPSState *env)
  52 {
  53     env->active_tc.DSPControl |= (target_ulong)flag << position;
  54 }
  55
  56 static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env)
  57 {
  58     env->active_tc.DSPControl |= (target_ulong)flag << 13;
  59 }
  60
  61 static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env)
  62 {
  63     return (env->active_tc.DSPControl >> 13) & 0x01;
  64 }
  65
  66 static inline void set_DSPControl_24(uint32_t flag, int len, CPUMIPSState *env)
  67 {
  68   uint32_t filter;
  69
  70   filter = ((0x01 << len) - 1) << 24;
  71   filter = ~filter;
  72
  73   env->active_tc.DSPControl &= filter;
  74   env->active_tc.DSPControl |= (target_ulong)flag << 24;
  75 }
  76
  77 static inline uint32_t get_DSPControl_24(int len, CPUMIPSState *env)
  78 {
  79   uint32_t filter;
  80
  81   filter = (0x01 << len) - 1;
  82
  83   return (env->active_tc.DSPControl >> 24) & filter;
  84 }
  85
  86 static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env)
  87 {
  88     target_ulong dspc;
  89
  90     dspc = env->active_tc.DSPControl;
  91 #ifndef TARGET_MIPS64
  92     dspc = dspc & 0xFFFFFFC0;
  93     dspc |= pos;
  94 #else
  95     dspc = dspc & 0xFFFFFF80;
  96     dspc |= pos;
  97 #endif
  98     env->active_tc.DSPControl = dspc;
  99 }
 100
 101 static inline uint32_t get_DSPControl_pos(CPUMIPSState *env)
 102 {
 103     target_ulong dspc;
 104     uint32_t pos;
 105
 106     dspc = env->active_tc.DSPControl;
 107
 108 #ifndef TARGET_MIPS64
 109     pos = dspc & 0x3F;
 110 #else
 111     pos = dspc & 0x7F;
 112 #endif
 113
 114     return pos;
 115 }
 116
 117 static inline void set_DSPControl_efi(uint32_t flag, CPUMIPSState *env)
 118 {
 119     env->active_tc.DSPControl &= 0xFFFFBFFF;
 120     env->active_tc.DSPControl |= (target_ulong)flag << 14;
 121 }
 122
 123 #define DO_MIPS_SAT_ABS(size)                                          \
 124 static inline int##size##_t mipsdsp_sat_abs##size(int##size##_t a,         \
 125                                                   CPUMIPSState *env)   \
 126 {                                                                      \
 127     if (a == INT##size##_MIN) {                                        \
 128         set_DSPControl_overflow_flag(1, 20, env);                      \
 129         return INT##size##_MAX;                                        \
 130     } else {                                                           \
 131         return MIPSDSP_ABS(a);                                         \
 132     }                                                                  \
 133 }
 134 DO_MIPS_SAT_ABS(8)
 135 DO_MIPS_SAT_ABS(16)
 136 DO_MIPS_SAT_ABS(32)
 137 #undef DO_MIPS_SAT_ABS
 138
 139 /* get sum value */
 140 static inline int16_t mipsdsp_add_i16(int16_t a, int16_t b, CPUMIPSState *env)
 141 {
 142     int16_t tempI;
 143
 144     tempI = a + b;
 145
 146     if (MIPSDSP_OVERFLOW_ADD(a, b, tempI, 0x8000)) {
 147         set_DSPControl_overflow_flag(1, 20, env);
 148     }
 149
 150     return tempI;
 151 }
 152
 153 static inline int16_t mipsdsp_sat_add_i16(int16_t a, int16_t b,
 154                                           CPUMIPSState *env)
 155 {
 156     int16_t tempS;
 157
 158     tempS = a + b;
 159
 160     if (MIPSDSP_OVERFLOW_ADD(a, b, tempS, 0x8000)) {
 161         if (a > 0) {
 162             tempS = 0x7FFF;
 163         } else {
 164             tempS = 0x8000;
 165         }
 166         set_DSPControl_overflow_flag(1, 20, env);
 167     }
 168
 169     return tempS;
 170 }
 171
 172 static inline int32_t mipsdsp_sat_add_i32(int32_t a, int32_t b,
 173                                           CPUMIPSState *env)
 174 {
 175     int32_t tempI;
 176
 177     tempI = a + b;
 178
 179     if (MIPSDSP_OVERFLOW_ADD(a, b, tempI, 0x80000000)) {
 180         if (a > 0) {
 181             tempI = 0x7FFFFFFF;
 182         } else {
 183             tempI = 0x80000000;
 184         }
 185         set_DSPControl_overflow_flag(1, 20, env);
 186     }
 187
 188     return tempI;
 189 }
 190
 191 static inline uint8_t mipsdsp_add_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
 192 {
 193     uint16_t temp;
 194
 195     temp = (uint16_t)a + (uint16_t)b;
 196
 197     if (temp & 0x0100) {
 198         set_DSPControl_overflow_flag(1, 20, env);
 199     }
 200
 201     return temp & 0xFF;
 202 }
 203
 204 static inline uint16_t mipsdsp_add_u16(uint16_t a, uint16_t b,
 205                                        CPUMIPSState *env)
 206 {
 207     uint32_t temp;
 208
 209     temp = (uint32_t)a + (uint32_t)b;
 210
 211     if (temp & 0x00010000) {
 212         set_DSPControl_overflow_flag(1, 20, env);
 213     }
 214
 215     return temp & 0xFFFF;
 216 }
 217
 218 static inline uint8_t mipsdsp_sat_add_u8(uint8_t a, uint8_t b,
 219                                          CPUMIPSState *env)
 220 {
 221     uint8_t  result;
 222     uint16_t temp;
 223
 224     temp = (uint16_t)a + (uint16_t)b;
 225     result = temp & 0xFF;
 226
 227     if (0x0100 & temp) {
 228         result = 0xFF;
 229         set_DSPControl_overflow_flag(1, 20, env);
 230     }
 231
 232     return result;
 233 }
 234
 235 static inline uint16_t mipsdsp_sat_add_u16(uint16_t a, uint16_t b,
 236                                            CPUMIPSState *env)
 237 {
 238     uint16_t result;
 239     uint32_t temp;
 240
 241     temp = (uint32_t)a + (uint32_t)b;
 242     result = temp & 0xFFFF;
 243
 244     if (0x00010000 & temp) {
 245         result = 0xFFFF;
 246         set_DSPControl_overflow_flag(1, 20, env);
 247     }
 248
 249     return result;
 250 }
 251
 252 static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a,
 253                                             CPUMIPSState *env)
 254 {
 255     int64_t temp;
 256     int32_t temp32, temp31, result;
 257     int64_t temp_sum;
 258
 259 #ifndef TARGET_MIPS64
 260     temp = ((uint64_t)env->active_tc.HI[acc] << 32) |
 261            (uint64_t)env->active_tc.LO[acc];
 262 #else
 263     temp = (uint64_t)env->active_tc.LO[acc];
 264 #endif
 265
 266     temp_sum = (int64_t)a + temp;
 267
 268     temp32 = (temp_sum >> 32) & 0x01;
 269     temp31 = (temp_sum >> 31) & 0x01;
 270     result = temp_sum & 0xFFFFFFFF;
 271
 272     if (temp32 != temp31) {
 273         if (temp32 == 0) {
 274             result = 0x7FFFFFFF;
 275         } else {
 276             result = 0x80000000;
 277         }
 278         set_DSPControl_overflow_flag(1, 16 + acc, env);
 279     }
 280
 281     return result;
 282 }
 283
 284 /* a[0] is LO, a[1] is HI. */
 285 static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret,
 286                                              int32_t ac,
 287                                              int64_t *a,
 288                                              CPUMIPSState *env)
 289 {
 290     bool temp64;
 291
 292     ret[0] = env->active_tc.LO[ac] + a[0];
 293     ret[1] = env->active_tc.HI[ac] + a[1];
 294
 295     if (((uint64_t)ret[0] < (uint64_t)env->active_tc.LO[ac]) &&
 296         ((uint64_t)ret[0] < (uint64_t)a[0])) {
 297         ret[1] += 1;
 298     }
 299     temp64 = ret[1] & 1;
 300     if (temp64 != ((ret[0] >> 63) & 0x01)) {
 301         if (temp64) {
 302             ret[0] = (0x01ull << 63);
 303             ret[1] = ~0ull;
 304         } else {
 305             ret[0] = (0x01ull << 63) - 1;
 306             ret[1] = 0x00;
 307         }
 308         set_DSPControl_overflow_flag(1, 16 + ac, env);
 309     }
 310 }
 311
 312 static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret,
 313                                              int32_t ac,
 314                                              int64_t *a,
 315                                              CPUMIPSState *env)
 316 {
 317     bool temp64;
 318
 319     ret[0] = env->active_tc.LO[ac] - a[0];
 320     ret[1] = env->active_tc.HI[ac] - a[1];
 321
 322     if ((uint64_t)ret[0] > (uint64_t)env->active_tc.LO[ac]) {
 323         ret[1] -= 1;
 324     }
 325     temp64 = ret[1] & 1;
 326     if (temp64 != ((ret[0] >> 63) & 0x01)) {
 327         if (temp64) {
 328             ret[0] = (0x01ull << 63);
 329             ret[1] = ~0ull;
 330         } else {
 331             ret[0] = (0x01ull << 63) - 1;
 332             ret[1] = 0x00;
 333         }
 334         set_DSPControl_overflow_flag(1, 16 + ac, env);
 335     }
 336 }
 337
 338 static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b,
 339                                           CPUMIPSState *env)
 340 {
 341     int32_t temp;
 342
 343     temp = (int32_t)a * (int32_t)b;
 344
 345     if ((temp > (int)0x7FFF) || (temp < (int)0xFFFF8000)) {
 346         set_DSPControl_overflow_flag(1, 21, env);
 347     }
 348     temp &= 0x0000FFFF;
 349
 350     return temp;
 351 }
 352
 353 static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b)
 354 {
 355     return a * b;
 356 }
 357
 358 static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b)
 359 {
 360     return a * b;
 361 }
 362
 363 static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b,
 364                                                 CPUMIPSState *env)
 365 {
 366     int32_t temp;
 367
 368     temp = (int32_t)a * (int32_t)b;
 369
 370     if (temp > (int)0x7FFF) {
 371         temp = 0x00007FFF;
 372         set_DSPControl_overflow_flag(1, 21, env);
 373     } else if (temp < (int)0xffff8000) {
 374         temp = 0xFFFF8000;
 375         set_DSPControl_overflow_flag(1, 21, env);
 376     }
 377     temp &= 0x0000FFFF;
 378
 379     return temp;
 380 }
 381
 382 static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b,
 383                                                          CPUMIPSState *env)
 384 {
 385     int32_t temp;
 386
 387     if ((a == 0x8000) && (b == 0x8000)) {
 388         temp = 0x7FFFFFFF;
 389         set_DSPControl_overflow_flag(1, 21, env);
 390     } else {
 391         temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1;
 392     }
 393
 394     return temp;
 395 }
 396
 397 /* right shift */
 398 static inline uint8_t mipsdsp_rshift_u8(uint8_t a, target_ulong mov)
 399 {
 400     return a >> mov;
 401 }
 402
 403 static inline uint16_t mipsdsp_rshift_u16(uint16_t a, target_ulong mov)
 404 {
 405     return a >> mov;
 406 }
 407
 408 static inline int8_t mipsdsp_rashift8(int8_t a, target_ulong mov)
 409 {
 410     return a >> mov;
 411 }
 412
 413 static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov)
 414 {
 415     return a >> mov;
 416 }
 417
 418 static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov)
 419 {
 420     return a >> mov;
 421 }
 422
 423 static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b)
 424 {
 425     int32_t temp;
 426
 427     temp = (int32_t)a + (int32_t)b;
 428
 429     return (temp >> 1) & 0xFFFF;
 430 }
 431
 432 /* round right shift */
 433 static inline int16_t mipsdsp_rrshift1_add_q16(int16_t a, int16_t b)
 434 {
 435     int32_t temp;
 436
 437     temp = (int32_t)a + (int32_t)b;
 438     temp += 1;
 439
 440     return (temp >> 1) & 0xFFFF;
 441 }
 442
 443 static inline int32_t mipsdsp_rshift1_add_q32(int32_t a, int32_t b)
 444 {
 445     int64_t temp;
 446
 447     temp = (int64_t)a + (int64_t)b;
 448
 449     return (temp >> 1) & 0xFFFFFFFF;
 450 }
 451
 452 static inline int32_t mipsdsp_rrshift1_add_q32(int32_t a, int32_t b)
 453 {
 454     int64_t temp;
 455
 456     temp = (int64_t)a + (int64_t)b;
 457     temp += 1;
 458
 459     return (temp >> 1) & 0xFFFFFFFF;
 460 }
 461
 462 static inline uint8_t mipsdsp_rshift1_add_u8(uint8_t a, uint8_t b)
 463 {
 464     uint16_t temp;
 465
 466     temp = (uint16_t)a + (uint16_t)b;
 467
 468     return (temp >> 1) & 0x00FF;
 469 }
 470
 471 static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b)
 472 {
 473     uint16_t temp;
 474
 475     temp = (uint16_t)a + (uint16_t)b + 1;
 476
 477     return (temp >> 1) & 0x00FF;
 478 }
 479
 480 static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b)
 481 {
 482     uint16_t temp;
 483
 484     temp = (uint16_t)a - (uint16_t)b;
 485
 486     return (temp >> 1) & 0x00FF;
 487 }
 488
 489 static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b)
 490 {
 491     uint16_t temp;
 492
 493     temp = (uint16_t)a - (uint16_t)b + 1;
 494
 495     return (temp >> 1) & 0x00FF;
 496 }
 497
 498 /*  128 bits long. p[0] is LO, p[1] is HI. */
 499 static inline void mipsdsp_rndrashift_short_acc(int64_t *p,
 500                                                 int32_t ac,
 501                                                 int32_t shift,
 502                                                 CPUMIPSState *env)
 503 {
 504     int64_t acc;
 505
 506     acc = ((int64_t)env->active_tc.HI[ac] << 32) |
 507           ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
 508     p[0] = (shift == 0) ? (acc << 1) : (acc >> (shift - 1));
 509     p[1] = (acc >> 63) & 0x01;
 510 }
 511
 512 /* 128 bits long. p[0] is LO, p[1] is HI */
 513 static inline void mipsdsp_rashift_acc(uint64_t *p,
 514                                        uint32_t ac,
 515                                        uint32_t shift,
 516                                        CPUMIPSState *env)
 517 {
 518     uint64_t tempB, tempA;
 519
 520     tempB = env->active_tc.HI[ac];
 521     tempA = env->active_tc.LO[ac];
 522     shift = shift & 0x1F;
 523
 524     if (shift == 0) {
 525         p[1] = tempB;
 526         p[0] = tempA;
 527     } else {
 528         p[0] = (tempB << (64 - shift)) | (tempA >> shift);
 529         p[1] = (int64_t)tempB >> shift;
 530     }
 531 }
 532
 533 /* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/
 534 static inline void mipsdsp_rndrashift_acc(uint64_t *p,
 535                                           uint32_t ac,
 536                                           uint32_t shift,
 537                                           CPUMIPSState *env)
 538 {
 539     int64_t tempB, tempA;
 540
 541     tempB = env->active_tc.HI[ac];
 542     tempA = env->active_tc.LO[ac];
 543     shift = shift & 0x3F;
 544
 545     if (shift == 0) {
 546         p[2] = tempB >> 63;
 547         p[1] = (tempB << 1) | (tempA >> 63);
 548         p[0] = tempA << 1;
 549     } else {
 550         p[0] = (tempB << (65 - shift)) | (tempA >> (shift - 1));
 551         p[1] = (int64_t)tempB >> (shift - 1);
 552         if (tempB >= 0) {
 553             p[2] = 0x0;
 554         } else {
 555             p[2] = ~0ull;
 556         }
 557     }
 558 }
 559
 560 static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b,
 561                                           CPUMIPSState *env)
 562 {
 563     int32_t temp;
 564
 565     if ((a == 0x8000) && (b == 0x8000)) {
 566         temp = 0x7FFFFFFF;
 567         set_DSPControl_overflow_flag(1, 16 + ac, env);
 568     } else {
 569         temp = ((int16_t)a * (int16_t)b) << 1;
 570     }
 571
 572     return temp;
 573 }
 574
 575 static inline int64_t mipsdsp_mul_q31_q31(int32_t ac, uint32_t a, uint32_t b,
 576                                           CPUMIPSState *env)
 577 {
 578     uint64_t temp;
 579
 580     if ((a == 0x80000000) && (b == 0x80000000)) {
 581         temp = (0x01ull << 63) - 1;
 582         set_DSPControl_overflow_flag(1, 16 + ac, env);
 583     } else {
 584         temp = ((uint64_t)a * (uint64_t)b) << 1;
 585     }
 586
 587     return temp;
 588 }
 589
 590 static inline uint16_t mipsdsp_mul_u8_u8(uint8_t a, uint8_t b)
 591 {
 592     return (uint16_t)a * (uint16_t)b;
 593 }
 594
 595 static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b,
 596                                           CPUMIPSState *env)
 597 {
 598     uint32_t tempI;
 599
 600     tempI = (uint32_t)a * (uint32_t)b;
 601     if (tempI > 0x0000FFFF) {
 602         tempI = 0x0000FFFF;
 603         set_DSPControl_overflow_flag(1, 21, env);
 604     }
 605
 606     return tempI & 0x0000FFFF;
 607 }
 608
 609 static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b)
 610 {
 611     return (uint64_t)a * (uint64_t)b;
 612 }
 613
 614 static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b,
 615                                                  CPUMIPSState *env)
 616 {
 617     uint32_t temp;
 618
 619     if ((a == 0x8000) && (b == 0x8000)) {
 620         temp = 0x7FFF0000;
 621         set_DSPControl_overflow_flag(1, 21, env);
 622     } else {
 623         temp = (a * b) << 1;
 624         temp = temp + 0x00008000;
 625     }
 626
 627     return (temp & 0xFFFF0000) >> 16;
 628 }
 629
 630 static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b,
 631                                                 CPUMIPSState *env)
 632 {
 633     int32_t temp;
 634
 635     if ((a == 0x8000) && (b == 0x8000)) {
 636         temp = 0x7FFF0000;
 637         set_DSPControl_overflow_flag(1, 21, env);
 638     } else {
 639         temp = (int16_t)a * (int16_t)b;
 640         temp = temp << 1;
 641     }
 642
 643     return (temp >> 16) & 0x0000FFFF;
 644 }
 645
 646 static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a,
 647                                                    CPUMIPSState *env)
 648 {
 649     int64_t temp;
 650
 651     temp = (int32_t)a + 0x00008000;
 652
 653     if (a > (int)0x7fff8000) {
 654         temp = 0x7FFFFFFF;
 655         set_DSPControl_overflow_flag(1, 22, env);
 656     }
 657
 658     return (temp >> 16) & 0xFFFF;
 659 }
 660
 661 static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a,
 662                                                     CPUMIPSState *env)
 663 {
 664     uint16_t mag;
 665     uint32_t sign;
 666
 667     sign = (a >> 15) & 0x01;
 668     mag = a & 0x7FFF;
 669
 670     if (sign == 0) {
 671         if (mag > 0x7F80) {
 672             set_DSPControl_overflow_flag(1, 22, env);
 673             return 0xFF;
 674         } else {
 675             return (mag >> 7) & 0xFFFF;
 676         }
 677     } else {
 678         set_DSPControl_overflow_flag(1, 22, env);
 679         return 0x00;
 680     }
 681 }
 682
 683 static inline uint8_t mipsdsp_lshift8(uint8_t a, uint8_t s, CPUMIPSState *env)
 684 {
 685     uint8_t sign;
 686     uint8_t discard;
 687
 688     if (s == 0) {
 689         return a;
 690     } else {
 691         sign = (a >> 7) & 0x01;
 692         if (sign != 0) {
 693             discard = (((0x01 << (8 - s)) - 1) << s) |
 694                       ((a >> (6 - (s - 1))) & ((0x01 << s) - 1));
 695         } else {
 696             discard = a >> (6 - (s - 1));
 697         }
 698
 699         if (discard != 0x00) {
 700             set_DSPControl_overflow_flag(1, 22, env);
 701         }
 702         return a << s;
 703     }
 704 }
 705
 706 static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s,
 707                                         CPUMIPSState *env)
 708 {
 709     uint8_t  sign;
 710     uint16_t discard;
 711
 712     if (s == 0) {
 713         return a;
 714     } else {
 715         sign = (a >> 15) & 0x01;
 716         if (sign != 0) {
 717             discard = (((0x01 << (16 - s)) - 1) << s) |
 718                       ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
 719         } else {
 720             discard = a >> (14 - (s - 1));
 721         }
 722
 723         if ((discard != 0x0000) && (discard != 0xFFFF)) {
 724             set_DSPControl_overflow_flag(1, 22, env);
 725         }
 726         return a << s;
 727     }
 728 }
 729
 730
 731 static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s,
 732                                         CPUMIPSState *env)
 733 {
 734     uint32_t discard;
 735
 736     if (s == 0) {
 737         return a;
 738     } else {
 739         discard = (int32_t)a >> (31 - (s - 1));
 740
 741         if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
 742             set_DSPControl_overflow_flag(1, 22, env);
 743         }
 744         return a << s;
 745     }
 746 }
 747
 748 static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s,
 749                                             CPUMIPSState *env)
 750 {
 751     uint8_t  sign;
 752     uint16_t discard;
 753
 754     if (s == 0) {
 755         return a;
 756     } else {
 757         sign = (a >> 15) & 0x01;
 758         if (sign != 0) {
 759             discard = (((0x01 << (16 - s)) - 1) << s) |
 760                       ((a >> (14 - (s - 1))) & ((0x01 << s) - 1));
 761         } else {
 762             discard = a >> (14 - (s - 1));
 763         }
 764
 765         if ((discard != 0x0000) && (discard != 0xFFFF)) {
 766             set_DSPControl_overflow_flag(1, 22, env);
 767             return (sign == 0) ? 0x7FFF : 0x8000;
 768         } else {
 769             return a << s;
 770         }
 771     }
 772 }
 773
 774 static inline uint32_t mipsdsp_sat32_lshift(uint32_t a, uint8_t s,
 775                                             CPUMIPSState *env)
 776 {
 777     uint8_t  sign;
 778     uint32_t discard;
 779
 780     if (s == 0) {
 781         return a;
 782     } else {
 783         sign = (a >> 31) & 0x01;
 784         if (sign != 0) {
 785             discard = (((0x01 << (32 - s)) - 1) << s) |
 786                       ((a >> (30 - (s - 1))) & ((0x01 << s) - 1));
 787         } else {
 788             discard = a >> (30 - (s - 1));
 789         }
 790
 791         if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) {
 792             set_DSPControl_overflow_flag(1, 22, env);
 793             return (sign == 0) ? 0x7FFFFFFF : 0x80000000;
 794         } else {
 795             return a << s;
 796         }
 797     }
 798 }
 799
 800 static inline uint8_t mipsdsp_rnd8_rashift(uint8_t a, uint8_t s)
 801 {
 802     uint32_t temp;
 803
 804     if (s == 0) {
 805         temp = (uint32_t)a << 1;
 806     } else {
 807         temp = (int32_t)(int8_t)a >> (s - 1);
 808     }
 809
 810     return (temp + 1) >> 1;
 811 }
 812
 813 static inline uint16_t mipsdsp_rnd16_rashift(uint16_t a, uint8_t s)
 814 {
 815     uint32_t temp;
 816
 817     if (s == 0) {
 818         temp = (uint32_t)a << 1;
 819     } else {
 820         temp = (int32_t)(int16_t)a >> (s - 1);
 821     }
 822
 823     return (temp + 1) >> 1;
 824 }
 825
 826 static inline uint32_t mipsdsp_rnd32_rashift(uint32_t a, uint8_t s)
 827 {
 828     int64_t temp;
 829
 830     if (s == 0) {
 831         temp = (uint64_t)a << 1;
 832     } else {
 833         temp = (int64_t)(int32_t)a >> (s - 1);
 834     }
 835     temp += 1;
 836
 837     return (temp >> 1) & 0xFFFFFFFFull;
 838 }
 839
 840 static inline uint16_t mipsdsp_sub_i16(int16_t a, int16_t b, CPUMIPSState *env)
 841 {
 842     int16_t  temp;
 843
 844     temp = a - b;
 845     if (MIPSDSP_OVERFLOW_SUB(a, b, temp, 0x8000)) {
 846         set_DSPControl_overflow_flag(1, 20, env);
 847     }
 848
 849     return temp;
 850 }
 851
 852 static inline uint16_t mipsdsp_sat16_sub(int16_t a, int16_t b,
 853                                          CPUMIPSState *env)
 854 {
 855     int16_t  temp;
 856
 857     temp = a - b;
 858     if (MIPSDSP_OVERFLOW_SUB(a, b, temp, 0x8000)) {
 859         if (a >= 0) {
 860             temp = 0x7FFF;
 861         } else {
 862             temp = 0x8000;
 863         }
 864         set_DSPControl_overflow_flag(1, 20, env);
 865     }
 866
 867     return temp;
 868 }
 869
 870 static inline uint32_t mipsdsp_sat32_sub(int32_t a, int32_t b,
 871                                          CPUMIPSState *env)
 872 {
 873     int32_t  temp;
 874
 875     temp = a - b;
 876     if (MIPSDSP_OVERFLOW_SUB(a, b, temp, 0x80000000)) {
 877         if (a >= 0) {
 878             temp = 0x7FFFFFFF;
 879         } else {
 880             temp = 0x80000000;
 881         }
 882         set_DSPControl_overflow_flag(1, 20, env);
 883     }
 884
 885     return temp & 0xFFFFFFFFull;
 886 }
 887
 888 static inline uint16_t mipsdsp_rshift1_sub_q16(int16_t a, int16_t b)
 889 {
 890     int32_t  temp;
 891
 892     temp = (int32_t)a - (int32_t)b;
 893
 894     return (temp >> 1) & 0x0000FFFF;
 895 }
 896
 897 static inline uint16_t mipsdsp_rrshift1_sub_q16(int16_t a, int16_t b)
 898 {
 899     int32_t  temp;
 900
 901     temp = (int32_t)a - (int32_t)b;
 902     temp += 1;
 903
 904     return (temp >> 1) & 0x0000FFFF;
 905 }
 906
 907 static inline uint32_t mipsdsp_rshift1_sub_q32(int32_t a, int32_t b)
 908 {
 909     int64_t  temp;
 910
 911     temp = (int64_t)a - (int64_t)b;
 912
 913     return (temp >> 1) & 0xFFFFFFFFull;
 914 }
 915
 916 static inline uint32_t mipsdsp_rrshift1_sub_q32(int32_t a, int32_t b)
 917 {
 918     int64_t  temp;
 919
 920     temp = (int64_t)a - (int64_t)b;
 921     temp += 1;
 922
 923     return (temp >> 1) & 0xFFFFFFFFull;
 924 }
 925
 926 static inline uint16_t mipsdsp_sub_u16_u16(uint16_t a, uint16_t b,
 927                                            CPUMIPSState *env)
 928 {
 929     uint8_t  temp16;
 930     uint32_t temp;
 931
 932     temp = (uint32_t)a - (uint32_t)b;
 933     temp16 = (temp >> 16) & 0x01;
 934     if (temp16 == 1) {
 935         set_DSPControl_overflow_flag(1, 20, env);
 936     }
 937     return temp & 0x0000FFFF;
 938 }
 939
 940 static inline uint16_t mipsdsp_satu16_sub_u16_u16(uint16_t a, uint16_t b,
 941                                                   CPUMIPSState *env)
 942 {
 943     uint8_t  temp16;
 944     uint32_t temp;
 945
 946     temp   = (uint32_t)a - (uint32_t)b;
 947     temp16 = (temp >> 16) & 0x01;
 948
 949     if (temp16 == 1) {
 950         temp = 0x0000;
 951         set_DSPControl_overflow_flag(1, 20, env);
 952     }
 953
 954     return temp & 0x0000FFFF;
 955 }
 956
 957 static inline uint8_t mipsdsp_sub_u8(uint8_t a, uint8_t b, CPUMIPSState *env)
 958 {
 959     uint8_t  temp8;
 960     uint16_t temp;
 961
 962     temp = (uint16_t)a - (uint16_t)b;
 963     temp8 = (temp >> 8) & 0x01;
 964     if (temp8 == 1) {
 965         set_DSPControl_overflow_flag(1, 20, env);
 966     }
 967
 968     return temp & 0x00FF;
 969 }
 970
 971 static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env)
 972 {
 973     uint8_t  temp8;
 974     uint16_t temp;
 975
 976     temp = (uint16_t)a - (uint16_t)b;
 977     temp8 = (temp >> 8) & 0x01;
 978     if (temp8 == 1) {
 979         temp = 0x00;
 980         set_DSPControl_overflow_flag(1, 20, env);
 981     }
 982
 983     return temp & 0x00FF;
 984 }
 985
 986 static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env)
 987 {
 988     int32_t temp;
 989
 990     temp = a - b;
 991     if (MIPSDSP_OVERFLOW_SUB(a, b, temp, 0x80000000)) {
 992         set_DSPControl_overflow_flag(1, 20, env);
 993     }
 994
 995     return temp;
 996 }
 997
 998 static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env)
 999 {
1000     int32_t temp;
1001
1002     temp = a + b;
1003
1004     if (MIPSDSP_OVERFLOW_ADD(a, b, temp, 0x80000000)) {
1005         set_DSPControl_overflow_flag(1, 20, env);
1006     }
1007
1008     return temp;
1009 }
1010
1011 static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b)
1012 {
1013     return a == b;
1014 }
1015
1016 static inline int32_t mipsdsp_cmp_le(int32_t a, int32_t b)
1017 {
1018     return a <= b;
1019 }
1020
1021 static inline int32_t mipsdsp_cmp_lt(int32_t a, int32_t b)
1022 {
1023     return a < b;
1024 }
1025
1026 static inline int32_t mipsdsp_cmpu_eq(uint32_t a, uint32_t b)
1027 {
1028     return a == b;
1029 }
1030
1031 static inline int32_t mipsdsp_cmpu_le(uint32_t a, uint32_t b)
1032 {
1033     return a <= b;
1034 }
1035
1036 static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b)
1037 {
1038     return a < b;
1039 }
1040 /*** MIPS DSP internal functions end ***/
1041
1042 #define MIPSDSP_LHI 0xFFFFFFFF00000000ull
1043 #define MIPSDSP_LLO 0x00000000FFFFFFFFull
1044 #define MIPSDSP_HI  0xFFFF0000
1045 #define MIPSDSP_LO  0x0000FFFF
1046 #define MIPSDSP_Q3  0xFF000000
1047 #define MIPSDSP_Q2  0x00FF0000
1048 #define MIPSDSP_Q1  0x0000FF00
1049 #define MIPSDSP_Q0  0x000000FF
1050
1051 #define MIPSDSP_SPLIT32_8(num, a, b, c, d)  \
1052     do {                                    \
1053         a = (num >> 24) & MIPSDSP_Q0;       \
1054         b = (num >> 16) & MIPSDSP_Q0;       \
1055         c = (num >> 8) & MIPSDSP_Q0;        \
1056         d = num & MIPSDSP_Q0;               \
1057     } while (0)
1058
1059 #define MIPSDSP_SPLIT32_16(num, a, b)       \
1060     do {                                    \
1061         a = (num >> 16) & MIPSDSP_LO;       \
1062         b = num & MIPSDSP_LO;               \
1063     } while (0)
1064
1065 #define MIPSDSP_RETURN32_8(a, b, c, d)  ((target_long)(int32_t) \
1066                                          (((uint32_t)a << 24) | \
1067                                          (((uint32_t)b << 16) | \
1068                                          (((uint32_t)c << 8) |  \
1069                                           ((uint32_t)d & 0xFF)))))
1070 #define MIPSDSP_RETURN32_16(a, b)       ((target_long)(int32_t) \
1071                                          (((uint32_t)a << 16) | \
1072                                           ((uint32_t)b & 0xFFFF)))
1073
1074 #ifdef TARGET_MIPS64
1075 #define MIPSDSP_SPLIT64_16(num, a, b, c, d)  \
1076     do {                                     \
1077         a = (num >> 48) & MIPSDSP_LO;        \
1078         b = (num >> 32) & MIPSDSP_LO;        \
1079         c = (num >> 16) & MIPSDSP_LO;        \
1080         d = num & MIPSDSP_LO;                \
1081     } while (0)
1082
1083 #define MIPSDSP_SPLIT64_32(num, a, b)       \
1084     do {                                    \
1085         a = (num >> 32) & MIPSDSP_LLO;      \
1086         b = num & MIPSDSP_LLO;              \
1087     } while (0)
1088
1089 #define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \
1090                                          ((uint64_t)b << 32) | \
1091                                          ((uint64_t)c << 16) | \
1092                                          (uint64_t)d)
1093 #define MIPSDSP_RETURN64_32(a, b)       (((uint64_t)a << 32) | (uint64_t)b)
1094 #endif
1095
1096 /** DSP Arithmetic Sub-class insns **/
1097 #define MIPSDSP32_UNOP_ENV(name, func, element)                            \
1098 target_ulong helper_##name(target_ulong rt, CPUMIPSState *env)             \
1099 {                                                                          \
1100     DSP32Value dt;                                                         \
1101     unsigned int i, n;                                                     \
1102                                                                            \
1103     n = sizeof(DSP32Value) / sizeof(dt.element[0]);                        \
1104     dt.sw[0] = rt;                                                         \
1105                                                                            \
1106     for (i = 0; i < n; i++) {                                              \
1107         dt.element[i] = mipsdsp_##func(dt.element[i], env);                \
1108     }                                                                      \
1109                                                                            \
1110     return (target_long)dt.sw[0];                                          \
1111 }
1112 MIPSDSP32_UNOP_ENV(absq_s_ph, sat_abs16, sh)
1113 MIPSDSP32_UNOP_ENV(absq_s_qb, sat_abs8, sb)
1114 MIPSDSP32_UNOP_ENV(absq_s_w, sat_abs32, sw)
1115 #undef MIPSDSP32_UNOP_ENV
1116
1117 #if defined(TARGET_MIPS64)
1118 #define MIPSDSP64_UNOP_ENV(name, func, element)                            \
1119 target_ulong helper_##name(target_ulong rt, CPUMIPSState *env)             \
1120 {                                                                          \
1121     DSP64Value dt;                                                         \
1122     unsigned int i, n;                                                     \
1123                                                                            \
1124     n = sizeof(DSP64Value) / sizeof(dt.element[0]);                        \
1125     dt.sl[0] = rt;                                                         \
1126                                                                            \
1127     for (i = 0; i < n; i++) {                                              \
1128         dt.element[i] = mipsdsp_##func(dt.element[i], env);                \
1129     }                                                                      \
1130                                                                            \
1131     return dt.sl[0];                                                       \
1132 }
1133 MIPSDSP64_UNOP_ENV(absq_s_ob, sat_abs8, sb)
1134 MIPSDSP64_UNOP_ENV(absq_s_qh, sat_abs16, sh)
1135 MIPSDSP64_UNOP_ENV(absq_s_pw, sat_abs32, sw)
1136 #undef MIPSDSP64_UNOP_ENV
1137 #endif
1138
1139 #define MIPSDSP32_BINOP(name, func, element)                               \
1140 target_ulong helper_##name(target_ulong rs, target_ulong rt)               \
1141 {                                                                          \
1142     DSP32Value ds, dt;                                                     \
1143     unsigned int i, n;                                                     \
1144                                                                            \
1145     n = sizeof(DSP32Value) / sizeof(ds.element[0]);                        \
1146     ds.sw[0] = rs;                                                         \
1147     dt.sw[0] = rt;                                                         \
1148                                                                            \
1149     for (i = 0; i < n; i++) {                                              \
1150         ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]);      \
1151     }                                                                      \
1152                                                                            \
1153     return (target_long)ds.sw[0];                                          \
1154 }
1155 MIPSDSP32_BINOP(addqh_ph, rshift1_add_q16, sh);
1156 MIPSDSP32_BINOP(addqh_r_ph, rrshift1_add_q16, sh);
1157 MIPSDSP32_BINOP(addqh_r_w, rrshift1_add_q32, sw);
1158 MIPSDSP32_BINOP(addqh_w, rshift1_add_q32, sw);
1159 MIPSDSP32_BINOP(adduh_qb, rshift1_add_u8, ub);
1160 MIPSDSP32_BINOP(adduh_r_qb, rrshift1_add_u8, ub);
1161 MIPSDSP32_BINOP(subqh_ph, rshift1_sub_q16, sh);
1162 MIPSDSP32_BINOP(subqh_r_ph, rrshift1_sub_q16, sh);
1163 MIPSDSP32_BINOP(subqh_r_w, rrshift1_sub_q32, sw);
1164 MIPSDSP32_BINOP(subqh_w, rshift1_sub_q32, sw);
1165 #undef MIPSDSP32_BINOP
1166
1167 #define MIPSDSP32_BINOP_ENV(name, func, element)                           \
1168 target_ulong helper_##name(target_ulong rs, target_ulong rt,               \
1169                            CPUMIPSState *env)                              \
1170 {                                                                          \
1171     DSP32Value ds, dt;                                                     \
1172     unsigned int i, n;                                                     \
1173                                                                            \
1174     n = sizeof(DSP32Value) / sizeof(ds.element[0]);                        \
1175     ds.sw[0] = rs;                                                         \
1176     dt.sw[0] = rt;                                                         \
1177                                                                            \
1178     for (i = 0 ; i < n ; i++) {                                            \
1179         ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
1180     }                                                                      \
1181                                                                            \
1182     return (target_long)ds.sw[0];                                          \
1183 }
1184 MIPSDSP32_BINOP_ENV(addq_ph, add_i16, sh)
1185 MIPSDSP32_BINOP_ENV(addq_s_ph, sat_add_i16, sh)
1186 MIPSDSP32_BINOP_ENV(addq_s_w, sat_add_i32, sw);
1187 MIPSDSP32_BINOP_ENV(addu_ph, add_u16, sh)
1188 MIPSDSP32_BINOP_ENV(addu_qb, add_u8, ub);
1189 MIPSDSP32_BINOP_ENV(addu_s_ph, sat_add_u16, sh)
1190 MIPSDSP32_BINOP_ENV(addu_s_qb, sat_add_u8, ub);
1191 MIPSDSP32_BINOP_ENV(subq_ph, sub_i16, sh);
1192 MIPSDSP32_BINOP_ENV(subq_s_ph, sat16_sub, sh);
1193 MIPSDSP32_BINOP_ENV(subq_s_w, sat32_sub, sw);
1194 MIPSDSP32_BINOP_ENV(subu_ph, sub_u16_u16, sh);
1195 MIPSDSP32_BINOP_ENV(subu_qb, sub_u8, ub);
1196 MIPSDSP32_BINOP_ENV(subu_s_ph, satu16_sub_u16_u16, sh);
1197 MIPSDSP32_BINOP_ENV(subu_s_qb, satu8_sub, ub);
1198 #undef MIPSDSP32_BINOP_ENV
1199
1200 #ifdef TARGET_MIPS64
1201 #define MIPSDSP64_BINOP(name, func, element)                               \
1202 target_ulong helper_##name(target_ulong rs, target_ulong rt)               \
1203 {                                                                          \
1204     DSP64Value ds, dt;                                                     \
1205     unsigned int i, n;                                                     \
1206                                                                            \
1207     n = sizeof(DSP64Value) / sizeof(ds.element[0]);                        \
1208     ds.sl[0] = rs;                                                         \
1209     dt.sl[0] = rt;                                                         \
1210                                                                            \
1211     for (i = 0 ; i < n ; i++) {                                            \
1212         ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]);      \
1213     }                                                                      \
1214                                                                            \
1215     return ds.sl[0];                                                       \
1216 }
1217 MIPSDSP64_BINOP(adduh_ob, rshift1_add_u8, ub);
1218 MIPSDSP64_BINOP(adduh_r_ob, rrshift1_add_u8, ub);
1219 MIPSDSP64_BINOP(subuh_ob, rshift1_sub_u8, ub);
1220 MIPSDSP64_BINOP(subuh_r_ob, rrshift1_sub_u8, ub);
1221 #undef MIPSDSP64_BINOP
1222
1223 #define MIPSDSP64_BINOP_ENV(name, func, element)                           \
1224 target_ulong helper_##name(target_ulong rs, target_ulong rt,               \
1225                            CPUMIPSState *env)                              \
1226 {                                                                          \
1227     DSP64Value ds, dt;                                                     \
1228     unsigned int i, n;                                                     \
1229                                                                            \
1230     n = sizeof(DSP64Value) / sizeof(ds.element[0]);                        \
1231     ds.sl[0] = rs;                                                         \
1232     dt.sl[0] = rt;                                                         \
1233                                                                            \
1234     for (i = 0 ; i < n ; i++) {                                            \
1235         ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i], env); \
1236     }                                                                      \
1237                                                                            \
1238     return ds.sl[0];                                                       \
1239 }
1240 MIPSDSP64_BINOP_ENV(addq_pw, add_i32, sw);
1241 MIPSDSP64_BINOP_ENV(addq_qh, add_i16, sh);
1242 MIPSDSP64_BINOP_ENV(addq_s_pw, sat_add_i32, sw);
1243 MIPSDSP64_BINOP_ENV(addq_s_qh, sat_add_i16, sh);
1244 MIPSDSP64_BINOP_ENV(addu_ob, add_u8, uh);
1245 MIPSDSP64_BINOP_ENV(addu_qh, add_u16, uh);
1246 MIPSDSP64_BINOP_ENV(addu_s_ob, sat_add_u8, uh);
1247 MIPSDSP64_BINOP_ENV(addu_s_qh, sat_add_u16, uh);
1248 MIPSDSP64_BINOP_ENV(subq_pw, sub32, sw);
1249 MIPSDSP64_BINOP_ENV(subq_qh, sub_i16, sh);
1250 MIPSDSP64_BINOP_ENV(subq_s_pw, sat32_sub, sw);
1251 MIPSDSP64_BINOP_ENV(subq_s_qh, sat16_sub, sh);
1252 MIPSDSP64_BINOP_ENV(subu_ob, sub_u8, uh);
1253 MIPSDSP64_BINOP_ENV(subu_qh, sub_u16_u16, uh);
1254 MIPSDSP64_BINOP_ENV(subu_s_ob, satu8_sub, uh);
1255 MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16, uh);
1256 #undef MIPSDSP64_BINOP_ENV
1257
1258 #endif
1259
1260 #define SUBUH_QB(name, var) \
1261 target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
1262 {                                                                 \
1263     uint8_t rs3, rs2, rs1, rs0;                                   \
1264     uint8_t rt3, rt2, rt1, rt0;                                   \
1265     uint8_t tempD, tempC, tempB, tempA;                           \
1266                                                                   \
1267     MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0);                    \
1268     MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0);                    \
1269                                                                   \
1270     tempD = ((uint16_t)rs3 - (uint16_t)rt3 + var) >> 1;           \
1271     tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1;           \
1272     tempB = ((uint16_t)rs1 - (uint16_t)rt1 + var) >> 1;           \
1273     tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1;           \
1274                                                                   \
1275     return ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) |    \
1276         ((uint32_t)tempB << 8) | ((uint32_t)tempA);               \
1277 }
1278
1279 SUBUH_QB(subuh, 0);
1280 SUBUH_QB(subuh_r, 1);
1281
1282 #undef SUBUH_QB
1283
1284 target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1285 {
1286     uint64_t temp, tempRs, tempRt;
1287     int32_t flag;
1288
1289     tempRs = (uint64_t)rs & MIPSDSP_LLO;
1290     tempRt = (uint64_t)rt & MIPSDSP_LLO;
1291
1292     temp = tempRs + tempRt;
1293     flag = (temp & 0x0100000000ull) >> 32;
1294     set_DSPControl_carryflag(flag, env);
1295
1296     return (target_long)(int32_t)(temp & MIPSDSP_LLO);
1297 }
1298
1299 target_ulong helper_addwc(target_ulong rs, target_ulong rt, CPUMIPSState *env)
1300 {
1301     uint32_t rd;
1302     int32_t temp32, temp31;
1303     int64_t tempL;
1304
1305     tempL = (int64_t)(int32_t)rs + (int64_t)(int32_t)rt +
1306         get_DSPControl_carryflag(env);
1307     temp31 = (tempL >> 31) & 0x01;
1308     temp32 = (tempL >> 32) & 0x01;
1309
1310     if (temp31 != temp32) {
1311         set_DSPControl_overflow_flag(1, 20, env);
1312     }
1313
1314     rd = tempL & MIPSDSP_LLO;
1315
1316     return (target_long)(int32_t)rd;
1317 }
1318
1319 target_ulong helper_modsub(target_ulong rs, target_ulong rt)
1320 {
1321     int32_t decr;
1322     uint16_t lastindex;
1323     target_ulong rd;
1324
1325     decr = rt & MIPSDSP_Q0;
1326     lastindex = (rt >> 8) & MIPSDSP_LO;
1327
1328     if ((rs & MIPSDSP_LLO) == 0x00000000) {
1329         rd = (target_ulong)lastindex;
1330     } else {
1331         rd = rs - decr;
1332     }
1333
1334     return rd;
1335 }
1336
1337 target_ulong helper_raddu_w_qb(target_ulong rs)
1338 {
1339     target_ulong ret = 0;
1340     DSP32Value ds;
1341     unsigned int i;
1342
1343     ds.uw[0] = rs;
1344     for (i = 0; i < 4; i++) {
1345         ret += ds.ub[i];
1346     }
1347     return ret;
1348 }
1349
1350 #if defined(TARGET_MIPS64)
1351 target_ulong helper_raddu_l_ob(target_ulong rs)
1352 {
1353     target_ulong ret = 0;
1354     DSP64Value ds;
1355     unsigned int i;
1356
1357     ds.ul[0] = rs;
1358     for (i = 0; i < 8; i++) {
1359         ret += ds.ub[i];
1360     }
1361     return ret;
1362 }
1363 #endif
1364
1365 #define PRECR_QB_PH(name, a, b)\
1366 target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \
1367 {                                                                    \
1368     uint8_t tempD, tempC, tempB, tempA;                              \
1369                                                                      \
1370     tempD = (rs >> a) & MIPSDSP_Q0;                                  \
1371     tempC = (rs >> b) & MIPSDSP_Q0;                                  \
1372     tempB = (rt >> a) & MIPSDSP_Q0;                                  \
1373     tempA = (rt >> b) & MIPSDSP_Q0;                                  \
1374                                                                      \
1375     return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);           \
1376 }
1377
1378 PRECR_QB_PH(precr, 16, 0);
1379 PRECR_QB_PH(precrq, 24, 8);
1380
1381 #undef PRECR_QB_OH
1382
1383 target_ulong helper_precr_sra_ph_w(uint32_t sa, target_ulong rs,
1384                                    target_ulong rt)
1385 {
1386     uint16_t tempB, tempA;
1387
1388     tempB = ((int32_t)rt >> sa) & MIPSDSP_LO;
1389     tempA = ((int32_t)rs >> sa) & MIPSDSP_LO;
1390
1391     return MIPSDSP_RETURN32_16(tempB, tempA);
1392 }
1393
1394 target_ulong helper_precr_sra_r_ph_w(uint32_t sa,
1395                                      target_ulong rs, target_ulong rt)
1396 {
1397     uint64_t tempB, tempA;
1398
1399     /* If sa = 0, then (sa - 1) = -1 will case shift error, so we need else. */
1400     if (sa == 0) {
1401         tempB = (rt & MIPSDSP_LO) << 1;
1402         tempA = (rs & MIPSDSP_LO) << 1;
1403     } else {
1404         tempB = ((int32_t)rt >> (sa - 1)) + 1;
1405         tempA = ((int32_t)rs >> (sa - 1)) + 1;
1406     }
1407     rt = (((tempB >> 1) & MIPSDSP_LO) << 16) | ((tempA >> 1) & MIPSDSP_LO);
1408
1409     return (target_long)(int32_t)rt;
1410 }
1411
1412 target_ulong helper_precrq_ph_w(target_ulong rs, target_ulong rt)
1413 {
1414     uint16_t tempB, tempA;
1415
1416     tempB = (rs & MIPSDSP_HI) >> 16;
1417     tempA = (rt & MIPSDSP_HI) >> 16;
1418
1419     return MIPSDSP_RETURN32_16(tempB, tempA);
1420 }
1421
1422 target_ulong helper_precrq_rs_ph_w(target_ulong rs, target_ulong rt,
1423                                    CPUMIPSState *env)
1424 {
1425     uint16_t tempB, tempA;
1426
1427     tempB = mipsdsp_trunc16_sat16_round(rs, env);
1428     tempA = mipsdsp_trunc16_sat16_round(rt, env);
1429
1430     return MIPSDSP_RETURN32_16(tempB, tempA);
1431 }
1432
1433 #if defined(TARGET_MIPS64)
1434 target_ulong helper_precr_ob_qh(target_ulong rs, target_ulong rt)
1435 {
1436     uint8_t rs6, rs4, rs2, rs0;
1437     uint8_t rt6, rt4, rt2, rt0;
1438     uint64_t temp;
1439
1440     rs6 = (rs >> 48) & MIPSDSP_Q0;
1441     rs4 = (rs >> 32) & MIPSDSP_Q0;
1442     rs2 = (rs >> 16) & MIPSDSP_Q0;
1443     rs0 = rs & MIPSDSP_Q0;
1444     rt6 = (rt >> 48) & MIPSDSP_Q0;
1445     rt4 = (rt >> 32) & MIPSDSP_Q0;
1446     rt2 = (rt >> 16) & MIPSDSP_Q0;
1447     rt0 = rt & MIPSDSP_Q0;
1448
1449     temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1450            ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1451            ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1452            ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1453
1454     return temp;
1455 }
1456
1457 #define PRECR_QH_PW(name, var) \
1458 target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \
1459                                     uint32_t sa)                      \
1460 {                                                                     \
1461     uint16_t rs3, rs2, rs1, rs0;                                      \
1462     uint16_t rt3, rt2, rt1, rt0;                                      \
1463     uint16_t tempD, tempC, tempB, tempA;                              \
1464                                                                       \
1465     MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);                       \
1466     MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);                       \
1467                                                                       \
1468     /* When sa = 0, we use rt2, rt0, rs2, rs0;                        \
1469      * when sa != 0, we use rt3, rt1, rs3, rs1. */                    \
1470     if (sa == 0) {                                                    \
1471         tempD = rt2 << var;                                           \
1472         tempC = rt0 << var;                                           \
1473         tempB = rs2 << var;                                           \
1474         tempA = rs0 << var;                                           \
1475     } else {                                                          \
1476         tempD = (((int16_t)rt3 >> sa) + var) >> var;                  \
1477         tempC = (((int16_t)rt1 >> sa) + var) >> var;                  \
1478         tempB = (((int16_t)rs3 >> sa) + var) >> var;                  \
1479         tempA = (((int16_t)rs1 >> sa) + var) >> var;                  \
1480     }                                                                 \
1481                                                                       \
1482     return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);           \
1483 }
1484
1485 PRECR_QH_PW(sra, 0);
1486 PRECR_QH_PW(sra_r, 1);
1487
1488 #undef PRECR_QH_PW
1489
1490 target_ulong helper_precrq_ob_qh(target_ulong rs, target_ulong rt)
1491 {
1492     uint8_t rs6, rs4, rs2, rs0;
1493     uint8_t rt6, rt4, rt2, rt0;
1494     uint64_t temp;
1495
1496     rs6 = (rs >> 56) & MIPSDSP_Q0;
1497     rs4 = (rs >> 40) & MIPSDSP_Q0;
1498     rs2 = (rs >> 24) & MIPSDSP_Q0;
1499     rs0 = (rs >> 8) & MIPSDSP_Q0;
1500     rt6 = (rt >> 56) & MIPSDSP_Q0;
1501     rt4 = (rt >> 40) & MIPSDSP_Q0;
1502     rt2 = (rt >> 24) & MIPSDSP_Q0;
1503     rt0 = (rt >> 8) & MIPSDSP_Q0;
1504
1505     temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) |
1506            ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) |
1507            ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) |
1508            ((uint64_t)rt2 << 8) | (uint64_t)rt0;
1509
1510     return temp;
1511 }
1512
1513 target_ulong helper_precrq_qh_pw(target_ulong rs, target_ulong rt)
1514 {
1515     uint16_t tempD, tempC, tempB, tempA;
1516
1517     tempD = (rs >> 48) & MIPSDSP_LO;
1518     tempC = (rs >> 16) & MIPSDSP_LO;
1519     tempB = (rt >> 48) & MIPSDSP_LO;
1520     tempA = (rt >> 16) & MIPSDSP_LO;
1521
1522     return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1523 }
1524
1525 target_ulong helper_precrq_rs_qh_pw(target_ulong rs, target_ulong rt,
1526                                     CPUMIPSState *env)
1527 {
1528     uint32_t rs2, rs0;
1529     uint32_t rt2, rt0;
1530     uint16_t tempD, tempC, tempB, tempA;
1531
1532     rs2 = (rs >> 32) & MIPSDSP_LLO;
1533     rs0 = rs & MIPSDSP_LLO;
1534     rt2 = (rt >> 32) & MIPSDSP_LLO;
1535     rt0 = rt & MIPSDSP_LLO;
1536
1537     tempD = mipsdsp_trunc16_sat16_round(rs2, env);
1538     tempC = mipsdsp_trunc16_sat16_round(rs0, env);
1539     tempB = mipsdsp_trunc16_sat16_round(rt2, env);
1540     tempA = mipsdsp_trunc16_sat16_round(rt0, env);
1541
1542     return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
1543 }
1544
1545 target_ulong helper_precrq_pw_l(target_ulong rs, target_ulong rt)
1546 {
1547     uint32_t tempB, tempA;
1548
1549     tempB = (rs >> 32) & MIPSDSP_LLO;
1550     tempA = (rt >> 32) & MIPSDSP_LLO;
1551
1552     return MIPSDSP_RETURN64_32(tempB, tempA);
1553 }
1554 #endif
1555
1556 target_ulong helper_precrqu_s_qb_ph(target_ulong rs, target_ulong rt,
1557                                     CPUMIPSState *env)
1558 {
1559     uint8_t  tempD, tempC, tempB, tempA;
1560     uint16_t rsh, rsl, rth, rtl;
1561
1562     rsh = (rs & MIPSDSP_HI) >> 16;
1563     rsl =  rs & MIPSDSP_LO;
1564     rth = (rt & MIPSDSP_HI) >> 16;
1565     rtl =  rt & MIPSDSP_LO;
1566
1567     tempD = mipsdsp_sat8_reduce_precision(rsh, env);
1568     tempC = mipsdsp_sat8_reduce_precision(rsl, env);
1569     tempB = mipsdsp_sat8_reduce_precision(rth, env);
1570     tempA = mipsdsp_sat8_reduce_precision(rtl, env);
1571
1572     return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
1573 }
1574
1575 #if defined(TARGET_MIPS64)
1576 target_ulong helper_precrqu_s_ob_qh(target_ulong rs, target_ulong rt,
1577                                     CPUMIPSState *env)
1578 {
1579     int i;
1580     uint16_t rs3, rs2, rs1, rs0;
1581     uint16_t rt3, rt2, rt1, rt0;
1582     uint8_t temp[8];
1583     uint64_t result;
1584
1585     result = 0;
1586
1587     MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
1588     MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
1589
1590     temp[7] = mipsdsp_sat8_reduce_precision(rs3, env);
1591     temp[6] = mipsdsp_sat8_reduce_precision(rs2, env);
1592     temp[5] = mipsdsp_sat8_reduce_precision(rs1, env);
1593     temp[4] = mipsdsp_sat8_reduce_precision(rs0, env);
1594     temp[3] = mipsdsp_sat8_reduce_precision(rt3, env);
1595     temp[2] = mipsdsp_sat8_reduce_precision(rt2, env);
1596     temp[1] = mipsdsp_sat8_reduce_precision(rt1, env);
1597     temp[0] = mipsdsp_sat8_reduce_precision(rt0, env);
1598
1599     for (i = 0; i < 8; i++) {
1600         result |= (uint64_t)temp[i] << (8 * i);
1601     }
1602
1603     return result;
1604 }
1605
1606 #define PRECEQ_PW(name, a, b) \
1607 target_ulong helper_preceq_pw_##name(target_ulong rt) \
1608 {                                                       \
1609     uint16_t tempB, tempA;                              \
1610     uint32_t tempBI, tempAI;                            \
1611                                                         \
1612     tempB = (rt >> a) & MIPSDSP_LO;                     \
1613     tempA = (rt >> b) & MIPSDSP_LO;                     \
1614                                                         \
1615     tempBI = (uint32_t)tempB << 16;                     \
1616     tempAI = (uint32_t)tempA << 16;                     \
1617                                                         \
1618     return MIPSDSP_RETURN64_32(tempBI, tempAI);         \
1619 }
1620
1621 PRECEQ_PW(qhl, 48, 32);
1622 PRECEQ_PW(qhr, 16, 0);
1623 PRECEQ_PW(qhla, 48, 16);
1624 PRECEQ_PW(qhra, 32, 0);
1625
1626 #undef PRECEQ_PW
1627
1628 #endif
1629
1630 #define PRECEQU_PH(name, a, b) \
1631 target_ulong helper_precequ_ph_##name(target_ulong rt) \
1632 {                                                        \
1633     uint16_t tempB, tempA;                               \
1634                                                          \
1635     tempB = (rt >> a) & MIPSDSP_Q0;                      \
1636     tempA = (rt >> b) & MIPSDSP_Q0;                      \
1637                                                          \
1638     tempB = tempB << 7;                                  \
1639     tempA = tempA << 7;                                  \
1640                                                          \
1641     return MIPSDSP_RETURN32_16(tempB, tempA);            \
1642 }
1643
1644 PRECEQU_PH(qbl, 24, 16);
1645 PRECEQU_PH(qbr, 8, 0);
1646 PRECEQU_PH(qbla, 24, 8);
1647 PRECEQU_PH(qbra, 16, 0);
1648
1649 #undef PRECEQU_PH
1650
1651 #if defined(TARGET_MIPS64)
1652 #define PRECEQU_QH(name, a, b, c, d) \
1653 target_ulong helper_precequ_qh_##name(target_ulong rt)       \
1654 {                                                            \
1655     uint16_t tempD, tempC, tempB, tempA;                     \
1656                                                              \
1657     tempD = (rt >> a) & MIPSDSP_Q0;                          \
1658     tempC = (rt >> b) & MIPSDSP_Q0;                          \
1659     tempB = (rt >> c) & MIPSDSP_Q0;                          \
1660     tempA = (rt >> d) & MIPSDSP_Q0;                          \
1661                                                              \
1662     tempD = tempD << 7;                                      \
1663     tempC = tempC << 7;                                      \
1664     tempB = tempB << 7;                                      \
1665     tempA = tempA << 7;                                      \
1666                                                              \
1667     return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);  \
1668 }
1669
1670 PRECEQU_QH(obl, 56, 48, 40, 32);
1671 PRECEQU_QH(obr, 24, 16, 8, 0);
1672 PRECEQU_QH(obla, 56, 40, 24, 8);
1673 PRECEQU_QH(obra, 48, 32, 16, 0);
1674
1675 #undef PRECEQU_QH
1676
1677 #endif
1678
1679 #define PRECEU_PH(name, a, b) \
1680 target_ulong helper_preceu_ph_##name(target_ulong rt) \
1681 {                                                     \
1682     uint16_t tempB, tempA;                            \
1683                                                       \
1684     tempB = (rt >> a) & MIPSDSP_Q0;                   \
1685     tempA = (rt >> b) & MIPSDSP_Q0;                   \
1686                                                       \
1687     return MIPSDSP_RETURN32_16(tempB, tempA);         \
1688 }
1689
1690 PRECEU_PH(qbl, 24, 16);
1691 PRECEU_PH(qbr, 8, 0);
1692 PRECEU_PH(qbla, 24, 8);
1693 PRECEU_PH(qbra, 16, 0);
1694
1695 #undef PRECEU_PH
1696
1697 #if defined(TARGET_MIPS64)
1698 #define PRECEU_QH(name, a, b, c, d) \
1699 target_ulong helper_preceu_qh_##name(target_ulong rt)        \
1700 {                                                            \
1701     uint16_t tempD, tempC, tempB, tempA;                     \
1702                                                              \
1703     tempD = (rt >> a) & MIPSDSP_Q0;                          \
1704     tempC = (rt >> b) & MIPSDSP_Q0;                          \
1705     tempB = (rt >> c) & MIPSDSP_Q0;                          \
1706     tempA = (rt >> d) & MIPSDSP_Q0;                          \
1707                                                              \
1708     return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);  \
1709 }
1710
1711 PRECEU_QH(obl, 56, 48, 40, 32);
1712 PRECEU_QH(obr, 24, 16, 8, 0);
1713 PRECEU_QH(obla, 56, 40, 24, 8);
1714 PRECEU_QH(obra, 48, 32, 16, 0);
1715
1716 #undef PRECEU_QH
1717
1718 #endif
1719
1720 /** DSP GPR-Based Shift Sub-class insns **/
1721 #define SHIFT_QB(name, func) \
1722 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt) \
1723 {                                                                    \
1724     uint8_t rt3, rt2, rt1, rt0;                                      \
1725                                                                      \
1726     sa = sa & 0x07;                                                  \
1727                                                                      \
1728     MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0);                       \
1729                                                                      \
1730     rt3 = mipsdsp_##func(rt3, sa);                                   \
1731     rt2 = mipsdsp_##func(rt2, sa);                                   \
1732     rt1 = mipsdsp_##func(rt1, sa);                                   \
1733     rt0 = mipsdsp_##func(rt0, sa);                                   \
1734                                                                      \
1735     return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0);                   \
1736 }
1737
1738 #define SHIFT_QB_ENV(name, func) \
1739 target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt,\
1740                                 CPUMIPSState *env) \
1741 {                                                                    \
1742     uint8_t rt3, rt2, rt1, rt0;                                      \
1743                                                                      \
1744     sa = sa & 0x07;                                                  \
1745                                                                      \
1746     MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0);                       \
1747                                                                      \
1748     rt3 = mipsdsp_##func(rt3, sa, env);                              \
1749     rt2 = mipsdsp_##func(rt2, sa, env);                              \
1750     rt1 = mipsdsp_##func(rt1, sa, env);                              \
1751     rt0 = mipsdsp_##func(rt0, sa, env);                              \
1752                                                                      \
1753     return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0);                   \
1754 }
1755
1756 SHIFT_QB_ENV(shll, lshift8);
1757 SHIFT_QB(shrl, rshift_u8);
1758
1759 SHIFT_QB(shra, rashift8);
1760 SHIFT_QB(shra_r, rnd8_rashift);
1761
1762 #undef SHIFT_QB
1763 #undef SHIFT_QB_ENV
1764
1765 #if defined(TARGET_MIPS64)
1766 #define SHIFT_OB(name, func) \
1767 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa) \
1768 {                                                                        \
1769     int i;                                                               \
1770     uint8_t rt_t[8];                                                     \
1771     uint64_t temp;                                                       \
1772                                                                          \
1773     sa = sa & 0x07;                                                      \
1774     temp = 0;                                                            \
1775                                                                          \
1776     for (i = 0; i < 8; i++) {                                            \
1777         rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0;                          \
1778         rt_t[i] = mipsdsp_##func(rt_t[i], sa);                           \
1779         temp |= (uint64_t)rt_t[i] << (8 * i);                            \
1780     }                                                                    \
1781                                                                          \
1782     return temp;                                                         \
1783 }
1784
1785 #define SHIFT_OB_ENV(name, func) \
1786 target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa, \
1787                                 CPUMIPSState *env)                       \
1788 {                                                                        \
1789     int i;                                                               \
1790     uint8_t rt_t[8];                                                     \
1791     uint64_t temp;                                                       \
1792                                                                          \
1793     sa = sa & 0x07;                                                      \
1794     temp = 0;                                                            \
1795                                                                          \
1796     for (i = 0; i < 8; i++) {                                            \
1797         rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0;                          \
1798         rt_t[i] = mipsdsp_##func(rt_t[i], sa, env);                      \
1799         temp |= (uint64_t)rt_t[i] << (8 * i);                            \
1800     }                                                                    \
1801                                                                          \
1802     return temp;                                                         \
1803 }
1804
1805 SHIFT_OB_ENV(shll, lshift8);
1806 SHIFT_OB(shrl, rshift_u8);
1807
1808 SHIFT_OB(shra, rashift8);
1809 SHIFT_OB(shra_r, rnd8_rashift);
1810
1811 #undef SHIFT_OB
1812 #undef SHIFT_OB_ENV
1813
1814 #endif
1815
1816 #define SHIFT_PH(name, func) \
1817 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt, \
1818                                 CPUMIPSState *env)                \
1819 {                                                                 \
1820     uint16_t rth, rtl;                                            \
1821                                                                   \
1822     sa = sa & 0x0F;                                               \
1823                                                                   \
1824     MIPSDSP_SPLIT32_16(rt, rth, rtl);                             \
1825                                                                   \
1826     rth = mipsdsp_##func(rth, sa, env);                           \
1827     rtl = mipsdsp_##func(rtl, sa, env);                           \
1828                                                                   \
1829     return MIPSDSP_RETURN32_16(rth, rtl);                         \
1830 }
1831
1832 SHIFT_PH(shll, lshift16);
1833 SHIFT_PH(shll_s, sat16_lshift);
1834
1835 #undef SHIFT_PH
1836
1837 #if defined(TARGET_MIPS64)
1838 #define SHIFT_QH(name, func) \
1839 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa) \
1840 {                                                                 \
1841     uint16_t rt3, rt2, rt1, rt0;                                  \
1842                                                                   \
1843     sa = sa & 0x0F;                                               \
1844                                                                   \
1845     MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);                   \
1846                                                                   \
1847     rt3 = mipsdsp_##func(rt3, sa);                                \
1848     rt2 = mipsdsp_##func(rt2, sa);                                \
1849     rt1 = mipsdsp_##func(rt1, sa);                                \
1850     rt0 = mipsdsp_##func(rt0, sa);                                \
1851                                                                   \
1852     return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0);               \
1853 }
1854
1855 #define SHIFT_QH_ENV(name, func) \
1856 target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa, \
1857                                 CPUMIPSState *env)                \
1858 {                                                                 \
1859     uint16_t rt3, rt2, rt1, rt0;                                  \
1860                                                                   \
1861     sa = sa & 0x0F;                                               \
1862                                                                   \
1863     MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);                   \
1864                                                                   \
1865     rt3 = mipsdsp_##func(rt3, sa, env);                           \
1866     rt2 = mipsdsp_##func(rt2, sa, env);                           \
1867     rt1 = mipsdsp_##func(rt1, sa, env);                           \
1868     rt0 = mipsdsp_##func(rt0, sa, env);                           \
1869                                                                   \
1870     return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0);               \
1871 }
1872
1873 SHIFT_QH_ENV(shll, lshift16);
1874 SHIFT_QH_ENV(shll_s, sat16_lshift);
1875
1876 SHIFT_QH(shrl, rshift_u16);
1877 SHIFT_QH(shra, rashift16);
1878 SHIFT_QH(shra_r, rnd16_rashift);
1879
1880 #undef SHIFT_QH
1881 #undef SHIFT_QH_ENV
1882
1883 #endif
1884
1885 #define SHIFT_W(name, func) \
1886 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt) \
1887 {                                                                       \
1888     uint32_t temp;                                                      \
1889                                                                         \
1890     sa = sa & 0x1F;                                                     \
1891     temp = mipsdsp_##func(rt, sa);                                      \
1892                                                                         \
1893     return (target_long)(int32_t)temp;                                  \
1894 }
1895
1896 #define SHIFT_W_ENV(name, func) \
1897 target_ulong helper_##name##_w(target_ulong sa, target_ulong rt, \
1898                                CPUMIPSState *env) \
1899 {                                                                       \
1900     uint32_t temp;                                                      \
1901                                                                         \
1902     sa = sa & 0x1F;                                                     \
1903     temp = mipsdsp_##func(rt, sa, env);                                 \
1904                                                                         \
1905     return (target_long)(int32_t)temp;                                  \
1906 }
1907
1908 SHIFT_W_ENV(shll_s, sat32_lshift);
1909 SHIFT_W(shra_r, rnd32_rashift);
1910
1911 #undef SHIFT_W
1912 #undef SHIFT_W_ENV
1913
1914 #if defined(TARGET_MIPS64)
1915 #define SHIFT_PW(name, func) \
1916 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa) \
1917 {                                                                 \
1918     uint32_t rt1, rt0;                                            \
1919                                                                   \
1920     sa = sa & 0x1F;                                               \
1921     MIPSDSP_SPLIT64_32(rt, rt1, rt0);                             \
1922                                                                   \
1923     rt1 = mipsdsp_##func(rt1, sa);                                \
1924     rt0 = mipsdsp_##func(rt0, sa);                                \
1925                                                                   \
1926     return MIPSDSP_RETURN64_32(rt1, rt0);                         \
1927 }
1928
1929 #define SHIFT_PW_ENV(name, func) \
1930 target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa, \
1931                                 CPUMIPSState *env)                \
1932 {                                                                 \
1933     uint32_t rt1, rt0;                                            \
1934                                                                   \
1935     sa = sa & 0x1F;                                               \
1936     MIPSDSP_SPLIT64_32(rt, rt1, rt0);                             \
1937                                                                   \
1938     rt1 = mipsdsp_##func(rt1, sa, env);                           \
1939     rt0 = mipsdsp_##func(rt0, sa, env);                           \
1940                                                                   \
1941     return MIPSDSP_RETURN64_32(rt1, rt0);                         \
1942 }
1943
1944 SHIFT_PW_ENV(shll, lshift32);
1945 SHIFT_PW_ENV(shll_s, sat32_lshift);
1946
1947 SHIFT_PW(shra, rashift32);
1948 SHIFT_PW(shra_r, rnd32_rashift);
1949
1950 #undef SHIFT_PW
1951 #undef SHIFT_PW_ENV
1952
1953 #endif
1954
1955 #define SHIFT_PH(name, func) \
1956 target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt) \
1957 {                                                                    \
1958     uint16_t rth, rtl;                                               \
1959                                                                      \
1960     sa = sa & 0x0F;                                                  \
1961                                                                      \
1962     MIPSDSP_SPLIT32_16(rt, rth, rtl);                                \
1963                                                                      \
1964     rth = mipsdsp_##func(rth, sa);                                   \
1965     rtl = mipsdsp_##func(rtl, sa);                                   \
1966                                                                      \
1967     return MIPSDSP_RETURN32_16(rth, rtl);                            \
1968 }
1969
1970 SHIFT_PH(shrl, rshift_u16);
1971 SHIFT_PH(shra, rashift16);
1972 SHIFT_PH(shra_r, rnd16_rashift);
1973
1974 #undef SHIFT_PH
1975
1976 /** DSP Multiply Sub-class insns **/
1977 /* Return value made up by two 16bits value.
1978  * FIXME give the macro a better name.
1979  */
1980 #define MUL_RETURN32_16_PH(name, func, \
1981                            rsmov1, rsmov2, rsfilter, \
1982                            rtmov1, rtmov2, rtfilter) \
1983 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
1984                            CPUMIPSState *env)                \
1985 {                                                            \
1986     uint16_t rsB, rsA, rtB, rtA;                             \
1987                                                              \
1988     rsB = (rs >> rsmov1) & rsfilter;                         \
1989     rsA = (rs >> rsmov2) & rsfilter;                         \
1990     rtB = (rt >> rtmov1) & rtfilter;                         \
1991     rtA = (rt >> rtmov2) & rtfilter;                         \
1992                                                              \
1993     rsB = mipsdsp_##func(rsB, rtB, env);                     \
1994     rsA = mipsdsp_##func(rsA, rtA, env);                     \
1995                                                              \
1996     return MIPSDSP_RETURN32_16(rsB, rsA);                    \
1997 }
1998
1999 MUL_RETURN32_16_PH(muleu_s_ph_qbl, mul_u8_u16, \
2000                       24, 16, MIPSDSP_Q0, \
2001                       16, 0, MIPSDSP_LO);
2002 MUL_RETURN32_16_PH(muleu_s_ph_qbr, mul_u8_u16, \
2003                       8, 0, MIPSDSP_Q0, \
2004                       16, 0, MIPSDSP_LO);
2005 MUL_RETURN32_16_PH(mulq_rs_ph, rndq15_mul_q15_q15, \
2006                       16, 0, MIPSDSP_LO, \
2007                       16, 0, MIPSDSP_LO);
2008 MUL_RETURN32_16_PH(mul_ph, mul_i16_i16, \
2009                       16, 0, MIPSDSP_LO, \
2010                       16, 0, MIPSDSP_LO);
2011 MUL_RETURN32_16_PH(mul_s_ph, sat16_mul_i16_i16, \
2012                       16, 0, MIPSDSP_LO, \
2013                       16, 0, MIPSDSP_LO);
2014 MUL_RETURN32_16_PH(mulq_s_ph, sat16_mul_q15_q15, \
2015                       16, 0, MIPSDSP_LO, \
2016                       16, 0, MIPSDSP_LO);
2017
2018 #undef MUL_RETURN32_16_PH
2019
2020 #define MUL_RETURN32_32_ph(name, func, movbits) \
2021 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2022                                   CPUMIPSState *env)         \
2023 {                                                            \
2024     int16_t rsh, rth;                                        \
2025     int32_t temp;                                            \
2026                                                              \
2027     rsh = (rs >> movbits) & MIPSDSP_LO;                      \
2028     rth = (rt >> movbits) & MIPSDSP_LO;                      \
2029     temp = mipsdsp_##func(rsh, rth, env);                    \
2030                                                              \
2031     return (target_long)(int32_t)temp;                       \
2032 }
2033
2034 MUL_RETURN32_32_ph(muleq_s_w_phl, mul_q15_q15_overflowflag21, 16);
2035 MUL_RETURN32_32_ph(muleq_s_w_phr, mul_q15_q15_overflowflag21, 0);
2036
2037 #undef MUL_RETURN32_32_ph
2038
2039 #define MUL_VOID_PH(name, use_ac_env) \
2040 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt,        \
2041                           CPUMIPSState *env)                             \
2042 {                                                                        \
2043     int16_t rsh, rsl, rth, rtl;                                          \
2044     int32_t tempB, tempA;                                                \
2045     int64_t acc, dotp;                                                   \
2046                                                                          \
2047     MIPSDSP_SPLIT32_16(rs, rsh, rsl);                                    \
2048     MIPSDSP_SPLIT32_16(rt, rth, rtl);                                    \
2049                                                                          \
2050     if (use_ac_env == 1) {                                               \
2051         tempB = mipsdsp_mul_q15_q15(ac, rsh, rth, env);                  \
2052         tempA = mipsdsp_mul_q15_q15(ac, rsl, rtl, env);                  \
2053     } else {                                                             \
2054         tempB = mipsdsp_mul_u16_u16(rsh, rth);                           \
2055         tempA = mipsdsp_mul_u16_u16(rsl, rtl);                           \
2056     }                                                                    \
2057                                                                          \
2058     dotp = (int64_t)tempB - (int64_t)tempA;                              \
2059     acc = ((uint64_t)env->active_tc.HI[ac] << 32) |                      \
2060           ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);               \
2061     dotp = dotp + acc;                                                   \
2062     env->active_tc.HI[ac] = (target_long)(int32_t)                       \
2063                             ((dotp & MIPSDSP_LHI) >> 32);                \
2064     env->active_tc.LO[ac] = (target_long)(int32_t)(dotp & MIPSDSP_LLO);  \
2065 }
2066
2067 MUL_VOID_PH(mulsaq_s_w_ph, 1);
2068 MUL_VOID_PH(mulsa_w_ph, 0);
2069
2070 #undef MUL_VOID_PH
2071
2072 #if defined(TARGET_MIPS64)
2073 #define MUL_RETURN64_16_QH(name, func, \
2074                            rsmov1, rsmov2, rsmov3, rsmov4, rsfilter, \
2075                            rtmov1, rtmov2, rtmov3, rtmov4, rtfilter) \
2076 target_ulong helper_##name(target_ulong rs, target_ulong rt,         \
2077                            CPUMIPSState *env)                        \
2078 {                                                                    \
2079     uint16_t rs3, rs2, rs1, rs0;                                     \
2080     uint16_t rt3, rt2, rt1, rt0;                                     \
2081     uint16_t tempD, tempC, tempB, tempA;                             \
2082                                                                      \
2083     rs3 = (rs >> rsmov1) & rsfilter;                                 \
2084     rs2 = (rs >> rsmov2) & rsfilter;                                 \
2085     rs1 = (rs >> rsmov3) & rsfilter;                                 \
2086     rs0 = (rs >> rsmov4) & rsfilter;                                 \
2087     rt3 = (rt >> rtmov1) & rtfilter;                                 \
2088     rt2 = (rt >> rtmov2) & rtfilter;                                 \
2089     rt1 = (rt >> rtmov3) & rtfilter;                                 \
2090     rt0 = (rt >> rtmov4) & rtfilter;                                 \
2091                                                                      \
2092     tempD = mipsdsp_##func(rs3, rt3, env);                           \
2093     tempC = mipsdsp_##func(rs2, rt2, env);                           \
2094     tempB = mipsdsp_##func(rs1, rt1, env);                           \
2095     tempA = mipsdsp_##func(rs0, rt0, env);                           \
2096                                                                      \
2097     return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);          \
2098 }
2099
2100 MUL_RETURN64_16_QH(muleu_s_qh_obl, mul_u8_u16, \
2101                    56, 48, 40, 32, MIPSDSP_Q0, \
2102                    48, 32, 16, 0, MIPSDSP_LO);
2103 MUL_RETURN64_16_QH(muleu_s_qh_obr, mul_u8_u16, \
2104                    24, 16, 8, 0, MIPSDSP_Q0, \
2105                    48, 32, 16, 0, MIPSDSP_LO);
2106 MUL_RETURN64_16_QH(mulq_rs_qh, rndq15_mul_q15_q15, \
2107                    48, 32, 16, 0, MIPSDSP_LO, \
2108                    48, 32, 16, 0, MIPSDSP_LO);
2109
2110 #undef MUL_RETURN64_16_QH
2111
2112 #define MUL_RETURN64_32_QH(name, \
2113                            rsmov1, rsmov2, \
2114                            rtmov1, rtmov2) \
2115 target_ulong helper_##name(target_ulong rs, target_ulong rt, \
2116                            CPUMIPSState *env)                \
2117 {                                                            \
2118     uint16_t rsB, rsA;                                       \
2119     uint16_t rtB, rtA;                                       \
2120     uint32_t tempB, tempA;                                   \
2121                                                              \
2122     rsB = (rs >> rsmov1) & MIPSDSP_LO;                       \
2123     rsA = (rs >> rsmov2) & MIPSDSP_LO;                       \
2124     rtB = (rt >> rtmov1) & MIPSDSP_LO;                       \
2125     rtA = (rt >> rtmov2) & MIPSDSP_LO;                       \
2126                                                              \
2127     tempB = mipsdsp_mul_q15_q15(5, rsB, rtB, env);           \
2128     tempA = mipsdsp_mul_q15_q15(5, rsA, rtA, env);           \
2129                                                              \
2130     return ((uint64_t)tempB << 32) | (uint64_t)tempA;        \
2131 }
2132
2133 MUL_RETURN64_32_QH(muleq_s_pw_qhl, 48, 32, 48, 32);
2134 MUL_RETURN64_32_QH(muleq_s_pw_qhr, 16, 0, 16, 0);
2135
2136 #undef MUL_RETURN64_32_QH
2137
2138 void helper_mulsaq_s_w_qh(target_ulong rs, target_ulong rt, uint32_t ac,
2139                           CPUMIPSState *env)
2140 {
2141     int16_t rs3, rs2, rs1, rs0;
2142     int16_t rt3, rt2, rt1, rt0;
2143     int32_t tempD, tempC, tempB, tempA;
2144     int64_t acc[2];
2145     int64_t temp[2];
2146     int64_t temp_sum;
2147
2148     MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);
2149     MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);
2150
2151     tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env);
2152     tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env);
2153     tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env);
2154     tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env);
2155
2156     temp[0] = ((int32_t)tempD - (int32_t)tempC) +
2157               ((int32_t)tempB - (int32_t)tempA);
2158     temp[0] = (int64_t)(temp[0] << 30) >> 30;
2159     if (((temp[0] >> 33) & 0x01) == 0) {
2160         temp[1] = 0x00;
2161     } else {
2162         temp[1] = ~0ull;
2163     }
2164
2165     acc[0] = env->active_tc.LO[ac];
2166     acc[1] = env->active_tc.HI[ac];
2167
2168     temp_sum = acc[0] + temp[0];
2169     if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2170        ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2171         acc[1] += 1;
2172     }
2173     acc[0] = temp_sum;
2174     acc[1] += temp[1];
2175
2176     env->active_tc.HI[ac] = acc[1];
2177     env->active_tc.LO[ac] = acc[0];
2178 }
2179 #endif
2180
2181 #define DP_QB(name, func, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2182 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt,        \
2183                    CPUMIPSState *env)                                    \
2184 {                                                                        \
2185     uint8_t rs3, rs2;                                                    \
2186     uint8_t rt3, rt2;                                                    \
2187     uint16_t tempB, tempA;                                               \
2188     uint64_t tempC, dotp;                                                \
2189                                                                          \
2190     rs3 = (rs >> rsmov1) & MIPSDSP_Q0;                                   \
2191     rs2 = (rs >> rsmov2) & MIPSDSP_Q0;                                   \
2192     rt3 = (rt >> rtmov1) & MIPSDSP_Q0;                                   \
2193     rt2 = (rt >> rtmov2) & MIPSDSP_Q0;                                   \
2194     tempB = mipsdsp_##func(rs3, rt3);                                    \
2195     tempA = mipsdsp_##func(rs2, rt2);                                    \
2196     dotp = (int64_t)tempB + (int64_t)tempA;                              \
2197     if (is_add) {                                                        \
2198         tempC = (((uint64_t)env->active_tc.HI[ac] << 32) |               \
2199                  ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO))        \
2200             + dotp;                                                      \
2201     } else {                                                             \
2202         tempC = (((uint64_t)env->active_tc.HI[ac] << 32) |               \
2203                  ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO))        \
2204             - dotp;                                                      \
2205     }                                                                    \
2206                                                                          \
2207     env->active_tc.HI[ac] = (target_long)(int32_t)                       \
2208                             ((tempC & MIPSDSP_LHI) >> 32);               \
2209     env->active_tc.LO[ac] = (target_long)(int32_t)(tempC & MIPSDSP_LLO); \
2210 }
2211
2212 DP_QB(dpau_h_qbl, mul_u8_u8, 1, 24, 16, 24, 16);
2213 DP_QB(dpau_h_qbr, mul_u8_u8, 1, 8, 0, 8, 0);
2214 DP_QB(dpsu_h_qbl, mul_u8_u8, 0, 24, 16, 24, 16);
2215 DP_QB(dpsu_h_qbr, mul_u8_u8, 0, 8, 0, 8, 0);
2216
2217 #undef DP_QB
2218
2219 #if defined(TARGET_MIPS64)
2220 #define DP_OB(name, add_sub, \
2221               rsmov1, rsmov2, rsmov3, rsmov4, \
2222               rtmov1, rtmov2, rtmov3, rtmov4) \
2223 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac,       \
2224                        CPUMIPSState *env)                               \
2225 {                                                                       \
2226     uint8_t rsD, rsC, rsB, rsA;                                         \
2227     uint8_t rtD, rtC, rtB, rtA;                                         \
2228     uint16_t tempD, tempC, tempB, tempA;                                \
2229     uint64_t temp[2];                                                   \
2230     uint64_t acc[2];                                                    \
2231     uint64_t temp_sum;                                                  \
2232                                                                         \
2233     temp[0] = 0;                                                        \
2234     temp[1] = 0;                                                        \
2235                                                                         \
2236     rsD = (rs >> rsmov1) & MIPSDSP_Q0;                                  \
2237     rsC = (rs >> rsmov2) & MIPSDSP_Q0;                                  \
2238     rsB = (rs >> rsmov3) & MIPSDSP_Q0;                                  \
2239     rsA = (rs >> rsmov4) & MIPSDSP_Q0;                                  \
2240     rtD = (rt >> rtmov1) & MIPSDSP_Q0;                                  \
2241     rtC = (rt >> rtmov2) & MIPSDSP_Q0;                                  \
2242     rtB = (rt >> rtmov3) & MIPSDSP_Q0;                                  \
2243     rtA = (rt >> rtmov4) & MIPSDSP_Q0;                                  \
2244                                                                         \
2245     tempD = mipsdsp_mul_u8_u8(rsD, rtD);                                \
2246     tempC = mipsdsp_mul_u8_u8(rsC, rtC);                                \
2247     tempB = mipsdsp_mul_u8_u8(rsB, rtB);                                \
2248     tempA = mipsdsp_mul_u8_u8(rsA, rtA);                                \
2249                                                                         \
2250     temp[0] = (uint64_t)tempD + (uint64_t)tempC +                       \
2251       (uint64_t)tempB + (uint64_t)tempA;                                \
2252                                                                         \
2253     acc[0] = env->active_tc.LO[ac];                                     \
2254     acc[1] = env->active_tc.HI[ac];                                     \
2255                                                                         \
2256     if (add_sub) {                                                      \
2257         temp_sum = acc[0] + temp[0];                                    \
2258         if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&                  \
2259             ((uint64_t)temp_sum < (uint64_t)temp[0])) {                 \
2260             acc[1] += 1;                                                \
2261         }                                                               \
2262         temp[0] = temp_sum;                                             \
2263         temp[1] = acc[1] + temp[1];                                     \
2264     } else {                                                            \
2265         temp_sum = acc[0] - temp[0];                                    \
2266         if ((uint64_t)temp_sum > (uint64_t)acc[0]) {                    \
2267             acc[1] -= 1;                                                \
2268         }                                                               \
2269         temp[0] = temp_sum;                                             \
2270         temp[1] = acc[1] - temp[1];                                     \
2271     }                                                                   \
2272                                                                         \
2273     env->active_tc.HI[ac] = temp[1];                                    \
2274     env->active_tc.LO[ac] = temp[0];                                    \
2275 }
2276
2277 DP_OB(dpau_h_obl, 1, 56, 48, 40, 32, 56, 48, 40, 32);
2278 DP_OB(dpau_h_obr, 1, 24, 16, 8, 0, 24, 16, 8, 0);
2279 DP_OB(dpsu_h_obl, 0, 56, 48, 40, 32, 56, 48, 40, 32);
2280 DP_OB(dpsu_h_obr, 0, 24, 16, 8, 0, 24, 16, 8, 0);
2281
2282 #undef DP_OB
2283 #endif
2284
2285 #define DP_NOFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2)             \
2286 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt,              \
2287                    CPUMIPSState *env)                                          \
2288 {                                                                              \
2289     int16_t rsB, rsA, rtB, rtA;                                                \
2290     int32_t  tempA, tempB;                                                     \
2291     int64_t  acc;                                                              \
2292                                                                                \
2293     rsB = (rs >> rsmov1) & MIPSDSP_LO;                                         \
2294     rsA = (rs >> rsmov2) & MIPSDSP_LO;                                         \
2295     rtB = (rt >> rtmov1) & MIPSDSP_LO;                                         \
2296     rtA = (rt >> rtmov2) & MIPSDSP_LO;                                         \
2297                                                                                \
2298     tempB = (int32_t)rsB * (int32_t)rtB;                                       \
2299     tempA = (int32_t)rsA * (int32_t)rtA;                                       \
2300                                                                                \
2301     acc = ((uint64_t)env->active_tc.HI[ac] << 32) |                            \
2302           ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);                     \
2303                                                                                \
2304     if (is_add) {                                                              \
2305         acc = acc + ((int64_t)tempB + (int64_t)tempA);                         \
2306     } else {                                                                   \
2307         acc = acc - ((int64_t)tempB + (int64_t)tempA);                         \
2308     }                                                                          \
2309                                                                                \
2310     env->active_tc.HI[ac] = (target_long)(int32_t)((acc & MIPSDSP_LHI) >> 32); \
2311     env->active_tc.LO[ac] = (target_long)(int32_t)(acc & MIPSDSP_LLO);         \
2312 }
2313
2314 DP_NOFUNC_PH(dpa_w_ph, 1, 16, 0, 16, 0);
2315 DP_NOFUNC_PH(dpax_w_ph, 1, 16, 0, 0, 16);
2316 DP_NOFUNC_PH(dps_w_ph, 0, 16, 0, 16, 0);
2317 DP_NOFUNC_PH(dpsx_w_ph, 0, 16, 0, 0, 16);
2318 #undef DP_NOFUNC_PH
2319
2320 #define DP_HASFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \
2321 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt,   \
2322                    CPUMIPSState *env)                      \
2323 {                                                          \
2324     int16_t rsB, rsA, rtB, rtA;                            \
2325     int32_t tempB, tempA;                                  \
2326     int64_t acc, dotp;                                     \
2327                                                            \
2328     rsB = (rs >> rsmov1) & MIPSDSP_LO;                     \
2329     rsA = (rs >> rsmov2) & MIPSDSP_LO;                     \
2330     rtB = (rt >> rtmov1) & MIPSDSP_LO;                     \
2331     rtA = (rt >> rtmov2) & MIPSDSP_LO;                     \
2332                                                            \
2333     tempB = mipsdsp_mul_q15_q15(ac, rsB, rtB, env);        \
2334     tempA = mipsdsp_mul_q15_q15(ac, rsA, rtA, env);        \
2335                                                            \
2336     dotp = (int64_t)tempB + (int64_t)tempA;                \
2337     acc = ((uint64_t)env->active_tc.HI[ac] << 32) |        \
2338           ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \
2339                                                            \
2340     if (is_add) {                                          \
2341         acc = acc + dotp;                                  \
2342     } else {                                               \
2343         acc = acc - dotp;                                  \
2344     }                                                      \
2345                                                            \
2346     env->active_tc.HI[ac] = (target_long)(int32_t)         \
2347         ((acc & MIPSDSP_LHI) >> 32);                       \
2348     env->active_tc.LO[ac] = (target_long)(int32_t)         \
2349         (acc & MIPSDSP_LLO);                               \
2350 }
2351
2352 DP_HASFUNC_PH(dpaq_s_w_ph, 1, 16, 0, 16, 0);
2353 DP_HASFUNC_PH(dpaqx_s_w_ph, 1, 16, 0, 0, 16);
2354 DP_HASFUNC_PH(dpsq_s_w_ph, 0, 16, 0, 16, 0);
2355 DP_HASFUNC_PH(dpsqx_s_w_ph, 0, 16, 0, 0, 16);
2356
2357 #undef DP_HASFUNC_PH
2358
2359 #define DP_128OPERATION_PH(name, is_add) \
2360 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2361                           CPUMIPSState *env)                             \
2362 {                                                                        \
2363     int16_t rsh, rsl, rth, rtl;                                          \
2364     int32_t tempB, tempA, tempC62_31, tempC63;                           \
2365     int64_t acc, dotp, tempC;                                            \
2366                                                                          \
2367     MIPSDSP_SPLIT32_16(rs, rsh, rsl);                                    \
2368     MIPSDSP_SPLIT32_16(rt, rth, rtl);                                    \
2369                                                                          \
2370     tempB = mipsdsp_mul_q15_q15(ac, rsh, rtl, env);                      \
2371     tempA = mipsdsp_mul_q15_q15(ac, rsl, rth, env);                      \
2372                                                                          \
2373     dotp = (int64_t)tempB + (int64_t)tempA;                              \
2374     acc = ((uint64_t)env->active_tc.HI[ac] << 32) |                      \
2375           ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);               \
2376     if (is_add) {                                                        \
2377         tempC = acc + dotp;                                              \
2378     } else {                                                             \
2379         tempC = acc - dotp;                                              \
2380     }                                                                    \
2381     tempC63 = (tempC >> 63) & 0x01;                                      \
2382     tempC62_31 = (tempC >> 31) & 0xFFFFFFFF;                             \
2383                                                                          \
2384     if ((tempC63 == 0) && (tempC62_31 != 0x00000000)) {                  \
2385         tempC = 0x7FFFFFFF;                                              \
2386         set_DSPControl_overflow_flag(1, 16 + ac, env);                   \
2387     }                                                                    \
2388                                                                          \
2389     if ((tempC63 == 1) && (tempC62_31 != 0xFFFFFFFF)) {                  \
2390         tempC = (int64_t)(int32_t)0x80000000;                            \
2391         set_DSPControl_overflow_flag(1, 16 + ac, env);                   \
2392     }                                                                    \
2393                                                                          \
2394     env->active_tc.HI[ac] = (target_long)(int32_t)                       \
2395         ((tempC & MIPSDSP_LHI) >> 32);                                   \
2396     env->active_tc.LO[ac] = (target_long)(int32_t)                       \
2397         (tempC & MIPSDSP_LLO);                                           \
2398 }
2399
2400 DP_128OPERATION_PH(dpaqx_sa_w_ph, 1);
2401 DP_128OPERATION_PH(dpsqx_sa_w_ph, 0);
2402
2403 #undef DP_128OPERATION_HP
2404
2405 #if defined(TARGET_MIPS64)
2406 #define DP_QH(name, is_add, use_ac_env) \
2407 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac,    \
2408                    CPUMIPSState *env)                                \
2409 {                                                                    \
2410     int32_t rs3, rs2, rs1, rs0;                                      \
2411     int32_t rt3, rt2, rt1, rt0;                                      \
2412     int32_t tempD, tempC, tempB, tempA;                              \
2413     int64_t acc[2];                                                  \
2414     int64_t temp[2];                                                 \
2415     int64_t temp_sum;                                                \
2416                                                                      \
2417     MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0);                      \
2418     MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0);                      \
2419                                                                      \
2420     if (use_ac_env) {                                                \
2421         tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env);              \
2422         tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env);              \
2423         tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env);              \
2424         tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env);              \
2425     } else {                                                         \
2426         tempD = mipsdsp_mul_u16_u16(rs3, rt3);                       \
2427         tempC = mipsdsp_mul_u16_u16(rs2, rt2);                       \
2428         tempB = mipsdsp_mul_u16_u16(rs1, rt1);                       \
2429         tempA = mipsdsp_mul_u16_u16(rs0, rt0);                       \
2430     }                                                                \
2431                                                                      \
2432     temp[0] = (int64_t)tempD + (int64_t)tempC +                      \
2433               (int64_t)tempB + (int64_t)tempA;                       \
2434                                                                      \
2435     if (temp[0] >= 0) {                                              \
2436         temp[1] = 0;                                                 \
2437     } else {                                                         \
2438         temp[1] = ~0ull;                                             \
2439     }                                                                \
2440                                                                      \
2441     acc[1] = env->active_tc.HI[ac];                                  \
2442     acc[0] = env->active_tc.LO[ac];                                  \
2443                                                                      \
2444     if (is_add) {                                                    \
2445         temp_sum = acc[0] + temp[0];                                 \
2446         if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&               \
2447             ((uint64_t)temp_sum < (uint64_t)temp[0])) {              \
2448             acc[1] = acc[1] + 1;                                     \
2449         }                                                            \
2450         temp[0] = temp_sum;                                          \
2451         temp[1] = acc[1] + temp[1];                                  \
2452     } else {                                                         \
2453         temp_sum = acc[0] - temp[0];                                 \
2454         if ((uint64_t)temp_sum > (uint64_t)acc[0]) {                 \
2455             acc[1] = acc[1] - 1;                                     \
2456         }                                                            \
2457         temp[0] = temp_sum;                                          \
2458         temp[1] = acc[1] - temp[1];                                  \
2459     }                                                                \
2460                                                                      \
2461     env->active_tc.HI[ac] = temp[1];                                 \
2462     env->active_tc.LO[ac] = temp[0];                                 \
2463 }
2464
2465 DP_QH(dpa_w_qh, 1, 0);
2466 DP_QH(dpaq_s_w_qh, 1, 1);
2467 DP_QH(dps_w_qh, 0, 0);
2468 DP_QH(dpsq_s_w_qh, 0, 1);
2469
2470 #undef DP_QH
2471
2472 #endif
2473
2474 #define DP_L_W(name, is_add) \
2475 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt,      \
2476                    CPUMIPSState *env)                                  \
2477 {                                                                      \
2478     int32_t temp63;                                                    \
2479     int64_t dotp, acc;                                                 \
2480     uint64_t temp;                                                     \
2481     bool overflow;                                                     \
2482                                                                        \
2483     dotp = mipsdsp_mul_q31_q31(ac, rs, rt, env);                       \
2484     acc = ((uint64_t)env->active_tc.HI[ac] << 32) |                    \
2485           ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);             \
2486     if (is_add) {                                                      \
2487         temp = acc + dotp;                                             \
2488         overflow = MIPSDSP_OVERFLOW_ADD((uint64_t)acc, (uint64_t)dotp, \
2489                                         temp, (0x01ull << 63));        \
2490     } else {                                                           \
2491         temp = acc - dotp;                                             \
2492         overflow = MIPSDSP_OVERFLOW_SUB((uint64_t)acc, (uint64_t)dotp, \
2493                                         temp, (0x01ull << 63));        \
2494     }                                                                  \
2495                                                                        \
2496     if (overflow) {                                                    \
2497         temp63 = (temp >> 63) & 0x01;                                  \
2498         if (temp63 == 1) {                                             \
2499             temp = (0x01ull << 63) - 1;                                \
2500         } else {                                                       \
2501             temp = 0x01ull << 63;                                      \
2502         }                                                              \
2503                                                                        \
2504         set_DSPControl_overflow_flag(1, 16 + ac, env);                 \
2505     }                                                                  \
2506                                                                        \
2507     env->active_tc.HI[ac] = (target_long)(int32_t)                     \
2508         ((temp & MIPSDSP_LHI) >> 32);                                  \
2509     env->active_tc.LO[ac] = (target_long)(int32_t)                     \
2510         (temp & MIPSDSP_LLO);                                          \
2511 }
2512
2513 DP_L_W(dpaq_sa_l_w, 1);
2514 DP_L_W(dpsq_sa_l_w, 0);
2515
2516 #undef DP_L_W
2517
2518 #if defined(TARGET_MIPS64)
2519 #define DP_L_PW(name, func) \
2520 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2521                    CPUMIPSState *env)                             \
2522 {                                                                 \
2523     int32_t rs1, rs0;                                             \
2524     int32_t rt1, rt0;                                             \
2525     int64_t tempB[2], tempA[2];                                   \
2526     int64_t temp[2];                                              \
2527     int64_t acc[2];                                               \
2528     int64_t temp_sum;                                             \
2529                                                                   \
2530     temp[0] = 0;                                                  \
2531     temp[1] = 0;                                                  \
2532                                                                   \
2533     MIPSDSP_SPLIT64_32(rs, rs1, rs0);                             \
2534     MIPSDSP_SPLIT64_32(rt, rt1, rt0);                             \
2535                                                                   \
2536     tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env);            \
2537     tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env);            \
2538                                                                   \
2539     if (tempB[0] >= 0) {                                          \
2540         tempB[1] = 0x00;                                          \
2541     } else {                                                      \
2542         tempB[1] = ~0ull;                                         \
2543     }                                                             \
2544                                                                   \
2545     if (tempA[0] >= 0) {                                          \
2546         tempA[1] = 0x00;                                          \
2547     } else {                                                      \
2548         tempA[1] = ~0ull;                                         \
2549     }                                                             \
2550                                                                   \
2551     temp_sum = tempB[0] + tempA[0];                               \
2552     if (((uint64_t)temp_sum < (uint64_t)tempB[0]) &&              \
2553         ((uint64_t)temp_sum < (uint64_t)tempA[0])) {              \
2554         temp[1] += 1;                                             \
2555     }                                                             \
2556     temp[0] = temp_sum;                                           \
2557     temp[1] += tempB[1] + tempA[1];                               \
2558                                                                   \
2559     mipsdsp_##func(acc, ac, temp, env);                           \
2560                                                                   \
2561     env->active_tc.HI[ac] = acc[1];                               \
2562     env->active_tc.LO[ac] = acc[0];                               \
2563 }
2564
2565 DP_L_PW(dpaq_sa_l_pw, sat64_acc_add_q63);
2566 DP_L_PW(dpsq_sa_l_pw, sat64_acc_sub_q63);
2567
2568 #undef DP_L_PW
2569
2570 void helper_mulsaq_s_l_pw(target_ulong rs, target_ulong rt, uint32_t ac,
2571                           CPUMIPSState *env)
2572 {
2573     int32_t rs1, rs0;
2574     int32_t rt1, rt0;
2575     int64_t tempB[2], tempA[2];
2576     int64_t temp[2];
2577     int64_t acc[2];
2578     int64_t temp_sum;
2579
2580     rs1 = (rs >> 32) & MIPSDSP_LLO;
2581     rs0 = rs & MIPSDSP_LLO;
2582     rt1 = (rt >> 32) & MIPSDSP_LLO;
2583     rt0 = rt & MIPSDSP_LLO;
2584
2585     tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env);
2586     tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env);
2587
2588     if (tempB[0] >= 0) {
2589         tempB[1] = 0x00;
2590     } else {
2591         tempB[1] = ~0ull;
2592     }
2593
2594     if (tempA[0] >= 0) {
2595         tempA[1] = 0x00;
2596     } else {
2597         tempA[1] = ~0ull;
2598     }
2599
2600     acc[0] = env->active_tc.LO[ac];
2601     acc[1] = env->active_tc.HI[ac];
2602
2603     temp_sum = tempB[0] - tempA[0];
2604     if ((uint64_t)temp_sum > (uint64_t)tempB[0]) {
2605         tempB[1] -= 1;
2606     }
2607     temp[0] = temp_sum;
2608     temp[1] = tempB[1] - tempA[1];
2609
2610     if ((temp[1] & 0x01) == 0) {
2611         temp[1] = 0x00;
2612     } else {
2613         temp[1] = ~0ull;
2614     }
2615
2616     temp_sum = acc[0] + temp[0];
2617     if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&
2618        ((uint64_t)temp_sum < (uint64_t)temp[0])) {
2619         acc[1] += 1;
2620     }
2621     acc[0] = temp_sum;
2622     acc[1] += temp[1];
2623
2624     env->active_tc.HI[ac] = acc[1];
2625     env->active_tc.LO[ac] = acc[0];
2626 }
2627 #endif
2628
2629 #define MAQ_S_W(name, mov) \
2630 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \
2631                    CPUMIPSState *env)                             \
2632 {                                                                 \
2633     int16_t rsh, rth;                                             \
2634     int32_t tempA;                                                \
2635     int64_t tempL, acc;                                           \
2636                                                                   \
2637     rsh = (rs >> mov) & MIPSDSP_LO;                               \
2638     rth = (rt >> mov) & MIPSDSP_LO;                               \
2639     tempA  = mipsdsp_mul_q15_q15(ac, rsh, rth, env);              \
2640     acc = ((uint64_t)env->active_tc.HI[ac] << 32) |               \
2641           ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);        \
2642     tempL  = (int64_t)tempA + acc;                                \
2643     env->active_tc.HI[ac] = (target_long)(int32_t)                \
2644         ((tempL & MIPSDSP_LHI) >> 32);                            \
2645     env->active_tc.LO[ac] = (target_long)(int32_t)                \
2646         (tempL & MIPSDSP_LLO);                                    \
2647 }
2648
2649 MAQ_S_W(maq_s_w_phl, 16);
2650 MAQ_S_W(maq_s_w_phr, 0);
2651
2652 #undef MAQ_S_W
2653
2654 #define MAQ_SA_W(name, mov) \
2655 void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt,        \
2656                    CPUMIPSState *env)                                    \
2657 {                                                                        \
2658     int16_t rsh, rth;                                                    \
2659     int32_t tempA;                                                       \
2660                                                                          \
2661     rsh = (rs >> mov) & MIPSDSP_LO;                                      \
2662     rth = (rt >> mov) & MIPSDSP_LO;                                      \
2663     tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env);                      \
2664     tempA = mipsdsp_sat32_acc_q31(ac, tempA, env);                       \
2665                                                                          \
2666     env->active_tc.HI[ac] = (target_long)(int32_t)(((int64_t)tempA &     \
2667                                                     MIPSDSP_LHI) >> 32); \
2668     env->active_tc.LO[ac] = (target_long)(int32_t)((int64_t)tempA &      \
2669                                                    MIPSDSP_LLO);         \
2670 }
2671
2672 MAQ_SA_W(maq_sa_w_phl, 16);
2673 MAQ_SA_W(maq_sa_w_phr, 0);
2674
2675 #undef MAQ_SA_W
2676
2677 #define MULQ_W(name, addvar) \
2678 target_ulong helper_##name(target_ulong rs, target_ulong rt,   \
2679                            CPUMIPSState *env)                  \
2680 {                                                              \
2681     int32_t rs_t, rt_t;                                        \
2682     int32_t tempI;                                             \
2683     int64_t tempL;                                             \
2684                                                                \
2685     rs_t = rs & MIPSDSP_LLO;                                   \
2686     rt_t = rt & MIPSDSP_LLO;                                   \
2687                                                                \
2688     if ((rs_t == 0x80000000) && (rt_t == 0x80000000)) {        \
2689         tempL = 0x7FFFFFFF00000000ull;                         \
2690         set_DSPControl_overflow_flag(1, 21, env);              \
2691     } else {                                                   \
2692         tempL  = ((int64_t)rs_t * (int64_t)rt_t) << 1;         \
2693         tempL += addvar;                                       \
2694     }                                                          \
2695     tempI = (tempL & MIPSDSP_LHI) >> 32;                       \
2696                                                                \
2697     return (target_long)(int32_t)tempI;                        \
2698 }
2699
2700 MULQ_W(mulq_s_w, 0);
2701 MULQ_W(mulq_rs_w, 0x80000000ull);
2702
2703 #undef MULQ_W
2704
2705 #if defined(TARGET_MIPS64)
2706
2707 #define MAQ_S_W_QH(name, mov) \
2708 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2709                    CPUMIPSState *env)                             \
2710 {                                                                 \
2711     int16_t rs_t, rt_t;                                           \
2712     int32_t temp_mul;                                             \
2713     int64_t temp[2];                                              \
2714     int64_t acc[2];                                               \
2715     int64_t temp_sum;                                             \
2716                                                                   \
2717     temp[0] = 0;                                                  \
2718     temp[1] = 0;                                                  \
2719                                                                   \
2720     rs_t = (rs >> mov) & MIPSDSP_LO;                              \
2721     rt_t = (rt >> mov) & MIPSDSP_LO;                              \
2722     temp_mul = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env);          \
2723                                                                   \
2724     temp[0] = (int64_t)temp_mul;                                  \
2725     if (temp[0] >= 0) {                                           \
2726         temp[1] = 0x00;                                           \
2727     } else {                                                      \
2728         temp[1] = ~0ull;                                          \
2729     }                                                             \
2730                                                                   \
2731     acc[0] = env->active_tc.LO[ac];                               \
2732     acc[1] = env->active_tc.HI[ac];                               \
2733                                                                   \
2734     temp_sum = acc[0] + temp[0];                                  \
2735     if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&                \
2736         ((uint64_t)temp_sum < (uint64_t)temp[0])) {               \
2737         acc[1] += 1;                                              \
2738     }                                                             \
2739     acc[0] = temp_sum;                                            \
2740     acc[1] += temp[1];                                            \
2741                                                                   \
2742     env->active_tc.HI[ac] = acc[1];                               \
2743     env->active_tc.LO[ac] = acc[0];                               \
2744 }
2745
2746 MAQ_S_W_QH(maq_s_w_qhll, 48);
2747 MAQ_S_W_QH(maq_s_w_qhlr, 32);
2748 MAQ_S_W_QH(maq_s_w_qhrl, 16);
2749 MAQ_S_W_QH(maq_s_w_qhrr, 0);
2750
2751 #undef MAQ_S_W_QH
2752
2753 #define MAQ_SA_W(name, mov) \
2754 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2755                    CPUMIPSState *env)                             \
2756 {                                                                 \
2757     int16_t rs_t, rt_t;                                           \
2758     int32_t temp;                                                 \
2759     int64_t acc[2];                                               \
2760                                                                   \
2761     rs_t = (rs >> mov) & MIPSDSP_LO;                              \
2762     rt_t = (rt >> mov) & MIPSDSP_LO;                              \
2763     temp = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env);              \
2764     temp = mipsdsp_sat32_acc_q31(ac, temp, env);                  \
2765                                                                   \
2766     acc[0] = (int64_t)(int32_t)temp;                              \
2767     if (acc[0] >= 0) {                                            \
2768         acc[1] = 0x00;                                            \
2769     } else {                                                      \
2770         acc[1] = ~0ull;                                           \
2771     }                                                             \
2772                                                                   \
2773     env->active_tc.HI[ac] = acc[1];                               \
2774     env->active_tc.LO[ac] = acc[0];                               \
2775 }
2776
2777 MAQ_SA_W(maq_sa_w_qhll, 48);
2778 MAQ_SA_W(maq_sa_w_qhlr, 32);
2779 MAQ_SA_W(maq_sa_w_qhrl, 16);
2780 MAQ_SA_W(maq_sa_w_qhrr, 0);
2781
2782 #undef MAQ_SA_W
2783
2784 #define MAQ_S_L_PW(name, mov) \
2785 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \
2786                    CPUMIPSState *env)                             \
2787 {                                                                 \
2788     int32_t rs_t, rt_t;                                           \
2789     int64_t temp[2];                                              \
2790     int64_t acc[2];                                               \
2791     int64_t temp_sum;                                             \
2792                                                                   \
2793     temp[0] = 0;                                                  \
2794     temp[1] = 0;                                                  \
2795                                                                   \
2796     rs_t = (rs >> mov) & MIPSDSP_LLO;                             \
2797     rt_t = (rt >> mov) & MIPSDSP_LLO;                             \
2798                                                                   \
2799     temp[0] = mipsdsp_mul_q31_q31(ac, rs_t, rt_t, env);           \
2800     if (temp[0] >= 0) {                                           \
2801         temp[1] = 0x00;                                           \
2802     } else {                                                      \
2803         temp[1] = ~0ull;                                          \
2804     }                                                             \
2805                                                                   \
2806     acc[0] = env->active_tc.LO[ac];                               \
2807     acc[1] = env->active_tc.HI[ac];                               \
2808                                                                   \
2809     temp_sum = acc[0] + temp[0];                                  \
2810     if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&                \
2811         ((uint64_t)temp_sum < (uint64_t)temp[0])) {               \
2812         acc[1] += 1;                                              \
2813     }                                                             \
2814     acc[0] = temp_sum;                                            \
2815     acc[1] += temp[1];                                            \
2816                                                                   \
2817     env->active_tc.HI[ac] = acc[1];                               \
2818     env->active_tc.LO[ac] = acc[0];                               \
2819 }
2820
2821 MAQ_S_L_PW(maq_s_l_pwl, 32);
2822 MAQ_S_L_PW(maq_s_l_pwr, 0);
2823
2824 #undef MAQ_S_L_PW
2825
2826 #define DM_OPERATE(name, func, is_add, sigext) \
2827 void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac,    \
2828                   CPUMIPSState *env)                                 \
2829 {                                                                    \
2830     int32_t rs1, rs0;                                                \
2831     int32_t rt1, rt0;                                                \
2832     int64_t tempBL[2], tempAL[2];                                    \
2833     int64_t acc[2];                                                  \
2834     int64_t temp[2];                                                 \
2835     int64_t temp_sum;                                                \
2836                                                                      \
2837     temp[0] = 0x00;                                                  \
2838     temp[1] = 0x00;                                                  \
2839                                                                      \
2840     MIPSDSP_SPLIT64_32(rs, rs1, rs0);                                \
2841     MIPSDSP_SPLIT64_32(rt, rt1, rt0);                                \
2842                                                                      \
2843     if (sigext) {                                                    \
2844         tempBL[0] = (int64_t)mipsdsp_##func(rs1, rt1);               \
2845         tempAL[0] = (int64_t)mipsdsp_##func(rs0, rt0);               \
2846                                                                      \
2847         if (tempBL[0] >= 0) {                                        \
2848             tempBL[1] = 0x0;                                         \
2849         } else {                                                     \
2850             tempBL[1] = ~0ull;                                       \
2851         }                                                            \
2852                                                                      \
2853         if (tempAL[0] >= 0) {                                        \
2854             tempAL[1] = 0x0;                                         \
2855         } else {                                                     \
2856             tempAL[1] = ~0ull;                                       \
2857         }                                                            \
2858     } else {                                                         \
2859         tempBL[0] = mipsdsp_##func(rs1, rt1);                        \
2860         tempAL[0] = mipsdsp_##func(rs0, rt0);                        \
2861         tempBL[1] = 0;                                               \
2862         tempAL[1] = 0;                                               \
2863     }                                                                \
2864                                                                      \
2865     acc[1] = env->active_tc.HI[ac];                                  \
2866     acc[0] = env->active_tc.LO[ac];                                  \
2867                                                                      \
2868     temp_sum = tempBL[0] + tempAL[0];                                \
2869     if (((uint64_t)temp_sum < (uint64_t)tempBL[0]) &&                \
2870         ((uint64_t)temp_sum < (uint64_t)tempAL[0])) {                \
2871         temp[1] += 1;                                                \
2872     }                                                                \
2873     temp[0] = temp_sum;                                              \
2874     temp[1] += tempBL[1] + tempAL[1];                                \
2875                                                                      \
2876     if (is_add) {                                                    \
2877         temp_sum = acc[0] + temp[0];                                 \
2878         if (((uint64_t)temp_sum < (uint64_t)acc[0]) &&               \
2879             ((uint64_t)temp_sum < (uint64_t)temp[0])) {              \
2880             acc[1] += 1;                                             \
2881         }                                                            \
2882         temp[0] = temp_sum;                                          \
2883         temp[1] = acc[1] + temp[1];                                  \
2884     } else {                                                         \
2885         temp_sum = acc[0] - temp[0];                                 \
2886         if ((uint64_t)temp_sum > (uint64_t)acc[0]) {                 \
2887             acc[1] -= 1;                                             \
2888         }                                                            \
2889         temp[0] = temp_sum;                                          \
2890         temp[1] = acc[1] - temp[1];                                  \
2891     }                                                                \
2892                                                                      \
2893     env->active_tc.HI[ac] = temp[1];                                 \
2894     env->active_tc.LO[ac] = temp[0];                                 \
2895 }
2896
2897 DM_OPERATE(dmadd, mul_i32_i32, 1, 1);
2898 DM_OPERATE(dmaddu, mul_u32_u32, 1, 0);
2899 DM_OPERATE(dmsub, mul_i32_i32, 0, 1);
2900 DM_OPERATE(dmsubu, mul_u32_u32, 0, 0);
2901 #undef DM_OPERATE
2902 #endif
2903
2904 /** DSP Bit/Manipulation Sub-class insns **/
2905 target_ulong helper_bitrev(target_ulong rt)
2906 {
2907     int32_t temp;
2908     uint32_t rd;
2909     int i;
2910
2911     temp = rt & MIPSDSP_LO;
2912     rd = 0;
2913     for (i = 0; i < 16; i++) {
2914         rd = (rd << 1) | (temp & 1);
2915         temp = temp >> 1;
2916     }
2917
2918     return (target_ulong)rd;
2919 }
2920
2921 #define BIT_INSV(name, posfilter, sizefilter, ret_type)         \
2922 target_ulong helper_##name(CPUMIPSState *env, target_ulong rs,  \
2923                            target_ulong rt)                     \
2924 {                                                               \
2925     uint32_t pos, size, msb, lsb;                               \
2926     target_ulong filter;                                        \
2927     target_ulong temp, temprs, temprt;                          \
2928     target_ulong dspc;                                          \
2929                                                                 \
2930     dspc = env->active_tc.DSPControl;                           \
2931                                                                 \
2932     pos  = dspc & posfilter;                                    \
2933     size = (dspc >> 7) & sizefilter;                            \
2934                                                                 \
2935     msb  = pos + size - 1;                                      \
2936     lsb  = pos;                                                 \
2937                                                                 \
2938     if (lsb > msb || (msb > TARGET_LONG_BITS)) {                \
2939         return rt;                                              \
2940     }                                                           \
2941                                                                 \
2942     filter = ((int32_t)0x01 << size) - 1;                       \
2943     filter = filter << pos;                                     \
2944     temprs = (rs << pos) & filter;                              \
2945     temprt = rt & ~filter;                                      \
2946     temp = temprs | temprt;                                     \
2947                                                                 \
2948     return (target_long)(ret_type)temp;                         \
2949 }
2950
2951 BIT_INSV(insv, 0x1F, 0x1F, int32_t);
2952 #ifdef TARGET_MIPS64
2953 BIT_INSV(dinsv, 0x7F, 0x3F, target_long);
2954 #endif
2955
2956 #undef BIT_INSV
2957
2958
2959 /** DSP Compare-Pick Sub-class insns **/
2960 #define CMP_HAS_RET(name, func, split_num, filter, bit_size) \
2961 target_ulong helper_##name(target_ulong rs, target_ulong rt) \
2962 {                                                       \
2963     uint32_t rs_t, rt_t;                                \
2964     uint8_t cc;                                         \
2965     uint32_t temp = 0;                                  \
2966     int i;                                              \
2967                                                         \
2968     for (i = 0; i < split_num; i++) {                   \
2969         rs_t = (rs >> (bit_size * i)) & filter;         \
2970         rt_t = (rt >> (bit_size * i)) & filter;         \
2971         cc = mipsdsp_##func(rs_t, rt_t);                \
2972         temp |= cc << i;                                \
2973     }                                                   \
2974                                                         \
2975     return (target_ulong)temp;                          \
2976 }
2977
2978 CMP_HAS_RET(cmpgu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
2979 CMP_HAS_RET(cmpgu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
2980 CMP_HAS_RET(cmpgu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
2981
2982 #ifdef TARGET_MIPS64
2983 CMP_HAS_RET(cmpgu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
2984 CMP_HAS_RET(cmpgu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
2985 CMP_HAS_RET(cmpgu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
2986 #endif
2987
2988 #undef CMP_HAS_RET
2989
2990
2991 #define CMP_NO_RET(name, func, split_num, filter, bit_size) \
2992 void helper_##name(target_ulong rs, target_ulong rt,        \
2993                             CPUMIPSState *env)              \
2994 {                                                           \
2995     int##bit_size##_t rs_t, rt_t;                           \
2996     int##bit_size##_t flag = 0;                             \
2997     int##bit_size##_t cc;                                   \
2998     int i;                                                  \
2999                                                             \
3000     for (i = 0; i < split_num; i++) {                       \
3001         rs_t = (rs >> (bit_size * i)) & filter;             \
3002         rt_t = (rt >> (bit_size * i)) & filter;             \
3003                                                             \
3004         cc = mipsdsp_##func((int32_t)rs_t, (int32_t)rt_t);  \
3005         flag |= cc << i;                                    \
3006     }                                                       \
3007                                                             \
3008     set_DSPControl_24(flag, split_num, env);                \
3009 }
3010
3011 CMP_NO_RET(cmpu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8);
3012 CMP_NO_RET(cmpu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8);
3013 CMP_NO_RET(cmpu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8);
3014
3015 CMP_NO_RET(cmp_eq_ph, cmp_eq, 2, MIPSDSP_LO, 16);
3016 CMP_NO_RET(cmp_lt_ph, cmp_lt, 2, MIPSDSP_LO, 16);
3017 CMP_NO_RET(cmp_le_ph, cmp_le, 2, MIPSDSP_LO, 16);
3018
3019 #ifdef TARGET_MIPS64
3020 CMP_NO_RET(cmpu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8);
3021 CMP_NO_RET(cmpu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8);
3022 CMP_NO_RET(cmpu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8);
3023
3024 CMP_NO_RET(cmp_eq_qh, cmp_eq, 4, MIPSDSP_LO, 16);
3025 CMP_NO_RET(cmp_lt_qh, cmp_lt, 4, MIPSDSP_LO, 16);
3026 CMP_NO_RET(cmp_le_qh, cmp_le, 4, MIPSDSP_LO, 16);
3027
3028 CMP_NO_RET(cmp_eq_pw, cmp_eq, 2, MIPSDSP_LLO, 32);
3029 CMP_NO_RET(cmp_lt_pw, cmp_lt, 2, MIPSDSP_LLO, 32);
3030 CMP_NO_RET(cmp_le_pw, cmp_le, 2, MIPSDSP_LLO, 32);
3031 #endif
3032 #undef CMP_NO_RET
3033
3034 #if defined(TARGET_MIPS64)
3035
3036 #define CMPGDU_OB(name) \
3037 target_ulong helper_cmpgdu_##name##_ob(target_ulong rs, target_ulong rt, \
3038                                        CPUMIPSState *env)  \
3039 {                                                     \
3040     int i;                                            \
3041     uint8_t rs_t, rt_t;                               \
3042     uint32_t cond;                                    \
3043                                                       \
3044     cond = 0;                                         \
3045                                                       \
3046     for (i = 0; i < 8; i++) {                         \
3047         rs_t = (rs >> (8 * i)) & MIPSDSP_Q0;          \
3048         rt_t = (rt >> (8 * i)) & MIPSDSP_Q0;          \
3049                                                       \
3050         if (mipsdsp_cmpu_##name(rs_t, rt_t)) {        \
3051             cond |= 0x01 << i;                        \
3052         }                                             \
3053     }                                                 \
3054                                                       \
3055     set_DSPControl_24(cond, 8, env);                  \
3056                                                       \
3057     return (uint64_t)cond;                            \
3058 }
3059
3060 CMPGDU_OB(eq)
3061 CMPGDU_OB(lt)
3062 CMPGDU_OB(le)
3063 #undef CMPGDU_OB
3064 #endif
3065
3066 #define PICK_INSN(name, split_num, filter, bit_size, ret32bit) \
3067 target_ulong helper_##name(target_ulong rs, target_ulong rt,   \
3068                             CPUMIPSState *env)                 \
3069 {                                                              \
3070     uint32_t rs_t, rt_t;                                       \
3071     uint32_t cc;                                               \
3072     target_ulong dsp;                                          \
3073     int i;                                                     \
3074     target_ulong result = 0;                                   \
3075                                                                \
3076     dsp = env->active_tc.DSPControl;                           \
3077     for (i = 0; i < split_num; i++) {                          \
3078         rs_t = (rs >> (bit_size * i)) & filter;                \
3079         rt_t = (rt >> (bit_size * i)) & filter;                \
3080         cc = (dsp >> (24 + i)) & 0x01;                         \
3081         cc = cc == 1 ? rs_t : rt_t;                            \
3082                                                                \
3083         result |= (target_ulong)cc << (bit_size * i);          \
3084     }                                                          \
3085                                                                \
3086     if (ret32bit) {                                            \
3087         result = (target_long)(int32_t)(result & MIPSDSP_LLO); \
3088     }                                                          \
3089                                                                \
3090     return result;                                             \
3091 }
3092
3093 PICK_INSN(pick_qb, 4, MIPSDSP_Q0, 8, 1);
3094 PICK_INSN(pick_ph, 2, MIPSDSP_LO, 16, 1);
3095
3096 #ifdef TARGET_MIPS64
3097 PICK_INSN(pick_ob, 8, MIPSDSP_Q0, 8, 0);
3098 PICK_INSN(pick_qh, 4, MIPSDSP_LO, 16, 0);
3099 PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0);
3100 #endif
3101 #undef PICK_INSN
3102
3103 target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt)
3104 {
3105     uint32_t rsl, rth;
3106
3107     rsl =  rs & MIPSDSP_LO;
3108     rth = (rt & MIPSDSP_HI) >> 16;
3109
3110     return (target_long)(int32_t)((rsl << 16) | rth);
3111 }
3112
3113 #if defined(TARGET_MIPS64)
3114 target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt)
3115 {
3116     uint32_t rs0, rt1;
3117
3118     rs0 = rs & MIPSDSP_LLO;
3119     rt1 = (rt >> 32) & MIPSDSP_LLO;
3120
3121     return ((uint64_t)rs0 << 32) | (uint64_t)rt1;
3122 }
3123 #endif
3124
3125 /** DSP Accumulator and DSPControl Access Sub-class insns **/
3126 target_ulong helper_extr_w(target_ulong ac, target_ulong shift,
3127                            CPUMIPSState *env)
3128 {
3129     int32_t tempI;
3130     int64_t tempDL[2];
3131
3132     shift = shift & 0x1F;
3133
3134     mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3135     if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3136         (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3137         set_DSPControl_overflow_flag(1, 23, env);
3138     }
3139
3140     tempI = (tempDL[0] >> 1) & MIPSDSP_LLO;
3141
3142     tempDL[0] += 1;
3143     if (tempDL[0] == 0) {
3144         tempDL[1] += 1;
3145     }
3146
3147     if (((tempDL[1] & 0x01) != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3148         ((tempDL[1] & 0x01) != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3149         set_DSPControl_overflow_flag(1, 23, env);
3150     }
3151
3152     return (target_long)tempI;
3153 }
3154
3155 target_ulong helper_extr_r_w(target_ulong ac, target_ulong shift,
3156                              CPUMIPSState *env)
3157 {
3158     int64_t tempDL[2];
3159
3160     shift = shift & 0x1F;
3161
3162     mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3163     if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3164         (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3165         set_DSPControl_overflow_flag(1, 23, env);
3166     }
3167
3168     tempDL[0] += 1;
3169     if (tempDL[0] == 0) {
3170         tempDL[1] += 1;
3171     }
3172
3173     if (((tempDL[1] & 0x01) != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3174         ((tempDL[1] & 0x01) != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3175         set_DSPControl_overflow_flag(1, 23, env);
3176     }
3177
3178     return (target_long)(int32_t)(tempDL[0] >> 1);
3179 }
3180
3181 target_ulong helper_extr_rs_w(target_ulong ac, target_ulong shift,
3182                               CPUMIPSState *env)
3183 {
3184     int32_t tempI, temp64;
3185     int64_t tempDL[2];
3186
3187     shift = shift & 0x1F;
3188
3189     mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env);
3190     if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3191         (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3192         set_DSPControl_overflow_flag(1, 23, env);
3193     }
3194     tempDL[0] += 1;
3195     if (tempDL[0] == 0) {
3196         tempDL[1] += 1;
3197     }
3198     tempI = tempDL[0] >> 1;
3199
3200     if (((tempDL[1] & 0x01) != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) &&
3201         ((tempDL[1] & 0x01) != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) {
3202         temp64 = tempDL[1] & 0x01;
3203         if (temp64 == 0) {
3204             tempI = 0x7FFFFFFF;
3205         } else {
3206             tempI = 0x80000000;
3207         }
3208         set_DSPControl_overflow_flag(1, 23, env);
3209     }
3210
3211     return (target_long)tempI;
3212 }
3213
3214 #if defined(TARGET_MIPS64)
3215 target_ulong helper_dextr_w(target_ulong ac, target_ulong shift,
3216                             CPUMIPSState *env)
3217 {
3218     uint64_t temp[3];
3219
3220     shift = shift & 0x3F;
3221
3222     mipsdsp_rndrashift_acc(temp, ac, shift, env);
3223
3224     return (int64_t)(int32_t)(temp[0] >> 1);
3225 }
3226
3227 target_ulong helper_dextr_r_w(target_ulong ac, target_ulong shift,
3228                               CPUMIPSState *env)
3229 {
3230     uint64_t temp[3];
3231     uint32_t temp128;
3232
3233     shift = shift & 0x3F;
3234     mipsdsp_rndrashift_acc(temp, ac, shift, env);
3235
3236     temp[0] += 1;
3237     if (temp[0] == 0) {
3238         temp[1] += 1;
3239         if (temp[1] == 0) {
3240             temp[2] += 1;
3241         }
3242     }
3243
3244     temp128 = temp[2] & 0x01;
3245
3246     if ((temp128 != 0 || temp[1] != 0) &&
3247        (temp128 != 1 || temp[1] != ~0ull)) {
3248         set_DSPControl_overflow_flag(1, 23, env);
3249     }
3250
3251     return (int64_t)(int32_t)(temp[0] >> 1);
3252 }
3253
3254 target_ulong helper_dextr_rs_w(target_ulong ac, target_ulong shift,
3255                                CPUMIPSState *env)
3256 {
3257     uint64_t temp[3];
3258     uint32_t temp128;
3259
3260     shift = shift & 0x3F;
3261     mipsdsp_rndrashift_acc(temp, ac, shift, env);
3262
3263     temp[0] += 1;
3264     if (temp[0] == 0) {
3265         temp[1] += 1;
3266         if (temp[1] == 0) {
3267             temp[2] += 1;
3268         }
3269     }
3270
3271     temp128 = temp[2] & 0x01;
3272
3273     if ((temp128 != 0 || temp[1] != 0) &&
3274        (temp128 != 1 || temp[1] != ~0ull)) {
3275         if (temp128 == 0) {
3276             temp[0] = 0x0FFFFFFFF;
3277         } else {
3278             temp[0] = 0x0100000000ULL;
3279         }
3280         set_DSPControl_overflow_flag(1, 23, env);
3281     }
3282
3283     return (int64_t)(int32_t)(temp[0] >> 1);
3284 }
3285
3286 target_ulong helper_dextr_l(target_ulong ac, target_ulong shift,
3287                             CPUMIPSState *env)
3288 {
3289     uint64_t temp[3];
3290     target_ulong result;
3291
3292     shift = shift & 0x3F;
3293
3294     mipsdsp_rndrashift_acc(temp, ac, shift, env);
3295     result = (temp[1] << 63) | (temp[0] >> 1);
3296
3297     return result;
3298 }
3299
3300 target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift,
3301                               CPUMIPSState *env)
3302 {
3303     uint64_t temp[3];
3304     uint32_t temp128;
3305     target_ulong result;
3306
3307     shift = shift & 0x3F;
3308     mipsdsp_rndrashift_acc(temp, ac, shift, env);
3309
3310     temp[0] += 1;
3311     if (temp[0] == 0) {
3312         temp[1] += 1;
3313         if (temp[1] == 0) {
3314             temp[2] += 1;
3315         }
3316     }
3317
3318     temp128 = temp[2] & 0x01;
3319
3320     if ((temp128 != 0 || temp[1] != 0) &&
3321        (temp128 != 1 || temp[1] != ~0ull)) {
3322         set_DSPControl_overflow_flag(1, 23, env);
3323     }
3324
3325     result = (temp[1] << 63) | (temp[0] >> 1);
3326
3327     return result;
3328 }
3329
3330 target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift,
3331                                CPUMIPSState *env)
3332 {
3333     uint64_t temp[3];
3334     uint32_t temp128;
3335     target_ulong result;
3336
3337     shift = shift & 0x3F;
3338     mipsdsp_rndrashift_acc(temp, ac, shift, env);
3339
3340     temp[0] += 1;
3341     if (temp[0] == 0) {
3342         temp[1] += 1;
3343         if (temp[1] == 0) {
3344             temp[2] += 1;
3345         }
3346     }
3347
3348     temp128 = temp[2] & 0x01;
3349
3350     if ((temp128 != 0 || temp[1] != 0) &&
3351        (temp128 != 1 || temp[1] != ~0ull)) {
3352         if (temp128 == 0) {
3353             temp[1] &= ~0x00ull - 1;
3354             temp[0] |= ~0x00ull - 1;
3355         } else {
3356             temp[1] |= 0x01;
3357             temp[0] &= 0x01;
3358         }
3359         set_DSPControl_overflow_flag(1, 23, env);
3360     }
3361     result = (temp[1] << 63) | (temp[0] >> 1);
3362
3363     return result;
3364 }
3365 #endif
3366
3367 target_ulong helper_extr_s_h(target_ulong ac, target_ulong shift,
3368                              CPUMIPSState *env)
3369 {
3370     int64_t temp, acc;
3371
3372     shift = shift & 0x1F;
3373
3374     acc = ((int64_t)env->active_tc.HI[ac] << 32) |
3375           ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF);
3376
3377     temp = acc >> shift;
3378
3379     if (temp > (int64_t)0x7FFF) {
3380         temp = 0x00007FFF;
3381         set_DSPControl_overflow_flag(1, 23, env);
3382     } else if (temp < (int64_t)0xFFFFFFFFFFFF8000ULL) {
3383         temp = 0xFFFF8000;
3384         set_DSPControl_overflow_flag(1, 23, env);
3385     }
3386
3387     return (target_long)(int32_t)(temp & 0xFFFFFFFF);
3388 }
3389
3390
3391 #if defined(TARGET_MIPS64)
3392 target_ulong helper_dextr_s_h(target_ulong ac, target_ulong shift,
3393                               CPUMIPSState *env)
3394 {
3395     int64_t temp[2];
3396     uint32_t temp127;
3397
3398     shift = shift & 0x1F;
3399
3400     mipsdsp_rashift_acc((uint64_t *)temp, ac, shift, env);
3401
3402     temp127 = (temp[1] >> 63) & 0x01;
3403
3404     if ((temp127 == 0) && (temp[1] > 0 || temp[0] > 32767)) {
3405         temp[0] &= 0xFFFF0000;
3406         temp[0] |= 0x00007FFF;
3407         set_DSPControl_overflow_flag(1, 23, env);
3408     } else if ((temp127 == 1) &&
3409             (temp[1] < 0xFFFFFFFFFFFFFFFFll
3410              || temp[0] < 0xFFFFFFFFFFFF1000ll)) {
3411         temp[0] &= 0xFFFF0000;
3412         temp[0] |= 0x00008000;
3413         set_DSPControl_overflow_flag(1, 23, env);
3414     }
3415
3416     return (int64_t)(int16_t)(temp[0] & MIPSDSP_LO);
3417 }
3418
3419 #endif
3420
3421 target_ulong helper_extp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3422 {
3423     int32_t start_pos;
3424     int sub;
3425     uint32_t temp;
3426     uint64_t acc;
3427
3428     size = size & 0x1F;
3429
3430     temp = 0;
3431     start_pos = get_DSPControl_pos(env);
3432     sub = start_pos - (size + 1);
3433     if (sub >= -1) {
3434         acc = ((uint64_t)env->active_tc.HI[ac] << 32) |
3435               ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3436         temp = (acc >> (start_pos - size)) &
3437                (((uint32_t)0x01 << (size + 1)) - 1);
3438         set_DSPControl_efi(0, env);
3439     } else {
3440         set_DSPControl_efi(1, env);
3441     }
3442
3443     return (target_ulong)temp;
3444 }
3445
3446 target_ulong helper_extpdp(target_ulong ac, target_ulong size,
3447                            CPUMIPSState *env)
3448 {
3449     int32_t start_pos;
3450     int sub;
3451     uint32_t temp;
3452     uint64_t acc;
3453
3454     size = size & 0x1F;
3455     temp = 0;
3456     start_pos = get_DSPControl_pos(env);
3457     sub = start_pos - (size + 1);
3458     if (sub >= -1) {
3459         acc  = ((uint64_t)env->active_tc.HI[ac] << 32) |
3460                ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3461         temp = (acc >> (start_pos - size)) &
3462                (((uint32_t)0x01 << (size + 1)) - 1);
3463
3464         set_DSPControl_pos(start_pos - (size + 1), env);
3465         set_DSPControl_efi(0, env);
3466     } else {
3467         set_DSPControl_efi(1, env);
3468     }
3469
3470     return (target_ulong)temp;
3471 }
3472
3473
3474 #if defined(TARGET_MIPS64)
3475 target_ulong helper_dextp(target_ulong ac, target_ulong size, CPUMIPSState *env)
3476 {
3477     int start_pos;
3478     int len;
3479     int sub;
3480     uint64_t tempB, tempA;
3481     uint64_t temp;
3482
3483     temp = 0;
3484
3485     size = size & 0x3F;
3486     start_pos = get_DSPControl_pos(env);
3487     len = start_pos - size;
3488     tempB = env->active_tc.HI[ac];
3489     tempA = env->active_tc.LO[ac];
3490
3491     sub = start_pos - (size + 1);
3492
3493     if (sub >= -1) {
3494         temp = (tempB << (64 - len)) | (tempA >> len);
3495         temp = temp & ((0x01 << (size + 1)) - 1);
3496         set_DSPControl_efi(0, env);
3497     } else {
3498         set_DSPControl_efi(1, env);
3499     }
3500
3501     return temp;
3502 }
3503
3504 target_ulong helper_dextpdp(target_ulong ac, target_ulong size,
3505                             CPUMIPSState *env)
3506 {
3507     int start_pos;
3508     int len;
3509     int sub;
3510     uint64_t tempB, tempA;
3511     uint64_t temp;
3512
3513     temp = 0;
3514     size = size & 0x3F;
3515     start_pos = get_DSPControl_pos(env);
3516     len = start_pos - size;
3517     tempB = env->active_tc.HI[ac];
3518     tempA = env->active_tc.LO[ac];
3519
3520     sub = start_pos - (size + 1);
3521
3522     if (sub >= -1) {
3523         temp = (tempB << (64 - len)) | (tempA >> len);
3524         temp = temp & ((0x01 << (size + 1)) - 1);
3525         set_DSPControl_pos(sub, env);
3526         set_DSPControl_efi(0, env);
3527     } else {
3528         set_DSPControl_efi(1, env);
3529     }
3530
3531     return temp;
3532 }
3533
3534 #endif
3535
3536 void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3537 {
3538     int8_t  rs5_0;
3539     uint64_t temp, acc;
3540
3541     rs5_0 = rs & 0x3F;
3542     rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
3543
3544     if (unlikely(rs5_0 == 0)) {
3545         return;
3546     }
3547
3548     acc   = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
3549             ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
3550
3551     if (rs5_0 > 0) {
3552         temp = acc >> rs5_0;
3553     } else {
3554         temp = acc << -rs5_0;
3555     }
3556
3557     env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);
3558     env->active_tc.LO[ac] = (target_ulong)(int32_t)(temp & MIPSDSP_LLO);
3559 }
3560
3561 #if defined(TARGET_MIPS64)
3562 void helper_dshilo(target_ulong shift, target_ulong ac, CPUMIPSState *env)
3563 {
3564     int8_t shift_t;
3565     uint64_t tempB, tempA;
3566
3567     shift_t = (int8_t)(shift << 1) >> 1;
3568
3569     tempB = env->active_tc.HI[ac];
3570     tempA = env->active_tc.LO[ac];
3571
3572     if (shift_t != 0) {
3573         if (shift_t >= 0) {
3574             tempA = (tempB << (64 - shift_t)) | (tempA >> shift_t);
3575             tempB = tempB >> shift_t;
3576         } else {
3577             shift_t = -shift_t;
3578             tempB = (tempB << shift_t) | (tempA >> (64 - shift_t));
3579             tempA = tempA << shift_t;
3580         }
3581     }
3582
3583     env->active_tc.HI[ac] = tempB;
3584     env->active_tc.LO[ac] = tempA;
3585 }
3586
3587 #endif
3588 void helper_mthlip(target_ulong ac, target_ulong rs, CPUMIPSState *env)
3589 {
3590     int32_t tempA, tempB, pos;
3591
3592     tempA = rs;
3593     tempB = env->active_tc.LO[ac];
3594     env->active_tc.HI[ac] = (target_long)tempB;
3595     env->active_tc.LO[ac] = (target_long)tempA;
3596     pos = get_DSPControl_pos(env);
3597
3598     if (pos > 32) {
3599         return;
3600     } else {
3601         set_DSPControl_pos(pos + 32, env);
3602     }
3603 }
3604
3605 #if defined(TARGET_MIPS64)
3606 void helper_dmthlip(target_ulong rs, target_ulong ac, CPUMIPSState *env)
3607 {
3608     uint8_t ac_t;
3609     uint8_t pos;
3610     uint64_t tempB, tempA;
3611
3612     ac_t = ac & 0x3;
3613
3614     tempA = rs;
3615     tempB = env->active_tc.LO[ac_t];
3616
3617     env->active_tc.HI[ac_t] = tempB;
3618     env->active_tc.LO[ac_t] = tempA;
3619
3620     pos = get_DSPControl_pos(env);
3621
3622     if (pos <= 64) {
3623         pos = pos + 64;
3624         set_DSPControl_pos(pos, env);
3625     }
3626 }
3627 #endif
3628
3629 void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env)
3630 {
3631     uint8_t  mask[6];
3632     uint8_t  i;
3633     uint32_t newbits, overwrite;
3634     target_ulong dsp;
3635
3636     newbits   = 0x00;
3637     overwrite = 0xFFFFFFFF;
3638     dsp = env->active_tc.DSPControl;
3639
3640     for (i = 0; i < 6; i++) {
3641         mask[i] = (mask_num >> i) & 0x01;
3642     }
3643
3644     if (mask[0] == 1) {
3645 #if defined(TARGET_MIPS64)
3646         overwrite &= 0xFFFFFF80;
3647         newbits   &= 0xFFFFFF80;
3648         newbits   |= 0x0000007F & rs;
3649 #else
3650         overwrite &= 0xFFFFFFC0;
3651         newbits   &= 0xFFFFFFC0;
3652         newbits   |= 0x0000003F & rs;
3653 #endif
3654     }
3655
3656     if (mask[1] == 1) {
3657         overwrite &= 0xFFFFE07F;
3658         newbits   &= 0xFFFFE07F;
3659         newbits   |= 0x00001F80 & rs;
3660     }
3661
3662     if (mask[2] == 1) {
3663         overwrite &= 0xFFFFDFFF;
3664         newbits   &= 0xFFFFDFFF;
3665         newbits   |= 0x00002000 & rs;
3666     }
3667
3668     if (mask[3] == 1) {
3669         overwrite &= 0xFF00FFFF;
3670         newbits   &= 0xFF00FFFF;
3671         newbits   |= 0x00FF0000 & rs;
3672     }
3673
3674     if (mask[4] == 1) {
3675         overwrite &= 0x00FFFFFF;
3676         newbits   &= 0x00FFFFFF;
3677 #if defined(TARGET_MIPS64)
3678         newbits   |= 0xFF000000 & rs;
3679 #else
3680         newbits   |= 0x0F000000 & rs;
3681 #endif
3682     }
3683
3684     if (mask[5] == 1) {
3685         overwrite &= 0xFFFFBFFF;
3686         newbits   &= 0xFFFFBFFF;
3687         newbits   |= 0x00004000 & rs;
3688     }
3689
3690     dsp = dsp & overwrite;
3691     dsp = dsp | newbits;
3692     env->active_tc.DSPControl = dsp;
3693 }
3694
3695 void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env)
3696 {
3697     return cpu_wrdsp(rs, mask_num, env);
3698 }
3699
3700 uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env)
3701 {
3702     uint8_t  mask[6];
3703     uint32_t ruler, i;
3704     target_ulong temp;
3705     target_ulong dsp;
3706
3707     ruler = 0x01;
3708     for (i = 0; i < 6; i++) {
3709         mask[i] = (mask_num & ruler) >> i ;
3710         ruler = ruler << 1;
3711     }
3712
3713     temp  = 0x00;
3714     dsp = env->active_tc.DSPControl;
3715
3716     if (mask[0] == 1) {
3717 #if defined(TARGET_MIPS64)
3718         temp |= dsp & 0x7F;
3719 #else
3720         temp |= dsp & 0x3F;
3721 #endif
3722     }
3723
3724     if (mask[1] == 1) {
3725         temp |= dsp & 0x1F80;
3726     }
3727
3728     if (mask[2] == 1) {
3729         temp |= dsp & 0x2000;
3730     }
3731
3732     if (mask[3] == 1) {
3733         temp |= dsp & 0x00FF0000;
3734     }
3735
3736     if (mask[4] == 1) {
3737 #if defined(TARGET_MIPS64)
3738         temp |= dsp & 0xFF000000;
3739 #else
3740         temp |= dsp & 0x0F000000;
3741 #endif
3742     }
3743
3744     if (mask[5] == 1) {
3745         temp |= dsp & 0x4000;
3746     }
3747
3748     return temp;
3749 }
3750
3751 target_ulong helper_rddsp(target_ulong mask_num, CPUMIPSState *env)
3752 {
3753     return cpu_rddsp(mask_num, env);
3754 }
3755
3756
3757 #undef MIPSDSP_LHI
3758 #undef MIPSDSP_LLO
3759 #undef MIPSDSP_HI
3760 #undef MIPSDSP_LO
3761 #undef MIPSDSP_Q3
3762 #undef MIPSDSP_Q2
3763 #undef MIPSDSP_Q1
3764 #undef MIPSDSP_Q0
3765
3766 #undef MIPSDSP_SPLIT32_8
3767 #undef MIPSDSP_SPLIT32_16
3768
3769 #undef MIPSDSP_RETURN32_8
3770 #undef MIPSDSP_RETURN32_16
3771
3772 #ifdef TARGET_MIPS64
3773 #undef MIPSDSP_SPLIT64_16
3774 #undef MIPSDSP_SPLIT64_32
3775 #undef MIPSDSP_RETURN64_16
3776 #undef MIPSDSP_RETURN64_32
3777 #endif