2 * ARM mach-virt emulation
4 * Copyright (c) 2013 Linaro Limited
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "qapi/error.h"
37 #include "hw/sysbus.h"
38 #include "hw/arm/boot.h"
39 #include "hw/arm/primecell.h"
40 #include "hw/arm/virt.h"
41 #include "hw/block/flash.h"
42 #include "hw/vfio/vfio-calxeda-xgmac.h"
43 #include "hw/vfio/vfio-amd-xgbe.h"
44 #include "hw/display/ramfb.h"
46 #include "sysemu/device_tree.h"
47 #include "sysemu/numa.h"
48 #include "sysemu/runstate.h"
49 #include "sysemu/tpm.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "hw/loader.h"
53 #include "qapi/error.h"
54 #include "qemu/bitops.h"
55 #include "qemu/error-report.h"
56 #include "qemu/module.h"
57 #include "hw/pci-host/gpex.h"
58 #include "hw/virtio/virtio-pci.h"
59 #include "hw/arm/sysbus-fdt.h"
60 #include "hw/platform-bus.h"
61 #include "hw/qdev-properties.h"
62 #include "hw/arm/fdt.h"
63 #include "hw/intc/arm_gic.h"
64 #include "hw/intc/arm_gicv3_common.h"
67 #include "hw/firmware/smbios.h"
68 #include "qapi/visitor.h"
69 #include "qapi/qapi-visit-common.h"
70 #include "standard-headers/linux/input.h"
71 #include "hw/arm/smmuv3.h"
72 #include "hw/acpi/acpi.h"
73 #include "target/arm/internals.h"
74 #include "hw/mem/pc-dimm.h"
75 #include "hw/mem/nvdimm.h"
76 #include "hw/acpi/generic_event_device.h"
77 #include "hw/virtio/virtio-iommu.h"
78 #include "hw/char/pl011.h"
79 #include "qemu/guest-random.h"
81 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
82 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
85 MachineClass *mc = MACHINE_CLASS(oc); \
86 virt_machine_##major##_##minor##_options(mc); \
87 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
92 static const TypeInfo machvirt_##major##_##minor##_info = { \
93 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
94 .parent = TYPE_VIRT_MACHINE, \
95 .class_init = virt_##major##_##minor##_class_init, \
97 static void machvirt_machine_##major##_##minor##_init(void) \
99 type_register_static(&machvirt_##major##_##minor##_info); \
101 type_init(machvirt_machine_##major##_##minor##_init);
103 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
104 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
105 #define DEFINE_VIRT_MACHINE(major, minor) \
106 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
109 /* Number of external interrupt lines to configure the GIC with */
112 #define PLATFORM_BUS_NUM_IRQS 64
114 /* Legacy RAM limit in GB (< version 4.0) */
115 #define LEGACY_RAMLIMIT_GB 255
116 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
118 /* Addresses and sizes of our components.
119 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
120 * 128MB..256MB is used for miscellaneous device I/O.
121 * 256MB..1GB is reserved for possible future PCI support (ie where the
122 * PCI memory window will go if we add a PCI host controller).
123 * 1GB and up is RAM (which may happily spill over into the
124 * high memory region beyond 4GB).
125 * This represents a compromise between how much RAM can be given to
126 * a 32 bit VM and leaving space for expansion and in particular for PCI.
127 * Note that devices should generally be placed at multiples of 0x10000,
128 * to accommodate guests using 64K pages.
130 static const MemMapEntry base_memmap[] = {
131 /* Space up to 0x8000000 is reserved for a boot ROM */
132 [VIRT_FLASH] = { 0, 0x08000000 },
133 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
134 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
135 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
136 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
137 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
138 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
139 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
140 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
141 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
142 /* This redistributor space allows up to 2*64kB*123 CPUs */
143 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
144 [VIRT_UART] = { 0x09000000, 0x00001000 },
145 [VIRT_RTC] = { 0x09010000, 0x00001000 },
146 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
147 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
148 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
149 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
150 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
151 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
152 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
153 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
154 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
155 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
156 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
157 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
158 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
159 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
160 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
161 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
162 /* Actual RAM size depends on initial RAM and device memory settings */
163 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
167 * Highmem IO Regions: This memory map is floating, located after the RAM.
168 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
169 * top of the RAM, so that its base get the same alignment as the size,
170 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
171 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
172 * Note the extended_memmap is sized so that it eventually also includes the
173 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
174 * index of base_memmap).
176 static MemMapEntry extended_memmap[] = {
177 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
178 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
179 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
180 /* Second PCIe window */
181 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
184 static const int a15irqmap[] = {
187 [VIRT_PCIE] = 3, /* ... to 6 */
189 [VIRT_SECURE_UART] = 8,
191 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
192 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
193 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
194 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
197 static const char *valid_cpus[] = {
198 ARM_CPU_TYPE_NAME("cortex-a7"),
199 ARM_CPU_TYPE_NAME("cortex-a15"),
200 ARM_CPU_TYPE_NAME("cortex-a53"),
201 ARM_CPU_TYPE_NAME("cortex-a57"),
202 ARM_CPU_TYPE_NAME("cortex-a72"),
203 ARM_CPU_TYPE_NAME("a64fx"),
204 ARM_CPU_TYPE_NAME("host"),
205 ARM_CPU_TYPE_NAME("max"),
208 static bool cpu_type_valid(const char *cpu)
212 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
213 if (strcmp(cpu, valid_cpus[i]) == 0) {
220 static void create_kaslr_seed(MachineState *ms, const char *node)
224 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
227 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed);
230 static void create_fdt(VirtMachineState *vms)
232 MachineState *ms = MACHINE(vms);
233 int nb_numa_nodes = ms->numa_state->num_nodes;
234 void *fdt = create_device_tree(&vms->fdt_size);
237 error_report("create_device_tree() failed");
244 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
245 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
246 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
248 /* /chosen must exist for load_dtb to fill in necessary properties later */
249 qemu_fdt_add_subnode(fdt, "/chosen");
250 if (vms->dtb_kaslr_seed) {
251 create_kaslr_seed(ms, "/chosen");
255 qemu_fdt_add_subnode(fdt, "/secure-chosen");
256 if (vms->dtb_kaslr_seed) {
257 create_kaslr_seed(ms, "/secure-chosen");
261 /* Clock node, for the benefit of the UART. The kernel device tree
262 * binding documentation claims the PL011 node clock properties are
263 * optional but in practice if you omit them the kernel refuses to
264 * probe for the device.
266 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
267 qemu_fdt_add_subnode(fdt, "/apb-pclk");
268 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
269 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
270 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
271 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
273 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
275 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
276 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
277 uint32_t *matrix = g_malloc0(size);
280 for (i = 0; i < nb_numa_nodes; i++) {
281 for (j = 0; j < nb_numa_nodes; j++) {
282 idx = (i * nb_numa_nodes + j) * 3;
283 matrix[idx + 0] = cpu_to_be32(i);
284 matrix[idx + 1] = cpu_to_be32(j);
286 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
290 qemu_fdt_add_subnode(fdt, "/distance-map");
291 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
292 "numa-distance-map-v1");
293 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
299 static void fdt_add_timer_nodes(const VirtMachineState *vms)
301 /* On real hardware these interrupts are level-triggered.
302 * On KVM they were edge-triggered before host kernel version 4.4,
303 * and level-triggered afterwards.
304 * On emulated QEMU they are level-triggered.
306 * Getting the DTB info about them wrong is awkward for some
308 * pre-4.8 ignore the DT and leave the interrupt configured
309 * with whatever the GIC reset value (or the bootloader) left it at
310 * 4.8 before rc6 honour the incorrect data by programming it back
311 * into the GIC, causing problems
312 * 4.8rc6 and later ignore the DT and always write "level triggered"
315 * For backwards-compatibility, virt-2.8 and earlier will continue
316 * to say these are edge-triggered, but later machines will report
317 * the correct information.
320 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
321 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
322 MachineState *ms = MACHINE(vms);
324 if (vmc->claim_edge_triggered_timers) {
325 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
328 if (vms->gic_version == VIRT_GIC_VERSION_2) {
329 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
330 GIC_FDT_IRQ_PPI_CPU_WIDTH,
331 (1 << MACHINE(vms)->smp.cpus) - 1);
334 qemu_fdt_add_subnode(ms->fdt, "/timer");
336 armcpu = ARM_CPU(qemu_get_cpu(0));
337 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
338 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
339 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
340 compat, sizeof(compat));
342 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
345 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
346 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
347 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
348 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
349 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
350 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
353 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
357 const MachineState *ms = MACHINE(vms);
358 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
359 int smp_cpus = ms->smp.cpus;
362 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
363 * On ARM v8 64-bit systems value should be set to 2,
364 * that corresponds to the MPIDR_EL1 register size.
365 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
366 * in the system, #address-cells can be set to 1, since
367 * MPIDR_EL1[63:32] bits are not used for CPUs
370 * Here we actually don't know whether our system is 32- or 64-bit one.
371 * The simplest way to go is to examine affinity IDs of all our CPUs. If
372 * at least one of them has Aff3 populated, we set #address-cells to 2.
374 for (cpu = 0; cpu < smp_cpus; cpu++) {
375 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
377 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
383 qemu_fdt_add_subnode(ms->fdt, "/cpus");
384 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
385 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
387 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
388 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
389 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
390 CPUState *cs = CPU(armcpu);
392 qemu_fdt_add_subnode(ms->fdt, nodename);
393 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
394 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
395 armcpu->dtb_compatible);
397 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
398 qemu_fdt_setprop_string(ms->fdt, nodename,
399 "enable-method", "psci");
402 if (addr_cells == 2) {
403 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
404 armcpu->mp_affinity);
406 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
407 armcpu->mp_affinity);
410 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
411 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
412 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
415 if (!vmc->no_cpu_topology) {
416 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
417 qemu_fdt_alloc_phandle(ms->fdt));
423 if (!vmc->no_cpu_topology) {
425 * Add vCPU topology description through fdt node cpu-map.
427 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
428 * In a SMP system, the hierarchy of CPUs can be defined through
429 * four entities that are used to describe the layout of CPUs in
430 * the system: socket/cluster/core/thread.
432 * A socket node represents the boundary of system physical package
433 * and its child nodes must be one or more cluster nodes. A system
434 * can contain several layers of clustering within a single physical
435 * package and cluster nodes can be contained in parent cluster nodes.
437 * Given that cluster is not yet supported in the vCPU topology,
438 * we currently generate one cluster node within each socket node
441 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
443 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
444 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
447 if (ms->smp.threads > 1) {
448 map_path = g_strdup_printf(
449 "/cpus/cpu-map/socket%d/cluster0/core%d/thread%d",
450 cpu / (ms->smp.cores * ms->smp.threads),
451 (cpu / ms->smp.threads) % ms->smp.cores,
452 cpu % ms->smp.threads);
454 map_path = g_strdup_printf(
455 "/cpus/cpu-map/socket%d/cluster0/core%d",
457 cpu % ms->smp.cores);
459 qemu_fdt_add_path(ms->fdt, map_path);
460 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
468 static void fdt_add_its_gic_node(VirtMachineState *vms)
471 MachineState *ms = MACHINE(vms);
473 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
474 nodename = g_strdup_printf("/intc/its@%" PRIx64,
475 vms->memmap[VIRT_GIC_ITS].base);
476 qemu_fdt_add_subnode(ms->fdt, nodename);
477 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
479 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
480 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
481 2, vms->memmap[VIRT_GIC_ITS].base,
482 2, vms->memmap[VIRT_GIC_ITS].size);
483 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
487 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
489 MachineState *ms = MACHINE(vms);
492 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
493 vms->memmap[VIRT_GIC_V2M].base);
494 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
495 qemu_fdt_add_subnode(ms->fdt, nodename);
496 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
497 "arm,gic-v2m-frame");
498 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
499 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
500 2, vms->memmap[VIRT_GIC_V2M].base,
501 2, vms->memmap[VIRT_GIC_V2M].size);
502 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
506 static void fdt_add_gic_node(VirtMachineState *vms)
508 MachineState *ms = MACHINE(vms);
511 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
512 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
514 nodename = g_strdup_printf("/intc@%" PRIx64,
515 vms->memmap[VIRT_GIC_DIST].base);
516 qemu_fdt_add_subnode(ms->fdt, nodename);
517 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
518 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
519 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
520 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
521 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
522 if (vms->gic_version == VIRT_GIC_VERSION_3) {
523 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
525 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
528 qemu_fdt_setprop_cell(ms->fdt, nodename,
529 "#redistributor-regions", nb_redist_regions);
531 if (nb_redist_regions == 1) {
532 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
533 2, vms->memmap[VIRT_GIC_DIST].base,
534 2, vms->memmap[VIRT_GIC_DIST].size,
535 2, vms->memmap[VIRT_GIC_REDIST].base,
536 2, vms->memmap[VIRT_GIC_REDIST].size);
538 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
539 2, vms->memmap[VIRT_GIC_DIST].base,
540 2, vms->memmap[VIRT_GIC_DIST].size,
541 2, vms->memmap[VIRT_GIC_REDIST].base,
542 2, vms->memmap[VIRT_GIC_REDIST].size,
543 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
544 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
548 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
549 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
550 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
553 /* 'cortex-a15-gic' means 'GIC v2' */
554 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
555 "arm,cortex-a15-gic");
557 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
558 2, vms->memmap[VIRT_GIC_DIST].base,
559 2, vms->memmap[VIRT_GIC_DIST].size,
560 2, vms->memmap[VIRT_GIC_CPU].base,
561 2, vms->memmap[VIRT_GIC_CPU].size);
563 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
564 2, vms->memmap[VIRT_GIC_DIST].base,
565 2, vms->memmap[VIRT_GIC_DIST].size,
566 2, vms->memmap[VIRT_GIC_CPU].base,
567 2, vms->memmap[VIRT_GIC_CPU].size,
568 2, vms->memmap[VIRT_GIC_HYP].base,
569 2, vms->memmap[VIRT_GIC_HYP].size,
570 2, vms->memmap[VIRT_GIC_VCPU].base,
571 2, vms->memmap[VIRT_GIC_VCPU].size);
572 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
573 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
574 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
578 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
582 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
584 ARMCPU *armcpu = ARM_CPU(first_cpu);
585 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
586 MachineState *ms = MACHINE(vms);
588 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
589 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
593 if (vms->gic_version == VIRT_GIC_VERSION_2) {
594 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
595 GIC_FDT_IRQ_PPI_CPU_WIDTH,
596 (1 << MACHINE(vms)->smp.cpus) - 1);
599 qemu_fdt_add_subnode(ms->fdt, "/pmu");
600 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
601 const char compat[] = "arm,armv8-pmuv3";
602 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
603 compat, sizeof(compat));
604 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
605 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
609 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
612 MachineState *ms = MACHINE(vms);
613 int irq = vms->irqmap[VIRT_ACPI_GED];
614 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
617 event |= ACPI_GED_MEM_HOTPLUG_EVT;
620 if (ms->nvdimms_state->is_enabled) {
621 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
624 dev = qdev_new(TYPE_ACPI_GED);
625 qdev_prop_set_uint32(dev, "ged-event", event);
627 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
628 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
629 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
631 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
636 static void create_its(VirtMachineState *vms)
638 const char *itsclass = its_class_name();
641 if (!strcmp(itsclass, "arm-gicv3-its")) {
648 /* Do nothing if not supported */
652 dev = qdev_new(itsclass);
654 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
656 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
657 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
659 fdt_add_its_gic_node(vms);
660 vms->msi_controller = VIRT_MSI_CTRL_ITS;
663 static void create_v2m(VirtMachineState *vms)
666 int irq = vms->irqmap[VIRT_GIC_V2M];
669 dev = qdev_new("arm-gicv2m");
670 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
671 qdev_prop_set_uint32(dev, "base-spi", irq);
672 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
673 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
675 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
676 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
677 qdev_get_gpio_in(vms->gic, irq + i));
680 fdt_add_v2m_gic_node(vms);
681 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
684 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
686 MachineState *ms = MACHINE(vms);
687 /* We create a standalone GIC */
688 SysBusDevice *gicbusdev;
690 int type = vms->gic_version, i;
691 unsigned int smp_cpus = ms->smp.cpus;
692 uint32_t nb_redist_regions = 0;
694 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
696 vms->gic = qdev_new(gictype);
697 qdev_prop_set_uint32(vms->gic, "revision", type);
698 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
699 /* Note that the num-irq property counts both internal and external
700 * interrupts; there are always 32 of the former (mandated by GIC spec).
702 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
703 if (!kvm_irqchip_in_kernel()) {
704 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
708 uint32_t redist0_capacity =
709 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
710 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
712 nb_redist_regions = virt_gicv3_redist_region_count(vms);
714 qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
716 qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
718 if (!kvm_irqchip_in_kernel()) {
720 object_property_set_link(OBJECT(vms->gic), "sysmem",
721 OBJECT(mem), &error_fatal);
722 qdev_prop_set_bit(vms->gic, "has-lpi", true);
726 if (nb_redist_regions == 2) {
727 uint32_t redist1_capacity =
728 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
730 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
731 MIN(smp_cpus - redist0_count, redist1_capacity));
734 if (!kvm_irqchip_in_kernel()) {
735 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
739 gicbusdev = SYS_BUS_DEVICE(vms->gic);
740 sysbus_realize_and_unref(gicbusdev, &error_fatal);
741 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
743 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
744 if (nb_redist_regions == 2) {
745 sysbus_mmio_map(gicbusdev, 2,
746 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
749 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
751 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
752 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
756 /* Wire the outputs from each CPU's generic timer and the GICv3
757 * maintenance interrupt signal to the appropriate GIC PPI inputs,
758 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
760 for (i = 0; i < smp_cpus; i++) {
761 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
762 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
764 /* Mapping from the output timer irq lines from the CPU to the
765 * GIC PPI inputs we use for the virt board.
767 const int timer_irq[] = {
768 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
769 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
770 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
771 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
774 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
775 qdev_connect_gpio_out(cpudev, irq,
776 qdev_get_gpio_in(vms->gic,
777 ppibase + timer_irq[irq]));
781 qemu_irq irq = qdev_get_gpio_in(vms->gic,
782 ppibase + ARCH_GIC_MAINT_IRQ);
783 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
785 } else if (vms->virt) {
786 qemu_irq irq = qdev_get_gpio_in(vms->gic,
787 ppibase + ARCH_GIC_MAINT_IRQ);
788 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
791 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
792 qdev_get_gpio_in(vms->gic, ppibase
795 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
796 sysbus_connect_irq(gicbusdev, i + smp_cpus,
797 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
798 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
799 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
800 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
801 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
804 fdt_add_gic_node(vms);
806 if (type == 3 && vms->its) {
808 } else if (type == 2) {
813 static void create_uart(const VirtMachineState *vms, int uart,
814 MemoryRegion *mem, Chardev *chr)
817 hwaddr base = vms->memmap[uart].base;
818 hwaddr size = vms->memmap[uart].size;
819 int irq = vms->irqmap[uart];
820 const char compat[] = "arm,pl011\0arm,primecell";
821 const char clocknames[] = "uartclk\0apb_pclk";
822 DeviceState *dev = qdev_new(TYPE_PL011);
823 SysBusDevice *s = SYS_BUS_DEVICE(dev);
824 MachineState *ms = MACHINE(vms);
826 qdev_prop_set_chr(dev, "chardev", chr);
827 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
828 memory_region_add_subregion(mem, base,
829 sysbus_mmio_get_region(s, 0));
830 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
832 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
833 qemu_fdt_add_subnode(ms->fdt, nodename);
834 /* Note that we can't use setprop_string because of the embedded NUL */
835 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
836 compat, sizeof(compat));
837 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
839 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
840 GIC_FDT_IRQ_TYPE_SPI, irq,
841 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
842 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
843 vms->clock_phandle, vms->clock_phandle);
844 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
845 clocknames, sizeof(clocknames));
847 if (uart == VIRT_UART) {
848 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
850 /* Mark as not usable by the normal world */
851 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
852 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
854 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
861 static void create_rtc(const VirtMachineState *vms)
864 hwaddr base = vms->memmap[VIRT_RTC].base;
865 hwaddr size = vms->memmap[VIRT_RTC].size;
866 int irq = vms->irqmap[VIRT_RTC];
867 const char compat[] = "arm,pl031\0arm,primecell";
868 MachineState *ms = MACHINE(vms);
870 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
872 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
873 qemu_fdt_add_subnode(ms->fdt, nodename);
874 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
875 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
877 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
878 GIC_FDT_IRQ_TYPE_SPI, irq,
879 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
880 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
881 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
885 static DeviceState *gpio_key_dev;
886 static void virt_powerdown_req(Notifier *n, void *opaque)
888 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
891 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
893 /* use gpio Pin 3 for power button event */
894 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
898 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
901 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
902 qdev_get_gpio_in(pl061_dev, 3));
904 qemu_fdt_add_subnode(fdt, "/gpio-keys");
905 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
906 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0);
907 qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1);
909 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
910 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
911 "label", "GPIO Key Poweroff");
912 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
914 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
915 "gpios", phandle, 3, 0);
918 #define SECURE_GPIO_POWEROFF 0
919 #define SECURE_GPIO_RESET 1
921 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
924 DeviceState *gpio_pwr_dev;
927 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
929 /* connect secure pl061 to gpio-pwr */
930 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
931 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
932 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
933 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
935 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
936 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
938 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
939 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
940 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
941 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
944 qemu_fdt_add_subnode(fdt, "/gpio-restart");
945 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
947 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
948 "gpios", phandle, SECURE_GPIO_RESET, 0);
949 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
950 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
954 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
958 DeviceState *pl061_dev;
959 hwaddr base = vms->memmap[gpio].base;
960 hwaddr size = vms->memmap[gpio].size;
961 int irq = vms->irqmap[gpio];
962 const char compat[] = "arm,pl061\0arm,primecell";
964 MachineState *ms = MACHINE(vms);
966 pl061_dev = qdev_new("pl061");
967 /* Pull lines down to 0 if not driven by the PL061 */
968 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
969 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
970 s = SYS_BUS_DEVICE(pl061_dev);
971 sysbus_realize_and_unref(s, &error_fatal);
972 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
973 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
975 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
976 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
977 qemu_fdt_add_subnode(ms->fdt, nodename);
978 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
980 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
981 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
982 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
983 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
984 GIC_FDT_IRQ_TYPE_SPI, irq,
985 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
986 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
987 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
988 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
990 if (gpio != VIRT_GPIO) {
991 /* Mark as not usable by the normal world */
992 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
993 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
997 /* Child gpio devices */
998 if (gpio == VIRT_GPIO) {
999 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1001 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1005 static void create_virtio_devices(const VirtMachineState *vms)
1008 hwaddr size = vms->memmap[VIRT_MMIO].size;
1009 MachineState *ms = MACHINE(vms);
1011 /* We create the transports in forwards order. Since qbus_realize()
1012 * prepends (not appends) new child buses, the incrementing loop below will
1013 * create a list of virtio-mmio buses with decreasing base addresses.
1015 * When a -device option is processed from the command line,
1016 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1017 * order. The upshot is that -device options in increasing command line
1018 * order are mapped to virtio-mmio buses with decreasing base addresses.
1020 * When this code was originally written, that arrangement ensured that the
1021 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1022 * the first -device on the command line. (The end-to-end order is a
1023 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1024 * guest kernel's name-to-address assignment strategy.)
1026 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1027 * the message, if not necessarily the code, of commit 70161ff336.
1028 * Therefore the loop now establishes the inverse of the original intent.
1030 * Unfortunately, we can't counteract the kernel change by reversing the
1031 * loop; it would break existing command lines.
1033 * In any case, the kernel makes no guarantee about the stability of
1034 * enumeration order of virtio devices (as demonstrated by it changing
1035 * between kernel versions). For reliable and stable identification
1036 * of disks users must use UUIDs or similar mechanisms.
1038 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1039 int irq = vms->irqmap[VIRT_MMIO] + i;
1040 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1042 sysbus_create_simple("virtio-mmio", base,
1043 qdev_get_gpio_in(vms->gic, irq));
1046 /* We add dtb nodes in reverse order so that they appear in the finished
1047 * device tree lowest address first.
1049 * Note that this mapping is independent of the loop above. The previous
1050 * loop influences virtio device to virtio transport assignment, whereas
1051 * this loop controls how virtio transports are laid out in the dtb.
1053 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1055 int irq = vms->irqmap[VIRT_MMIO] + i;
1056 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1058 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1059 qemu_fdt_add_subnode(ms->fdt, nodename);
1060 qemu_fdt_setprop_string(ms->fdt, nodename,
1061 "compatible", "virtio,mmio");
1062 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1064 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1065 GIC_FDT_IRQ_TYPE_SPI, irq,
1066 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1067 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1072 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1074 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1076 const char *alias_prop_name)
1079 * Create a single flash device. We use the same parameters as
1080 * the flash devices on the Versatile Express board.
1082 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1084 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1085 qdev_prop_set_uint8(dev, "width", 4);
1086 qdev_prop_set_uint8(dev, "device-width", 2);
1087 qdev_prop_set_bit(dev, "big-endian", false);
1088 qdev_prop_set_uint16(dev, "id0", 0x89);
1089 qdev_prop_set_uint16(dev, "id1", 0x18);
1090 qdev_prop_set_uint16(dev, "id2", 0x00);
1091 qdev_prop_set_uint16(dev, "id3", 0x00);
1092 qdev_prop_set_string(dev, "name", name);
1093 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1094 object_property_add_alias(OBJECT(vms), alias_prop_name,
1095 OBJECT(dev), "drive");
1096 return PFLASH_CFI01(dev);
1099 static void virt_flash_create(VirtMachineState *vms)
1101 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1102 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1105 static void virt_flash_map1(PFlashCFI01 *flash,
1106 hwaddr base, hwaddr size,
1107 MemoryRegion *sysmem)
1109 DeviceState *dev = DEVICE(flash);
1111 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1112 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1113 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1114 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1116 memory_region_add_subregion(sysmem, base,
1117 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1121 static void virt_flash_map(VirtMachineState *vms,
1122 MemoryRegion *sysmem,
1123 MemoryRegion *secure_sysmem)
1126 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1127 * sysmem is the system memory space. secure_sysmem is the secure view
1128 * of the system, and the first flash device should be made visible only
1129 * there. The second flash device is visible to both secure and nonsecure.
1130 * If sysmem == secure_sysmem this means there is no separate Secure
1131 * address space and both flash devices are generally visible.
1133 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1134 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1136 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1138 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1142 static void virt_flash_fdt(VirtMachineState *vms,
1143 MemoryRegion *sysmem,
1144 MemoryRegion *secure_sysmem)
1146 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1147 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1148 MachineState *ms = MACHINE(vms);
1151 if (sysmem == secure_sysmem) {
1152 /* Report both flash devices as a single node in the DT */
1153 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1154 qemu_fdt_add_subnode(ms->fdt, nodename);
1155 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1156 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1157 2, flashbase, 2, flashsize,
1158 2, flashbase + flashsize, 2, flashsize);
1159 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1163 * Report the devices as separate nodes so we can mark one as
1164 * only visible to the secure world.
1166 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1167 qemu_fdt_add_subnode(ms->fdt, nodename);
1168 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1169 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1170 2, flashbase, 2, flashsize);
1171 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1172 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1173 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1176 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1177 qemu_fdt_add_subnode(ms->fdt, nodename);
1178 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1179 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1180 2, flashbase + flashsize, 2, flashsize);
1181 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1186 static bool virt_firmware_init(VirtMachineState *vms,
1187 MemoryRegion *sysmem,
1188 MemoryRegion *secure_sysmem)
1191 const char *bios_name;
1192 BlockBackend *pflash_blk0;
1194 /* Map legacy -drive if=pflash to machine properties */
1195 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1196 pflash_cfi01_legacy_drive(vms->flash[i],
1197 drive_get(IF_PFLASH, 0, i));
1200 virt_flash_map(vms, sysmem, secure_sysmem);
1202 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1204 bios_name = MACHINE(vms)->firmware;
1211 error_report("The contents of the first flash device may be "
1212 "specified with -bios or with -drive if=pflash... "
1213 "but you cannot use both options at once");
1217 /* Fall back to -bios */
1219 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1221 error_report("Could not find ROM image '%s'", bios_name);
1224 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1225 image_size = load_image_mr(fname, mr);
1227 if (image_size < 0) {
1228 error_report("Could not load ROM image '%s'", bios_name);
1233 return pflash_blk0 || bios_name;
1236 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1238 MachineState *ms = MACHINE(vms);
1239 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1240 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1244 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1245 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1247 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1248 qemu_fdt_add_subnode(ms->fdt, nodename);
1249 qemu_fdt_setprop_string(ms->fdt, nodename,
1250 "compatible", "qemu,fw-cfg-mmio");
1251 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1253 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1258 static void create_pcie_irq_map(const MachineState *ms,
1259 uint32_t gic_phandle,
1260 int first_irq, const char *nodename)
1263 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1264 uint32_t *irq_map = full_irq_map;
1266 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1267 for (pin = 0; pin < 4; pin++) {
1268 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1269 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1270 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1274 devfn << 8, 0, 0, /* devfn */
1275 pin + 1, /* PCI pin */
1276 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1278 /* Convert map to big endian */
1279 for (i = 0; i < 10; i++) {
1280 irq_map[i] = cpu_to_be32(map[i]);
1286 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1287 full_irq_map, sizeof(full_irq_map));
1289 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1290 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1295 static void create_smmu(const VirtMachineState *vms,
1299 const char compat[] = "arm,smmu-v3";
1300 int irq = vms->irqmap[VIRT_SMMU];
1302 hwaddr base = vms->memmap[VIRT_SMMU].base;
1303 hwaddr size = vms->memmap[VIRT_SMMU].size;
1304 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1306 MachineState *ms = MACHINE(vms);
1308 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1312 dev = qdev_new("arm-smmuv3");
1314 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1316 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1317 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1318 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1319 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1320 qdev_get_gpio_in(vms->gic, irq + i));
1323 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1324 qemu_fdt_add_subnode(ms->fdt, node);
1325 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1326 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1328 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1329 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1330 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1331 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1332 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1334 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1337 qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
1338 qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
1339 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1341 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1343 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1347 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1349 const char compat[] = "virtio,pci-iommu";
1350 uint16_t bdf = vms->virtio_iommu_bdf;
1351 MachineState *ms = MACHINE(vms);
1354 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1356 node = g_strdup_printf("%s/virtio_iommu@%d", vms->pciehb_nodename, bdf);
1357 qemu_fdt_add_subnode(ms->fdt, node);
1358 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1359 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1360 1, bdf << 8, 1, 0, 1, 0,
1363 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1364 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1367 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1368 0x0, vms->iommu_phandle, 0x0, bdf,
1369 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1372 static void create_pcie(VirtMachineState *vms)
1374 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1375 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1376 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1377 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1378 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1379 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1380 hwaddr base_ecam, size_ecam;
1381 hwaddr base = base_mmio;
1383 int irq = vms->irqmap[VIRT_PCIE];
1384 MemoryRegion *mmio_alias;
1385 MemoryRegion *mmio_reg;
1386 MemoryRegion *ecam_alias;
1387 MemoryRegion *ecam_reg;
1392 MachineState *ms = MACHINE(vms);
1394 dev = qdev_new(TYPE_GPEX_HOST);
1395 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1397 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1398 base_ecam = vms->memmap[ecam_id].base;
1399 size_ecam = vms->memmap[ecam_id].size;
1400 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1401 /* Map only the first size_ecam bytes of ECAM space */
1402 ecam_alias = g_new0(MemoryRegion, 1);
1403 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1404 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1405 ecam_reg, 0, size_ecam);
1406 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1408 /* Map the MMIO window into system address space so as to expose
1409 * the section of PCI MMIO space which starts at the same base address
1410 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1413 mmio_alias = g_new0(MemoryRegion, 1);
1414 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1415 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1416 mmio_reg, base_mmio, size_mmio);
1417 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1420 /* Map high MMIO space */
1421 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1423 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1424 mmio_reg, base_mmio_high, size_mmio_high);
1425 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1429 /* Map IO port space */
1430 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1432 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1433 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1434 qdev_get_gpio_in(vms->gic, irq + i));
1435 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1438 pci = PCI_HOST_BRIDGE(dev);
1439 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1440 vms->bus = pci->bus;
1442 for (i = 0; i < nb_nics; i++) {
1443 NICInfo *nd = &nd_table[i];
1446 nd->model = g_strdup("virtio");
1449 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1453 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1454 qemu_fdt_add_subnode(ms->fdt, nodename);
1455 qemu_fdt_setprop_string(ms->fdt, nodename,
1456 "compatible", "pci-host-ecam-generic");
1457 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1458 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1459 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1460 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1461 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1463 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1465 if (vms->msi_phandle) {
1466 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
1470 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1471 2, base_ecam, 2, size_ecam);
1474 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1475 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1476 2, base_pio, 2, size_pio,
1477 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1478 2, base_mmio, 2, size_mmio,
1479 1, FDT_PCI_RANGE_MMIO_64BIT,
1481 2, base_mmio_high, 2, size_mmio_high);
1483 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1484 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1485 2, base_pio, 2, size_pio,
1486 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1487 2, base_mmio, 2, size_mmio);
1490 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1491 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1494 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1496 switch (vms->iommu) {
1497 case VIRT_IOMMU_SMMUV3:
1498 create_smmu(vms, vms->bus);
1499 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1500 0x0, vms->iommu_phandle, 0x0, 0x10000);
1503 g_assert_not_reached();
1508 static void create_platform_bus(VirtMachineState *vms)
1513 MemoryRegion *sysmem = get_system_memory();
1515 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1516 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1517 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1518 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1519 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1520 vms->platform_bus_dev = dev;
1522 s = SYS_BUS_DEVICE(dev);
1523 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1524 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1525 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1528 memory_region_add_subregion(sysmem,
1529 vms->memmap[VIRT_PLATFORM_BUS].base,
1530 sysbus_mmio_get_region(s, 0));
1533 static void create_tag_ram(MemoryRegion *tag_sysmem,
1534 hwaddr base, hwaddr size,
1537 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1539 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1540 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1543 static void create_secure_ram(VirtMachineState *vms,
1544 MemoryRegion *secure_sysmem,
1545 MemoryRegion *secure_tag_sysmem)
1547 MemoryRegion *secram = g_new(MemoryRegion, 1);
1549 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1550 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1551 MachineState *ms = MACHINE(vms);
1553 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1555 memory_region_add_subregion(secure_sysmem, base, secram);
1557 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1558 qemu_fdt_add_subnode(ms->fdt, nodename);
1559 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1560 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1561 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1562 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1564 if (secure_tag_sysmem) {
1565 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1571 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1573 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1575 MachineState *ms = MACHINE(board);
1578 *fdt_size = board->fdt_size;
1582 static void virt_build_smbios(VirtMachineState *vms)
1584 MachineClass *mc = MACHINE_GET_CLASS(vms);
1585 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1586 uint8_t *smbios_tables, *smbios_anchor;
1587 size_t smbios_tables_len, smbios_anchor_len;
1588 const char *product = "QEMU Virtual Machine";
1590 if (kvm_enabled()) {
1591 product = "KVM Virtual Machine";
1594 smbios_set_defaults("QEMU", product,
1595 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1596 true, SMBIOS_ENTRY_POINT_TYPE_64);
1598 smbios_get_tables(MACHINE(vms), NULL, 0,
1599 &smbios_tables, &smbios_tables_len,
1600 &smbios_anchor, &smbios_anchor_len,
1603 if (smbios_anchor) {
1604 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1605 smbios_tables, smbios_tables_len);
1606 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1607 smbios_anchor, smbios_anchor_len);
1612 void virt_machine_done(Notifier *notifier, void *data)
1614 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1616 MachineState *ms = MACHINE(vms);
1617 ARMCPU *cpu = ARM_CPU(first_cpu);
1618 struct arm_boot_info *info = &vms->bootinfo;
1619 AddressSpace *as = arm_boot_address_space(cpu, info);
1622 * If the user provided a dtb, we assume the dynamic sysbus nodes
1623 * already are integrated there. This corresponds to a use case where
1624 * the dynamic sysbus nodes are complex and their generation is not yet
1625 * supported. In that case the user can take charge of the guest dt
1626 * while qemu takes charge of the qom stuff.
1628 if (info->dtb_filename == NULL) {
1629 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1630 vms->memmap[VIRT_PLATFORM_BUS].base,
1631 vms->memmap[VIRT_PLATFORM_BUS].size,
1632 vms->irqmap[VIRT_PLATFORM_BUS]);
1634 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1638 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1640 virt_acpi_setup(vms);
1641 virt_build_smbios(vms);
1644 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1646 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1647 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1649 if (!vmc->disallow_affinity_adjustment) {
1650 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1651 * GIC's target-list limitations. 32-bit KVM hosts currently
1652 * always create clusters of 4 CPUs, but that is expected to
1653 * change when they gain support for gicv3. When KVM is enabled
1654 * it will override the changes we make here, therefore our
1655 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1656 * and to improve SGI efficiency.
1658 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1659 clustersz = GICV3_TARGETLIST_BITS;
1661 clustersz = GIC_TARGETLIST_BITS;
1664 return arm_cpu_mp_affinity(idx, clustersz);
1667 static void virt_set_memmap(VirtMachineState *vms)
1669 MachineState *ms = MACHINE(vms);
1670 hwaddr base, device_memory_base, device_memory_size;
1673 vms->memmap = extended_memmap;
1675 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1676 vms->memmap[i] = base_memmap[i];
1679 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1680 error_report("unsupported number of memory slots: %"PRIu64,
1686 * We compute the base of the high IO region depending on the
1687 * amount of initial and device memory. The device memory start/size
1688 * is aligned on 1GiB. We never put the high IO region below 256GiB
1689 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1690 * The device region size assumes 1GiB page max alignment per slot.
1692 device_memory_base =
1693 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1694 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1696 /* Base address of the high IO region */
1697 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1698 if (base < device_memory_base) {
1699 error_report("maxmem/slots too huge");
1702 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1703 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1706 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1707 hwaddr size = extended_memmap[i].size;
1709 base = ROUND_UP(base, size);
1710 vms->memmap[i].base = base;
1711 vms->memmap[i].size = size;
1714 vms->highest_gpa = base - 1;
1715 if (device_memory_size > 0) {
1716 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1717 ms->device_memory->base = device_memory_base;
1718 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1719 "device-memory", device_memory_size);
1724 * finalize_gic_version - Determines the final gic_version
1725 * according to the gic-version property
1727 * Default GIC type is v2
1729 static void finalize_gic_version(VirtMachineState *vms)
1731 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1733 if (kvm_enabled()) {
1736 if (!kvm_irqchip_in_kernel()) {
1737 switch (vms->gic_version) {
1738 case VIRT_GIC_VERSION_HOST:
1740 "gic-version=host not relevant with kernel-irqchip=off "
1741 "as only userspace GICv2 is supported. Using v2 ...");
1743 case VIRT_GIC_VERSION_MAX:
1744 case VIRT_GIC_VERSION_NOSEL:
1745 vms->gic_version = VIRT_GIC_VERSION_2;
1747 case VIRT_GIC_VERSION_2:
1749 case VIRT_GIC_VERSION_3:
1751 "gic-version=3 is not supported with kernel-irqchip=off");
1756 probe_bitmap = kvm_arm_vgic_probe();
1757 if (!probe_bitmap) {
1758 error_report("Unable to determine GIC version supported by host");
1762 switch (vms->gic_version) {
1763 case VIRT_GIC_VERSION_HOST:
1764 case VIRT_GIC_VERSION_MAX:
1765 if (probe_bitmap & KVM_ARM_VGIC_V3) {
1766 vms->gic_version = VIRT_GIC_VERSION_3;
1768 vms->gic_version = VIRT_GIC_VERSION_2;
1771 case VIRT_GIC_VERSION_NOSEL:
1772 if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <= GIC_NCPU) {
1773 vms->gic_version = VIRT_GIC_VERSION_2;
1774 } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
1776 * in case the host does not support v2 in-kernel emulation or
1777 * the end-user requested more than 8 VCPUs we now default
1778 * to v3. In any case defaulting to v2 would be broken.
1780 vms->gic_version = VIRT_GIC_VERSION_3;
1781 } else if (max_cpus > GIC_NCPU) {
1782 error_report("host only supports in-kernel GICv2 emulation "
1783 "but more than 8 vcpus are requested");
1787 case VIRT_GIC_VERSION_2:
1788 case VIRT_GIC_VERSION_3:
1792 /* Check chosen version is effectively supported by the host */
1793 if (vms->gic_version == VIRT_GIC_VERSION_2 &&
1794 !(probe_bitmap & KVM_ARM_VGIC_V2)) {
1795 error_report("host does not support in-kernel GICv2 emulation");
1797 } else if (vms->gic_version == VIRT_GIC_VERSION_3 &&
1798 !(probe_bitmap & KVM_ARM_VGIC_V3)) {
1799 error_report("host does not support in-kernel GICv3 emulation");
1806 switch (vms->gic_version) {
1807 case VIRT_GIC_VERSION_NOSEL:
1808 vms->gic_version = VIRT_GIC_VERSION_2;
1810 case VIRT_GIC_VERSION_MAX:
1811 vms->gic_version = VIRT_GIC_VERSION_3;
1813 case VIRT_GIC_VERSION_HOST:
1814 error_report("gic-version=host requires KVM");
1816 case VIRT_GIC_VERSION_2:
1817 case VIRT_GIC_VERSION_3:
1823 * virt_cpu_post_init() must be called after the CPUs have
1824 * been realized and the GIC has been created.
1826 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
1828 int max_cpus = MACHINE(vms)->smp.max_cpus;
1829 bool aarch64, pmu, steal_time;
1832 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
1833 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
1834 steal_time = object_property_get_bool(OBJECT(first_cpu),
1835 "kvm-steal-time", NULL);
1837 if (kvm_enabled()) {
1838 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
1839 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
1842 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
1843 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
1845 /* The memory region size must be a multiple of host page size. */
1846 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
1848 if (pvtime_size > pvtime_reg_size) {
1849 error_report("pvtime requires a %" HWADDR_PRId
1850 " byte memory region for %d CPUs,"
1851 " but only %" HWADDR_PRId " has been reserved",
1852 pvtime_size, max_cpus, pvtime_reg_size);
1856 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
1857 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
1862 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
1863 if (kvm_irqchip_in_kernel()) {
1864 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
1866 kvm_arm_pmu_init(cpu);
1869 kvm_arm_pvtime_init(cpu, pvtime_reg_base +
1870 cpu->cpu_index * PVTIME_SIZE_PER_CPU);
1874 if (aarch64 && vms->highmem) {
1875 int requested_pa_size = 64 - clz64(vms->highest_gpa);
1876 int pamax = arm_pamax(ARM_CPU(first_cpu));
1878 if (pamax < requested_pa_size) {
1879 error_report("VCPU supports less PA bits (%d) than "
1880 "requested by the memory map (%d)",
1881 pamax, requested_pa_size);
1888 static void machvirt_init(MachineState *machine)
1890 VirtMachineState *vms = VIRT_MACHINE(machine);
1891 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1892 MachineClass *mc = MACHINE_GET_CLASS(machine);
1893 const CPUArchIdList *possible_cpus;
1894 MemoryRegion *sysmem = get_system_memory();
1895 MemoryRegion *secure_sysmem = NULL;
1896 MemoryRegion *tag_sysmem = NULL;
1897 MemoryRegion *secure_tag_sysmem = NULL;
1898 int n, virt_max_cpus;
1899 bool firmware_loaded;
1900 bool aarch64 = true;
1901 bool has_ged = !vmc->no_ged;
1902 unsigned int smp_cpus = machine->smp.cpus;
1903 unsigned int max_cpus = machine->smp.max_cpus;
1906 * In accelerated mode, the memory map is computed earlier in kvm_type()
1907 * to create a VM with the right number of IPA bits.
1910 virt_set_memmap(vms);
1913 /* We can probe only here because during property set
1914 * KVM is not available yet
1916 finalize_gic_version(vms);
1918 if (!cpu_type_valid(machine->cpu_type)) {
1919 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1925 * The Secure view of the world is the same as the NonSecure,
1926 * but with a few extra devices. Create it as a container region
1927 * containing the system memory at low priority; any secure-only
1928 * devices go in at higher priority and take precedence.
1930 secure_sysmem = g_new(MemoryRegion, 1);
1931 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1933 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1936 firmware_loaded = virt_firmware_init(vms, sysmem,
1937 secure_sysmem ?: sysmem);
1939 /* If we have an EL3 boot ROM then the assumption is that it will
1940 * implement PSCI itself, so disable QEMU's internal implementation
1941 * so it doesn't get in the way. Instead of starting secondary
1942 * CPUs in PSCI powerdown state we will start them all running and
1943 * let the boot ROM sort them out.
1944 * The usual case is that we do use QEMU's PSCI implementation;
1945 * if the guest has EL2 then we will use SMC as the conduit,
1946 * and otherwise we will use HVC (for backwards compatibility and
1947 * because if we're using KVM then we must use HVC).
1949 if (vms->secure && firmware_loaded) {
1950 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1951 } else if (vms->virt) {
1952 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1954 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1957 /* The maximum number of CPUs depends on the GIC version, or on how
1958 * many redistributors we can fit into the memory map.
1960 if (vms->gic_version == VIRT_GIC_VERSION_3) {
1962 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1964 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1966 virt_max_cpus = GIC_NCPU;
1969 if (max_cpus > virt_max_cpus) {
1970 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1971 "supported by machine 'mach-virt' (%d)",
1972 max_cpus, virt_max_cpus);
1976 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
1977 error_report("mach-virt: %s does not support providing "
1978 "Virtualization extensions to the guest CPU",
1979 kvm_enabled() ? "KVM" : "HVF");
1983 if (vms->mte && (kvm_enabled() || hvf_enabled())) {
1984 error_report("mach-virt: %s does not support providing "
1985 "MTE to the guest CPU",
1986 kvm_enabled() ? "KVM" : "HVF");
1992 possible_cpus = mc->possible_cpu_arch_ids(machine);
1993 assert(possible_cpus->len == max_cpus);
1994 for (n = 0; n < possible_cpus->len; n++) {
1998 if (n >= smp_cpus) {
2002 cpuobj = object_new(possible_cpus->cpus[n].type);
2003 object_property_set_int(cpuobj, "mp-affinity",
2004 possible_cpus->cpus[n].arch_id, NULL);
2009 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2012 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2015 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2018 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2019 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2022 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
2023 object_property_set_int(cpuobj, "psci-conduit", vms->psci_conduit,
2026 /* Secondary CPUs start in PSCI powered-down state */
2028 object_property_set_bool(cpuobj, "start-powered-off", true,
2033 if (vmc->kvm_no_adjvtime &&
2034 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2035 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2038 if (vmc->no_kvm_steal_time &&
2039 object_property_find(cpuobj, "kvm-steal-time")) {
2040 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2043 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2044 object_property_set_bool(cpuobj, "pmu", false, NULL);
2047 if (object_property_find(cpuobj, "reset-cbar")) {
2048 object_property_set_int(cpuobj, "reset-cbar",
2049 vms->memmap[VIRT_CPUPERIPHS].base,
2053 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2056 object_property_set_link(cpuobj, "secure-memory",
2057 OBJECT(secure_sysmem), &error_abort);
2061 /* Create the memory region only once, but link to all cpus. */
2064 * The property exists only if MemTag is supported.
2065 * If it is, we must allocate the ram to back that up.
2067 if (!object_property_find(cpuobj, "tag-memory")) {
2068 error_report("MTE requested, but not supported "
2069 "by the guest CPU");
2073 tag_sysmem = g_new(MemoryRegion, 1);
2074 memory_region_init(tag_sysmem, OBJECT(machine),
2075 "tag-memory", UINT64_MAX / 32);
2078 secure_tag_sysmem = g_new(MemoryRegion, 1);
2079 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2080 "secure-tag-memory", UINT64_MAX / 32);
2082 /* As with ram, secure-tag takes precedence over tag. */
2083 memory_region_add_subregion_overlap(secure_tag_sysmem, 0,
2088 object_property_set_link(cpuobj, "tag-memory", OBJECT(tag_sysmem),
2091 object_property_set_link(cpuobj, "secure-tag-memory",
2092 OBJECT(secure_tag_sysmem),
2097 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2098 object_unref(cpuobj);
2100 fdt_add_timer_nodes(vms);
2101 fdt_add_cpu_nodes(vms);
2103 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2105 if (machine->device_memory) {
2106 memory_region_add_subregion(sysmem, machine->device_memory->base,
2107 &machine->device_memory->mr);
2110 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2112 create_gic(vms, sysmem);
2114 virt_cpu_post_init(vms, sysmem);
2116 fdt_add_pmu_nodes(vms);
2118 create_uart(vms, VIRT_UART, sysmem, serial_hd(0));
2121 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2122 create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
2126 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2127 machine->ram_size, "mach-virt.tag");
2130 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
2136 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2137 vms->acpi_dev = create_acpi_ged(vms);
2139 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2142 if (vms->secure && !vmc->no_secure_gpio) {
2143 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2146 /* connect powerdown request */
2147 vms->powerdown_notifier.notify = virt_powerdown_req;
2148 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2150 /* Create mmio transports, so the user can create virtio backends
2151 * (which will be automatically plugged in to the transports). If
2152 * no backend is created the transport will just sit harmlessly idle.
2154 create_virtio_devices(vms);
2156 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2157 rom_set_fw(vms->fw_cfg);
2159 create_platform_bus(vms);
2161 if (machine->nvdimms_state->is_enabled) {
2162 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2163 .space_id = AML_AS_SYSTEM_MEMORY,
2164 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2165 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2168 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2169 arm_virt_nvdimm_acpi_dsmio,
2170 vms->fw_cfg, OBJECT(vms));
2173 vms->bootinfo.ram_size = machine->ram_size;
2174 vms->bootinfo.nb_cpus = smp_cpus;
2175 vms->bootinfo.board_id = -1;
2176 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2177 vms->bootinfo.get_dtb = machvirt_dtb;
2178 vms->bootinfo.skip_dtb_autoload = true;
2179 vms->bootinfo.firmware_loaded = firmware_loaded;
2180 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2182 vms->machine_done.notify = virt_machine_done;
2183 qemu_add_machine_init_done_notifier(&vms->machine_done);
2186 static bool virt_get_secure(Object *obj, Error **errp)
2188 VirtMachineState *vms = VIRT_MACHINE(obj);
2193 static void virt_set_secure(Object *obj, bool value, Error **errp)
2195 VirtMachineState *vms = VIRT_MACHINE(obj);
2197 vms->secure = value;
2200 static bool virt_get_virt(Object *obj, Error **errp)
2202 VirtMachineState *vms = VIRT_MACHINE(obj);
2207 static void virt_set_virt(Object *obj, bool value, Error **errp)
2209 VirtMachineState *vms = VIRT_MACHINE(obj);
2214 static bool virt_get_highmem(Object *obj, Error **errp)
2216 VirtMachineState *vms = VIRT_MACHINE(obj);
2218 return vms->highmem;
2221 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2223 VirtMachineState *vms = VIRT_MACHINE(obj);
2225 vms->highmem = value;
2228 static bool virt_get_its(Object *obj, Error **errp)
2230 VirtMachineState *vms = VIRT_MACHINE(obj);
2235 static void virt_set_its(Object *obj, bool value, Error **errp)
2237 VirtMachineState *vms = VIRT_MACHINE(obj);
2242 static bool virt_get_dtb_kaslr_seed(Object *obj, Error **errp)
2244 VirtMachineState *vms = VIRT_MACHINE(obj);
2246 return vms->dtb_kaslr_seed;
2249 static void virt_set_dtb_kaslr_seed(Object *obj, bool value, Error **errp)
2251 VirtMachineState *vms = VIRT_MACHINE(obj);
2253 vms->dtb_kaslr_seed = value;
2256 static char *virt_get_oem_id(Object *obj, Error **errp)
2258 VirtMachineState *vms = VIRT_MACHINE(obj);
2260 return g_strdup(vms->oem_id);
2263 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2265 VirtMachineState *vms = VIRT_MACHINE(obj);
2266 size_t len = strlen(value);
2270 "User specified oem-id value is bigger than 6 bytes in size");
2274 strncpy(vms->oem_id, value, 6);
2277 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2279 VirtMachineState *vms = VIRT_MACHINE(obj);
2281 return g_strdup(vms->oem_table_id);
2284 static void virt_set_oem_table_id(Object *obj, const char *value,
2287 VirtMachineState *vms = VIRT_MACHINE(obj);
2288 size_t len = strlen(value);
2292 "User specified oem-table-id value is bigger than 8 bytes in size");
2295 strncpy(vms->oem_table_id, value, 8);
2299 bool virt_is_acpi_enabled(VirtMachineState *vms)
2301 if (vms->acpi == ON_OFF_AUTO_OFF) {
2307 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2308 void *opaque, Error **errp)
2310 VirtMachineState *vms = VIRT_MACHINE(obj);
2311 OnOffAuto acpi = vms->acpi;
2313 visit_type_OnOffAuto(v, name, &acpi, errp);
2316 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2317 void *opaque, Error **errp)
2319 VirtMachineState *vms = VIRT_MACHINE(obj);
2321 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2324 static bool virt_get_ras(Object *obj, Error **errp)
2326 VirtMachineState *vms = VIRT_MACHINE(obj);
2331 static void virt_set_ras(Object *obj, bool value, Error **errp)
2333 VirtMachineState *vms = VIRT_MACHINE(obj);
2338 static bool virt_get_mte(Object *obj, Error **errp)
2340 VirtMachineState *vms = VIRT_MACHINE(obj);
2345 static void virt_set_mte(Object *obj, bool value, Error **errp)
2347 VirtMachineState *vms = VIRT_MACHINE(obj);
2352 static char *virt_get_gic_version(Object *obj, Error **errp)
2354 VirtMachineState *vms = VIRT_MACHINE(obj);
2355 const char *val = vms->gic_version == VIRT_GIC_VERSION_3 ? "3" : "2";
2357 return g_strdup(val);
2360 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2362 VirtMachineState *vms = VIRT_MACHINE(obj);
2364 if (!strcmp(value, "3")) {
2365 vms->gic_version = VIRT_GIC_VERSION_3;
2366 } else if (!strcmp(value, "2")) {
2367 vms->gic_version = VIRT_GIC_VERSION_2;
2368 } else if (!strcmp(value, "host")) {
2369 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2370 } else if (!strcmp(value, "max")) {
2371 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2373 error_setg(errp, "Invalid gic-version value");
2374 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2378 static char *virt_get_iommu(Object *obj, Error **errp)
2380 VirtMachineState *vms = VIRT_MACHINE(obj);
2382 switch (vms->iommu) {
2383 case VIRT_IOMMU_NONE:
2384 return g_strdup("none");
2385 case VIRT_IOMMU_SMMUV3:
2386 return g_strdup("smmuv3");
2388 g_assert_not_reached();
2392 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2394 VirtMachineState *vms = VIRT_MACHINE(obj);
2396 if (!strcmp(value, "smmuv3")) {
2397 vms->iommu = VIRT_IOMMU_SMMUV3;
2398 } else if (!strcmp(value, "none")) {
2399 vms->iommu = VIRT_IOMMU_NONE;
2401 error_setg(errp, "Invalid iommu value");
2402 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2406 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2408 VirtMachineState *vms = VIRT_MACHINE(obj);
2410 return vms->default_bus_bypass_iommu;
2413 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2416 VirtMachineState *vms = VIRT_MACHINE(obj);
2418 vms->default_bus_bypass_iommu = value;
2421 static CpuInstanceProperties
2422 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2424 MachineClass *mc = MACHINE_GET_CLASS(ms);
2425 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2427 assert(cpu_index < possible_cpus->len);
2428 return possible_cpus->cpus[cpu_index].props;
2431 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2433 return idx % ms->numa_state->num_nodes;
2436 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2439 unsigned int max_cpus = ms->smp.max_cpus;
2440 VirtMachineState *vms = VIRT_MACHINE(ms);
2442 if (ms->possible_cpus) {
2443 assert(ms->possible_cpus->len == max_cpus);
2444 return ms->possible_cpus;
2447 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2448 sizeof(CPUArchId) * max_cpus);
2449 ms->possible_cpus->len = max_cpus;
2450 for (n = 0; n < ms->possible_cpus->len; n++) {
2451 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2452 ms->possible_cpus->cpus[n].arch_id =
2453 virt_cpu_mp_affinity(vms, n);
2454 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2455 ms->possible_cpus->cpus[n].props.thread_id = n;
2457 return ms->possible_cpus;
2460 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2463 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2464 const MachineState *ms = MACHINE(hotplug_dev);
2465 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2467 if (!vms->acpi_dev) {
2469 "memory hotplug is not enabled: missing acpi-ged device");
2474 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2478 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2479 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2483 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp);
2486 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2487 DeviceState *dev, Error **errp)
2489 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2490 MachineState *ms = MACHINE(hotplug_dev);
2491 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2493 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2496 nvdimm_plug(ms->nvdimms_state);
2499 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2503 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2504 DeviceState *dev, Error **errp)
2506 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2508 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2509 virt_memory_pre_plug(hotplug_dev, dev, errp);
2510 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2511 hwaddr db_start = 0, db_end = 0;
2512 char *resv_prop_str;
2514 if (vms->iommu != VIRT_IOMMU_NONE) {
2515 error_setg(errp, "virt machine does not support multiple IOMMUs");
2519 switch (vms->msi_controller) {
2520 case VIRT_MSI_CTRL_NONE:
2522 case VIRT_MSI_CTRL_ITS:
2523 /* GITS_TRANSLATER page */
2524 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2525 db_end = base_memmap[VIRT_GIC_ITS].base +
2526 base_memmap[VIRT_GIC_ITS].size - 1;
2528 case VIRT_MSI_CTRL_GICV2M:
2529 /* MSI_SETSPI_NS page */
2530 db_start = base_memmap[VIRT_GIC_V2M].base;
2531 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2534 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2536 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2538 object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
2539 object_property_set_str(OBJECT(dev), "reserved-regions[0]",
2540 resv_prop_str, errp);
2541 g_free(resv_prop_str);
2545 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2546 DeviceState *dev, Error **errp)
2548 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2550 if (vms->platform_bus_dev) {
2551 MachineClass *mc = MACHINE_GET_CLASS(vms);
2553 if (device_is_dynamic_sysbus(mc, dev)) {
2554 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2555 SYS_BUS_DEVICE(dev));
2558 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2559 virt_memory_plug(hotplug_dev, dev, errp);
2561 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2562 PCIDevice *pdev = PCI_DEVICE(dev);
2564 vms->iommu = VIRT_IOMMU_VIRTIO;
2565 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2566 create_virtio_iommu_dt_bindings(vms);
2570 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2571 DeviceState *dev, Error **errp)
2573 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2574 Error *local_err = NULL;
2576 if (!vms->acpi_dev) {
2577 error_setg(&local_err,
2578 "memory hotplug is not enabled: missing acpi-ged device");
2582 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2583 error_setg(&local_err,
2584 "nvdimm device hot unplug is not supported yet.");
2588 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2591 error_propagate(errp, local_err);
2594 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2595 DeviceState *dev, Error **errp)
2597 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2598 Error *local_err = NULL;
2600 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2605 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2606 qdev_unrealize(dev);
2609 error_propagate(errp, local_err);
2612 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2613 DeviceState *dev, Error **errp)
2615 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2616 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2618 error_setg(errp, "device unplug request for unsupported device"
2619 " type: %s", object_get_typename(OBJECT(dev)));
2623 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2624 DeviceState *dev, Error **errp)
2626 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2627 virt_dimm_unplug(hotplug_dev, dev, errp);
2629 error_setg(errp, "virt: device unplug for unsupported device"
2630 " type: %s", object_get_typename(OBJECT(dev)));
2634 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2637 MachineClass *mc = MACHINE_GET_CLASS(machine);
2639 if (device_is_dynamic_sysbus(mc, dev) ||
2640 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
2641 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2642 return HOTPLUG_HANDLER(machine);
2648 * for arm64 kvm_type [7-0] encodes the requested number of bits
2649 * in the IPA address space
2651 static int virt_kvm_type(MachineState *ms, const char *type_str)
2653 VirtMachineState *vms = VIRT_MACHINE(ms);
2654 int max_vm_pa_size, requested_pa_size;
2657 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
2659 /* we freeze the memory map to compute the highest gpa */
2660 virt_set_memmap(vms);
2662 requested_pa_size = 64 - clz64(vms->highest_gpa);
2665 * KVM requires the IPA size to be at least 32 bits.
2667 if (requested_pa_size < 32) {
2668 requested_pa_size = 32;
2671 if (requested_pa_size > max_vm_pa_size) {
2672 error_report("-m and ,maxmem option values "
2673 "require an IPA range (%d bits) larger than "
2674 "the one supported by the host (%d bits)",
2675 requested_pa_size, max_vm_pa_size);
2679 * We return the requested PA log size, unless KVM only supports
2680 * the implicit legacy 40b IPA setting, in which case the kvm_type
2683 return fixed_ipa ? 0 : requested_pa_size;
2686 static void virt_machine_class_init(ObjectClass *oc, void *data)
2688 MachineClass *mc = MACHINE_CLASS(oc);
2689 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2691 mc->init = machvirt_init;
2692 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
2693 * The value may be reduced later when we have more information about the
2694 * configuration of the particular instance.
2697 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
2698 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
2699 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
2700 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
2702 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
2704 mc->block_default_type = IF_VIRTIO;
2706 mc->pci_allow_0_address = true;
2707 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
2708 mc->minimum_page_bits = 12;
2709 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
2710 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
2711 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
2712 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
2713 mc->kvm_type = virt_kvm_type;
2714 assert(!mc->get_hotplug_handler);
2715 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
2716 hc->pre_plug = virt_machine_device_pre_plug_cb;
2717 hc->plug = virt_machine_device_plug_cb;
2718 hc->unplug_request = virt_machine_device_unplug_request_cb;
2719 hc->unplug = virt_machine_device_unplug_cb;
2720 mc->nvdimm_supported = true;
2721 mc->auto_enable_numa_with_memhp = true;
2722 mc->auto_enable_numa_with_memdev = true;
2723 mc->default_ram_id = "mach-virt.ram";
2725 object_class_property_add(oc, "acpi", "OnOffAuto",
2726 virt_get_acpi, virt_set_acpi,
2728 object_class_property_set_description(oc, "acpi",
2730 object_class_property_add_bool(oc, "secure", virt_get_secure,
2732 object_class_property_set_description(oc, "secure",
2733 "Set on/off to enable/disable the ARM "
2734 "Security Extensions (TrustZone)");
2736 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
2738 object_class_property_set_description(oc, "virtualization",
2739 "Set on/off to enable/disable emulating a "
2740 "guest CPU which implements the ARM "
2741 "Virtualization Extensions");
2743 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
2745 object_class_property_set_description(oc, "highmem",
2746 "Set on/off to enable/disable using "
2747 "physical address space above 32 bits");
2749 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
2750 virt_set_gic_version);
2751 object_class_property_set_description(oc, "gic-version",
2753 "Valid values are 2, 3, host and max");
2755 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
2756 object_class_property_set_description(oc, "iommu",
2757 "Set the IOMMU type. "
2758 "Valid values are none and smmuv3");
2760 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
2761 virt_get_default_bus_bypass_iommu,
2762 virt_set_default_bus_bypass_iommu);
2763 object_class_property_set_description(oc, "default-bus-bypass-iommu",
2764 "Set on/off to enable/disable "
2765 "bypass_iommu for default root bus");
2767 object_class_property_add_bool(oc, "ras", virt_get_ras,
2769 object_class_property_set_description(oc, "ras",
2770 "Set on/off to enable/disable reporting host memory errors "
2771 "to a KVM guest using ACPI and guest external abort exceptions");
2773 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
2774 object_class_property_set_description(oc, "mte",
2775 "Set on/off to enable/disable emulating a "
2776 "guest CPU which implements the ARM "
2777 "Memory Tagging Extension");
2779 object_class_property_add_bool(oc, "its", virt_get_its,
2781 object_class_property_set_description(oc, "its",
2782 "Set on/off to enable/disable "
2783 "ITS instantiation");
2785 object_class_property_add_bool(oc, "dtb-kaslr-seed",
2786 virt_get_dtb_kaslr_seed,
2787 virt_set_dtb_kaslr_seed);
2788 object_class_property_set_description(oc, "dtb-kaslr-seed",
2789 "Set off to disable passing of kaslr-seed "
2790 "dtb node to guest");
2792 object_class_property_add_str(oc, "x-oem-id",
2795 object_class_property_set_description(oc, "x-oem-id",
2796 "Override the default value of field OEMID "
2797 "in ACPI table header."
2798 "The string may be up to 6 bytes in size");
2801 object_class_property_add_str(oc, "x-oem-table-id",
2802 virt_get_oem_table_id,
2803 virt_set_oem_table_id);
2804 object_class_property_set_description(oc, "x-oem-table-id",
2805 "Override the default value of field OEM Table ID "
2806 "in ACPI table header."
2807 "The string may be up to 8 bytes in size");
2811 static void virt_instance_init(Object *obj)
2813 VirtMachineState *vms = VIRT_MACHINE(obj);
2814 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
2816 /* EL3 is disabled by default on virt: this makes us consistent
2817 * between KVM and TCG for this board, and it also allows us to
2818 * boot UEFI blobs which assume no TrustZone support.
2820 vms->secure = false;
2822 /* EL2 is also disabled by default, for similar reasons */
2825 /* High memory is enabled by default */
2826 vms->highmem = true;
2827 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
2829 vms->highmem_ecam = !vmc->no_highmem_ecam;
2834 /* Default allows ITS instantiation */
2837 if (vmc->no_tcg_its) {
2838 vms->tcg_its = false;
2840 vms->tcg_its = true;
2844 /* Default disallows iommu instantiation */
2845 vms->iommu = VIRT_IOMMU_NONE;
2847 /* The default root bus is attached to iommu by default */
2848 vms->default_bus_bypass_iommu = false;
2850 /* Default disallows RAS instantiation */
2853 /* MTE is disabled by default. */
2856 /* Supply a kaslr-seed by default */
2857 vms->dtb_kaslr_seed = true;
2859 vms->irqmap = a15irqmap;
2861 virt_flash_create(vms);
2863 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
2864 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
2867 static const TypeInfo virt_machine_info = {
2868 .name = TYPE_VIRT_MACHINE,
2869 .parent = TYPE_MACHINE,
2871 .instance_size = sizeof(VirtMachineState),
2872 .class_size = sizeof(VirtMachineClass),
2873 .class_init = virt_machine_class_init,
2874 .instance_init = virt_instance_init,
2875 .interfaces = (InterfaceInfo[]) {
2876 { TYPE_HOTPLUG_HANDLER },
2881 static void machvirt_machine_init(void)
2883 type_register_static(&virt_machine_info);
2885 type_init(machvirt_machine_init);
2887 static void virt_machine_7_0_options(MachineClass *mc)
2890 DEFINE_VIRT_MACHINE_AS_LATEST(7, 0)
2892 static void virt_machine_6_2_options(MachineClass *mc)
2894 virt_machine_7_0_options(mc);
2895 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
2897 DEFINE_VIRT_MACHINE(6, 2)
2899 static void virt_machine_6_1_options(MachineClass *mc)
2901 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2903 virt_machine_6_2_options(mc);
2904 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
2905 mc->smp_props.prefer_sockets = true;
2906 vmc->no_cpu_topology = true;
2908 /* qemu ITS was introduced with 6.2 */
2909 vmc->no_tcg_its = true;
2911 DEFINE_VIRT_MACHINE(6, 1)
2913 static void virt_machine_6_0_options(MachineClass *mc)
2915 virt_machine_6_1_options(mc);
2916 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
2918 DEFINE_VIRT_MACHINE(6, 0)
2920 static void virt_machine_5_2_options(MachineClass *mc)
2922 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2924 virt_machine_6_0_options(mc);
2925 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
2926 vmc->no_secure_gpio = true;
2928 DEFINE_VIRT_MACHINE(5, 2)
2930 static void virt_machine_5_1_options(MachineClass *mc)
2932 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2934 virt_machine_5_2_options(mc);
2935 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
2936 vmc->no_kvm_steal_time = true;
2938 DEFINE_VIRT_MACHINE(5, 1)
2940 static void virt_machine_5_0_options(MachineClass *mc)
2942 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2944 virt_machine_5_1_options(mc);
2945 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
2946 mc->numa_mem_supported = true;
2947 vmc->acpi_expose_flash = true;
2948 mc->auto_enable_numa_with_memdev = false;
2950 DEFINE_VIRT_MACHINE(5, 0)
2952 static void virt_machine_4_2_options(MachineClass *mc)
2954 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2956 virt_machine_5_0_options(mc);
2957 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
2958 vmc->kvm_no_adjvtime = true;
2960 DEFINE_VIRT_MACHINE(4, 2)
2962 static void virt_machine_4_1_options(MachineClass *mc)
2964 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2966 virt_machine_4_2_options(mc);
2967 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
2969 mc->auto_enable_numa_with_memhp = false;
2971 DEFINE_VIRT_MACHINE(4, 1)
2973 static void virt_machine_4_0_options(MachineClass *mc)
2975 virt_machine_4_1_options(mc);
2976 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2978 DEFINE_VIRT_MACHINE(4, 0)
2980 static void virt_machine_3_1_options(MachineClass *mc)
2982 virt_machine_4_0_options(mc);
2983 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2985 DEFINE_VIRT_MACHINE(3, 1)
2987 static void virt_machine_3_0_options(MachineClass *mc)
2989 virt_machine_3_1_options(mc);
2990 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2992 DEFINE_VIRT_MACHINE(3, 0)
2994 static void virt_machine_2_12_options(MachineClass *mc)
2996 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2998 virt_machine_3_0_options(mc);
2999 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3000 vmc->no_highmem_ecam = true;
3003 DEFINE_VIRT_MACHINE(2, 12)
3005 static void virt_machine_2_11_options(MachineClass *mc)
3007 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3009 virt_machine_2_12_options(mc);
3010 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3011 vmc->smbios_old_sys_ver = true;
3013 DEFINE_VIRT_MACHINE(2, 11)
3015 static void virt_machine_2_10_options(MachineClass *mc)
3017 virt_machine_2_11_options(mc);
3018 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3019 /* before 2.11 we never faulted accesses to bad addresses */
3020 mc->ignore_memory_transaction_failures = true;
3022 DEFINE_VIRT_MACHINE(2, 10)
3024 static void virt_machine_2_9_options(MachineClass *mc)
3026 virt_machine_2_10_options(mc);
3027 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3029 DEFINE_VIRT_MACHINE(2, 9)
3031 static void virt_machine_2_8_options(MachineClass *mc)
3033 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3035 virt_machine_2_9_options(mc);
3036 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3037 /* For 2.8 and earlier we falsely claimed in the DT that
3038 * our timers were edge-triggered, not level-triggered.
3040 vmc->claim_edge_triggered_timers = true;
3042 DEFINE_VIRT_MACHINE(2, 8)
3044 static void virt_machine_2_7_options(MachineClass *mc)
3046 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3048 virt_machine_2_8_options(mc);
3049 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3050 /* ITS was introduced with 2.8 */
3052 /* Stick with 1K pages for migration compatibility */
3053 mc->minimum_page_bits = 0;
3055 DEFINE_VIRT_MACHINE(2, 7)
3057 static void virt_machine_2_6_options(MachineClass *mc)
3059 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3061 virt_machine_2_7_options(mc);
3062 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3063 vmc->disallow_affinity_adjustment = true;
3064 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3067 DEFINE_VIRT_MACHINE(2, 6)