tcg/ia64/tcg-target.c

   1 /*
   2  * Tiny Code Generator for QEMU
   3  *
   4  * Copyright (c) 2009-2010 Aurelien Jarno <[email protected]>
   5  * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 /*
  27  * Register definitions
  28  */
  29
  30 #ifndef NDEBUG
  31 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
  32      "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
  33      "r8",  "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  34     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  35     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
  36     "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
  37     "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
  38     "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
  39     "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
  40 };
  41 #endif
  42
  43 #ifdef CONFIG_USE_GUEST_BASE
  44 #define TCG_GUEST_BASE_REG TCG_REG_R55
  45 #else
  46 #define TCG_GUEST_BASE_REG TCG_REG_R0
  47 #endif
  48 #ifndef GUEST_BASE
  49 #define GUEST_BASE 0
  50 #endif
  51
  52 /* Branch registers */
  53 enum {
  54     TCG_REG_B0 = 0,
  55     TCG_REG_B1,
  56     TCG_REG_B2,
  57     TCG_REG_B3,
  58     TCG_REG_B4,
  59     TCG_REG_B5,
  60     TCG_REG_B6,
  61     TCG_REG_B7,
  62 };
  63
  64 /* Floating point registers */
  65 enum {
  66     TCG_REG_F0 = 0,
  67     TCG_REG_F1,
  68     TCG_REG_F2,
  69     TCG_REG_F3,
  70     TCG_REG_F4,
  71     TCG_REG_F5,
  72     TCG_REG_F6,
  73     TCG_REG_F7,
  74     TCG_REG_F8,
  75     TCG_REG_F9,
  76     TCG_REG_F10,
  77     TCG_REG_F11,
  78     TCG_REG_F12,
  79     TCG_REG_F13,
  80     TCG_REG_F14,
  81     TCG_REG_F15,
  82 };
  83
  84 /* Predicate registers */
  85 enum {
  86     TCG_REG_P0 = 0,
  87     TCG_REG_P1,
  88     TCG_REG_P2,
  89     TCG_REG_P3,
  90     TCG_REG_P4,
  91     TCG_REG_P5,
  92     TCG_REG_P6,
  93     TCG_REG_P7,
  94     TCG_REG_P8,
  95     TCG_REG_P9,
  96     TCG_REG_P10,
  97     TCG_REG_P11,
  98     TCG_REG_P12,
  99     TCG_REG_P13,
 100     TCG_REG_P14,
 101     TCG_REG_P15,
 102 };
 103
 104 /* Application registers */
 105 enum {
 106     TCG_REG_PFS = 64,
 107 };
 108
 109 static const int tcg_target_reg_alloc_order[] = {
 110     TCG_REG_R34,
 111     TCG_REG_R35,
 112     TCG_REG_R36,
 113     TCG_REG_R37,
 114     TCG_REG_R38,
 115     TCG_REG_R39,
 116     TCG_REG_R40,
 117     TCG_REG_R41,
 118     TCG_REG_R42,
 119     TCG_REG_R43,
 120     TCG_REG_R44,
 121     TCG_REG_R45,
 122     TCG_REG_R46,
 123     TCG_REG_R47,
 124     TCG_REG_R48,
 125     TCG_REG_R49,
 126     TCG_REG_R50,
 127     TCG_REG_R51,
 128     TCG_REG_R52,
 129     TCG_REG_R53,
 130     TCG_REG_R54,
 131     TCG_REG_R55,
 132     TCG_REG_R14,
 133     TCG_REG_R15,
 134     TCG_REG_R16,
 135     TCG_REG_R17,
 136     TCG_REG_R18,
 137     TCG_REG_R19,
 138     TCG_REG_R20,
 139     TCG_REG_R21,
 140     TCG_REG_R22,
 141     TCG_REG_R23,
 142     TCG_REG_R24,
 143     TCG_REG_R25,
 144     TCG_REG_R26,
 145     TCG_REG_R27,
 146     TCG_REG_R28,
 147     TCG_REG_R29,
 148     TCG_REG_R30,
 149     TCG_REG_R31,
 150     TCG_REG_R56,
 151     TCG_REG_R57,
 152     TCG_REG_R58,
 153     TCG_REG_R59,
 154     TCG_REG_R60,
 155     TCG_REG_R61,
 156     TCG_REG_R62,
 157     TCG_REG_R63,
 158     TCG_REG_R8,
 159     TCG_REG_R9,
 160     TCG_REG_R10,
 161     TCG_REG_R11
 162 };
 163
 164 static const int tcg_target_call_iarg_regs[8] = {
 165     TCG_REG_R56,
 166     TCG_REG_R57,
 167     TCG_REG_R58,
 168     TCG_REG_R59,
 169     TCG_REG_R60,
 170     TCG_REG_R61,
 171     TCG_REG_R62,
 172     TCG_REG_R63,
 173 };
 174
 175 static const int tcg_target_call_oarg_regs[2] = {
 176     TCG_REG_R8,
 177     TCG_REG_R9
 178 };
 179
 180 /* maximum number of register used for input function arguments */
 181 static inline int tcg_target_get_call_iarg_regs_count(int flags)
 182 {
 183     return 8;
 184 }
 185
 186 /*
 187  * opcode formation
 188  */
 189
 190 /* bundle templates: stops (double bar in the IA64 manual) are marked with
 191    an uppercase letter. */
 192 enum {
 193     mii = 0x00,
 194     miI = 0x01,
 195     mIi = 0x02,
 196     mII = 0x03,
 197     mlx = 0x04,
 198     mLX = 0x05,
 199     mmi = 0x08,
 200     mmI = 0x09,
 201     Mmi = 0x0a,
 202     MmI = 0x0b,
 203     mfi = 0x0c,
 204     mfI = 0x0d,
 205     mmf = 0x0e,
 206     mmF = 0x0f,
 207     mib = 0x10,
 208     miB = 0x11,
 209     mbb = 0x12,
 210     mbB = 0x13,
 211     bbb = 0x16,
 212     bbB = 0x17,
 213     mmb = 0x18,
 214     mmB = 0x19,
 215     mfb = 0x1c,
 216     mfB = 0x1d,
 217 };
 218
 219 enum {
 220     OPC_ADD_A1                = 0x10000000000ull,
 221     OPC_AND_A1                = 0x10060000000ull,
 222     OPC_AND_A3                = 0x10160000000ull,
 223     OPC_ANDCM_A1              = 0x10068000000ull,
 224     OPC_ANDCM_A3              = 0x10168000000ull,
 225     OPC_ADDS_A4               = 0x10800000000ull,
 226     OPC_ADDL_A5               = 0x12000000000ull,
 227     OPC_ALLOC_M34             = 0x02c00000000ull,
 228     OPC_BR_DPTK_FEW_B1        = 0x08400000000ull,
 229     OPC_BR_SPTK_MANY_B1       = 0x08000001000ull,
 230     OPC_BR_SPTK_MANY_B4       = 0x00100001000ull,
 231     OPC_BR_CALL_SPTK_MANY_B5  = 0x02100001000ull,
 232     OPC_BR_RET_SPTK_MANY_B4   = 0x00108001100ull,
 233     OPC_BRL_SPTK_MANY_X3      = 0x18000001000ull,
 234     OPC_CMP_LT_A6             = 0x18000000000ull,
 235     OPC_CMP_LTU_A6            = 0x1a000000000ull,
 236     OPC_CMP_EQ_A6             = 0x1c000000000ull,
 237     OPC_CMP4_LT_A6            = 0x18400000000ull,
 238     OPC_CMP4_LTU_A6           = 0x1a400000000ull,
 239     OPC_CMP4_EQ_A6            = 0x1c400000000ull,
 240     OPC_DEP_Z_I12             = 0x0a600000000ull,
 241     OPC_EXTR_I11              = 0x0a400002000ull,
 242     OPC_EXTR_U_I11            = 0x0a400000000ull,
 243     OPC_FCVT_FX_TRUNC_S1_F10  = 0x004d0000000ull,
 244     OPC_FCVT_FXU_TRUNC_S1_F10 = 0x004d8000000ull,
 245     OPC_FCVT_XF_F11           = 0x000e0000000ull,
 246     OPC_FMA_S1_F1             = 0x10400000000ull,
 247     OPC_FNMA_S1_F1            = 0x18400000000ull,
 248     OPC_FRCPA_S1_F6           = 0x00600000000ull,
 249     OPC_GETF_SIG_M19          = 0x08708000000ull,
 250     OPC_LD1_M1                = 0x08000000000ull,
 251     OPC_LD1_M3                = 0x0a000000000ull,
 252     OPC_LD2_M1                = 0x08040000000ull,
 253     OPC_LD2_M3                = 0x0a040000000ull,
 254     OPC_LD4_M1                = 0x08080000000ull,
 255     OPC_LD4_M3                = 0x0a080000000ull,
 256     OPC_LD8_M1                = 0x080c0000000ull,
 257     OPC_LD8_M3                = 0x0a0c0000000ull,
 258     OPC_MUX1_I3               = 0x0eca0000000ull,
 259     OPC_NOP_B9                = 0x04008000000ull,
 260     OPC_NOP_F16               = 0x00008000000ull,
 261     OPC_NOP_I18               = 0x00008000000ull,
 262     OPC_NOP_M48               = 0x00008000000ull,
 263     OPC_MOV_I21               = 0x00e00100000ull,
 264     OPC_MOV_RET_I21           = 0x00e00500000ull,
 265     OPC_MOV_I22               = 0x00188000000ull,
 266     OPC_MOV_I_I26             = 0x00150000000ull,
 267     OPC_MOVL_X2               = 0x0c000000000ull,
 268     OPC_OR_A1                 = 0x10070000000ull,
 269     OPC_SETF_EXP_M18          = 0x0c748000000ull,
 270     OPC_SETF_SIG_M18          = 0x0c708000000ull,
 271     OPC_SHL_I7                = 0x0f240000000ull,
 272     OPC_SHR_I5                = 0x0f220000000ull,
 273     OPC_SHR_U_I5              = 0x0f200000000ull,
 274     OPC_SHRP_I10              = 0x0ac00000000ull,
 275     OPC_SXT1_I29              = 0x000a0000000ull,
 276     OPC_SXT2_I29              = 0x000a8000000ull,
 277     OPC_SXT4_I29              = 0x000b0000000ull,
 278     OPC_ST1_M4                = 0x08c00000000ull,
 279     OPC_ST2_M4                = 0x08c40000000ull,
 280     OPC_ST4_M4                = 0x08c80000000ull,
 281     OPC_ST8_M4                = 0x08cc0000000ull,
 282     OPC_SUB_A1                = 0x10028000000ull,
 283     OPC_SUB_A3                = 0x10128000000ull,
 284     OPC_UNPACK4_L_I2          = 0x0f860000000ull,
 285     OPC_XMA_L_F2              = 0x1d000000000ull,
 286     OPC_XOR_A1                = 0x10078000000ull,
 287     OPC_ZXT1_I29              = 0x00080000000ull,
 288     OPC_ZXT2_I29              = 0x00088000000ull,
 289     OPC_ZXT4_I29              = 0x00090000000ull,
 290 };
 291
 292 static inline uint64_t tcg_opc_a1(int qp, uint64_t opc, int r1,
 293                                   int r2, int r3)
 294 {
 295     return opc
 296            | ((r3 & 0x7f) << 20)
 297            | ((r2 & 0x7f) << 13)
 298            | ((r1 & 0x7f) << 6)
 299            | (qp & 0x3f);
 300 }
 301
 302 static inline uint64_t tcg_opc_a3(int qp, uint64_t opc, int r1,
 303                                   uint64_t imm, int r3)
 304 {
 305     return opc
 306            | ((imm & 0x80) << 29) /* s */
 307            | ((imm & 0x7f) << 13) /* imm7b */
 308            | ((r3 & 0x7f) << 20)
 309            | ((r1 & 0x7f) << 6)
 310            | (qp & 0x3f);
 311 }
 312
 313 static inline uint64_t tcg_opc_a4(int qp, uint64_t opc, int r1,
 314                                   uint64_t imm, int r3)
 315 {
 316     return opc
 317            | ((imm & 0x2000) << 23) /* s */
 318            | ((imm & 0x1f80) << 20) /* imm6d */
 319            | ((imm & 0x007f) << 13) /* imm7b */
 320            | ((r3 & 0x7f) << 20)
 321            | ((r1 & 0x7f) << 6)
 322            | (qp & 0x3f);
 323 }
 324
 325 static inline uint64_t tcg_opc_a5(int qp, uint64_t opc, int r1,
 326                                   uint64_t imm, int r3)
 327 {
 328     return opc
 329            | ((imm & 0x200000) << 15) /* s */
 330            | ((imm & 0x1f0000) <<  6) /* imm5c */
 331            | ((imm & 0x00ff80) << 20) /* imm9d */
 332            | ((imm & 0x00007f) << 13) /* imm7b */
 333            | ((r3 & 0x03) << 20)
 334            | ((r1 & 0x7f) << 6)
 335            | (qp & 0x3f);
 336 }
 337
 338 static inline uint64_t tcg_opc_a6(int qp, uint64_t opc, int p1,
 339                                   int p2, int r2, int r3)
 340 {
 341     return opc
 342            | ((p2 & 0x3f) << 27)
 343            | ((r3 & 0x7f) << 20)
 344            | ((r2 & 0x7f) << 13)
 345            | ((p1 & 0x3f) << 6)
 346            | (qp & 0x3f);
 347 }
 348
 349 static inline uint64_t tcg_opc_b1(int qp, uint64_t opc, uint64_t imm)
 350 {
 351     return opc
 352            | ((imm & 0x100000) << 16) /* s */
 353            | ((imm & 0x0fffff) << 13) /* imm20b */
 354            | (qp & 0x3f);
 355 }
 356
 357 static inline uint64_t tcg_opc_b4(int qp, uint64_t opc, int b2)
 358 {
 359     return opc
 360            | ((b2 & 0x7) << 13)
 361            | (qp & 0x3f);
 362 }
 363
 364 static inline uint64_t tcg_opc_b5(int qp, uint64_t opc, int b1, int b2)
 365 {
 366     return opc
 367            | ((b2 & 0x7) << 13)
 368            | ((b1 & 0x7) << 6)
 369            | (qp & 0x3f);
 370 }
 371
 372
 373 static inline uint64_t tcg_opc_b9(int qp, uint64_t opc, uint64_t imm)
 374 {
 375     return opc
 376            | ((imm & 0x100000) << 16) /* i */
 377            | ((imm & 0x0fffff) << 6)  /* imm20a */
 378            | (qp & 0x3f);
 379 }
 380
 381 static inline uint64_t tcg_opc_f1(int qp, uint64_t opc, int f1,
 382                                   int f3, int f4, int f2)
 383 {
 384     return opc
 385            | ((f4 & 0x7f) << 27)
 386            | ((f3 & 0x7f) << 20)
 387            | ((f2 & 0x7f) << 13)
 388            | ((f1 & 0x7f) << 6)
 389            | (qp & 0x3f);
 390 }
 391
 392 static inline uint64_t tcg_opc_f2(int qp, uint64_t opc, int f1,
 393                                   int f3, int f4, int f2)
 394 {
 395     return opc
 396            | ((f4 & 0x7f) << 27)
 397            | ((f3 & 0x7f) << 20)
 398            | ((f2 & 0x7f) << 13)
 399            | ((f1 & 0x7f) << 6)
 400            | (qp & 0x3f);
 401 }
 402
 403 static inline uint64_t tcg_opc_f6(int qp, uint64_t opc, int f1,
 404                                   int p2, int f2, int f3)
 405 {
 406     return opc
 407            | ((p2 & 0x3f) << 27)
 408            | ((f3 & 0x7f) << 20)
 409            | ((f2 & 0x7f) << 13)
 410            | ((f1 & 0x7f) << 6)
 411            | (qp & 0x3f);
 412 }
 413
 414 static inline uint64_t tcg_opc_f10(int qp, uint64_t opc, int f1, int f2)
 415 {
 416     return opc
 417            | ((f2 & 0x7f) << 13)
 418            | ((f1 & 0x7f) << 6)
 419            | (qp & 0x3f);
 420 }
 421
 422 static inline uint64_t tcg_opc_f11(int qp, uint64_t opc, int f1, int f2)
 423 {
 424     return opc
 425            | ((f2 & 0x7f) << 13)
 426            | ((f1 & 0x7f) << 6)
 427            | (qp & 0x3f);
 428 }
 429
 430 static inline uint64_t tcg_opc_f16(int qp, uint64_t opc, uint64_t imm)
 431 {
 432     return opc
 433            | ((imm & 0x100000) << 16) /* i */
 434            | ((imm & 0x0fffff) << 6)  /* imm20a */
 435            | (qp & 0x3f);
 436 }
 437
 438 static inline uint64_t tcg_opc_i2(int qp, uint64_t opc, int r1,
 439                                   int r2, int r3)
 440 {
 441     return opc
 442            | ((r3 & 0x7f) << 20)
 443            | ((r2 & 0x7f) << 13)
 444            | ((r1 & 0x7f) << 6)
 445            | (qp & 0x3f);
 446 }
 447
 448 static inline uint64_t tcg_opc_i3(int qp, uint64_t opc, int r1,
 449                                   int r2, int mbtype)
 450 {
 451     return opc
 452            | ((mbtype & 0x0f) << 20)
 453            | ((r2 & 0x7f) << 13)
 454            | ((r1 & 0x7f) << 6)
 455            | (qp & 0x3f);
 456 }
 457
 458 static inline uint64_t tcg_opc_i5(int qp, uint64_t opc, int r1,
 459                                   int r3, int r2)
 460 {
 461     return opc
 462            | ((r3 & 0x7f) << 20)
 463            | ((r2 & 0x7f) << 13)
 464            | ((r1 & 0x7f) << 6)
 465            | (qp & 0x3f);
 466 }
 467
 468 static inline uint64_t tcg_opc_i7(int qp, uint64_t opc, int r1,
 469                                   int r2, int r3)
 470 {
 471     return opc
 472            | ((r3 & 0x7f) << 20)
 473            | ((r2 & 0x7f) << 13)
 474            | ((r1 & 0x7f) << 6)
 475            | (qp & 0x3f);
 476 }
 477
 478 static inline uint64_t tcg_opc_i10(int qp, uint64_t opc, int r1,
 479                                    int r2, int r3, uint64_t count)
 480 {
 481     return opc
 482            | ((count & 0x3f) << 27)
 483            | ((r3 & 0x7f) << 20)
 484            | ((r2 & 0x7f) << 13)
 485            | ((r1 & 0x7f) << 6)
 486            | (qp & 0x3f);
 487 }
 488
 489 static inline uint64_t tcg_opc_i11(int qp, uint64_t opc, int r1,
 490                                    int r3, uint64_t pos, uint64_t len)
 491 {
 492     return opc
 493            | ((len & 0x3f) << 27)
 494            | ((r3 & 0x7f) << 20)
 495            | ((pos & 0x3f) << 14)
 496            | ((r1 & 0x7f) << 6)
 497            | (qp & 0x3f);
 498 }
 499
 500 static inline uint64_t tcg_opc_i12(int qp, uint64_t opc, int r1,
 501                                    int r2, uint64_t pos, uint64_t len)
 502 {
 503     return opc
 504            | ((len & 0x3f) << 27)
 505            | ((pos & 0x3f) << 20)
 506            | ((r2 & 0x7f) << 13)
 507            | ((r1 & 0x7f) << 6)
 508            | (qp & 0x3f);
 509 }
 510
 511 static inline uint64_t tcg_opc_i18(int qp, uint64_t opc, uint64_t imm)
 512 {
 513     return opc
 514            | ((imm & 0x100000) << 16) /* i */
 515            | ((imm & 0x0fffff) << 6)  /* imm20a */
 516            | (qp & 0x3f);
 517 }
 518
 519 static inline uint64_t tcg_opc_i21(int qp, uint64_t opc, int b1,
 520                                    int r2, uint64_t imm)
 521 {
 522     return opc
 523            | ((imm & 0x1ff) << 24)
 524            | ((r2 & 0x7f) << 13)
 525            | ((b1 & 0x7) << 6)
 526            | (qp & 0x3f);
 527 }
 528
 529 static inline uint64_t tcg_opc_i22(int qp, uint64_t opc, int r1, int b2)
 530 {
 531     return opc
 532            | ((b2 & 0x7) << 13)
 533            | ((r1 & 0x7f) << 6)
 534            | (qp & 0x3f);
 535 }
 536
 537 static inline uint64_t tcg_opc_i26(int qp, uint64_t opc, int ar3, int r2)
 538 {
 539     return opc
 540            | ((ar3 & 0x7f) << 20)
 541            | ((r2 & 0x7f) << 13)
 542            | (qp & 0x3f);
 543 }
 544
 545 static inline uint64_t tcg_opc_i29(int qp, uint64_t opc, int r1, int r3)
 546 {
 547     return opc
 548            | ((r3 & 0x7f) << 20)
 549            | ((r1 & 0x7f) << 6)
 550            | (qp & 0x3f);
 551 }
 552
 553 static inline uint64_t tcg_opc_l2(uint64_t imm)
 554 {
 555     return (imm & 0x7fffffffffc00000ull) >> 22;
 556 }
 557
 558 static inline uint64_t tcg_opc_l3(uint64_t imm)
 559 {
 560     return (imm & 0x07fffffffff00000ull) >> 18;
 561 }
 562
 563 static inline uint64_t tcg_opc_m1(int qp, uint64_t opc, int r1, int r3)
 564 {
 565     return opc
 566            | ((r3 & 0x7f) << 20)
 567            | ((r1 & 0x7f) << 6)
 568            | (qp & 0x3f);
 569 }
 570
 571 static inline uint64_t tcg_opc_m3(int qp, uint64_t opc, int r1,
 572                                   int r3, uint64_t imm)
 573 {
 574     return opc
 575            | ((imm & 0x100) << 28) /* s */
 576            | ((imm & 0x080) << 20) /* i */
 577            | ((imm & 0x07f) << 13) /* imm7b */
 578            | ((r3 & 0x7f) << 20)
 579            | ((r1 & 0x7f) << 6)
 580            | (qp & 0x3f);
 581 }
 582
 583 static inline uint64_t tcg_opc_m4(int qp, uint64_t opc, int r2, int r3)
 584 {
 585     return opc
 586            | ((r3 & 0x7f) << 20)
 587            | ((r2 & 0x7f) << 13)
 588            | (qp & 0x3f);
 589 }
 590
 591 static inline uint64_t tcg_opc_m18(int qp, uint64_t opc, int f1, int r2)
 592 {
 593     return opc
 594            | ((r2 & 0x7f) << 13)
 595            | ((f1 & 0x7f) << 6)
 596            | (qp & 0x3f);
 597 }
 598
 599 static inline uint64_t tcg_opc_m19(int qp, uint64_t opc, int r1, int f2)
 600 {
 601     return opc
 602            | ((f2 & 0x7f) << 13)
 603            | ((r1 & 0x7f) << 6)
 604            | (qp & 0x3f);
 605 }
 606
 607 static inline uint64_t tcg_opc_m34(int qp, uint64_t opc, int r1,
 608                                    int sof, int sol, int sor)
 609 {
 610     return opc
 611            | ((sor & 0x0f) << 27)
 612            | ((sol & 0x7f) << 20)
 613            | ((sof & 0x7f) << 13)
 614            | ((r1 & 0x7f) << 6)
 615            | (qp & 0x3f);
 616 }
 617
 618 static inline uint64_t tcg_opc_m48(int qp, uint64_t opc, uint64_t imm)
 619 {
 620     return opc
 621            | ((imm & 0x100000) << 16) /* i */
 622            | ((imm & 0x0fffff) << 6)  /* imm20a */
 623            | (qp & 0x3f);
 624 }
 625
 626 static inline uint64_t tcg_opc_x2(int qp, uint64_t opc,
 627                                   int r1, uint64_t imm)
 628 {
 629     return opc
 630            | ((imm & 0x8000000000000000ull) >> 27) /* i */
 631            |  (imm & 0x0000000000200000ull)        /* ic */
 632            | ((imm & 0x00000000001f0000ull) << 6)  /* imm5c */
 633            | ((imm & 0x000000000000ff80ull) << 20) /* imm9d */
 634            | ((imm & 0x000000000000007full) << 13) /* imm7b */
 635            | ((r1 & 0x7f) << 6)
 636            | (qp & 0x3f);
 637 }
 638
 639 static inline uint64_t tcg_opc_x3(int qp, uint64_t opc, uint64_t imm)
 640 {
 641     return opc
 642            | ((imm & 0x0800000000000000ull) >> 23) /* i */
 643            | ((imm & 0x00000000000fffffull) << 13) /* imm20b */
 644            | (qp & 0x3f);
 645 }
 646
 647
 648 /*
 649  * Relocations
 650  */
 651
 652 static inline void reloc_pcrel21b (void *pc, tcg_target_long target)
 653 {
 654     uint64_t imm;
 655     int64_t disp;
 656     int slot;
 657
 658     slot = (tcg_target_long) pc & 3;
 659     pc = (void *)((tcg_target_long) pc & ~3);
 660
 661     disp = target - (tcg_target_long) pc;
 662     imm = (uint64_t) disp >> 4;
 663
 664     switch(slot) {
 665     case 0:
 666         *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 8) & 0xfffffdc00003ffffull)
 667                                 | ((imm & 0x100000) << 21)  /* s */
 668                                 | ((imm & 0x0fffff) << 18); /* imm20b */
 669         break;
 670     case 1:
 671         *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xfffffffffffb8000ull)
 672                                 | ((imm & 0x100000) >> 2)   /* s */
 673                                 | ((imm & 0x0fffe0) >> 5);  /* imm20b */
 674         *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x07ffffffffffffffull)
 675                                 | ((imm & 0x00001f) << 59); /* imm20b */
 676         break;
 677     case 2:
 678         *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fffffffffull)
 679                                 | ((imm & 0x100000) << 39)  /* s */
 680                                 | ((imm & 0x0fffff) << 36); /* imm20b */
 681         break;
 682     }
 683 }
 684
 685 static inline uint64_t get_reloc_pcrel21b (void *pc)
 686 {
 687     int64_t low, high;
 688     int slot;
 689
 690     slot = (tcg_target_long) pc & 3;
 691     pc = (void *)((tcg_target_long) pc & ~3);
 692
 693     low  = (*(uint64_t *)(pc + 0));
 694     high = (*(uint64_t *)(pc + 8));
 695
 696     switch(slot) {
 697     case 0:
 698         return ((low >> 21) & 0x100000) + /* s */
 699                ((low >> 18) & 0x0fffff);  /* imm20b */
 700     case 1:
 701         return ((high << 2) & 0x100000) + /* s */
 702                ((high << 5) & 0x0fffe0) + /* imm20b */
 703                ((low >> 59) & 0x00001f);  /* imm20b */
 704     case 2:
 705         return ((high >> 39) & 0x100000) + /* s */
 706                ((high >> 36) & 0x0fffff);  /* imm20b */
 707     default:
 708         tcg_abort();
 709     }
 710 }
 711
 712 static inline void reloc_pcrel60b (void *pc, tcg_target_long target)
 713 {
 714     int64_t disp;
 715     uint64_t imm;
 716
 717     disp = target - (tcg_target_long) pc;
 718     imm = (uint64_t) disp >> 4;
 719
 720     *(uint64_t *)(pc + 8) = (*(uint64_t *)(pc + 8) & 0xf700000fff800000ull)
 721                              |  (imm & 0x0800000000000000ull)         /* s */
 722                              | ((imm & 0x07fffff000000000ull) >> 36)  /* imm39 */
 723                              | ((imm & 0x00000000000fffffull) << 36); /* imm20b */
 724     *(uint64_t *)(pc + 0) = (*(uint64_t *)(pc + 0) & 0x00003fffffffffffull)
 725                              | ((imm & 0x0000000ffff00000ull) << 28); /* imm39 */
 726 }
 727
 728 static inline uint64_t get_reloc_pcrel60b (void *pc)
 729 {
 730     int64_t low, high;
 731
 732     low  = (*(uint64_t *)(pc + 0));
 733     high = (*(uint64_t *)(pc + 8));
 734
 735     return ((high)       & 0x0800000000000000ull) + /* s */
 736            ((high >> 36) & 0x00000000000fffffull) + /* imm20b */
 737            ((high << 36) & 0x07fffff000000000ull) + /* imm39 */
 738            ((low >> 28)  & 0x0000000ffff00000ull);  /* imm39 */
 739 }
 740
 741
 742 static void patch_reloc(uint8_t *code_ptr, int type,
 743                         tcg_target_long value, tcg_target_long addend)
 744 {
 745     value += addend;
 746     switch (type) {
 747     case R_IA64_PCREL21B:
 748         reloc_pcrel21b(code_ptr, value);
 749         break;
 750     case R_IA64_PCREL60B:
 751         reloc_pcrel60b(code_ptr, value);
 752     default:
 753         tcg_abort();
 754     }
 755 }
 756
 757 /*
 758  * Constraints
 759  */
 760
 761 /* parse target specific constraints */
 762 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
 763 {
 764     const char *ct_str;
 765
 766     ct_str = *pct_str;
 767     switch(ct_str[0]) {
 768     case 'r':
 769         ct->ct |= TCG_CT_REG;
 770         tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
 771         break;
 772     case 'I':
 773         ct->ct |= TCG_CT_CONST_S22;
 774         break;
 775     case 'S':
 776         ct->ct |= TCG_CT_REG;
 777         tcg_regset_set(ct->u.regs, 0xffffffffffffffffull);
 778 #if defined(CONFIG_SOFTMMU)
 779         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R56);
 780         tcg_regset_reset_reg(ct->u.regs, TCG_REG_R57);
 781 #endif
 782         break;
 783     case 'Z':
 784         /* We are cheating a bit here, using the fact that the register
 785            r0 is also the register number 0. Hence there is no need
 786            to check for const_args in each instruction. */
 787         ct->ct |= TCG_CT_CONST_ZERO;
 788         break;
 789     default:
 790         return -1;
 791     }
 792     ct_str++;
 793     *pct_str = ct_str;
 794     return 0;
 795 }
 796
 797 /* test if a constant matches the constraint */
 798 static inline int tcg_target_const_match(tcg_target_long val,
 799                                          const TCGArgConstraint *arg_ct)
 800 {
 801     int ct;
 802     ct = arg_ct->ct;
 803     if (ct & TCG_CT_CONST)
 804         return 1;
 805     else if ((ct & TCG_CT_CONST_ZERO) && val == 0)
 806         return 1;
 807     else if ((ct & TCG_CT_CONST_S22) && val == ((int32_t)val << 10) >> 10)
 808         return 1;
 809     else
 810         return 0;
 811 }
 812
 813 /*
 814  * Code generation
 815  */
 816
 817 static uint8_t *tb_ret_addr;
 818
 819 static inline void tcg_out_bundle(TCGContext *s, int template,
 820                                   uint64_t slot0, uint64_t slot1,
 821                                   uint64_t slot2)
 822 {
 823     template &= 0x1f;          /* 5 bits */
 824     slot0 &= 0x1ffffffffffull; /* 41 bits */
 825     slot1 &= 0x1ffffffffffull; /* 41 bits */
 826     slot2 &= 0x1ffffffffffull; /* 41 bits */
 827
 828     *(uint64_t *)(s->code_ptr + 0) = (slot1 << 46) | (slot0 << 5) | template;
 829     *(uint64_t *)(s->code_ptr + 8) = (slot2 << 23) | (slot1 >> 18);
 830     s->code_ptr += 16;
 831 }
 832
 833 static inline void tcg_out_mov(TCGContext *s, TCGType type,
 834                                TCGArg ret, TCGArg arg)
 835 {
 836     tcg_out_bundle(s, mmI,
 837                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 838                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 839                    tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, ret, 0, arg));
 840 }
 841
 842 static inline void tcg_out_movi(TCGContext *s, TCGType type,
 843                                 TCGArg reg, tcg_target_long arg)
 844 {
 845     tcg_out_bundle(s, mLX,
 846                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 847                    tcg_opc_l2 (arg),
 848                    tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2, reg, arg));
 849 }
 850
 851 static inline void tcg_out_addi(TCGContext *s, TCGArg reg, tcg_target_long val)
 852 {
 853     if (val == ((int32_t)val << 10) >> 10) {
 854         tcg_out_bundle(s, MmI,
 855                        tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
 856                                   TCG_REG_R2, val, TCG_REG_R0),
 857                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 858                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg,
 859                                    reg, TCG_REG_R2));
 860     } else {
 861         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, val);
 862         tcg_out_bundle(s, mmI,
 863                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 864                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 865                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, reg,
 866                                    reg, TCG_REG_R2));
 867     }
 868 }
 869
 870 static void tcg_out_br(TCGContext *s, int label_index)
 871 {
 872     TCGLabel *l = &s->labels[label_index];
 873
 874     /* We pay attention here to not modify the branch target by reading
 875        the existing value and using it again. This ensure that caches and
 876        memory are kept coherent during retranslation. */
 877     tcg_out_bundle(s, mmB,
 878                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 879                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 880                    tcg_opc_b1 (TCG_REG_P0, OPC_BR_SPTK_MANY_B1,
 881                                get_reloc_pcrel21b(s->code_ptr + 2)));
 882
 883     if (l->has_value) {
 884         reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
 885     } else {
 886         tcg_out_reloc(s, (s->code_ptr - 16) + 2,
 887                       R_IA64_PCREL21B, label_index, 0);
 888     }
 889 }
 890
 891 static inline void tcg_out_call(TCGContext *s, TCGArg addr)
 892 {
 893     tcg_out_bundle(s, MmI,
 894                    tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, addr),
 895                    tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R3, 8, addr),
 896                    tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
 897                                TCG_REG_B6, TCG_REG_R2, 0));
 898     tcg_out_bundle(s, mmB,
 899                    tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R3),
 900                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 901                    tcg_opc_b5 (TCG_REG_P0, OPC_BR_CALL_SPTK_MANY_B5,
 902                                TCG_REG_B0, TCG_REG_B6));
 903 }
 904
 905 static void tcg_out_exit_tb(TCGContext *s, tcg_target_long arg)
 906 {
 907     int64_t disp;
 908     uint64_t imm;
 909
 910     tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R8, arg);
 911
 912     disp = tb_ret_addr - s->code_ptr;
 913     imm = (uint64_t)disp >> 4;
 914
 915     tcg_out_bundle(s, mLX,
 916                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 917                    tcg_opc_l3 (imm),
 918                    tcg_opc_x3 (TCG_REG_P0, OPC_BRL_SPTK_MANY_X3, imm));
 919 }
 920
 921 static inline void tcg_out_goto_tb(TCGContext *s, TCGArg arg)
 922 {
 923     if (s->tb_jmp_offset) {
 924         /* direct jump method */
 925         tcg_abort();
 926     } else {
 927         /* indirect jump method */
 928         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2,
 929                      (tcg_target_long)(s->tb_next + arg));
 930         tcg_out_bundle(s, MmI,
 931                        tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1,
 932                                    TCG_REG_R2, TCG_REG_R2),
 933                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 934                        tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6,
 935                                    TCG_REG_R2, 0));
 936         tcg_out_bundle(s, mmB,
 937                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 938                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 939                        tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4,
 940                                    TCG_REG_B6));
 941     }
 942     s->tb_next_offset[arg] = s->code_ptr - s->code_buf;
 943 }
 944
 945 static inline void tcg_out_jmp(TCGContext *s, TCGArg addr)
 946 {
 947     tcg_out_bundle(s, mmI,
 948                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 949                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 950                    tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21, TCG_REG_B6, addr, 0));
 951     tcg_out_bundle(s, mmB,
 952                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 953                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
 954                    tcg_opc_b4(TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
 955 }
 956
 957 static inline void tcg_out_ld_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
 958                                   TCGArg arg1, tcg_target_long arg2)
 959 {
 960     if (arg2 == ((int16_t)arg2 >> 2) << 2) {
 961         tcg_out_bundle(s, MmI,
 962                        tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
 963                                   TCG_REG_R2, arg2, arg1),
 964                        tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
 965                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
 966     } else {
 967         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
 968         tcg_out_bundle(s, MmI,
 969                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
 970                                    TCG_REG_R2, TCG_REG_R2, arg1),
 971                        tcg_opc_m1 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
 972                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
 973     }
 974 }
 975
 976 static inline void tcg_out_st_rel(TCGContext *s, uint64_t opc_m4, TCGArg arg,
 977                                   TCGArg arg1, tcg_target_long arg2)
 978 {
 979     if (arg2 == ((int16_t)arg2 >> 2) << 2) {
 980         tcg_out_bundle(s, MmI,
 981                        tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4,
 982                                   TCG_REG_R2, arg2, arg1),
 983                        tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
 984                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
 985     } else {
 986         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg2);
 987         tcg_out_bundle(s, MmI,
 988                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1,
 989                                    TCG_REG_R2, TCG_REG_R2, arg1),
 990                        tcg_opc_m4 (TCG_REG_P0, opc_m4, arg, TCG_REG_R2),
 991                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
 992     }
 993 }
 994
 995 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGArg arg,
 996                               TCGArg arg1, tcg_target_long arg2)
 997 {
 998     if (type == TCG_TYPE_I32) {
 999         tcg_out_ld_rel(s, OPC_LD4_M1, arg, arg1, arg2);
1000     } else {
1001         tcg_out_ld_rel(s, OPC_LD8_M1, arg, arg1, arg2);
1002     }
1003 }
1004
1005 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGArg arg,
1006                               TCGArg arg1, tcg_target_long arg2)
1007 {
1008     if (type == TCG_TYPE_I32) {
1009         tcg_out_st_rel(s, OPC_ST4_M4, arg, arg1, arg2);
1010     } else {
1011         tcg_out_st_rel(s, OPC_ST8_M4, arg, arg1, arg2);
1012     }
1013 }
1014
1015 static inline void tcg_out_alu(TCGContext *s, uint64_t opc_a1, TCGArg ret,
1016                                TCGArg arg1, int const_arg1,
1017                                TCGArg arg2, int const_arg2)
1018 {
1019     uint64_t opc1, opc2;
1020
1021     if (const_arg1 && arg1 != 0) {
1022         opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1023                           TCG_REG_R2, arg1, TCG_REG_R0);
1024         arg1 = TCG_REG_R2;
1025     } else {
1026         opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1027     }
1028
1029     if (const_arg2 && arg2 != 0) {
1030         opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5,
1031                           TCG_REG_R3, arg2, TCG_REG_R0);
1032         arg2 = TCG_REG_R3;
1033     } else {
1034         opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1035     }
1036
1037     tcg_out_bundle(s, mII,
1038                    opc1,
1039                    opc2,
1040                    tcg_opc_a1(TCG_REG_P0, opc_a1, ret, arg1, arg2));
1041 }
1042
1043 static inline void tcg_out_eqv(TCGContext *s, TCGArg ret,
1044                                TCGArg arg1, int const_arg1,
1045                                TCGArg arg2, int const_arg2)
1046 {
1047     tcg_out_bundle(s, mII,
1048                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1049                    tcg_opc_a1 (TCG_REG_P0, OPC_XOR_A1, ret, arg1, arg2),
1050                    tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1051 }
1052
1053 static inline void tcg_out_nand(TCGContext *s, TCGArg ret,
1054                                 TCGArg arg1, int const_arg1,
1055                                 TCGArg arg2, int const_arg2)
1056 {
1057     tcg_out_bundle(s, mII,
1058                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1059                    tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, ret, arg1, arg2),
1060                    tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1061 }
1062
1063 static inline void tcg_out_nor(TCGContext *s, TCGArg ret,
1064                                TCGArg arg1, int const_arg1,
1065                                TCGArg arg2, int const_arg2)
1066 {
1067     tcg_out_bundle(s, mII,
1068                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1069                    tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, arg2),
1070                    tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, ret, -1, ret));
1071 }
1072
1073 static inline void tcg_out_orc(TCGContext *s, TCGArg ret,
1074                                TCGArg arg1, int const_arg1,
1075                                TCGArg arg2, int const_arg2)
1076 {
1077     tcg_out_bundle(s, mII,
1078                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1079                    tcg_opc_a3 (TCG_REG_P0, OPC_ANDCM_A3, TCG_REG_R2, -1, arg2),
1080                    tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret, arg1, TCG_REG_R2));
1081 }
1082
1083 static inline void tcg_out_mul(TCGContext *s, TCGArg ret,
1084                                TCGArg arg1, TCGArg arg2)
1085 {
1086     tcg_out_bundle(s, mmI,
1087                    tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F6, arg1),
1088                    tcg_opc_m18(TCG_REG_P0, OPC_SETF_SIG_M18, TCG_REG_F7, arg2),
1089                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1090     tcg_out_bundle(s, mmF,
1091                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1092                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1093                    tcg_opc_f2 (TCG_REG_P0, OPC_XMA_L_F2, TCG_REG_F6, TCG_REG_F6,
1094                                TCG_REG_F7, TCG_REG_F0));
1095     tcg_out_bundle(s, miI,
1096                    tcg_opc_m19(TCG_REG_P0, OPC_GETF_SIG_M19, ret, TCG_REG_F6),
1097                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1098                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1099 }
1100
1101 static inline void tcg_out_sar_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1102                                    TCGArg arg2, int const_arg2)
1103 {
1104     if (const_arg2) {
1105         tcg_out_bundle(s, miI,
1106                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1107                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1108                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1109                                    ret, arg1, arg2, 31 - arg2));
1110     } else {
1111         tcg_out_bundle(s, mII,
1112                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3,
1113                                    TCG_REG_R3, 0x1f, arg2),
1114                        tcg_opc_i29(TCG_REG_P0, OPC_SXT4_I29, TCG_REG_R2, arg1),
1115                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret,
1116                                    TCG_REG_R2, TCG_REG_R3));
1117     }
1118 }
1119
1120 static inline void tcg_out_sar_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1121                                    TCGArg arg2, int const_arg2)
1122 {
1123     if (const_arg2) {
1124         tcg_out_bundle(s, miI,
1125                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1126                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1127                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_I11,
1128                                    ret, arg1, arg2, 63 - arg2));
1129     } else {
1130         tcg_out_bundle(s, miI,
1131                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1132                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1133                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_I5, ret, arg1, arg2));
1134     }
1135 }
1136
1137 static inline void tcg_out_shl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1138                                    TCGArg arg2, int const_arg2)
1139 {
1140     if (const_arg2) {
1141         tcg_out_bundle(s, miI,
1142                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1143                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1144                        tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1145                                    arg1, 63 - arg2, 31 - arg2));
1146     } else {
1147         tcg_out_bundle(s, mII,
1148                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1149                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R2,
1150                                    0x1f, arg2),
1151                        tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1152                                    arg1, TCG_REG_R2));
1153     }
1154 }
1155
1156 static inline void tcg_out_shl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1157                                    TCGArg arg2, int const_arg2)
1158 {
1159     if (const_arg2) {
1160         tcg_out_bundle(s, miI,
1161                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1162                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1163                        tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret,
1164                                    arg1, 63 - arg2, 63 - arg2));
1165     } else {
1166         tcg_out_bundle(s, miI,
1167                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1168                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1169                        tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, ret,
1170                                    arg1, arg2));
1171     }
1172 }
1173
1174 static inline void tcg_out_shr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1175                                    TCGArg arg2, int const_arg2)
1176 {
1177     if (const_arg2) {
1178         tcg_out_bundle(s, miI,
1179                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1180                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1181                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1182                                    arg1, arg2, 31 - arg2));
1183     } else {
1184         tcg_out_bundle(s, mII,
1185                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1186                                    0x1f, arg2),
1187                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R2, arg1),
1188                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1189                                    TCG_REG_R2, TCG_REG_R3));
1190     }
1191 }
1192
1193 static inline void tcg_out_shr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1194                                    TCGArg arg2, int const_arg2)
1195 {
1196     if (const_arg2) {
1197         tcg_out_bundle(s, miI,
1198                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1199                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1200                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1201                                    arg1, arg2, 63 - arg2));
1202     } else {
1203         tcg_out_bundle(s, miI,
1204                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1205                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1206                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1207                                    arg1, arg2));
1208     }
1209 }
1210
1211 static inline void tcg_out_rotl_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1212                                     TCGArg arg2, int const_arg2)
1213 {
1214     if (const_arg2) {
1215         tcg_out_bundle(s, mII,
1216                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1217                        tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1218                                    TCG_REG_R2, arg1, arg1),
1219                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1220                                    TCG_REG_R2, 32 - arg2, 31));
1221     } else {
1222         tcg_out_bundle(s, miI,
1223                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1224                        tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1225                                    TCG_REG_R2, arg1, arg1),
1226                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1227                                    0x1f, arg2));
1228         tcg_out_bundle(s, mII,
1229                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1230                        tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R3,
1231                                    0x20, TCG_REG_R3),
1232                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1233                                    TCG_REG_R2, TCG_REG_R3));
1234     }
1235 }
1236
1237 static inline void tcg_out_rotl_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1238                                     TCGArg arg2, int const_arg2)
1239 {
1240     if (const_arg2) {
1241         tcg_out_bundle(s, miI,
1242                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1243                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1244                        tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1245                                    arg1, 0x40 - arg2));
1246     } else {
1247         tcg_out_bundle(s, mII,
1248                        tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1249                                    0x40, arg2),
1250                        tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R3,
1251                                    arg1, arg2),
1252                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R2,
1253                                    arg1, TCG_REG_R2));
1254         tcg_out_bundle(s, miI,
1255                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1256                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1257                        tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1258                                    TCG_REG_R2, TCG_REG_R3));
1259     }
1260 }
1261
1262 static inline void tcg_out_rotr_i32(TCGContext *s, TCGArg ret, TCGArg arg1,
1263                                     TCGArg arg2, int const_arg2)
1264 {
1265     if (const_arg2) {
1266         tcg_out_bundle(s, mII,
1267                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1268                        tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1269                                    TCG_REG_R2, arg1, arg1),
1270                        tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, ret,
1271                                    TCG_REG_R2, arg2, 31));
1272     } else {
1273         tcg_out_bundle(s, mII,
1274                        tcg_opc_a3 (TCG_REG_P0, OPC_AND_A3, TCG_REG_R3,
1275                                    0x1f, arg2),
1276                        tcg_opc_i2 (TCG_REG_P0, OPC_UNPACK4_L_I2,
1277                                    TCG_REG_R2, arg1, arg1),
1278                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, ret,
1279                                    TCG_REG_R2, TCG_REG_R3));
1280     }
1281 }
1282
1283 static inline void tcg_out_rotr_i64(TCGContext *s, TCGArg ret, TCGArg arg1,
1284                                     TCGArg arg2, int const_arg2)
1285 {
1286     if (const_arg2) {
1287         tcg_out_bundle(s, miI,
1288                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1289                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1290                        tcg_opc_i10(TCG_REG_P0, OPC_SHRP_I10, ret, arg1,
1291                                    arg1, arg2));
1292     } else {
1293         tcg_out_bundle(s, mII,
1294                        tcg_opc_a3 (TCG_REG_P0, OPC_SUB_A3, TCG_REG_R2,
1295                                    0x40, arg2),
1296                        tcg_opc_i5 (TCG_REG_P0, OPC_SHR_U_I5, TCG_REG_R3,
1297                                    arg1, arg2),
1298                        tcg_opc_i7 (TCG_REG_P0, OPC_SHL_I7, TCG_REG_R2,
1299                                    arg1, TCG_REG_R2));
1300         tcg_out_bundle(s, miI,
1301                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1302                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1303                        tcg_opc_a1 (TCG_REG_P0, OPC_OR_A1, ret,
1304                                    TCG_REG_R2, TCG_REG_R3));
1305     }
1306 }
1307
1308 static inline void tcg_out_ext(TCGContext *s, uint64_t opc_i29,
1309                                TCGArg ret, TCGArg arg)
1310 {
1311     tcg_out_bundle(s, miI,
1312                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1313                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1314                    tcg_opc_i29(TCG_REG_P0, opc_i29, ret, arg));
1315 }
1316
1317 static inline void tcg_out_bswap16(TCGContext *s, TCGArg ret, TCGArg arg)
1318 {
1319     tcg_out_bundle(s, mII,
1320                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1321                    tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 15, 15),
1322                    tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1323 }
1324
1325 static inline void tcg_out_bswap32(TCGContext *s, TCGArg ret, TCGArg arg)
1326 {
1327     tcg_out_bundle(s, mII,
1328                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1329                    tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, ret, arg, 31, 31),
1330                    tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, ret, 0xb));
1331 }
1332
1333 static inline void tcg_out_bswap64(TCGContext *s, TCGArg ret, TCGArg arg)
1334 {
1335     tcg_out_bundle(s, miI,
1336                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1337                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1338                    tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, ret, arg, 0xb));
1339 }
1340
1341 static inline uint64_t tcg_opc_cmp_a(int qp, TCGCond cond, TCGArg arg1,
1342                                      TCGArg arg2, int cmp4)
1343 {
1344     uint64_t opc_eq_a6, opc_lt_a6, opc_ltu_a6;
1345
1346     if (cmp4) {
1347         opc_eq_a6 = OPC_CMP4_EQ_A6;
1348         opc_lt_a6 = OPC_CMP4_LT_A6;
1349         opc_ltu_a6 = OPC_CMP4_LTU_A6;
1350     } else {
1351         opc_eq_a6 = OPC_CMP_EQ_A6;
1352         opc_lt_a6 = OPC_CMP_LT_A6;
1353         opc_ltu_a6 = OPC_CMP_LTU_A6;
1354     }
1355
1356     switch (cond) {
1357     case TCG_COND_EQ:
1358         return tcg_opc_a6 (qp, opc_eq_a6,  TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1359     case TCG_COND_NE:
1360         return tcg_opc_a6 (qp, opc_eq_a6,  TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1361     case TCG_COND_LT:
1362         return tcg_opc_a6 (qp, opc_lt_a6,  TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1363     case TCG_COND_LTU:
1364         return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg1, arg2);
1365     case TCG_COND_GE:
1366         return tcg_opc_a6 (qp, opc_lt_a6,  TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1367     case TCG_COND_GEU:
1368         return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg1, arg2);
1369     case TCG_COND_LE:
1370         return tcg_opc_a6 (qp, opc_lt_a6,  TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1371     case TCG_COND_LEU:
1372         return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P7, TCG_REG_P6, arg2, arg1);
1373     case TCG_COND_GT:
1374         return tcg_opc_a6 (qp, opc_lt_a6,  TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1375     case TCG_COND_GTU:
1376         return tcg_opc_a6 (qp, opc_ltu_a6, TCG_REG_P6, TCG_REG_P7, arg2, arg1);
1377     default:
1378         tcg_abort();
1379         break;
1380     }
1381 }
1382
1383 static inline void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGArg arg1,
1384                                   int const_arg1, TCGArg arg2, int const_arg2,
1385                                   int label_index, int cmp4)
1386 {
1387     TCGLabel *l = &s->labels[label_index];
1388     uint64_t opc1, opc2;
1389
1390     if (const_arg1 && arg1 != 0) {
1391         opc1 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1392                           arg1, TCG_REG_R0);
1393         arg1 = TCG_REG_R2;
1394     } else {
1395         opc1 = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1396     }
1397
1398     if (const_arg2 && arg2 != 0) {
1399         opc2 = tcg_opc_a5(TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1400                           arg2, TCG_REG_R0);
1401         arg2 = TCG_REG_R3;
1402     } else {
1403         opc2 = tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0);
1404     }
1405
1406     tcg_out_bundle(s, mII,
1407                    opc1,
1408                    opc2,
1409                    tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4));
1410     tcg_out_bundle(s, mmB,
1411                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1412                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1413                    tcg_opc_b1 (TCG_REG_P6, OPC_BR_DPTK_FEW_B1,
1414                                get_reloc_pcrel21b(s->code_ptr + 2)));
1415
1416     if (l->has_value) {
1417         reloc_pcrel21b((s->code_ptr - 16) + 2, l->u.value);
1418     } else {
1419         tcg_out_reloc(s, (s->code_ptr - 16) + 2,
1420                       R_IA64_PCREL21B, label_index, 0);
1421     }
1422 }
1423
1424 static inline void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGArg ret,
1425                                    TCGArg arg1, TCGArg arg2, int cmp4)
1426 {
1427     tcg_out_bundle(s, MmI,
1428                    tcg_opc_cmp_a(TCG_REG_P0, cond, arg1, arg2, cmp4),
1429                    tcg_opc_a5(TCG_REG_P6, OPC_ADDL_A5, ret, 1, TCG_REG_R0),
1430                    tcg_opc_a5(TCG_REG_P7, OPC_ADDL_A5, ret, 0, TCG_REG_R0));
1431 }
1432
1433 #if defined(CONFIG_SOFTMMU)
1434
1435 #include "../../softmmu_defs.h"
1436
1437 /* Load and compare a TLB entry, and return the result in (p6, p7).
1438    R2 is loaded with the address of the addend TLB entry.
1439    R56 is loaded with the address, zero extented on 32-bit targets. */
1440 static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
1441                                     int s_bits, uint64_t offset_rw,
1442                                     uint64_t offset_addend)
1443 {
1444     tcg_out_bundle(s, mII,
1445                    tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R3,
1446                                TARGET_PAGE_MASK | ((1 << s_bits) - 1),
1447                                TCG_REG_R0),
1448                    tcg_opc_i11(TCG_REG_P0, OPC_EXTR_U_I11, TCG_REG_R2,
1449                                addr_reg, TARGET_PAGE_BITS, CPU_TLB_BITS - 1),
1450                    tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, TCG_REG_R2,
1451                                TCG_REG_R2, 63 - CPU_TLB_ENTRY_BITS,
1452                                63 - CPU_TLB_ENTRY_BITS));
1453     tcg_out_bundle(s, mII,
1454                    tcg_opc_a5 (TCG_REG_P0, OPC_ADDL_A5, TCG_REG_R2,
1455                                offset_rw, TCG_REG_R2),
1456 #if TARGET_LONG_BITS == 32
1457                    tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29, TCG_REG_R56, addr_reg),
1458 #else
1459                    tcg_opc_a4(TCG_REG_P0, OPC_ADDS_A4, TCG_REG_R56,
1460                               0, addr_reg),
1461 #endif
1462                    tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1463                                TCG_REG_R2, TCG_AREG0));
1464     tcg_out_bundle(s, mII,
1465                    tcg_opc_m3 (TCG_REG_P0,
1466                                (TARGET_LONG_BITS == 32
1467                                 ? OPC_LD4_M3 : OPC_LD8_M3), TCG_REG_R57,
1468                                TCG_REG_R2, offset_addend - offset_rw),
1469                    tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3,
1470                                TCG_REG_R3, TCG_REG_R56),
1471                    tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
1472                                TCG_REG_P7, TCG_REG_R3, TCG_REG_R57));
1473 }
1474
1475 static void *qemu_ld_helpers[4] = {
1476     __ldb_mmu,
1477     __ldw_mmu,
1478     __ldl_mmu,
1479     __ldq_mmu,
1480 };
1481
1482 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1483 {
1484     int addr_reg, data_reg, mem_index, s_bits, bswap;
1485     uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 };
1486     uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0,
1487                                 OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 };
1488
1489     data_reg = *args++;
1490     addr_reg = *args++;
1491     mem_index = *args;
1492     s_bits = opc & 3;
1493
1494 #ifdef TARGET_WORDS_BIGENDIAN
1495     bswap = 1;
1496 #else
1497     bswap = 0;
1498 #endif
1499
1500     /* Read the TLB entry */
1501     tcg_out_qemu_tlb(s, addr_reg, s_bits,
1502                      offsetof(CPUState, tlb_table[mem_index][0].addr_read),
1503                      offsetof(CPUState, tlb_table[mem_index][0].addend));
1504
1505     /* P6 is the fast path, and P7 the slow path */
1506     tcg_out_bundle(s, mLX,
1507                    tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R57,
1508                                mem_index, TCG_REG_R0),
1509                    tcg_opc_l2 ((tcg_target_long) qemu_ld_helpers[s_bits]),
1510                    tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1511                                (tcg_target_long) qemu_ld_helpers[s_bits]));
1512     tcg_out_bundle(s, MmI,
1513                    tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1514                                TCG_REG_R2, 8),
1515                    tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1516                                TCG_REG_R3, TCG_REG_R56),
1517                    tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1518                                TCG_REG_R3, 0));
1519     if (bswap && s_bits == 1) {
1520         tcg_out_bundle(s, MmI,
1521                        tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1522                                    TCG_REG_R8, TCG_REG_R3),
1523                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1524                        tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1525                                    TCG_REG_R8, TCG_REG_R8, 15, 15));
1526     } else if (bswap && s_bits == 2) {
1527         tcg_out_bundle(s, MmI,
1528                        tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1529                                    TCG_REG_R8, TCG_REG_R3),
1530                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1531                        tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1532                                    TCG_REG_R8, TCG_REG_R8, 31, 31));
1533     } else {
1534         tcg_out_bundle(s, mmI,
1535                        tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
1536                                    TCG_REG_R8, TCG_REG_R3),
1537                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
1538                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1539     }
1540     if (!bswap || s_bits == 0) {
1541         tcg_out_bundle(s, miB,
1542                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1543                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1544                        tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1545                                    TCG_REG_B0, TCG_REG_B6));
1546     } else {
1547         tcg_out_bundle(s, miB,
1548                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1549                        tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1550                                    TCG_REG_R8, TCG_REG_R8, 0xb),
1551                        tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1552                                    TCG_REG_B0, TCG_REG_B6));
1553     }
1554
1555     if (opc == 3) {
1556         tcg_out_bundle(s, miI,
1557                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1558                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1559                        tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
1560                                    data_reg, 0, TCG_REG_R8));
1561     } else {
1562         tcg_out_bundle(s, miI,
1563                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1564                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1565                        tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc],
1566                                    data_reg, TCG_REG_R8));
1567     }
1568 }
1569
1570 static void *qemu_st_helpers[4] = {
1571     __stb_mmu,
1572     __stw_mmu,
1573     __stl_mmu,
1574     __stq_mmu,
1575 };
1576
1577 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1578 {
1579     int addr_reg, data_reg, mem_index, bswap;
1580     uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 };
1581
1582     data_reg = *args++;
1583     addr_reg = *args++;
1584     mem_index = *args;
1585
1586 #ifdef TARGET_WORDS_BIGENDIAN
1587     bswap = 1;
1588 #else
1589     bswap = 0;
1590 #endif
1591
1592     tcg_out_qemu_tlb(s, addr_reg, opc,
1593                      offsetof(CPUState, tlb_table[mem_index][0].addr_write),
1594                      offsetof(CPUState, tlb_table[mem_index][0].addend));
1595
1596     /* P6 is the fast path, and P7 the slow path */
1597     tcg_out_bundle(s, mLX,
1598                    tcg_opc_a4(TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R57,
1599                               0, data_reg),
1600                    tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]),
1601                    tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
1602                                (tcg_target_long) qemu_st_helpers[opc]));
1603     tcg_out_bundle(s, MmI,
1604                    tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
1605                                TCG_REG_R2, 8),
1606                    tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
1607                                TCG_REG_R3, TCG_REG_R56),
1608                    tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
1609                                TCG_REG_R3, 0));
1610
1611     if (!bswap || opc == 0) {
1612         tcg_out_bundle(s, mII,
1613                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1614                                    TCG_REG_R1, TCG_REG_R2),
1615                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1616                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1617     } else if (opc == 1) {
1618         tcg_out_bundle(s, mII,
1619                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1620                                    TCG_REG_R1, TCG_REG_R2),
1621                        tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1622                                    TCG_REG_R2, data_reg, 15, 15),
1623                        tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1624                                    TCG_REG_R2, TCG_REG_R2, 0xb));
1625         data_reg = TCG_REG_R2;
1626     } else if (opc == 2) {
1627         tcg_out_bundle(s, mII,
1628                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1629                                    TCG_REG_R1, TCG_REG_R2),
1630                        tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
1631                                    TCG_REG_R2, data_reg, 31, 31),
1632                        tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1633                                    TCG_REG_R2, TCG_REG_R2, 0xb));
1634         data_reg = TCG_REG_R2;
1635     } else if (opc == 3) {
1636         tcg_out_bundle(s, miI,
1637                        tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1,
1638                                    TCG_REG_R1, TCG_REG_R2),
1639                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1640                        tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3,
1641                                    TCG_REG_R2, data_reg, 0xb));
1642         data_reg = TCG_REG_R2;
1643     }
1644
1645     tcg_out_bundle(s, miB,
1646                    tcg_opc_m4 (TCG_REG_P6, opc_st_m4[opc],
1647                                data_reg, TCG_REG_R3),
1648                    tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58,
1649                                mem_index, TCG_REG_R0),
1650                    tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
1651                                TCG_REG_B0, TCG_REG_B6));
1652 }
1653
1654 #else /* !CONFIG_SOFTMMU */
1655
1656 static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
1657 {
1658     static uint64_t const opc_ld_m1[4] = {
1659         OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
1660     };
1661     static uint64_t const opc_sxt_i29[4] = {
1662         OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0
1663     };
1664     int addr_reg, data_reg, s_bits, bswap;
1665
1666     data_reg = *args++;
1667     addr_reg = *args++;
1668     s_bits = opc & 3;
1669
1670 #ifdef TARGET_WORDS_BIGENDIAN
1671     bswap = 1;
1672 #else
1673     bswap = 0;
1674 #endif
1675
1676 #if TARGET_LONG_BITS == 32
1677     if (GUEST_BASE != 0) {
1678         tcg_out_bundle(s, mII,
1679                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1680                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1681                                    TCG_REG_R3, addr_reg),
1682                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1683                                    TCG_GUEST_BASE_REG, TCG_REG_R3));
1684     } else {
1685         tcg_out_bundle(s, miI,
1686                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1687                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1688                                    TCG_REG_R2, addr_reg),
1689                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1690     }
1691
1692     if (!bswap || s_bits == 0) {
1693         if (s_bits == opc) {
1694             tcg_out_bundle(s, miI,
1695                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1696                                        data_reg, TCG_REG_R2),
1697                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1698                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1699         } else {
1700             tcg_out_bundle(s, mII,
1701                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1702                                        data_reg, TCG_REG_R2),
1703                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1704                            tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1705                                        data_reg, data_reg));
1706         }
1707     } else if (s_bits == 3) {
1708             tcg_out_bundle(s, mII,
1709                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1710                                        data_reg, TCG_REG_R2),
1711                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1712                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1713                                        data_reg, data_reg, 0xb));
1714     } else {
1715         if (s_bits == 1) {
1716             tcg_out_bundle(s, mII,
1717                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1718                                        data_reg, TCG_REG_R2),
1719                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1720                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1721                                       data_reg, data_reg, 15, 15));
1722         } else {
1723             tcg_out_bundle(s, mII,
1724                            tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1725                                        data_reg, TCG_REG_R2),
1726                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1727                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1728                                       data_reg, data_reg, 31, 31));
1729         }
1730         if (opc == s_bits) {
1731             tcg_out_bundle(s, miI,
1732                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1733                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1734                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1735                                        data_reg, data_reg, 0xb));
1736         } else {
1737             tcg_out_bundle(s, mII,
1738                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1739                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1740                                        data_reg, data_reg, 0xb),
1741                            tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1742                                        data_reg, data_reg));
1743         }
1744     }
1745 #else
1746     if (GUEST_BASE != 0) {
1747         tcg_out_bundle(s, MmI,
1748                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1749                                    TCG_GUEST_BASE_REG, addr_reg),
1750                        tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1751                                    data_reg, TCG_REG_R2),
1752                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1753     } else {
1754         tcg_out_bundle(s, mmI,
1755                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1756                        tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits],
1757                                    data_reg, addr_reg),
1758                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1759     }
1760
1761     if (bswap && s_bits == 1) {
1762         tcg_out_bundle(s, mII,
1763                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1764                        tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1765                                    data_reg, data_reg, 15, 15),
1766                        tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1767                                    data_reg, data_reg, 0xb));
1768     } else if (bswap && s_bits == 2) {
1769         tcg_out_bundle(s, mII,
1770                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1771                        tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1772                                    data_reg, data_reg, 31, 31),
1773                        tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1774                                    data_reg, data_reg, 0xb));
1775     } else if (bswap && s_bits == 3) {
1776         tcg_out_bundle(s, miI,
1777                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1778                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1779                        tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1780                                    data_reg, data_reg, 0xb));
1781     }
1782     if (s_bits != opc) {
1783         tcg_out_bundle(s, miI,
1784                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1785                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1786                        tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits],
1787                                    data_reg, data_reg));
1788     }
1789 #endif
1790 }
1791
1792 static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
1793 {
1794     static uint64_t const opc_st_m4[4] = {
1795         OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4
1796     };
1797     int addr_reg, data_reg, bswap;
1798 #if TARGET_LONG_BITS == 64
1799     uint64_t add_guest_base;
1800 #endif
1801
1802     data_reg = *args++;
1803     addr_reg = *args++;
1804
1805 #ifdef TARGET_WORDS_BIGENDIAN
1806     bswap = 1;
1807 #else
1808     bswap = 0;
1809 #endif
1810
1811 #if TARGET_LONG_BITS == 32
1812     if (GUEST_BASE != 0) {
1813         tcg_out_bundle(s, mII,
1814                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1815                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1816                                    TCG_REG_R3, addr_reg),
1817                        tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1818                                    TCG_GUEST_BASE_REG, TCG_REG_R3));
1819     } else {
1820         tcg_out_bundle(s, miI,
1821                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1822                        tcg_opc_i29(TCG_REG_P0, OPC_ZXT4_I29,
1823                                    TCG_REG_R2, addr_reg),
1824                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1825     }
1826
1827     if (bswap) {
1828         if (opc == 1) {
1829             tcg_out_bundle(s, mII,
1830                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1831                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1832                                        TCG_REG_R3, data_reg, 15, 15),
1833                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1834                                        TCG_REG_R3, TCG_REG_R3, 0xb));
1835             data_reg = TCG_REG_R3;
1836         } else if (opc == 2) {
1837             tcg_out_bundle(s, mII,
1838                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1839                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1840                                        TCG_REG_R3, data_reg, 31, 31),
1841                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1842                                        TCG_REG_R3, TCG_REG_R3, 0xb));
1843             data_reg = TCG_REG_R3;
1844         } else if (opc == 3) {
1845             tcg_out_bundle(s, miI,
1846                            tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1847                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1848                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1849                                        TCG_REG_R3, data_reg, 0xb));
1850             data_reg = TCG_REG_R3;
1851         }
1852     }
1853     tcg_out_bundle(s, mmI,
1854                    tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1855                                data_reg, TCG_REG_R2),
1856                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
1857                    tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1858 #else
1859     if (GUEST_BASE != 0) {
1860         add_guest_base = tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
1861                                      TCG_GUEST_BASE_REG, addr_reg);
1862         addr_reg = TCG_REG_R2;
1863     } else {
1864         add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0);
1865     }
1866
1867     if (!bswap || opc == 0) {
1868         tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI),
1869                        add_guest_base,
1870                        tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1871                                    data_reg, addr_reg),
1872                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1873     } else {
1874         if (opc == 1) {
1875             tcg_out_bundle(s, mII,
1876                            add_guest_base,
1877                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1878                                        TCG_REG_R3, data_reg, 15, 15),
1879                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1880                                        TCG_REG_R3, TCG_REG_R3, 0xb));
1881             data_reg = TCG_REG_R3;
1882         } else if (opc == 2) {
1883             tcg_out_bundle(s, mII,
1884                            add_guest_base,
1885                            tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12,
1886                                        TCG_REG_R3, data_reg, 31, 31),
1887                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1888                                        TCG_REG_R3, TCG_REG_R3, 0xb));
1889             data_reg = TCG_REG_R3;
1890         } else if (opc == 3) {
1891             tcg_out_bundle(s, miI,
1892                            add_guest_base,
1893                            tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1894                            tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3,
1895                                        TCG_REG_R3, data_reg, 0xb));
1896             data_reg = TCG_REG_R3;
1897         }
1898         tcg_out_bundle(s, miI,
1899                        tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc],
1900                                    data_reg, addr_reg),
1901                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0),
1902                        tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0));
1903     }
1904 #endif
1905 }
1906
1907 #endif
1908
1909 static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
1910                               const TCGArg *args, const int *const_args)
1911 {
1912     switch(opc) {
1913     case INDEX_op_exit_tb:
1914         tcg_out_exit_tb(s, args[0]);
1915         break;
1916     case INDEX_op_br:
1917         tcg_out_br(s, args[0]);
1918         break;
1919     case INDEX_op_call:
1920         tcg_out_call(s, args[0]);
1921         break;
1922     case INDEX_op_goto_tb:
1923         tcg_out_goto_tb(s, args[0]);
1924         break;
1925     case INDEX_op_jmp:
1926         tcg_out_jmp(s, args[0]);
1927         break;
1928
1929     case INDEX_op_movi_i32:
1930         tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]);
1931         break;
1932     case INDEX_op_movi_i64:
1933         tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
1934         break;
1935
1936     case INDEX_op_ld8u_i32:
1937     case INDEX_op_ld8u_i64:
1938         tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1939         break;
1940     case INDEX_op_ld8s_i32:
1941     case INDEX_op_ld8s_i64:
1942         tcg_out_ld_rel(s, OPC_LD1_M1, args[0], args[1], args[2]);
1943         tcg_out_ext(s, OPC_SXT1_I29, args[0], args[0]);
1944         break;
1945     case INDEX_op_ld16u_i32:
1946     case INDEX_op_ld16u_i64:
1947         tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1948         break;
1949     case INDEX_op_ld16s_i32:
1950     case INDEX_op_ld16s_i64:
1951         tcg_out_ld_rel(s, OPC_LD2_M1, args[0], args[1], args[2]);
1952         tcg_out_ext(s, OPC_SXT2_I29, args[0], args[0]);
1953         break;
1954     case INDEX_op_ld_i32:
1955     case INDEX_op_ld32u_i64:
1956         tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1957         break;
1958     case INDEX_op_ld32s_i64:
1959         tcg_out_ld_rel(s, OPC_LD4_M1, args[0], args[1], args[2]);
1960         tcg_out_ext(s, OPC_SXT4_I29, args[0], args[0]);
1961         break;
1962     case INDEX_op_ld_i64:
1963         tcg_out_ld_rel(s, OPC_LD8_M1, args[0], args[1], args[2]);
1964         break;
1965     case INDEX_op_st8_i32:
1966     case INDEX_op_st8_i64:
1967         tcg_out_st_rel(s, OPC_ST1_M4, args[0], args[1], args[2]);
1968         break;
1969     case INDEX_op_st16_i32:
1970     case INDEX_op_st16_i64:
1971         tcg_out_st_rel(s, OPC_ST2_M4, args[0], args[1], args[2]);
1972         break;
1973     case INDEX_op_st_i32:
1974     case INDEX_op_st32_i64:
1975         tcg_out_st_rel(s, OPC_ST4_M4, args[0], args[1], args[2]);
1976         break;
1977     case INDEX_op_st_i64:
1978         tcg_out_st_rel(s, OPC_ST8_M4, args[0], args[1], args[2]);
1979         break;
1980
1981     case INDEX_op_add_i32:
1982     case INDEX_op_add_i64:
1983         tcg_out_alu(s, OPC_ADD_A1, args[0], args[1], const_args[1],
1984                     args[2], const_args[2]);
1985         break;
1986     case INDEX_op_sub_i32:
1987     case INDEX_op_sub_i64:
1988         tcg_out_alu(s, OPC_SUB_A1, args[0], args[1], const_args[1],
1989                     args[2], const_args[2]);
1990         break;
1991
1992     case INDEX_op_and_i32:
1993     case INDEX_op_and_i64:
1994         tcg_out_alu(s, OPC_AND_A1, args[0], args[1], const_args[1],
1995                     args[2], const_args[2]);
1996         break;
1997     case INDEX_op_andc_i32:
1998     case INDEX_op_andc_i64:
1999         tcg_out_alu(s, OPC_ANDCM_A1, args[0], args[1], const_args[1],
2000                     args[2], const_args[2]);
2001         break;
2002     case INDEX_op_eqv_i32:
2003     case INDEX_op_eqv_i64:
2004         tcg_out_eqv(s, args[0], args[1], const_args[1],
2005                     args[2], const_args[2]);
2006         break;
2007     case INDEX_op_nand_i32:
2008     case INDEX_op_nand_i64:
2009         tcg_out_nand(s, args[0], args[1], const_args[1],
2010                      args[2], const_args[2]);
2011         break;
2012     case INDEX_op_nor_i32:
2013     case INDEX_op_nor_i64:
2014         tcg_out_nor(s, args[0], args[1], const_args[1],
2015                     args[2], const_args[2]);
2016         break;
2017     case INDEX_op_or_i32:
2018     case INDEX_op_or_i64:
2019         tcg_out_alu(s, OPC_OR_A1, args[0], args[1], const_args[1],
2020                     args[2], const_args[2]);
2021         break;
2022     case INDEX_op_orc_i32:
2023     case INDEX_op_orc_i64:
2024         tcg_out_orc(s, args[0], args[1], const_args[1],
2025                     args[2], const_args[2]);
2026         break;
2027     case INDEX_op_xor_i32:
2028     case INDEX_op_xor_i64:
2029         tcg_out_alu(s, OPC_XOR_A1, args[0], args[1], const_args[1],
2030                     args[2], const_args[2]);
2031         break;
2032
2033     case INDEX_op_mul_i32:
2034     case INDEX_op_mul_i64:
2035         tcg_out_mul(s, args[0], args[1], args[2]);
2036         break;
2037
2038     case INDEX_op_sar_i32:
2039         tcg_out_sar_i32(s, args[0], args[1], args[2], const_args[2]);
2040         break;
2041     case INDEX_op_sar_i64:
2042         tcg_out_sar_i64(s, args[0], args[1], args[2], const_args[2]);
2043         break;
2044     case INDEX_op_shl_i32:
2045         tcg_out_shl_i32(s, args[0], args[1], args[2], const_args[2]);
2046         break;
2047     case INDEX_op_shl_i64:
2048         tcg_out_shl_i64(s, args[0], args[1], args[2], const_args[2]);
2049         break;
2050     case INDEX_op_shr_i32:
2051         tcg_out_shr_i32(s, args[0], args[1], args[2], const_args[2]);
2052         break;
2053     case INDEX_op_shr_i64:
2054         tcg_out_shr_i64(s, args[0], args[1], args[2], const_args[2]);
2055         break;
2056     case INDEX_op_rotl_i32:
2057         tcg_out_rotl_i32(s, args[0], args[1], args[2], const_args[2]);
2058         break;
2059     case INDEX_op_rotl_i64:
2060         tcg_out_rotl_i64(s, args[0], args[1], args[2], const_args[2]);
2061         break;
2062     case INDEX_op_rotr_i32:
2063         tcg_out_rotr_i32(s, args[0], args[1], args[2], const_args[2]);
2064         break;
2065     case INDEX_op_rotr_i64:
2066         tcg_out_rotr_i64(s, args[0], args[1], args[2], const_args[2]);
2067         break;
2068
2069     case INDEX_op_ext8s_i32:
2070     case INDEX_op_ext8s_i64:
2071         tcg_out_ext(s, OPC_SXT1_I29, args[0], args[1]);
2072         break;
2073     case INDEX_op_ext8u_i32:
2074     case INDEX_op_ext8u_i64:
2075         tcg_out_ext(s, OPC_ZXT1_I29, args[0], args[1]);
2076         break;
2077     case INDEX_op_ext16s_i32:
2078     case INDEX_op_ext16s_i64:
2079         tcg_out_ext(s, OPC_SXT2_I29, args[0], args[1]);
2080         break;
2081     case INDEX_op_ext16u_i32:
2082     case INDEX_op_ext16u_i64:
2083         tcg_out_ext(s, OPC_ZXT2_I29, args[0], args[1]);
2084         break;
2085     case INDEX_op_ext32s_i64:
2086         tcg_out_ext(s, OPC_SXT4_I29, args[0], args[1]);
2087         break;
2088     case INDEX_op_ext32u_i64:
2089         tcg_out_ext(s, OPC_ZXT4_I29, args[0], args[1]);
2090         break;
2091
2092     case INDEX_op_bswap16_i32:
2093     case INDEX_op_bswap16_i64:
2094         tcg_out_bswap16(s, args[0], args[1]);
2095         break;
2096     case INDEX_op_bswap32_i32:
2097     case INDEX_op_bswap32_i64:
2098         tcg_out_bswap32(s, args[0], args[1]);
2099         break;
2100     case INDEX_op_bswap64_i64:
2101         tcg_out_bswap64(s, args[0], args[1]);
2102         break;
2103
2104     case INDEX_op_brcond_i32:
2105         tcg_out_brcond(s, args[2], args[0], const_args[0],
2106                        args[1], const_args[1], args[3], 1);
2107         break;
2108     case INDEX_op_brcond_i64:
2109         tcg_out_brcond(s, args[2], args[0], const_args[0],
2110                        args[1], const_args[1], args[3], 0);
2111         break;
2112     case INDEX_op_setcond_i32:
2113         tcg_out_setcond(s, args[3], args[0], args[1], args[2], 1);
2114         break;
2115     case INDEX_op_setcond_i64:
2116         tcg_out_setcond(s, args[3], args[0], args[1], args[2], 0);
2117         break;
2118
2119     case INDEX_op_qemu_ld8u:
2120         tcg_out_qemu_ld(s, args, 0);
2121         break;
2122     case INDEX_op_qemu_ld8s:
2123         tcg_out_qemu_ld(s, args, 0 | 4);
2124         break;
2125     case INDEX_op_qemu_ld16u:
2126         tcg_out_qemu_ld(s, args, 1);
2127         break;
2128     case INDEX_op_qemu_ld16s:
2129         tcg_out_qemu_ld(s, args, 1 | 4);
2130         break;
2131     case INDEX_op_qemu_ld32:
2132     case INDEX_op_qemu_ld32u:
2133         tcg_out_qemu_ld(s, args, 2);
2134         break;
2135     case INDEX_op_qemu_ld32s:
2136         tcg_out_qemu_ld(s, args, 2 | 4);
2137         break;
2138     case INDEX_op_qemu_ld64:
2139         tcg_out_qemu_ld(s, args, 3);
2140         break;
2141
2142     case INDEX_op_qemu_st8:
2143         tcg_out_qemu_st(s, args, 0);
2144         break;
2145     case INDEX_op_qemu_st16:
2146         tcg_out_qemu_st(s, args, 1);
2147         break;
2148     case INDEX_op_qemu_st32:
2149         tcg_out_qemu_st(s, args, 2);
2150         break;
2151     case INDEX_op_qemu_st64:
2152         tcg_out_qemu_st(s, args, 3);
2153         break;
2154
2155     default:
2156         tcg_abort();
2157     }
2158 }
2159
2160 static const TCGTargetOpDef ia64_op_defs[] = {
2161     { INDEX_op_br, { } },
2162     { INDEX_op_call, { "r" } },
2163     { INDEX_op_exit_tb, { } },
2164     { INDEX_op_goto_tb, { } },
2165     { INDEX_op_jmp, { "r" } },
2166
2167     { INDEX_op_mov_i32, { "r", "r" } },
2168     { INDEX_op_movi_i32, { "r" } },
2169
2170     { INDEX_op_ld8u_i32, { "r", "r" } },
2171     { INDEX_op_ld8s_i32, { "r", "r" } },
2172     { INDEX_op_ld16u_i32, { "r", "r" } },
2173     { INDEX_op_ld16s_i32, { "r", "r" } },
2174     { INDEX_op_ld_i32, { "r", "r" } },
2175     { INDEX_op_st8_i32, { "rZ", "r" } },
2176     { INDEX_op_st16_i32, { "rZ", "r" } },
2177     { INDEX_op_st_i32, { "rZ", "r" } },
2178
2179     { INDEX_op_add_i32, { "r", "rI", "rI" } },
2180     { INDEX_op_sub_i32, { "r", "rI", "rI" } },
2181
2182     { INDEX_op_and_i32, { "r", "rI", "rI" } },
2183     { INDEX_op_andc_i32, { "r", "rI", "rI" } },
2184     { INDEX_op_eqv_i32, { "r", "rZ", "rZ" } },
2185     { INDEX_op_nand_i32, { "r", "rZ", "rZ" } },
2186     { INDEX_op_nor_i32, { "r", "rZ", "rZ" } },
2187     { INDEX_op_or_i32, { "r", "rI", "rI" } },
2188     { INDEX_op_orc_i32, { "r", "rZ", "rZ" } },
2189     { INDEX_op_xor_i32, { "r", "rI", "rI" } },
2190
2191     { INDEX_op_mul_i32, { "r", "rZ", "rZ" } },
2192
2193     { INDEX_op_sar_i32, { "r", "rZ", "ri" } },
2194     { INDEX_op_shl_i32, { "r", "rZ", "ri" } },
2195     { INDEX_op_shr_i32, { "r", "rZ", "ri" } },
2196     { INDEX_op_rotl_i32, { "r", "rZ", "ri" } },
2197     { INDEX_op_rotr_i32, { "r", "rZ", "ri" } },
2198
2199     { INDEX_op_ext8s_i32, { "r", "rZ"} },
2200     { INDEX_op_ext8u_i32, { "r", "rZ"} },
2201     { INDEX_op_ext16s_i32, { "r", "rZ"} },
2202     { INDEX_op_ext16u_i32, { "r", "rZ"} },
2203
2204     { INDEX_op_bswap16_i32, { "r", "rZ" } },
2205     { INDEX_op_bswap32_i32, { "r", "rZ" } },
2206
2207     { INDEX_op_brcond_i32, { "rI", "rI" } },
2208     { INDEX_op_setcond_i32, { "r", "rZ", "rZ" } },
2209
2210     { INDEX_op_mov_i64, { "r", "r" } },
2211     { INDEX_op_movi_i64, { "r" } },
2212
2213     { INDEX_op_ld8u_i64, { "r", "r" } },
2214     { INDEX_op_ld8s_i64, { "r", "r" } },
2215     { INDEX_op_ld16u_i64, { "r", "r" } },
2216     { INDEX_op_ld16s_i64, { "r", "r" } },
2217     { INDEX_op_ld32u_i64, { "r", "r" } },
2218     { INDEX_op_ld32s_i64, { "r", "r" } },
2219     { INDEX_op_ld_i64, { "r", "r" } },
2220     { INDEX_op_st8_i64, { "rZ", "r" } },
2221     { INDEX_op_st16_i64, { "rZ", "r" } },
2222     { INDEX_op_st32_i64, { "rZ", "r" } },
2223     { INDEX_op_st_i64, { "rZ", "r" } },
2224
2225     { INDEX_op_add_i64, { "r", "rI", "rI" } },
2226     { INDEX_op_sub_i64, { "r", "rI", "rI" } },
2227
2228     { INDEX_op_and_i64, { "r", "rI", "rI" } },
2229     { INDEX_op_andc_i64, { "r", "rI", "rI" } },
2230     { INDEX_op_eqv_i64, { "r", "rZ", "rZ" } },
2231     { INDEX_op_nand_i64, { "r", "rZ", "rZ" } },
2232     { INDEX_op_nor_i64, { "r", "rZ", "rZ" } },
2233     { INDEX_op_or_i64, { "r", "rI", "rI" } },
2234     { INDEX_op_orc_i64, { "r", "rZ", "rZ" } },
2235     { INDEX_op_xor_i64, { "r", "rI", "rI" } },
2236
2237     { INDEX_op_mul_i64, { "r", "rZ", "rZ" } },
2238
2239     { INDEX_op_sar_i64, { "r", "rZ", "ri" } },
2240     { INDEX_op_shl_i64, { "r", "rZ", "ri" } },
2241     { INDEX_op_shr_i64, { "r", "rZ", "ri" } },
2242     { INDEX_op_rotl_i64, { "r", "rZ", "ri" } },
2243     { INDEX_op_rotr_i64, { "r", "rZ", "ri" } },
2244
2245     { INDEX_op_ext8s_i64, { "r", "rZ"} },
2246     { INDEX_op_ext8u_i64, { "r", "rZ"} },
2247     { INDEX_op_ext16s_i64, { "r", "rZ"} },
2248     { INDEX_op_ext16u_i64, { "r", "rZ"} },
2249     { INDEX_op_ext32s_i64, { "r", "rZ"} },
2250     { INDEX_op_ext32u_i64, { "r", "rZ"} },
2251
2252     { INDEX_op_bswap16_i64, { "r", "rZ" } },
2253     { INDEX_op_bswap32_i64, { "r", "rZ" } },
2254     { INDEX_op_bswap64_i64, { "r", "rZ" } },
2255
2256     { INDEX_op_brcond_i64, { "rI", "rI" } },
2257     { INDEX_op_setcond_i64, { "r", "rZ", "rZ" } },
2258
2259     { INDEX_op_qemu_ld8u, { "r", "r" } },
2260     { INDEX_op_qemu_ld8s, { "r", "r" } },
2261     { INDEX_op_qemu_ld16u, { "r", "r" } },
2262     { INDEX_op_qemu_ld16s, { "r", "r" } },
2263     { INDEX_op_qemu_ld32, { "r", "r" } },
2264     { INDEX_op_qemu_ld32u, { "r", "r" } },
2265     { INDEX_op_qemu_ld32s, { "r", "r" } },
2266     { INDEX_op_qemu_ld64, { "r", "r" } },
2267
2268     { INDEX_op_qemu_st8, { "SZ", "r" } },
2269     { INDEX_op_qemu_st16, { "SZ", "r" } },
2270     { INDEX_op_qemu_st32, { "SZ", "r" } },
2271     { INDEX_op_qemu_st64, { "SZ", "r" } },
2272
2273     { -1 },
2274 };
2275
2276 /* Generate global QEMU prologue and epilogue code */
2277 static void tcg_target_qemu_prologue(TCGContext *s)
2278 {
2279     int frame_size;
2280
2281     /* reserve some stack space */
2282     frame_size = TCG_STATIC_CALL_ARGS_SIZE;
2283     frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
2284                  ~(TCG_TARGET_STACK_ALIGN - 1);
2285
2286     /* First emit adhoc function descriptor */
2287     *(uint64_t *)(s->code_ptr) = (uint64_t)s->code_ptr + 16; /* entry point */
2288     s->code_ptr += 16; /* skip GP */
2289
2290     /* prologue */
2291     tcg_out_bundle(s, mII,
2292                    tcg_opc_m34(TCG_REG_P0, OPC_ALLOC_M34,
2293                                TCG_REG_R33, 32, 24, 0),
2294                    tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2295                                TCG_REG_B6, TCG_REG_R33, 0),
2296                    tcg_opc_i22(TCG_REG_P0, OPC_MOV_I22,
2297                                TCG_REG_R32, TCG_REG_B0));
2298
2299     /* ??? If GUEST_BASE < 0x200000, we could load the register via
2300        an ADDL in the M slot of the next bundle.  */
2301     if (GUEST_BASE != 0) {
2302         tcg_out_bundle(s, mlx,
2303                        tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2304                        tcg_opc_l2 (GUEST_BASE),
2305                        tcg_opc_x2 (TCG_REG_P0, OPC_MOVL_X2,
2306                                    TCG_GUEST_BASE_REG, GUEST_BASE));
2307         tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2308     }
2309
2310     tcg_out_bundle(s, miB,
2311                    tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2312                                TCG_AREG0, 0, TCG_REG_R32),
2313                    tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2314                                TCG_REG_R12, -frame_size, TCG_REG_R12),
2315                    tcg_opc_b4 (TCG_REG_P0, OPC_BR_SPTK_MANY_B4, TCG_REG_B6));
2316
2317     /* epilogue */
2318     tb_ret_addr = s->code_ptr;
2319     tcg_out_bundle(s, miI,
2320                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2321                    tcg_opc_i21(TCG_REG_P0, OPC_MOV_I21,
2322                                TCG_REG_B0, TCG_REG_R32, 0),
2323                    tcg_opc_a4 (TCG_REG_P0, OPC_ADDS_A4,
2324                                TCG_REG_R12, frame_size, TCG_REG_R12));
2325     tcg_out_bundle(s, miB,
2326                    tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0),
2327                    tcg_opc_i26(TCG_REG_P0, OPC_MOV_I_I26,
2328                                TCG_REG_PFS, TCG_REG_R33),
2329                    tcg_opc_b4 (TCG_REG_P0, OPC_BR_RET_SPTK_MANY_B4,
2330                                TCG_REG_B0));
2331 }
2332
2333 static void tcg_target_init(TCGContext *s)
2334 {
2335     tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32],
2336                    0xffffffffffffffffull);
2337     tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64],
2338                    0xffffffffffffffffull);
2339
2340     tcg_regset_clear(tcg_target_call_clobber_regs);
2341     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8);
2342     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9);
2343     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10);
2344     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11);
2345     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R14);
2346     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R15);
2347     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R16);
2348     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R17);
2349     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R18);
2350     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R19);
2351     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R20);
2352     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R21);
2353     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R22);
2354     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R23);
2355     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R24);
2356     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R25);
2357     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R26);
2358     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R27);
2359     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R28);
2360     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R29);
2361     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R30);
2362     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R31);
2363     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R56);
2364     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R57);
2365     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R58);
2366     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R59);
2367     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R60);
2368     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R61);
2369     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R62);
2370     tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R63);
2371
2372     tcg_regset_clear(s->reserved_regs);
2373     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);   /* zero register */
2374     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1);   /* global pointer */
2375     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2);   /* internal use */
2376     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R3);   /* internal use */
2377     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12);  /* stack pointer */
2378     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13);  /* thread pointer */
2379     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R32);  /* return address */
2380     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R33);  /* PFS */
2381
2382     /* The following 3 are not in use, are call-saved, but *not* saved
2383        by the prologue.  Therefore we cannot use them without modifying
2384        the prologue.  There doesn't seem to be any good reason to use
2385        these as opposed to the windowed registers.  */
2386     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R4);
2387     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R5);
2388     tcg_regset_set_reg(s->reserved_regs, TCG_REG_R6);
2389
2390     tcg_add_target_add_op_defs(ia64_op_defs);
2391     tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
2392                   CPU_TEMP_BUF_NLONGS * sizeof(long));
2393 }