hw/pci-host/piix.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/isa/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "qemu/range.h"
  32 #include "hw/xen/xen.h"
  33 #include "hw/pci-host/pam.h"
  34 #include "sysemu/sysemu.h"
  35 #include "hw/i386/ioapic.h"
  36 #include "qapi/visitor.h"
  37
  38 /*
  39  * I440FX chipset data sheet.
  40  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  41  */
  42
  43 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
  44 #define I440FX_PCI_HOST_BRIDGE(obj) \
  45     OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
  46
  47 typedef struct I440FXState {
  48     PCIHostState parent_obj;
  49     PcPciInfo pci_info;
  50     uint64_t pci_hole64_size;
  51     uint32_t short_root_bus;
  52 } I440FXState;
  53
  54 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  55 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  56 #define XEN_PIIX_NUM_PIRQS      128ULL
  57 #define PIIX_PIRQC              0x60
  58
  59 /*
  60  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  61  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  62  */
  63 #define RCR_IOPORT 0xcf9
  64
  65 typedef struct PIIX3State {
  66     PCIDevice dev;
  67
  68     /*
  69      * bitmap to track pic levels.
  70      * The pic level is the logical OR of all the PCI irqs mapped to it
  71      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  72      *
  73      * PIRQ is mapped to PIC pins, we track it by
  74      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  75      * pic_irq * PIIX_NUM_PIRQS + pirq
  76      */
  77 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  78 #error "unable to encode pic state in 64bit in pic_levels."
  79 #endif
  80     uint64_t pic_levels;
  81
  82     qemu_irq *pic;
  83
  84     /* This member isn't used. Just for save/load compatibility */
  85     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  86
  87     /* Reset Control Register contents */
  88     uint8_t rcr;
  89
  90     /* IO memory region for Reset Control Register (RCR_IOPORT) */
  91     MemoryRegion rcr_mem;
  92 } PIIX3State;
  93
  94 #define TYPE_I440FX_PCI_DEVICE "i440FX"
  95 #define I440FX_PCI_DEVICE(obj) \
  96     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
  97
  98 struct PCII440FXState {
  99     /*< private >*/
 100     PCIDevice parent_obj;
 101     /*< public >*/
 102
 103     MemoryRegion *system_memory;
 104     MemoryRegion *pci_address_space;
 105     MemoryRegion *ram_memory;
 106     PAMMemoryRegion pam_regions[13];
 107     MemoryRegion smram_region;
 108     uint8_t smm_enabled;
 109 };
 110
 111
 112 #define I440FX_PAM      0x59
 113 #define I440FX_PAM_SIZE 7
 114 #define I440FX_SMRAM    0x72
 115
 116 static void piix3_set_irq(void *opaque, int pirq, int level);
 117 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 118 static void piix3_write_config_xen(PCIDevice *dev,
 119                                uint32_t address, uint32_t val, int len);
 120
 121 /* return the global irq number corresponding to a given device irq
 122    pin. We could also use the bus number to have a more precise
 123    mapping. */
 124 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 125 {
 126     int slot_addend;
 127     slot_addend = (pci_dev->devfn >> 3) - 1;
 128     return (pci_intx + slot_addend) & 3;
 129 }
 130
 131 static void i440fx_update_memory_mappings(PCII440FXState *d)
 132 {
 133     int i;
 134     PCIDevice *pd = PCI_DEVICE(d);
 135
 136     memory_region_transaction_begin();
 137     for (i = 0; i < 13; i++) {
 138         pam_update(&d->pam_regions[i], i,
 139                    pd->config[I440FX_PAM + ((i + 1) / 2)]);
 140     }
 141     smram_update(&d->smram_region, pd->config[I440FX_SMRAM], d->smm_enabled);
 142     memory_region_transaction_commit();
 143 }
 144
 145 static void i440fx_set_smm(int val, void *arg)
 146 {
 147     PCII440FXState *d = arg;
 148     PCIDevice *pd = PCI_DEVICE(d);
 149
 150     memory_region_transaction_begin();
 151     smram_set_smm(&d->smm_enabled, val, pd->config[I440FX_SMRAM],
 152                   &d->smram_region);
 153     memory_region_transaction_commit();
 154 }
 155
 156
 157 static void i440fx_write_config(PCIDevice *dev,
 158                                 uint32_t address, uint32_t val, int len)
 159 {
 160     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 161
 162     /* XXX: implement SMRAM.D_LOCK */
 163     pci_default_write_config(dev, address, val, len);
 164     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 165         range_covers_byte(address, len, I440FX_SMRAM)) {
 166         i440fx_update_memory_mappings(d);
 167     }
 168 }
 169
 170 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 171 {
 172     PCII440FXState *d = opaque;
 173     PCIDevice *pd = PCI_DEVICE(d);
 174     int ret, i;
 175
 176     ret = pci_device_load(pd, f);
 177     if (ret < 0)
 178         return ret;
 179     i440fx_update_memory_mappings(d);
 180     qemu_get_8s(f, &d->smm_enabled);
 181
 182     if (version_id == 2) {
 183         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 184             qemu_get_be32(f); /* dummy load for compatibility */
 185         }
 186     }
 187
 188     return 0;
 189 }
 190
 191 static int i440fx_post_load(void *opaque, int version_id)
 192 {
 193     PCII440FXState *d = opaque;
 194
 195     i440fx_update_memory_mappings(d);
 196     return 0;
 197 }
 198
 199 static const VMStateDescription vmstate_i440fx = {
 200     .name = "I440FX",
 201     .version_id = 3,
 202     .minimum_version_id = 3,
 203     .minimum_version_id_old = 1,
 204     .load_state_old = i440fx_load_old,
 205     .post_load = i440fx_post_load,
 206     .fields = (VMStateField[]) {
 207         VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
 208         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 209         VMSTATE_END_OF_LIST()
 210     }
 211 };
 212
 213 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
 214                                               void *opaque, const char *name,
 215                                               Error **errp)
 216 {
 217     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 218     uint32_t value = s->pci_info.w32.begin;
 219
 220     visit_type_uint32(v, &value, name, errp);
 221 }
 222
 223 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
 224                                             void *opaque, const char *name,
 225                                             Error **errp)
 226 {
 227     I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
 228     uint32_t value = s->pci_info.w32.end;
 229
 230     visit_type_uint32(v, &value, name, errp);
 231 }
 232
 233 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
 234                                                 void *opaque, const char *name,
 235                                                 Error **errp)
 236 {
 237     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 238     Range w64;
 239
 240     pci_bus_get_w64_range(h->bus, &w64);
 241
 242     visit_type_uint64(v, &w64.begin, name, errp);
 243 }
 244
 245 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
 246                                               void *opaque, const char *name,
 247                                               Error **errp)
 248 {
 249     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 250     Range w64;
 251
 252     pci_bus_get_w64_range(h->bus, &w64);
 253
 254     visit_type_uint64(v, &w64.end, name, errp);
 255 }
 256
 257 static void i440fx_pcihost_initfn(Object *obj)
 258 {
 259     PCIHostState *s = PCI_HOST_BRIDGE(obj);
 260     I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
 261
 262     memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
 263                           "pci-conf-idx", 4);
 264     memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
 265                           "pci-conf-data", 4);
 266
 267     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
 268                         i440fx_pcihost_get_pci_hole_start,
 269                         NULL, NULL, NULL, NULL);
 270
 271     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
 272                         i440fx_pcihost_get_pci_hole_end,
 273                         NULL, NULL, NULL, NULL);
 274
 275     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
 276                         i440fx_pcihost_get_pci_hole64_start,
 277                         NULL, NULL, NULL, NULL);
 278
 279     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
 280                         i440fx_pcihost_get_pci_hole64_end,
 281                         NULL, NULL, NULL, NULL);
 282
 283     d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
 284 }
 285
 286 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
 287 {
 288     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 289     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 290
 291     sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
 292     sysbus_init_ioports(sbd, 0xcf8, 4);
 293
 294     sysbus_add_io(sbd, 0xcfc, &s->data_mem);
 295     sysbus_init_ioports(sbd, 0xcfc, 4);
 296 }
 297
 298 static int i440fx_initfn(PCIDevice *dev)
 299 {
 300     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 301
 302     dev->config[I440FX_SMRAM] = 0x02;
 303
 304     cpu_smm_register(&i440fx_set_smm, d);
 305     return 0;
 306 }
 307
 308 PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
 309                     int *piix3_devfn,
 310                     ISABus **isa_bus, qemu_irq *pic,
 311                     MemoryRegion *address_space_mem,
 312                     MemoryRegion *address_space_io,
 313                     ram_addr_t ram_size,
 314                     ram_addr_t below_4g_mem_size,
 315                     ram_addr_t above_4g_mem_size,
 316                     MemoryRegion *pci_address_space,
 317                     MemoryRegion *ram_memory)
 318 {
 319     DeviceState *dev;
 320     PCIBus *b;
 321     PCIDevice *d;
 322     PCIHostState *s;
 323     PIIX3State *piix3;
 324     PCII440FXState *f;
 325     unsigned i;
 326     I440FXState *i440fx;
 327
 328     dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
 329     s = PCI_HOST_BRIDGE(dev);
 330     b = pci_bus_new(dev, NULL, pci_address_space,
 331                     address_space_io, 0, TYPE_PCI_BUS);
 332     s->bus = b;
 333     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 334     qdev_init_nofail(dev);
 335
 336     d = pci_create_simple(b, 0, TYPE_I440FX_PCI_DEVICE);
 337     *pi440fx_state = I440FX_PCI_DEVICE(d);
 338     f = *pi440fx_state;
 339     f->system_memory = address_space_mem;
 340     f->pci_address_space = pci_address_space;
 341     f->ram_memory = ram_memory;
 342
 343     i440fx = I440FX_PCI_HOST_BRIDGE(dev);
 344     i440fx->pci_info.w32.begin = below_4g_mem_size;
 345
 346     /* setup pci memory mapping */
 347     pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
 348                            f->pci_address_space);
 349
 350     memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
 351                              f->pci_address_space, 0xa0000, 0x20000);
 352     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 353                                         &f->smram_region, 1);
 354     memory_region_set_enabled(&f->smram_region, false);
 355     init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 356              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 357     for (i = 0; i < 12; ++i) {
 358         init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
 359                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 360                  PAM_EXPAN_SIZE);
 361     }
 362
 363     /* Xen supports additional interrupt routes from the PCI devices to
 364      * the IOAPIC: the four pins of each PCI device on the bus are also
 365      * connected to the IOAPIC directly.
 366      * These additional routes can be discovered through ACPI. */
 367     if (xen_enabled()) {
 368         piix3 = DO_UPCAST(PIIX3State, dev,
 369                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 370         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 371                 piix3, XEN_PIIX_NUM_PIRQS);
 372     } else {
 373         piix3 = DO_UPCAST(PIIX3State, dev,
 374                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 375         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 376                 PIIX_NUM_PIRQS);
 377         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 378     }
 379     piix3->pic = pic;
 380     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
 381
 382     *piix3_devfn = piix3->dev.devfn;
 383
 384     ram_size = ram_size / 8 / 1024 / 1024;
 385     if (ram_size > 255) {
 386         ram_size = 255;
 387     }
 388     d->config[0x57] = ram_size;
 389
 390     i440fx_update_memory_mappings(f);
 391
 392     return b;
 393 }
 394
 395 PCIBus *find_i440fx(void)
 396 {
 397     PCIHostState *s = OBJECT_CHECK(PCIHostState,
 398                                    object_resolve_path("/machine/i440fx", NULL),
 399                                    TYPE_PCI_HOST_BRIDGE);
 400     return s ? s->bus : NULL;
 401 }
 402
 403 /* PIIX3 PCI to ISA bridge */
 404 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 405 {
 406     qemu_set_irq(piix3->pic[pic_irq],
 407                  !!(piix3->pic_levels &
 408                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 409                      (pic_irq * PIIX_NUM_PIRQS))));
 410 }
 411
 412 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 413 {
 414     int pic_irq;
 415     uint64_t mask;
 416
 417     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 418     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 419         return;
 420     }
 421
 422     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 423     piix3->pic_levels &= ~mask;
 424     piix3->pic_levels |= mask * !!level;
 425
 426     piix3_set_irq_pic(piix3, pic_irq);
 427 }
 428
 429 static void piix3_set_irq(void *opaque, int pirq, int level)
 430 {
 431     PIIX3State *piix3 = opaque;
 432     piix3_set_irq_level(piix3, pirq, level);
 433 }
 434
 435 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 436 {
 437     PIIX3State *piix3 = opaque;
 438     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 439     PCIINTxRoute route;
 440
 441     if (irq < PIIX_NUM_PIC_IRQS) {
 442         route.mode = PCI_INTX_ENABLED;
 443         route.irq = irq;
 444     } else {
 445         route.mode = PCI_INTX_DISABLED;
 446         route.irq = -1;
 447     }
 448     return route;
 449 }
 450
 451 /* irq routing is changed. so rebuild bitmap */
 452 static void piix3_update_irq_levels(PIIX3State *piix3)
 453 {
 454     int pirq;
 455
 456     piix3->pic_levels = 0;
 457     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 458         piix3_set_irq_level(piix3, pirq,
 459                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 460     }
 461 }
 462
 463 static void piix3_write_config(PCIDevice *dev,
 464                                uint32_t address, uint32_t val, int len)
 465 {
 466     pci_default_write_config(dev, address, val, len);
 467     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 468         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 469         int pic_irq;
 470
 471         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 472         piix3_update_irq_levels(piix3);
 473         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 474             piix3_set_irq_pic(piix3, pic_irq);
 475         }
 476     }
 477 }
 478
 479 static void piix3_write_config_xen(PCIDevice *dev,
 480                                uint32_t address, uint32_t val, int len)
 481 {
 482     xen_piix_pci_write_config_client(address, val, len);
 483     piix3_write_config(dev, address, val, len);
 484 }
 485
 486 static void piix3_reset(void *opaque)
 487 {
 488     PIIX3State *d = opaque;
 489     uint8_t *pci_conf = d->dev.config;
 490
 491     pci_conf[0x04] = 0x07; /* master, memory and I/O */
 492     pci_conf[0x05] = 0x00;
 493     pci_conf[0x06] = 0x00;
 494     pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
 495     pci_conf[0x4c] = 0x4d;
 496     pci_conf[0x4e] = 0x03;
 497     pci_conf[0x4f] = 0x00;
 498     pci_conf[0x60] = 0x80;
 499     pci_conf[0x61] = 0x80;
 500     pci_conf[0x62] = 0x80;
 501     pci_conf[0x63] = 0x80;
 502     pci_conf[0x69] = 0x02;
 503     pci_conf[0x70] = 0x80;
 504     pci_conf[0x76] = 0x0c;
 505     pci_conf[0x77] = 0x0c;
 506     pci_conf[0x78] = 0x02;
 507     pci_conf[0x79] = 0x00;
 508     pci_conf[0x80] = 0x00;
 509     pci_conf[0x82] = 0x00;
 510     pci_conf[0xa0] = 0x08;
 511     pci_conf[0xa2] = 0x00;
 512     pci_conf[0xa3] = 0x00;
 513     pci_conf[0xa4] = 0x00;
 514     pci_conf[0xa5] = 0x00;
 515     pci_conf[0xa6] = 0x00;
 516     pci_conf[0xa7] = 0x00;
 517     pci_conf[0xa8] = 0x0f;
 518     pci_conf[0xaa] = 0x00;
 519     pci_conf[0xab] = 0x00;
 520     pci_conf[0xac] = 0x00;
 521     pci_conf[0xae] = 0x00;
 522
 523     d->pic_levels = 0;
 524     d->rcr = 0;
 525 }
 526
 527 static int piix3_post_load(void *opaque, int version_id)
 528 {
 529     PIIX3State *piix3 = opaque;
 530     piix3_update_irq_levels(piix3);
 531     return 0;
 532 }
 533
 534 static void piix3_pre_save(void *opaque)
 535 {
 536     int i;
 537     PIIX3State *piix3 = opaque;
 538
 539     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 540         piix3->pci_irq_levels_vmstate[i] =
 541             pci_bus_get_irq_level(piix3->dev.bus, i);
 542     }
 543 }
 544
 545 static bool piix3_rcr_needed(void *opaque)
 546 {
 547     PIIX3State *piix3 = opaque;
 548
 549     return (piix3->rcr != 0);
 550 }
 551
 552 static const VMStateDescription vmstate_piix3_rcr = {
 553     .name = "PIIX3/rcr",
 554     .version_id = 1,
 555     .minimum_version_id = 1,
 556     .fields = (VMStateField[]) {
 557         VMSTATE_UINT8(rcr, PIIX3State),
 558         VMSTATE_END_OF_LIST()
 559     }
 560 };
 561
 562 static const VMStateDescription vmstate_piix3 = {
 563     .name = "PIIX3",
 564     .version_id = 3,
 565     .minimum_version_id = 2,
 566     .post_load = piix3_post_load,
 567     .pre_save = piix3_pre_save,
 568     .fields = (VMStateField[]) {
 569         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 570         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 571                               PIIX_NUM_PIRQS, 3),
 572         VMSTATE_END_OF_LIST()
 573     },
 574     .subsections = (VMStateSubsection[]) {
 575         {
 576             .vmsd = &vmstate_piix3_rcr,
 577             .needed = piix3_rcr_needed,
 578         },
 579         { 0 }
 580     }
 581 };
 582
 583
 584 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 585 {
 586     PIIX3State *d = opaque;
 587
 588     if (val & 4) {
 589         qemu_system_reset_request();
 590         return;
 591     }
 592     d->rcr = val & 2; /* keep System Reset type only */
 593 }
 594
 595 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 596 {
 597     PIIX3State *d = opaque;
 598
 599     return d->rcr;
 600 }
 601
 602 static const MemoryRegionOps rcr_ops = {
 603     .read = rcr_read,
 604     .write = rcr_write,
 605     .endianness = DEVICE_LITTLE_ENDIAN
 606 };
 607
 608 static int piix3_initfn(PCIDevice *dev)
 609 {
 610     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 611
 612     isa_bus_new(DEVICE(d), pci_address_space_io(dev));
 613
 614     memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
 615                           "piix3-reset-control", 1);
 616     memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
 617                                         &d->rcr_mem, 1);
 618
 619     qemu_register_reset(piix3_reset, d);
 620     return 0;
 621 }
 622
 623 static void piix3_class_init(ObjectClass *klass, void *data)
 624 {
 625     DeviceClass *dc = DEVICE_CLASS(klass);
 626     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 627
 628     dc->desc        = "ISA bridge";
 629     dc->vmsd        = &vmstate_piix3;
 630     dc->hotpluggable   = false;
 631     k->init         = piix3_initfn;
 632     k->config_write = piix3_write_config;
 633     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 634     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 635     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 636     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 637     /*
 638      * Reason: part of PIIX3 southbridge, needs to be wired up by
 639      * pc_piix.c's pc_init1()
 640      */
 641     dc->cannot_instantiate_with_device_add_yet = true;
 642 }
 643
 644 static const TypeInfo piix3_info = {
 645     .name          = "PIIX3",
 646     .parent        = TYPE_PCI_DEVICE,
 647     .instance_size = sizeof(PIIX3State),
 648     .class_init    = piix3_class_init,
 649 };
 650
 651 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 652 {
 653     DeviceClass *dc = DEVICE_CLASS(klass);
 654     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 655
 656     dc->desc        = "ISA bridge";
 657     dc->vmsd        = &vmstate_piix3;
 658     dc->hotpluggable   = false;
 659     k->init         = piix3_initfn;
 660     k->config_write = piix3_write_config_xen;
 661     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 662     /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
 663     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0;
 664     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 665     /*
 666      * Reason: part of PIIX3 southbridge, needs to be wired up by
 667      * pc_piix.c's pc_init1()
 668      */
 669     dc->cannot_instantiate_with_device_add_yet = true;
 670 };
 671
 672 static const TypeInfo piix3_xen_info = {
 673     .name          = "PIIX3-xen",
 674     .parent        = TYPE_PCI_DEVICE,
 675     .instance_size = sizeof(PIIX3State),
 676     .class_init    = piix3_xen_class_init,
 677 };
 678
 679 static void i440fx_class_init(ObjectClass *klass, void *data)
 680 {
 681     DeviceClass *dc = DEVICE_CLASS(klass);
 682     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 683
 684     k->init = i440fx_initfn;
 685     k->config_write = i440fx_write_config;
 686     k->vendor_id = PCI_VENDOR_ID_INTEL;
 687     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 688     k->revision = 0x02;
 689     k->class_id = PCI_CLASS_BRIDGE_HOST;
 690     dc->desc = "Host bridge";
 691     dc->vmsd = &vmstate_i440fx;
 692     /*
 693      * PCI-facing part of the host bridge, not usable without the
 694      * host-facing part, which can't be device_add'ed, yet.
 695      */
 696     dc->cannot_instantiate_with_device_add_yet = true;
 697     dc->hotpluggable   = false;
 698 }
 699
 700 static const TypeInfo i440fx_info = {
 701     .name          = TYPE_I440FX_PCI_DEVICE,
 702     .parent        = TYPE_PCI_DEVICE,
 703     .instance_size = sizeof(PCII440FXState),
 704     .class_init    = i440fx_class_init,
 705 };
 706
 707 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
 708                                                 PCIBus *rootbus)
 709 {
 710     I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
 711
 712     /* For backwards compat with old device paths */
 713     if (s->short_root_bus) {
 714         return "0000";
 715     }
 716     return "0000:00";
 717 }
 718
 719 static Property i440fx_props[] = {
 720     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
 721                      pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
 722     DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
 723     DEFINE_PROP_END_OF_LIST(),
 724 };
 725
 726 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 727 {
 728     DeviceClass *dc = DEVICE_CLASS(klass);
 729     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 730
 731     hc->root_bus_path = i440fx_pcihost_root_bus_path;
 732     dc->realize = i440fx_pcihost_realize;
 733     dc->fw_name = "pci";
 734     dc->props = i440fx_props;
 735 }
 736
 737 static const TypeInfo i440fx_pcihost_info = {
 738     .name          = TYPE_I440FX_PCI_HOST_BRIDGE,
 739     .parent        = TYPE_PCI_HOST_BRIDGE,
 740     .instance_size = sizeof(I440FXState),
 741     .instance_init = i440fx_pcihost_initfn,
 742     .class_init    = i440fx_pcihost_class_init,
 743 };
 744
 745 static void i440fx_register_types(void)
 746 {
 747     type_register_static(&i440fx_info);
 748     type_register_static(&piix3_info);
 749     type_register_static(&piix3_xen_info);
 750     type_register_static(&i440fx_pcihost_info);
 751 }
 752
 753 type_init(i440fx_register_types)