hw/arm/stm32f205_soc.c

   1 /*
   2  * STM32F205 SoC
   3  *
   4  * Copyright (c) 2014 Alistair Francis <[email protected]>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "qapi/error.h"
  27 #include "qemu/module.h"
  28 #include "hw/arm/boot.h"
  29 #include "exec/address-spaces.h"
  30 #include "hw/arm/stm32f205_soc.h"
  31 #include "hw/qdev-properties.h"
  32
  33 /* At the moment only Timer 2 to 5 are modelled */
  34 static const uint32_t timer_addr[STM_NUM_TIMERS] = { 0x40000000, 0x40000400,
  35     0x40000800, 0x40000C00 };
  36 static const uint32_t usart_addr[STM_NUM_USARTS] = { 0x40011000, 0x40004400,
  37     0x40004800, 0x40004C00, 0x40005000, 0x40011400 };
  38 static const uint32_t adc_addr[STM_NUM_ADCS] = { 0x40012000, 0x40012100,
  39     0x40012200 };
  40 static const uint32_t spi_addr[STM_NUM_SPIS] = { 0x40013000, 0x40003800,
  41     0x40003C00 };
  42
  43 static const int timer_irq[STM_NUM_TIMERS] = {28, 29, 30, 50};
  44 static const int usart_irq[STM_NUM_USARTS] = {37, 38, 39, 52, 53, 71};
  45 #define ADC_IRQ 18
  46 static const int spi_irq[STM_NUM_SPIS] = {35, 36, 51};
  47
  48 static void stm32f205_soc_initfn(Object *obj)
  49 {
  50     STM32F205State *s = STM32F205_SOC(obj);
  51     int i;
  52
  53     sysbus_init_child_obj(obj, "armv7m", &s->armv7m, sizeof(s->armv7m),
  54                           TYPE_ARMV7M);
  55
  56     sysbus_init_child_obj(obj, "syscfg", &s->syscfg, sizeof(s->syscfg),
  57                           TYPE_STM32F2XX_SYSCFG);
  58
  59     for (i = 0; i < STM_NUM_USARTS; i++) {
  60         sysbus_init_child_obj(obj, "usart[*]", &s->usart[i],
  61                               sizeof(s->usart[i]), TYPE_STM32F2XX_USART);
  62     }
  63
  64     for (i = 0; i < STM_NUM_TIMERS; i++) {
  65         sysbus_init_child_obj(obj, "timer[*]", &s->timer[i],
  66                               sizeof(s->timer[i]), TYPE_STM32F2XX_TIMER);
  67     }
  68
  69     s->adc_irqs = OR_IRQ(object_new(TYPE_OR_IRQ));
  70
  71     for (i = 0; i < STM_NUM_ADCS; i++) {
  72         sysbus_init_child_obj(obj, "adc[*]", &s->adc[i], sizeof(s->adc[i]),
  73                               TYPE_STM32F2XX_ADC);
  74     }
  75
  76     for (i = 0; i < STM_NUM_SPIS; i++) {
  77         sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]),
  78                               TYPE_STM32F2XX_SPI);
  79     }
  80 }
  81
  82 static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp)
  83 {
  84     STM32F205State *s = STM32F205_SOC(dev_soc);
  85     DeviceState *dev, *armv7m;
  86     SysBusDevice *busdev;
  87     Error *err = NULL;
  88     int i;
  89
  90     MemoryRegion *system_memory = get_system_memory();
  91     MemoryRegion *sram = g_new(MemoryRegion, 1);
  92     MemoryRegion *flash = g_new(MemoryRegion, 1);
  93     MemoryRegion *flash_alias = g_new(MemoryRegion, 1);
  94
  95     memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE,
  96                            &error_fatal);
  97     memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias",
  98                              flash, 0, FLASH_SIZE);
  99
 100     memory_region_set_readonly(flash, true);
 101     memory_region_set_readonly(flash_alias, true);
 102
 103     memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash);
 104     memory_region_add_subregion(system_memory, 0, flash_alias);
 105
 106     memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE,
 107                            &error_fatal);
 108     memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram);
 109
 110     armv7m = DEVICE(&s->armv7m);
 111     qdev_prop_set_uint32(armv7m, "num-irq", 96);
 112     qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type);
 113     qdev_prop_set_bit(armv7m, "enable-bitband", true);
 114     object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory()),
 115                                      "memory", &error_abort);
 116     object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err);
 117     if (err != NULL) {
 118         error_propagate(errp, err);
 119         return;
 120     }
 121
 122     /* System configuration controller */
 123     dev = DEVICE(&s->syscfg);
 124     object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err);
 125     if (err != NULL) {
 126         error_propagate(errp, err);
 127         return;
 128     }
 129     busdev = SYS_BUS_DEVICE(dev);
 130     sysbus_mmio_map(busdev, 0, 0x40013800);
 131     sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71));
 132
 133     /* Attach UART (uses USART registers) and USART controllers */
 134     for (i = 0; i < STM_NUM_USARTS; i++) {
 135         dev = DEVICE(&(s->usart[i]));
 136         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
 137         object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &err);
 138         if (err != NULL) {
 139             error_propagate(errp, err);
 140             return;
 141         }
 142         busdev = SYS_BUS_DEVICE(dev);
 143         sysbus_mmio_map(busdev, 0, usart_addr[i]);
 144         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
 145     }
 146
 147     /* Timer 2 to 5 */
 148     for (i = 0; i < STM_NUM_TIMERS; i++) {
 149         dev = DEVICE(&(s->timer[i]));
 150         qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
 151         object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &err);
 152         if (err != NULL) {
 153             error_propagate(errp, err);
 154             return;
 155         }
 156         busdev = SYS_BUS_DEVICE(dev);
 157         sysbus_mmio_map(busdev, 0, timer_addr[i]);
 158         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
 159     }
 160
 161     /* ADC 1 to 3 */
 162     object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS,
 163                             "num-lines", &err);
 164     object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err);
 165     if (err != NULL) {
 166         error_propagate(errp, err);
 167         return;
 168     }
 169     qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0,
 170                           qdev_get_gpio_in(armv7m, ADC_IRQ));
 171
 172     for (i = 0; i < STM_NUM_ADCS; i++) {
 173         dev = DEVICE(&(s->adc[i]));
 174         object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err);
 175         if (err != NULL) {
 176             error_propagate(errp, err);
 177             return;
 178         }
 179         busdev = SYS_BUS_DEVICE(dev);
 180         sysbus_mmio_map(busdev, 0, adc_addr[i]);
 181         sysbus_connect_irq(busdev, 0,
 182                            qdev_get_gpio_in(DEVICE(s->adc_irqs), i));
 183     }
 184
 185     /* SPI 1 and 2 */
 186     for (i = 0; i < STM_NUM_SPIS; i++) {
 187         dev = DEVICE(&(s->spi[i]));
 188         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
 189         if (err != NULL) {
 190             error_propagate(errp, err);
 191             return;
 192         }
 193         busdev = SYS_BUS_DEVICE(dev);
 194         sysbus_mmio_map(busdev, 0, spi_addr[i]);
 195         sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
 196     }
 197 }
 198
 199 static Property stm32f205_soc_properties[] = {
 200     DEFINE_PROP_STRING("cpu-type", STM32F205State, cpu_type),
 201     DEFINE_PROP_END_OF_LIST(),
 202 };
 203
 204 static void stm32f205_soc_class_init(ObjectClass *klass, void *data)
 205 {
 206     DeviceClass *dc = DEVICE_CLASS(klass);
 207
 208     dc->realize = stm32f205_soc_realize;
 209     dc->props = stm32f205_soc_properties;
 210 }
 211
 212 static const TypeInfo stm32f205_soc_info = {
 213     .name          = TYPE_STM32F205_SOC,
 214     .parent        = TYPE_SYS_BUS_DEVICE,
 215     .instance_size = sizeof(STM32F205State),
 216     .instance_init = stm32f205_soc_initfn,
 217     .class_init    = stm32f205_soc_class_init,
 218 };
 219
 220 static void stm32f205_soc_types(void)
 221 {
 222     type_register_static(&stm32f205_soc_info);
 223 }
 224
 225 type_init(stm32f205_soc_types)