hw/timer/exynos4210_rtc.c

   1 /*
   2  * Samsung exynos4210 Real Time Clock
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *  Ogurtsov Oleg <[email protected]>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms of the GNU General Public License as published by the
   9  *  Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful, but WITHOUT
  13  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15  *  for more details.
  16  *
  17  *  You should have received a copy of the GNU General Public License along
  18  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  19  *
  20  */
  21
  22 /* Description:
  23  * Register RTCCON:
  24  *  CLKSEL Bit[1] not used
  25  *  CLKOUTEN Bit[9] not used
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qemu-common.h"
  30 #include "qemu/log.h"
  31 #include "qemu/module.h"
  32 #include "hw/sysbus.h"
  33 #include "qemu/timer.h"
  34 #include "qemu/bcd.h"
  35 #include "hw/ptimer.h"
  36
  37 #include "hw/hw.h"
  38 #include "sysemu/sysemu.h"
  39
  40 #include "hw/arm/exynos4210.h"
  41
  42 #define DEBUG_RTC 0
  43
  44 #if DEBUG_RTC
  45 #define DPRINTF(fmt, ...) \
  46         do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
  47                 ## __VA_ARGS__); } while (0)
  48 #else
  49 #define DPRINTF(fmt, ...) do {} while (0)
  50 #endif
  51
  52 #define     EXYNOS4210_RTC_REG_MEM_SIZE     0x0100
  53
  54 #define     INTP            0x0030
  55 #define     RTCCON          0x0040
  56 #define     TICCNT          0x0044
  57 #define     RTCALM          0x0050
  58 #define     ALMSEC          0x0054
  59 #define     ALMMIN          0x0058
  60 #define     ALMHOUR         0x005C
  61 #define     ALMDAY          0x0060
  62 #define     ALMMON          0x0064
  63 #define     ALMYEAR         0x0068
  64 #define     BCDSEC          0x0070
  65 #define     BCDMIN          0x0074
  66 #define     BCDHOUR         0x0078
  67 #define     BCDDAY          0x007C
  68 #define     BCDDAYWEEK      0x0080
  69 #define     BCDMON          0x0084
  70 #define     BCDYEAR         0x0088
  71 #define     CURTICNT        0x0090
  72
  73 #define     TICK_TIMER_ENABLE   0x0100
  74 #define     TICNT_THRESHOLD     2
  75
  76
  77 #define     RTC_ENABLE          0x0001
  78
  79 #define     INTP_TICK_ENABLE    0x0001
  80 #define     INTP_ALM_ENABLE     0x0002
  81
  82 #define     ALARM_INT_ENABLE    0x0040
  83
  84 #define     RTC_BASE_FREQ       32768
  85
  86 #define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
  87 #define EXYNOS4210_RTC(obj) \
  88     OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC)
  89
  90 typedef struct Exynos4210RTCState {
  91     SysBusDevice parent_obj;
  92
  93     MemoryRegion iomem;
  94
  95     /* registers */
  96     uint32_t    reg_intp;
  97     uint32_t    reg_rtccon;
  98     uint32_t    reg_ticcnt;
  99     uint32_t    reg_rtcalm;
 100     uint32_t    reg_almsec;
 101     uint32_t    reg_almmin;
 102     uint32_t    reg_almhour;
 103     uint32_t    reg_almday;
 104     uint32_t    reg_almmon;
 105     uint32_t    reg_almyear;
 106     uint32_t    reg_curticcnt;
 107
 108     ptimer_state    *ptimer;        /* tick timer */
 109     ptimer_state    *ptimer_1Hz;    /* clock timer */
 110     uint32_t        freq;
 111
 112     qemu_irq        tick_irq;   /* Time Tick Generator irq */
 113     qemu_irq        alm_irq;    /* alarm irq */
 114
 115     struct tm   current_tm;     /* current time */
 116 } Exynos4210RTCState;
 117
 118 #define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)
 119
 120 /*** VMState ***/
 121 static const VMStateDescription vmstate_exynos4210_rtc_state = {
 122     .name = "exynos4210.rtc",
 123     .version_id = 1,
 124     .minimum_version_id = 1,
 125     .fields = (VMStateField[]) {
 126         VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
 127         VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
 128         VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState),
 129         VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState),
 130         VMSTATE_UINT32(reg_almsec, Exynos4210RTCState),
 131         VMSTATE_UINT32(reg_almmin, Exynos4210RTCState),
 132         VMSTATE_UINT32(reg_almhour, Exynos4210RTCState),
 133         VMSTATE_UINT32(reg_almday, Exynos4210RTCState),
 134         VMSTATE_UINT32(reg_almmon, Exynos4210RTCState),
 135         VMSTATE_UINT32(reg_almyear, Exynos4210RTCState),
 136         VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState),
 137         VMSTATE_PTIMER(ptimer, Exynos4210RTCState),
 138         VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState),
 139         VMSTATE_UINT32(freq, Exynos4210RTCState),
 140         VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState),
 141         VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState),
 142         VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState),
 143         VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState),
 144         VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState),
 145         VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState),
 146         VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState),
 147         VMSTATE_END_OF_LIST()
 148     }
 149 };
 150
 151 #define BCD3DIGITS(x) \
 152     ((uint32_t)to_bcd((uint8_t)(x % 100)) + \
 153     ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))
 154
 155 static void check_alarm_raise(Exynos4210RTCState *s)
 156 {
 157     unsigned int alarm_raise = 0;
 158     struct tm stm = s->current_tm;
 159
 160     if ((s->reg_rtcalm & 0x01) &&
 161         (to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) {
 162         alarm_raise = 1;
 163     }
 164     if ((s->reg_rtcalm & 0x02) &&
 165         (to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) {
 166         alarm_raise = 1;
 167     }
 168     if ((s->reg_rtcalm & 0x04) &&
 169         (to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) {
 170         alarm_raise = 1;
 171     }
 172     if ((s->reg_rtcalm & 0x08) &&
 173         (to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) {
 174         alarm_raise = 1;
 175     }
 176     if ((s->reg_rtcalm & 0x10) &&
 177          (to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) {
 178         alarm_raise = 1;
 179     }
 180     if ((s->reg_rtcalm & 0x20) &&
 181         (BCD3DIGITS(stm.tm_year) == s->reg_almyear)) {
 182         alarm_raise = 1;
 183     }
 184
 185     if (alarm_raise) {
 186         DPRINTF("ALARM IRQ\n");
 187         /* set irq status */
 188         s->reg_intp |= INTP_ALM_ENABLE;
 189         qemu_irq_raise(s->alm_irq);
 190     }
 191 }
 192
 193 /*
 194  * RTC update frequency
 195  * Parameters:
 196  *     reg_value - current RTCCON register or his new value
 197  */
 198 static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
 199                                        uint32_t reg_value)
 200 {
 201     uint32_t freq;
 202
 203     freq = s->freq;
 204     /* set frequncy for time generator */
 205     s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));
 206
 207     if (freq != s->freq) {
 208         ptimer_set_freq(s->ptimer, s->freq);
 209         DPRINTF("freq=%dHz\n", s->freq);
 210     }
 211 }
 212
 213 /* month is between 0 and 11. */
 214 static int get_days_in_month(int month, int year)
 215 {
 216     static const int days_tab[12] = {
 217         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 218     };
 219     int d;
 220     if ((unsigned)month >= 12) {
 221         return 31;
 222     }
 223     d = days_tab[month];
 224     if (month == 1) {
 225         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) {
 226             d++;
 227         }
 228     }
 229     return d;
 230 }
 231
 232 /* update 'tm' to the next second */
 233 static void rtc_next_second(struct tm *tm)
 234 {
 235     int days_in_month;
 236
 237     tm->tm_sec++;
 238     if ((unsigned)tm->tm_sec >= 60) {
 239         tm->tm_sec = 0;
 240         tm->tm_min++;
 241         if ((unsigned)tm->tm_min >= 60) {
 242             tm->tm_min = 0;
 243             tm->tm_hour++;
 244             if ((unsigned)tm->tm_hour >= 24) {
 245                 tm->tm_hour = 0;
 246                 /* next day */
 247                 tm->tm_wday++;
 248                 if ((unsigned)tm->tm_wday >= 7) {
 249                     tm->tm_wday = 0;
 250                 }
 251                 days_in_month = get_days_in_month(tm->tm_mon,
 252                                                   tm->tm_year + 1900);
 253                 tm->tm_mday++;
 254                 if (tm->tm_mday < 1) {
 255                     tm->tm_mday = 1;
 256                 } else if (tm->tm_mday > days_in_month) {
 257                     tm->tm_mday = 1;
 258                     tm->tm_mon++;
 259                     if (tm->tm_mon >= 12) {
 260                         tm->tm_mon = 0;
 261                         tm->tm_year++;
 262                     }
 263                 }
 264             }
 265         }
 266     }
 267 }
 268
 269 /*
 270  * tick handler
 271  */
 272 static void exynos4210_rtc_tick(void *opaque)
 273 {
 274     Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
 275
 276     DPRINTF("TICK IRQ\n");
 277     /* set irq status */
 278     s->reg_intp |= INTP_TICK_ENABLE;
 279     /* raise IRQ */
 280     qemu_irq_raise(s->tick_irq);
 281
 282     /* restart timer */
 283     ptimer_set_count(s->ptimer, s->reg_ticcnt);
 284     ptimer_run(s->ptimer, 1);
 285 }
 286
 287 /*
 288  * 1Hz clock handler
 289  */
 290 static void exynos4210_rtc_1Hz_tick(void *opaque)
 291 {
 292     Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
 293
 294     rtc_next_second(&s->current_tm);
 295     /* DPRINTF("1Hz tick\n"); */
 296
 297     /* raise IRQ */
 298     if (s->reg_rtcalm & ALARM_INT_ENABLE) {
 299         check_alarm_raise(s);
 300     }
 301
 302     ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
 303     ptimer_run(s->ptimer_1Hz, 1);
 304 }
 305
 306 /*
 307  * RTC Read
 308  */
 309 static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
 310         unsigned size)
 311 {
 312     uint32_t value = 0;
 313     Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
 314
 315     switch (offset) {
 316     case INTP:
 317         value = s->reg_intp;
 318         break;
 319     case RTCCON:
 320         value = s->reg_rtccon;
 321         break;
 322     case TICCNT:
 323         value = s->reg_ticcnt;
 324         break;
 325     case RTCALM:
 326         value = s->reg_rtcalm;
 327         break;
 328     case ALMSEC:
 329         value = s->reg_almsec;
 330         break;
 331     case ALMMIN:
 332         value = s->reg_almmin;
 333         break;
 334     case ALMHOUR:
 335         value = s->reg_almhour;
 336         break;
 337     case ALMDAY:
 338         value = s->reg_almday;
 339         break;
 340     case ALMMON:
 341         value = s->reg_almmon;
 342         break;
 343     case ALMYEAR:
 344         value = s->reg_almyear;
 345         break;
 346
 347     case BCDSEC:
 348         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec);
 349         break;
 350     case BCDMIN:
 351         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min);
 352         break;
 353     case BCDHOUR:
 354         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour);
 355         break;
 356     case BCDDAYWEEK:
 357         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday);
 358         break;
 359     case BCDDAY:
 360         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday);
 361         break;
 362     case BCDMON:
 363         value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1);
 364         break;
 365     case BCDYEAR:
 366         value = BCD3DIGITS(s->current_tm.tm_year);
 367         break;
 368
 369     case CURTICNT:
 370         s->reg_curticcnt = ptimer_get_count(s->ptimer);
 371         value = s->reg_curticcnt;
 372         break;
 373
 374     default:
 375         qemu_log_mask(LOG_GUEST_ERROR,
 376                       "exynos4210.rtc: bad read offset " TARGET_FMT_plx,
 377                       offset);
 378         break;
 379     }
 380     return value;
 381 }
 382
 383 /*
 384  * RTC Write
 385  */
 386 static void exynos4210_rtc_write(void *opaque, hwaddr offset,
 387         uint64_t value, unsigned size)
 388 {
 389     Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
 390
 391     switch (offset) {
 392     case INTP:
 393         if (value & INTP_ALM_ENABLE) {
 394             qemu_irq_lower(s->alm_irq);
 395             s->reg_intp &= (~INTP_ALM_ENABLE);
 396         }
 397         if (value & INTP_TICK_ENABLE) {
 398             qemu_irq_lower(s->tick_irq);
 399             s->reg_intp &= (~INTP_TICK_ENABLE);
 400         }
 401         break;
 402     case RTCCON:
 403         if (value & RTC_ENABLE) {
 404             exynos4210_rtc_update_freq(s, value);
 405         }
 406         if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) {
 407             /* clock timer */
 408             ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
 409             ptimer_run(s->ptimer_1Hz, 1);
 410             DPRINTF("run clock timer\n");
 411         }
 412         if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) {
 413             /* tick timer */
 414             ptimer_stop(s->ptimer);
 415             /* clock timer */
 416             ptimer_stop(s->ptimer_1Hz);
 417             DPRINTF("stop all timers\n");
 418         }
 419         if (value & RTC_ENABLE) {
 420             if ((value & TICK_TIMER_ENABLE) >
 421                 (s->reg_rtccon & TICK_TIMER_ENABLE) &&
 422                 (s->reg_ticcnt)) {
 423                 ptimer_set_count(s->ptimer, s->reg_ticcnt);
 424                 ptimer_run(s->ptimer, 1);
 425                 DPRINTF("run tick timer\n");
 426             }
 427             if ((value & TICK_TIMER_ENABLE) <
 428                 (s->reg_rtccon & TICK_TIMER_ENABLE)) {
 429                 ptimer_stop(s->ptimer);
 430             }
 431         }
 432         s->reg_rtccon = value;
 433         break;
 434     case TICCNT:
 435         if (value > TICNT_THRESHOLD) {
 436             s->reg_ticcnt = value;
 437         } else {
 438             qemu_log_mask(LOG_GUEST_ERROR,
 439                           "exynos4210.rtc: bad TICNT value %u",
 440                           (uint32_t)value);
 441         }
 442         break;
 443
 444     case RTCALM:
 445         s->reg_rtcalm = value;
 446         break;
 447     case ALMSEC:
 448         s->reg_almsec = (value & 0x7f);
 449         break;
 450     case ALMMIN:
 451         s->reg_almmin = (value & 0x7f);
 452         break;
 453     case ALMHOUR:
 454         s->reg_almhour = (value & 0x3f);
 455         break;
 456     case ALMDAY:
 457         s->reg_almday = (value & 0x3f);
 458         break;
 459     case ALMMON:
 460         s->reg_almmon = (value & 0x1f);
 461         break;
 462     case ALMYEAR:
 463         s->reg_almyear = (value & 0x0fff);
 464         break;
 465
 466     case BCDSEC:
 467         if (s->reg_rtccon & RTC_ENABLE) {
 468             s->current_tm.tm_sec = (int)from_bcd((uint8_t)value);
 469         }
 470         break;
 471     case BCDMIN:
 472         if (s->reg_rtccon & RTC_ENABLE) {
 473             s->current_tm.tm_min = (int)from_bcd((uint8_t)value);
 474         }
 475         break;
 476     case BCDHOUR:
 477         if (s->reg_rtccon & RTC_ENABLE) {
 478             s->current_tm.tm_hour = (int)from_bcd((uint8_t)value);
 479         }
 480         break;
 481     case BCDDAYWEEK:
 482         if (s->reg_rtccon & RTC_ENABLE) {
 483             s->current_tm.tm_wday = (int)from_bcd((uint8_t)value);
 484         }
 485         break;
 486     case BCDDAY:
 487         if (s->reg_rtccon & RTC_ENABLE) {
 488             s->current_tm.tm_mday = (int)from_bcd((uint8_t)value);
 489         }
 490         break;
 491     case BCDMON:
 492         if (s->reg_rtccon & RTC_ENABLE) {
 493             s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1;
 494         }
 495         break;
 496     case BCDYEAR:
 497         if (s->reg_rtccon & RTC_ENABLE) {
 498             /* 3 digits */
 499             s->current_tm.tm_year = (int)from_bcd((uint8_t)value) +
 500                     (int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100;
 501         }
 502         break;
 503
 504     default:
 505         qemu_log_mask(LOG_GUEST_ERROR,
 506                       "exynos4210.rtc: bad write offset " TARGET_FMT_plx,
 507                       offset);
 508         break;
 509
 510     }
 511 }
 512
 513 /*
 514  * Set default values to timer fields and registers
 515  */
 516 static void exynos4210_rtc_reset(DeviceState *d)
 517 {
 518     Exynos4210RTCState *s = EXYNOS4210_RTC(d);
 519
 520     qemu_get_timedate(&s->current_tm, 0);
 521
 522     DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
 523             s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday,
 524             s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec);
 525
 526     s->reg_intp = 0;
 527     s->reg_rtccon = 0;
 528     s->reg_ticcnt = 0;
 529     s->reg_rtcalm = 0;
 530     s->reg_almsec = 0;
 531     s->reg_almmin = 0;
 532     s->reg_almhour = 0;
 533     s->reg_almday = 0;
 534     s->reg_almmon = 0;
 535     s->reg_almyear = 0;
 536
 537     s->reg_curticcnt = 0;
 538
 539     exynos4210_rtc_update_freq(s, s->reg_rtccon);
 540     ptimer_stop(s->ptimer);
 541     ptimer_stop(s->ptimer_1Hz);
 542 }
 543
 544 static const MemoryRegionOps exynos4210_rtc_ops = {
 545     .read = exynos4210_rtc_read,
 546     .write = exynos4210_rtc_write,
 547     .endianness = DEVICE_NATIVE_ENDIAN,
 548 };
 549
 550 /*
 551  * RTC timer initialization
 552  */
 553 static void exynos4210_rtc_init(Object *obj)
 554 {
 555     Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
 556     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 557     QEMUBH *bh;
 558
 559     bh = qemu_bh_new(exynos4210_rtc_tick, s);
 560     s->ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
 561     ptimer_set_freq(s->ptimer, RTC_BASE_FREQ);
 562     exynos4210_rtc_update_freq(s, 0);
 563
 564     bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s);
 565     s->ptimer_1Hz = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
 566     ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ);
 567
 568     sysbus_init_irq(dev, &s->alm_irq);
 569     sysbus_init_irq(dev, &s->tick_irq);
 570
 571     memory_region_init_io(&s->iomem, obj, &exynos4210_rtc_ops, s,
 572                           "exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE);
 573     sysbus_init_mmio(dev, &s->iomem);
 574 }
 575
 576 static void exynos4210_rtc_class_init(ObjectClass *klass, void *data)
 577 {
 578     DeviceClass *dc = DEVICE_CLASS(klass);
 579
 580     dc->reset = exynos4210_rtc_reset;
 581     dc->vmsd = &vmstate_exynos4210_rtc_state;
 582 }
 583
 584 static const TypeInfo exynos4210_rtc_info = {
 585     .name          = TYPE_EXYNOS4210_RTC,
 586     .parent        = TYPE_SYS_BUS_DEVICE,
 587     .instance_size = sizeof(Exynos4210RTCState),
 588     .instance_init = exynos4210_rtc_init,
 589     .class_init    = exynos4210_rtc_class_init,
 590 };
 591
 592 static void exynos4210_rtc_register_types(void)
 593 {
 594     type_register_static(&exynos4210_rtc_info);
 595 }
 596
 597 type_init(exynos4210_rtc_register_types)