target/i386/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "exec/exec-all.h"
   5 #include "hw/hw.h"
   6 #include "hw/boards.h"
   7 #include "hw/i386/pc.h"
   8 #include "hw/isa/isa.h"
   9 #include "migration/cpu.h"
  10
  11 #include "sysemu/kvm.h"
  12
  13 #include "qemu/error-report.h"
  14
  15 static const VMStateDescription vmstate_segment = {
  16     .name = "segment",
  17     .version_id = 1,
  18     .minimum_version_id = 1,
  19     .fields = (VMStateField[]) {
  20         VMSTATE_UINT32(selector, SegmentCache),
  21         VMSTATE_UINTTL(base, SegmentCache),
  22         VMSTATE_UINT32(limit, SegmentCache),
  23         VMSTATE_UINT32(flags, SegmentCache),
  24         VMSTATE_END_OF_LIST()
  25     }
  26 };
  27
  28 #define VMSTATE_SEGMENT(_field, _state) {                            \
  29     .name       = (stringify(_field)),                               \
  30     .size       = sizeof(SegmentCache),                              \
  31     .vmsd       = &vmstate_segment,                                  \
  32     .flags      = VMS_STRUCT,                                        \
  33     .offset     = offsetof(_state, _field)                           \
  34             + type_check(SegmentCache,typeof_field(_state, _field))  \
  35 }
  36
  37 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  38     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  39
  40 static const VMStateDescription vmstate_xmm_reg = {
  41     .name = "xmm_reg",
  42     .version_id = 1,
  43     .minimum_version_id = 1,
  44     .fields = (VMStateField[]) {
  45         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  46         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  47         VMSTATE_END_OF_LIST()
  48     }
  49 };
  50
  51 #define VMSTATE_XMM_REGS(_field, _state, _start)                         \
  52     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  53                              vmstate_xmm_reg, ZMMReg)
  54
  55 /* YMMH format is the same as XMM, but for bits 128-255 */
  56 static const VMStateDescription vmstate_ymmh_reg = {
  57     .name = "ymmh_reg",
  58     .version_id = 1,
  59     .minimum_version_id = 1,
  60     .fields = (VMStateField[]) {
  61         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  62         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  63         VMSTATE_END_OF_LIST()
  64     }
  65 };
  66
  67 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v)               \
  68     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v,    \
  69                              vmstate_ymmh_reg, ZMMReg)
  70
  71 static const VMStateDescription vmstate_zmmh_reg = {
  72     .name = "zmmh_reg",
  73     .version_id = 1,
  74     .minimum_version_id = 1,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  77         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
  78         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
  79         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
  80         VMSTATE_END_OF_LIST()
  81     }
  82 };
  83
  84 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start)                   \
  85     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  86                              vmstate_zmmh_reg, ZMMReg)
  87
  88 #ifdef TARGET_X86_64
  89 static const VMStateDescription vmstate_hi16_zmm_reg = {
  90     .name = "hi16_zmm_reg",
  91     .version_id = 1,
  92     .minimum_version_id = 1,
  93     .fields = (VMStateField[]) {
  94         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  95         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  96         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  97         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  98         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  99         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
 100         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
 101         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
 102         VMSTATE_END_OF_LIST()
 103     }
 104 };
 105
 106 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start)               \
 107     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
 108                              vmstate_hi16_zmm_reg, ZMMReg)
 109 #endif
 110
 111 static const VMStateDescription vmstate_bnd_regs = {
 112     .name = "bnd_regs",
 113     .version_id = 1,
 114     .minimum_version_id = 1,
 115     .fields = (VMStateField[]) {
 116         VMSTATE_UINT64(lb, BNDReg),
 117         VMSTATE_UINT64(ub, BNDReg),
 118         VMSTATE_END_OF_LIST()
 119     }
 120 };
 121
 122 #define VMSTATE_BND_REGS(_field, _state, _n)          \
 123     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
 124
 125 static const VMStateDescription vmstate_mtrr_var = {
 126     .name = "mtrr_var",
 127     .version_id = 1,
 128     .minimum_version_id = 1,
 129     .fields = (VMStateField[]) {
 130         VMSTATE_UINT64(base, MTRRVar),
 131         VMSTATE_UINT64(mask, MTRRVar),
 132         VMSTATE_END_OF_LIST()
 133     }
 134 };
 135
 136 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
 137     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
 138
 139 typedef struct x86_FPReg_tmp {
 140     FPReg *parent;
 141     uint64_t tmp_mant;
 142     uint16_t tmp_exp;
 143 } x86_FPReg_tmp;
 144
 145 static void fpreg_pre_save(void *opaque)
 146 {
 147     x86_FPReg_tmp *tmp = opaque;
 148
 149     /* we save the real CPU data (in case of MMX usage only 'mant'
 150        contains the MMX register */
 151     cpu_get_fp80(&tmp->tmp_mant, &tmp->tmp_exp, tmp->parent->d);
 152 }
 153
 154 static int fpreg_post_load(void *opaque, int version)
 155 {
 156     x86_FPReg_tmp *tmp = opaque;
 157
 158     tmp->parent->d = cpu_set_fp80(tmp->tmp_mant, tmp->tmp_exp);
 159     return 0;
 160 }
 161
 162 static const VMStateDescription vmstate_fpreg_tmp = {
 163     .name = "fpreg_tmp",
 164     .post_load = fpreg_post_load,
 165     .pre_save  = fpreg_pre_save,
 166     .fields = (VMStateField[]) {
 167         VMSTATE_UINT64(tmp_mant, x86_FPReg_tmp),
 168         VMSTATE_UINT16(tmp_exp, x86_FPReg_tmp),
 169         VMSTATE_END_OF_LIST()
 170     }
 171 };
 172
 173 static const VMStateDescription vmstate_fpreg = {
 174     .name = "fpreg",
 175     .fields = (VMStateField[]) {
 176         VMSTATE_WITH_TMP(FPReg, x86_FPReg_tmp, vmstate_fpreg_tmp),
 177         VMSTATE_END_OF_LIST()
 178     }
 179 };
 180
 181 static void cpu_pre_save(void *opaque)
 182 {
 183     X86CPU *cpu = opaque;
 184     CPUX86State *env = &cpu->env;
 185     int i;
 186
 187     /* FPU */
 188     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 189     env->fptag_vmstate = 0;
 190     for(i = 0; i < 8; i++) {
 191         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 192     }
 193
 194     env->fpregs_format_vmstate = 0;
 195
 196     /*
 197      * Real mode guest segments register DPL should be zero.
 198      * Older KVM version were setting it wrongly.
 199      * Fixing it will allow live migration to host with unrestricted guest
 200      * support (otherwise the migration will fail with invalid guest state
 201      * error).
 202      */
 203     if (!(env->cr[0] & CR0_PE_MASK) &&
 204         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 205         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 206         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 207         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 208         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 209         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 210         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 211     }
 212
 213 }
 214
 215 static int cpu_post_load(void *opaque, int version_id)
 216 {
 217     X86CPU *cpu = opaque;
 218     CPUState *cs = CPU(cpu);
 219     CPUX86State *env = &cpu->env;
 220     int i;
 221
 222     if (env->tsc_khz && env->user_tsc_khz &&
 223         env->tsc_khz != env->user_tsc_khz) {
 224         error_report("Mismatch between user-specified TSC frequency and "
 225                      "migrated TSC frequency");
 226         return -EINVAL;
 227     }
 228
 229     if (env->fpregs_format_vmstate) {
 230         error_report("Unsupported old non-softfloat CPU state");
 231         return -EINVAL;
 232     }
 233     /*
 234      * Real mode guest segments register DPL should be zero.
 235      * Older KVM version were setting it wrongly.
 236      * Fixing it will allow live migration from such host that don't have
 237      * restricted guest support to a host with unrestricted guest support
 238      * (otherwise the migration will fail with invalid guest state
 239      * error).
 240      */
 241     if (!(env->cr[0] & CR0_PE_MASK) &&
 242         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 243         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 244         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 245         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 246         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 247         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 248         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 249     }
 250
 251     /* Older versions of QEMU incorrectly used CS.DPL as the CPL when
 252      * running under KVM.  This is wrong for conforming code segments.
 253      * Luckily, in our implementation the CPL field of hflags is redundant
 254      * and we can get the right value from the SS descriptor privilege level.
 255      */
 256     env->hflags &= ~HF_CPL_MASK;
 257     env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 258
 259     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 260     env->fpus = env->fpus_vmstate & ~0x3800;
 261     env->fptag_vmstate ^= 0xff;
 262     for(i = 0; i < 8; i++) {
 263         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 264     }
 265     update_fp_status(env);
 266
 267     cpu_breakpoint_remove_all(cs, BP_CPU);
 268     cpu_watchpoint_remove_all(cs, BP_CPU);
 269     {
 270         /* Indicate all breakpoints disabled, as they are, then
 271            let the helper re-enable them.  */
 272         target_ulong dr7 = env->dr[7];
 273         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
 274         cpu_x86_update_dr7(env, dr7);
 275     }
 276     tlb_flush(cs);
 277     return 0;
 278 }
 279
 280 static bool async_pf_msr_needed(void *opaque)
 281 {
 282     X86CPU *cpu = opaque;
 283
 284     return cpu->env.async_pf_en_msr != 0;
 285 }
 286
 287 static bool pv_eoi_msr_needed(void *opaque)
 288 {
 289     X86CPU *cpu = opaque;
 290
 291     return cpu->env.pv_eoi_en_msr != 0;
 292 }
 293
 294 static bool steal_time_msr_needed(void *opaque)
 295 {
 296     X86CPU *cpu = opaque;
 297
 298     return cpu->env.steal_time_msr != 0;
 299 }
 300
 301 static const VMStateDescription vmstate_steal_time_msr = {
 302     .name = "cpu/steal_time_msr",
 303     .version_id = 1,
 304     .minimum_version_id = 1,
 305     .needed = steal_time_msr_needed,
 306     .fields = (VMStateField[]) {
 307         VMSTATE_UINT64(env.steal_time_msr, X86CPU),
 308         VMSTATE_END_OF_LIST()
 309     }
 310 };
 311
 312 static const VMStateDescription vmstate_async_pf_msr = {
 313     .name = "cpu/async_pf_msr",
 314     .version_id = 1,
 315     .minimum_version_id = 1,
 316     .needed = async_pf_msr_needed,
 317     .fields = (VMStateField[]) {
 318         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
 319         VMSTATE_END_OF_LIST()
 320     }
 321 };
 322
 323 static const VMStateDescription vmstate_pv_eoi_msr = {
 324     .name = "cpu/async_pv_eoi_msr",
 325     .version_id = 1,
 326     .minimum_version_id = 1,
 327     .needed = pv_eoi_msr_needed,
 328     .fields = (VMStateField[]) {
 329         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
 330         VMSTATE_END_OF_LIST()
 331     }
 332 };
 333
 334 static bool fpop_ip_dp_needed(void *opaque)
 335 {
 336     X86CPU *cpu = opaque;
 337     CPUX86State *env = &cpu->env;
 338
 339     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 340 }
 341
 342 static const VMStateDescription vmstate_fpop_ip_dp = {
 343     .name = "cpu/fpop_ip_dp",
 344     .version_id = 1,
 345     .minimum_version_id = 1,
 346     .needed = fpop_ip_dp_needed,
 347     .fields = (VMStateField[]) {
 348         VMSTATE_UINT16(env.fpop, X86CPU),
 349         VMSTATE_UINT64(env.fpip, X86CPU),
 350         VMSTATE_UINT64(env.fpdp, X86CPU),
 351         VMSTATE_END_OF_LIST()
 352     }
 353 };
 354
 355 static bool tsc_adjust_needed(void *opaque)
 356 {
 357     X86CPU *cpu = opaque;
 358     CPUX86State *env = &cpu->env;
 359
 360     return env->tsc_adjust != 0;
 361 }
 362
 363 static const VMStateDescription vmstate_msr_tsc_adjust = {
 364     .name = "cpu/msr_tsc_adjust",
 365     .version_id = 1,
 366     .minimum_version_id = 1,
 367     .needed = tsc_adjust_needed,
 368     .fields = (VMStateField[]) {
 369         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
 370         VMSTATE_END_OF_LIST()
 371     }
 372 };
 373
 374 static bool tscdeadline_needed(void *opaque)
 375 {
 376     X86CPU *cpu = opaque;
 377     CPUX86State *env = &cpu->env;
 378
 379     return env->tsc_deadline != 0;
 380 }
 381
 382 static const VMStateDescription vmstate_msr_tscdeadline = {
 383     .name = "cpu/msr_tscdeadline",
 384     .version_id = 1,
 385     .minimum_version_id = 1,
 386     .needed = tscdeadline_needed,
 387     .fields = (VMStateField[]) {
 388         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
 389         VMSTATE_END_OF_LIST()
 390     }
 391 };
 392
 393 static bool misc_enable_needed(void *opaque)
 394 {
 395     X86CPU *cpu = opaque;
 396     CPUX86State *env = &cpu->env;
 397
 398     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 399 }
 400
 401 static bool feature_control_needed(void *opaque)
 402 {
 403     X86CPU *cpu = opaque;
 404     CPUX86State *env = &cpu->env;
 405
 406     return env->msr_ia32_feature_control != 0;
 407 }
 408
 409 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 410     .name = "cpu/msr_ia32_misc_enable",
 411     .version_id = 1,
 412     .minimum_version_id = 1,
 413     .needed = misc_enable_needed,
 414     .fields = (VMStateField[]) {
 415         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
 416         VMSTATE_END_OF_LIST()
 417     }
 418 };
 419
 420 static const VMStateDescription vmstate_msr_ia32_feature_control = {
 421     .name = "cpu/msr_ia32_feature_control",
 422     .version_id = 1,
 423     .minimum_version_id = 1,
 424     .needed = feature_control_needed,
 425     .fields = (VMStateField[]) {
 426         VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
 427         VMSTATE_END_OF_LIST()
 428     }
 429 };
 430
 431 static bool pmu_enable_needed(void *opaque)
 432 {
 433     X86CPU *cpu = opaque;
 434     CPUX86State *env = &cpu->env;
 435     int i;
 436
 437     if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
 438         env->msr_global_status || env->msr_global_ovf_ctrl) {
 439         return true;
 440     }
 441     for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
 442         if (env->msr_fixed_counters[i]) {
 443             return true;
 444         }
 445     }
 446     for (i = 0; i < MAX_GP_COUNTERS; i++) {
 447         if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
 448             return true;
 449         }
 450     }
 451
 452     return false;
 453 }
 454
 455 static const VMStateDescription vmstate_msr_architectural_pmu = {
 456     .name = "cpu/msr_architectural_pmu",
 457     .version_id = 1,
 458     .minimum_version_id = 1,
 459     .needed = pmu_enable_needed,
 460     .fields = (VMStateField[]) {
 461         VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
 462         VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
 463         VMSTATE_UINT64(env.msr_global_status, X86CPU),
 464         VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
 465         VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
 466         VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
 467         VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
 468         VMSTATE_END_OF_LIST()
 469     }
 470 };
 471
 472 static bool mpx_needed(void *opaque)
 473 {
 474     X86CPU *cpu = opaque;
 475     CPUX86State *env = &cpu->env;
 476     unsigned int i;
 477
 478     for (i = 0; i < 4; i++) {
 479         if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
 480             return true;
 481         }
 482     }
 483
 484     if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
 485         return true;
 486     }
 487
 488     return !!env->msr_bndcfgs;
 489 }
 490
 491 static const VMStateDescription vmstate_mpx = {
 492     .name = "cpu/mpx",
 493     .version_id = 1,
 494     .minimum_version_id = 1,
 495     .needed = mpx_needed,
 496     .fields = (VMStateField[]) {
 497         VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
 498         VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
 499         VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
 500         VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
 501         VMSTATE_END_OF_LIST()
 502     }
 503 };
 504
 505 static bool hyperv_hypercall_enable_needed(void *opaque)
 506 {
 507     X86CPU *cpu = opaque;
 508     CPUX86State *env = &cpu->env;
 509
 510     return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
 511 }
 512
 513 static const VMStateDescription vmstate_msr_hypercall_hypercall = {
 514     .name = "cpu/msr_hyperv_hypercall",
 515     .version_id = 1,
 516     .minimum_version_id = 1,
 517     .needed = hyperv_hypercall_enable_needed,
 518     .fields = (VMStateField[]) {
 519         VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
 520         VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
 521         VMSTATE_END_OF_LIST()
 522     }
 523 };
 524
 525 static bool hyperv_vapic_enable_needed(void *opaque)
 526 {
 527     X86CPU *cpu = opaque;
 528     CPUX86State *env = &cpu->env;
 529
 530     return env->msr_hv_vapic != 0;
 531 }
 532
 533 static const VMStateDescription vmstate_msr_hyperv_vapic = {
 534     .name = "cpu/msr_hyperv_vapic",
 535     .version_id = 1,
 536     .minimum_version_id = 1,
 537     .needed = hyperv_vapic_enable_needed,
 538     .fields = (VMStateField[]) {
 539         VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
 540         VMSTATE_END_OF_LIST()
 541     }
 542 };
 543
 544 static bool hyperv_time_enable_needed(void *opaque)
 545 {
 546     X86CPU *cpu = opaque;
 547     CPUX86State *env = &cpu->env;
 548
 549     return env->msr_hv_tsc != 0;
 550 }
 551
 552 static const VMStateDescription vmstate_msr_hyperv_time = {
 553     .name = "cpu/msr_hyperv_time",
 554     .version_id = 1,
 555     .minimum_version_id = 1,
 556     .needed = hyperv_time_enable_needed,
 557     .fields = (VMStateField[]) {
 558         VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
 559         VMSTATE_END_OF_LIST()
 560     }
 561 };
 562
 563 static bool hyperv_crash_enable_needed(void *opaque)
 564 {
 565     X86CPU *cpu = opaque;
 566     CPUX86State *env = &cpu->env;
 567     int i;
 568
 569     for (i = 0; i < HV_X64_MSR_CRASH_PARAMS; i++) {
 570         if (env->msr_hv_crash_params[i]) {
 571             return true;
 572         }
 573     }
 574     return false;
 575 }
 576
 577 static const VMStateDescription vmstate_msr_hyperv_crash = {
 578     .name = "cpu/msr_hyperv_crash",
 579     .version_id = 1,
 580     .minimum_version_id = 1,
 581     .needed = hyperv_crash_enable_needed,
 582     .fields = (VMStateField[]) {
 583         VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params,
 584                              X86CPU, HV_X64_MSR_CRASH_PARAMS),
 585         VMSTATE_END_OF_LIST()
 586     }
 587 };
 588
 589 static bool hyperv_runtime_enable_needed(void *opaque)
 590 {
 591     X86CPU *cpu = opaque;
 592     CPUX86State *env = &cpu->env;
 593
 594     if (!cpu->hyperv_runtime) {
 595         return false;
 596     }
 597
 598     return env->msr_hv_runtime != 0;
 599 }
 600
 601 static const VMStateDescription vmstate_msr_hyperv_runtime = {
 602     .name = "cpu/msr_hyperv_runtime",
 603     .version_id = 1,
 604     .minimum_version_id = 1,
 605     .needed = hyperv_runtime_enable_needed,
 606     .fields = (VMStateField[]) {
 607         VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
 608         VMSTATE_END_OF_LIST()
 609     }
 610 };
 611
 612 static bool hyperv_synic_enable_needed(void *opaque)
 613 {
 614     X86CPU *cpu = opaque;
 615     CPUX86State *env = &cpu->env;
 616     int i;
 617
 618     if (env->msr_hv_synic_control != 0 ||
 619         env->msr_hv_synic_evt_page != 0 ||
 620         env->msr_hv_synic_msg_page != 0) {
 621         return true;
 622     }
 623
 624     for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
 625         if (env->msr_hv_synic_sint[i] != 0) {
 626             return true;
 627         }
 628     }
 629
 630     return false;
 631 }
 632
 633 static const VMStateDescription vmstate_msr_hyperv_synic = {
 634     .name = "cpu/msr_hyperv_synic",
 635     .version_id = 1,
 636     .minimum_version_id = 1,
 637     .needed = hyperv_synic_enable_needed,
 638     .fields = (VMStateField[]) {
 639         VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
 640         VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
 641         VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
 642         VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU,
 643                              HV_SYNIC_SINT_COUNT),
 644         VMSTATE_END_OF_LIST()
 645     }
 646 };
 647
 648 static bool hyperv_stimer_enable_needed(void *opaque)
 649 {
 650     X86CPU *cpu = opaque;
 651     CPUX86State *env = &cpu->env;
 652     int i;
 653
 654     for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
 655         if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
 656             return true;
 657         }
 658     }
 659     return false;
 660 }
 661
 662 static const VMStateDescription vmstate_msr_hyperv_stimer = {
 663     .name = "cpu/msr_hyperv_stimer",
 664     .version_id = 1,
 665     .minimum_version_id = 1,
 666     .needed = hyperv_stimer_enable_needed,
 667     .fields = (VMStateField[]) {
 668         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config,
 669                              X86CPU, HV_SYNIC_STIMER_COUNT),
 670         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count,
 671                              X86CPU, HV_SYNIC_STIMER_COUNT),
 672         VMSTATE_END_OF_LIST()
 673     }
 674 };
 675
 676 static bool avx512_needed(void *opaque)
 677 {
 678     X86CPU *cpu = opaque;
 679     CPUX86State *env = &cpu->env;
 680     unsigned int i;
 681
 682     for (i = 0; i < NB_OPMASK_REGS; i++) {
 683         if (env->opmask_regs[i]) {
 684             return true;
 685         }
 686     }
 687
 688     for (i = 0; i < CPU_NB_REGS; i++) {
 689 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
 690         if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
 691             ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
 692             return true;
 693         }
 694 #ifdef TARGET_X86_64
 695         if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
 696             ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
 697             ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
 698             ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
 699             return true;
 700         }
 701 #endif
 702     }
 703
 704     return false;
 705 }
 706
 707 static const VMStateDescription vmstate_avx512 = {
 708     .name = "cpu/avx512",
 709     .version_id = 1,
 710     .minimum_version_id = 1,
 711     .needed = avx512_needed,
 712     .fields = (VMStateField[]) {
 713         VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
 714         VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
 715 #ifdef TARGET_X86_64
 716         VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
 717 #endif
 718         VMSTATE_END_OF_LIST()
 719     }
 720 };
 721
 722 static bool xss_needed(void *opaque)
 723 {
 724     X86CPU *cpu = opaque;
 725     CPUX86State *env = &cpu->env;
 726
 727     return env->xss != 0;
 728 }
 729
 730 static const VMStateDescription vmstate_xss = {
 731     .name = "cpu/xss",
 732     .version_id = 1,
 733     .minimum_version_id = 1,
 734     .needed = xss_needed,
 735     .fields = (VMStateField[]) {
 736         VMSTATE_UINT64(env.xss, X86CPU),
 737         VMSTATE_END_OF_LIST()
 738     }
 739 };
 740
 741 #ifdef TARGET_X86_64
 742 static bool pkru_needed(void *opaque)
 743 {
 744     X86CPU *cpu = opaque;
 745     CPUX86State *env = &cpu->env;
 746
 747     return env->pkru != 0;
 748 }
 749
 750 static const VMStateDescription vmstate_pkru = {
 751     .name = "cpu/pkru",
 752     .version_id = 1,
 753     .minimum_version_id = 1,
 754     .needed = pkru_needed,
 755     .fields = (VMStateField[]){
 756         VMSTATE_UINT32(env.pkru, X86CPU),
 757         VMSTATE_END_OF_LIST()
 758     }
 759 };
 760 #endif
 761
 762 static bool tsc_khz_needed(void *opaque)
 763 {
 764     X86CPU *cpu = opaque;
 765     CPUX86State *env = &cpu->env;
 766     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
 767     PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
 768     return env->tsc_khz && pcmc->save_tsc_khz;
 769 }
 770
 771 static const VMStateDescription vmstate_tsc_khz = {
 772     .name = "cpu/tsc_khz",
 773     .version_id = 1,
 774     .minimum_version_id = 1,
 775     .needed = tsc_khz_needed,
 776     .fields = (VMStateField[]) {
 777         VMSTATE_INT64(env.tsc_khz, X86CPU),
 778         VMSTATE_END_OF_LIST()
 779     }
 780 };
 781
 782 static bool mcg_ext_ctl_needed(void *opaque)
 783 {
 784     X86CPU *cpu = opaque;
 785     CPUX86State *env = &cpu->env;
 786     return cpu->enable_lmce && env->mcg_ext_ctl;
 787 }
 788
 789 static const VMStateDescription vmstate_mcg_ext_ctl = {
 790     .name = "cpu/mcg_ext_ctl",
 791     .version_id = 1,
 792     .minimum_version_id = 1,
 793     .needed = mcg_ext_ctl_needed,
 794     .fields = (VMStateField[]) {
 795         VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU),
 796         VMSTATE_END_OF_LIST()
 797     }
 798 };
 799
 800 VMStateDescription vmstate_x86_cpu = {
 801     .name = "cpu",
 802     .version_id = 12,
 803     .minimum_version_id = 11,
 804     .pre_save = cpu_pre_save,
 805     .post_load = cpu_post_load,
 806     .fields = (VMStateField[]) {
 807         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
 808         VMSTATE_UINTTL(env.eip, X86CPU),
 809         VMSTATE_UINTTL(env.eflags, X86CPU),
 810         VMSTATE_UINT32(env.hflags, X86CPU),
 811         /* FPU */
 812         VMSTATE_UINT16(env.fpuc, X86CPU),
 813         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
 814         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
 815         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
 816
 817         VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg),
 818
 819         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
 820         VMSTATE_SEGMENT(env.ldt, X86CPU),
 821         VMSTATE_SEGMENT(env.tr, X86CPU),
 822         VMSTATE_SEGMENT(env.gdt, X86CPU),
 823         VMSTATE_SEGMENT(env.idt, X86CPU),
 824
 825         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
 826         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
 827         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
 828
 829         VMSTATE_UINTTL(env.cr[0], X86CPU),
 830         VMSTATE_UINTTL(env.cr[2], X86CPU),
 831         VMSTATE_UINTTL(env.cr[3], X86CPU),
 832         VMSTATE_UINTTL(env.cr[4], X86CPU),
 833         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
 834         /* MMU */
 835         VMSTATE_INT32(env.a20_mask, X86CPU),
 836         /* XMM */
 837         VMSTATE_UINT32(env.mxcsr, X86CPU),
 838         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
 839
 840 #ifdef TARGET_X86_64
 841         VMSTATE_UINT64(env.efer, X86CPU),
 842         VMSTATE_UINT64(env.star, X86CPU),
 843         VMSTATE_UINT64(env.lstar, X86CPU),
 844         VMSTATE_UINT64(env.cstar, X86CPU),
 845         VMSTATE_UINT64(env.fmask, X86CPU),
 846         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
 847 #endif
 848         VMSTATE_UINT32(env.smbase, X86CPU),
 849
 850         VMSTATE_UINT64(env.pat, X86CPU),
 851         VMSTATE_UINT32(env.hflags2, X86CPU),
 852
 853         VMSTATE_UINT64(env.vm_hsave, X86CPU),
 854         VMSTATE_UINT64(env.vm_vmcb, X86CPU),
 855         VMSTATE_UINT64(env.tsc_offset, X86CPU),
 856         VMSTATE_UINT64(env.intercept, X86CPU),
 857         VMSTATE_UINT16(env.intercept_cr_read, X86CPU),
 858         VMSTATE_UINT16(env.intercept_cr_write, X86CPU),
 859         VMSTATE_UINT16(env.intercept_dr_read, X86CPU),
 860         VMSTATE_UINT16(env.intercept_dr_write, X86CPU),
 861         VMSTATE_UINT32(env.intercept_exceptions, X86CPU),
 862         VMSTATE_UINT8(env.v_tpr, X86CPU),
 863         /* MTRRs */
 864         VMSTATE_UINT64_ARRAY(env.mtrr_fixed, X86CPU, 11),
 865         VMSTATE_UINT64(env.mtrr_deftype, X86CPU),
 866         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
 867         /* KVM-related states */
 868         VMSTATE_INT32(env.interrupt_injected, X86CPU),
 869         VMSTATE_UINT32(env.mp_state, X86CPU),
 870         VMSTATE_UINT64(env.tsc, X86CPU),
 871         VMSTATE_INT32(env.exception_injected, X86CPU),
 872         VMSTATE_UINT8(env.soft_interrupt, X86CPU),
 873         VMSTATE_UINT8(env.nmi_injected, X86CPU),
 874         VMSTATE_UINT8(env.nmi_pending, X86CPU),
 875         VMSTATE_UINT8(env.has_error_code, X86CPU),
 876         VMSTATE_UINT32(env.sipi_vector, X86CPU),
 877         /* MCE */
 878         VMSTATE_UINT64(env.mcg_cap, X86CPU),
 879         VMSTATE_UINT64(env.mcg_status, X86CPU),
 880         VMSTATE_UINT64(env.mcg_ctl, X86CPU),
 881         VMSTATE_UINT64_ARRAY(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4),
 882         /* rdtscp */
 883         VMSTATE_UINT64(env.tsc_aux, X86CPU),
 884         /* KVM pvclock msr */
 885         VMSTATE_UINT64(env.system_time_msr, X86CPU),
 886         VMSTATE_UINT64(env.wall_clock_msr, X86CPU),
 887         /* XSAVE related fields */
 888         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
 889         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
 890         VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
 891         VMSTATE_END_OF_LIST()
 892         /* The above list is not sorted /wrt version numbers, watch out! */
 893     },
 894     .subsections = (const VMStateDescription*[]) {
 895         &vmstate_async_pf_msr,
 896         &vmstate_pv_eoi_msr,
 897         &vmstate_steal_time_msr,
 898         &vmstate_fpop_ip_dp,
 899         &vmstate_msr_tsc_adjust,
 900         &vmstate_msr_tscdeadline,
 901         &vmstate_msr_ia32_misc_enable,
 902         &vmstate_msr_ia32_feature_control,
 903         &vmstate_msr_architectural_pmu,
 904         &vmstate_mpx,
 905         &vmstate_msr_hypercall_hypercall,
 906         &vmstate_msr_hyperv_vapic,
 907         &vmstate_msr_hyperv_time,
 908         &vmstate_msr_hyperv_crash,
 909         &vmstate_msr_hyperv_runtime,
 910         &vmstate_msr_hyperv_synic,
 911         &vmstate_msr_hyperv_stimer,
 912         &vmstate_avx512,
 913         &vmstate_xss,
 914         &vmstate_tsc_khz,
 915 #ifdef TARGET_X86_64
 916         &vmstate_pkru,
 917 #endif
 918         &vmstate_mcg_ext_ctl,
 919         NULL
 920     }
 921 };