target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "sysemu/kvm.h"
  26 #include "sysemu/cpus.h"
  27 #include "topology.h"
  28
  29 #include "qemu/option.h"
  30 #include "qemu/config-file.h"
  31 #include "qapi/qmp/qerror.h"
  32
  33 #include "qapi-types.h"
  34 #include "qapi-visit.h"
  35 #include "qapi/visitor.h"
  36 #include "sysemu/arch_init.h"
  37
  38 #include "hw/hw.h"
  39 #if defined(CONFIG_KVM)
  40 #include <linux/kvm_para.h>
  41 #endif
  42
  43 #include "sysemu/sysemu.h"
  44 #include "hw/qdev-properties.h"
  45 #include "hw/cpu/icc_bus.h"
  46 #ifndef CONFIG_USER_ONLY
  47 #include "hw/xen/xen.h"
  48 #include "hw/i386/apic_internal.h"
  49 #endif
  50
  51
  52 /* Cache topology CPUID constants: */
  53
  54 /* CPUID Leaf 2 Descriptors */
  55
  56 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
  57 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
  58 #define CPUID_2_L2_2MB_8WAY_64B   0x7d
  59
  60
  61 /* CPUID Leaf 4 constants: */
  62
  63 /* EAX: */
  64 #define CPUID_4_TYPE_DCACHE  1
  65 #define CPUID_4_TYPE_ICACHE  2
  66 #define CPUID_4_TYPE_UNIFIED 3
  67
  68 #define CPUID_4_LEVEL(l)          ((l) << 5)
  69
  70 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
  71 #define CPUID_4_FULLY_ASSOC     (1 << 9)
  72
  73 /* EDX: */
  74 #define CPUID_4_NO_INVD_SHARING (1 << 0)
  75 #define CPUID_4_INCLUSIVE       (1 << 1)
  76 #define CPUID_4_COMPLEX_IDX     (1 << 2)
  77
  78 #define ASSOC_FULL 0xFF
  79
  80 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
  81 #define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
  82                           a ==   2 ? 0x2 : \
  83                           a ==   4 ? 0x4 : \
  84                           a ==   8 ? 0x6 : \
  85                           a ==  16 ? 0x8 : \
  86                           a ==  32 ? 0xA : \
  87                           a ==  48 ? 0xB : \
  88                           a ==  64 ? 0xC : \
  89                           a ==  96 ? 0xD : \
  90                           a == 128 ? 0xE : \
  91                           a == ASSOC_FULL ? 0xF : \
  92                           0 /* invalid value */)
  93
  94
  95 /* Definitions of the hardcoded cache entries we expose: */
  96
  97 /* L1 data cache: */
  98 #define L1D_LINE_SIZE         64
  99 #define L1D_ASSOCIATIVITY      8
 100 #define L1D_SETS              64
 101 #define L1D_PARTITIONS         1
 102 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 103 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
 104 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 105 #define L1D_LINES_PER_TAG      1
 106 #define L1D_SIZE_KB_AMD       64
 107 #define L1D_ASSOCIATIVITY_AMD  2
 108
 109 /* L1 instruction cache: */
 110 #define L1I_LINE_SIZE         64
 111 #define L1I_ASSOCIATIVITY      8
 112 #define L1I_SETS              64
 113 #define L1I_PARTITIONS         1
 114 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 115 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
 116 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 117 #define L1I_LINES_PER_TAG      1
 118 #define L1I_SIZE_KB_AMD       64
 119 #define L1I_ASSOCIATIVITY_AMD  2
 120
 121 /* Level 2 unified cache: */
 122 #define L2_LINE_SIZE          64
 123 #define L2_ASSOCIATIVITY      16
 124 #define L2_SETS             4096
 125 #define L2_PARTITIONS          1
 126 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
 127 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
 128 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
 129 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
 130 #define L2_LINES_PER_TAG       1
 131 #define L2_SIZE_KB_AMD       512
 132
 133 /* No L3 cache: */
 134 #define L3_SIZE_KB             0 /* disabled */
 135 #define L3_ASSOCIATIVITY       0 /* disabled */
 136 #define L3_LINES_PER_TAG       0 /* disabled */
 137 #define L3_LINE_SIZE           0 /* disabled */
 138
 139 /* TLB definitions: */
 140
 141 #define L1_DTLB_2M_ASSOC       1
 142 #define L1_DTLB_2M_ENTRIES   255
 143 #define L1_DTLB_4K_ASSOC       1
 144 #define L1_DTLB_4K_ENTRIES   255
 145
 146 #define L1_ITLB_2M_ASSOC       1
 147 #define L1_ITLB_2M_ENTRIES   255
 148 #define L1_ITLB_4K_ASSOC       1
 149 #define L1_ITLB_4K_ENTRIES   255
 150
 151 #define L2_DTLB_2M_ASSOC       0 /* disabled */
 152 #define L2_DTLB_2M_ENTRIES     0 /* disabled */
 153 #define L2_DTLB_4K_ASSOC       4
 154 #define L2_DTLB_4K_ENTRIES   512
 155
 156 #define L2_ITLB_2M_ASSOC       0 /* disabled */
 157 #define L2_ITLB_2M_ENTRIES     0 /* disabled */
 158 #define L2_ITLB_4K_ASSOC       4
 159 #define L2_ITLB_4K_ENTRIES   512
 160
 161
 162
 163 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 164                                      uint32_t vendor2, uint32_t vendor3)
 165 {
 166     int i;
 167     for (i = 0; i < 4; i++) {
 168         dst[i] = vendor1 >> (8 * i);
 169         dst[i + 4] = vendor2 >> (8 * i);
 170         dst[i + 8] = vendor3 >> (8 * i);
 171     }
 172     dst[CPUID_VENDOR_SZ] = '\0';
 173 }
 174
 175 /* feature flags taken from "Intel Processor Identification and the CPUID
 176  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
 177  * between feature naming conventions, aliases may be added.
 178  */
 179 static const char *feature_name[] = {
 180     "fpu", "vme", "de", "pse",
 181     "tsc", "msr", "pae", "mce",
 182     "cx8", "apic", NULL, "sep",
 183     "mtrr", "pge", "mca", "cmov",
 184     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
 185     NULL, "ds" /* Intel dts */, "acpi", "mmx",
 186     "fxsr", "sse", "sse2", "ss",
 187     "ht" /* Intel htt */, "tm", "ia64", "pbe",
 188 };
 189 static const char *ext_feature_name[] = {
 190     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
 191     "ds_cpl", "vmx", "smx", "est",
 192     "tm2", "ssse3", "cid", NULL,
 193     "fma", "cx16", "xtpr", "pdcm",
 194     NULL, "pcid", "dca", "sse4.1|sse4_1",
 195     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
 196     "tsc-deadline", "aes", "xsave", "osxsave",
 197     "avx", "f16c", "rdrand", "hypervisor",
 198 };
 199 /* Feature names that are already defined on feature_name[] but are set on
 200  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
 201  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
 202  * if and only if CPU vendor is AMD.
 203  */
 204 static const char *ext2_feature_name[] = {
 205     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
 206     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
 207     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
 208     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
 209     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
 210     "nx|xd", NULL, "mmxext", NULL /* mmx */,
 211     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
 212     NULL, "lm|i64", "3dnowext", "3dnow",
 213 };
 214 static const char *ext3_feature_name[] = {
 215     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
 216     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
 217     "3dnowprefetch", "osvw", "ibs", "xop",
 218     "skinit", "wdt", NULL, "lwp",
 219     "fma4", "tce", NULL, "nodeid_msr",
 220     NULL, "tbm", "topoext", "perfctr_core",
 221     "perfctr_nb", NULL, NULL, NULL,
 222     NULL, NULL, NULL, NULL,
 223 };
 224
 225 static const char *ext4_feature_name[] = {
 226     NULL, NULL, "xstore", "xstore-en",
 227     NULL, NULL, "xcrypt", "xcrypt-en",
 228     "ace2", "ace2-en", "phe", "phe-en",
 229     "pmm", "pmm-en", NULL, NULL,
 230     NULL, NULL, NULL, NULL,
 231     NULL, NULL, NULL, NULL,
 232     NULL, NULL, NULL, NULL,
 233     NULL, NULL, NULL, NULL,
 234 };
 235
 236 static const char *kvm_feature_name[] = {
 237     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 238     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
 239     NULL, NULL, NULL, NULL,
 240     NULL, NULL, NULL, NULL,
 241     NULL, NULL, NULL, NULL,
 242     NULL, NULL, NULL, NULL,
 243     NULL, NULL, NULL, NULL,
 244     NULL, NULL, NULL, NULL,
 245 };
 246
 247 static const char *svm_feature_name[] = {
 248     "npt", "lbrv", "svm_lock", "nrip_save",
 249     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 250     NULL, NULL, "pause_filter", NULL,
 251     "pfthreshold", NULL, NULL, NULL,
 252     NULL, NULL, NULL, NULL,
 253     NULL, NULL, NULL, NULL,
 254     NULL, NULL, NULL, NULL,
 255     NULL, NULL, NULL, NULL,
 256 };
 257
 258 static const char *cpuid_7_0_ebx_feature_name[] = {
 259     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
 260     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
 261     NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
 262     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 263 };
 264
 265 typedef struct FeatureWordInfo {
 266     const char **feat_names;
 267     uint32_t cpuid_eax;   /* Input EAX for CPUID */
 268     bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
 269     uint32_t cpuid_ecx;   /* Input ECX value for CPUID */
 270     int cpuid_reg;        /* output register (R_* constant) */
 271 } FeatureWordInfo;
 272
 273 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 274     [FEAT_1_EDX] = {
 275         .feat_names = feature_name,
 276         .cpuid_eax = 1, .cpuid_reg = R_EDX,
 277     },
 278     [FEAT_1_ECX] = {
 279         .feat_names = ext_feature_name,
 280         .cpuid_eax = 1, .cpuid_reg = R_ECX,
 281     },
 282     [FEAT_8000_0001_EDX] = {
 283         .feat_names = ext2_feature_name,
 284         .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
 285     },
 286     [FEAT_8000_0001_ECX] = {
 287         .feat_names = ext3_feature_name,
 288         .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
 289     },
 290     [FEAT_C000_0001_EDX] = {
 291         .feat_names = ext4_feature_name,
 292         .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
 293     },
 294     [FEAT_KVM] = {
 295         .feat_names = kvm_feature_name,
 296         .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
 297     },
 298     [FEAT_SVM] = {
 299         .feat_names = svm_feature_name,
 300         .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
 301     },
 302     [FEAT_7_0_EBX] = {
 303         .feat_names = cpuid_7_0_ebx_feature_name,
 304         .cpuid_eax = 7,
 305         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
 306         .cpuid_reg = R_EBX,
 307     },
 308 };
 309
 310 typedef struct X86RegisterInfo32 {
 311     /* Name of register */
 312     const char *name;
 313     /* QAPI enum value register */
 314     X86CPURegister32 qapi_enum;
 315 } X86RegisterInfo32;
 316
 317 #define REGISTER(reg) \
 318     [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
 319 X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
 320     REGISTER(EAX),
 321     REGISTER(ECX),
 322     REGISTER(EDX),
 323     REGISTER(EBX),
 324     REGISTER(ESP),
 325     REGISTER(EBP),
 326     REGISTER(ESI),
 327     REGISTER(EDI),
 328 };
 329 #undef REGISTER
 330
 331 typedef struct ExtSaveArea {
 332     uint32_t feature, bits;
 333     uint32_t offset, size;
 334 } ExtSaveArea;
 335
 336 static const ExtSaveArea ext_save_areas[] = {
 337     [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
 338             .offset = 0x240, .size = 0x100 },
 339     [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 340             .offset = 0x3c0, .size = 0x40  },
 341     [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 342             .offset = 0x400, .size = 0x40  },
 343 };
 344
 345 const char *get_register_name_32(unsigned int reg)
 346 {
 347     if (reg >= CPU_NB_REGS32) {
 348         return NULL;
 349     }
 350     return x86_reg_info_32[reg].name;
 351 }
 352
 353 /* collects per-function cpuid data
 354  */
 355 typedef struct model_features_t {
 356     uint32_t *guest_feat;
 357     uint32_t *host_feat;
 358     FeatureWord feat_word;
 359 } model_features_t;
 360
 361 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
 362         (1 << KVM_FEATURE_NOP_IO_DELAY) |
 363         (1 << KVM_FEATURE_CLOCKSOURCE2) |
 364         (1 << KVM_FEATURE_ASYNC_PF) |
 365         (1 << KVM_FEATURE_STEAL_TIME) |
 366         (1 << KVM_FEATURE_PV_EOI) |
 367         (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
 368
 369 void disable_kvm_pv_eoi(void)
 370 {
 371     kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
 372 }
 373
 374 void host_cpuid(uint32_t function, uint32_t count,
 375                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 376 {
 377     uint32_t vec[4];
 378
 379 #ifdef __x86_64__
 380     asm volatile("cpuid"
 381                  : "=a"(vec[0]), "=b"(vec[1]),
 382                    "=c"(vec[2]), "=d"(vec[3])
 383                  : "0"(function), "c"(count) : "cc");
 384 #elif defined(__i386__)
 385     asm volatile("pusha \n\t"
 386                  "cpuid \n\t"
 387                  "mov %%eax, 0(%2) \n\t"
 388                  "mov %%ebx, 4(%2) \n\t"
 389                  "mov %%ecx, 8(%2) \n\t"
 390                  "mov %%edx, 12(%2) \n\t"
 391                  "popa"
 392                  : : "a"(function), "c"(count), "S"(vec)
 393                  : "memory", "cc");
 394 #else
 395     abort();
 396 #endif
 397
 398     if (eax)
 399         *eax = vec[0];
 400     if (ebx)
 401         *ebx = vec[1];
 402     if (ecx)
 403         *ecx = vec[2];
 404     if (edx)
 405         *edx = vec[3];
 406 }
 407
 408 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 409
 410 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 411  * a substring.  ex if !NULL points to the first char after a substring,
 412  * otherwise the string is assumed to sized by a terminating nul.
 413  * Return lexical ordering of *s1:*s2.
 414  */
 415 static int sstrcmp(const char *s1, const char *e1, const char *s2,
 416     const char *e2)
 417 {
 418     for (;;) {
 419         if (!*s1 || !*s2 || *s1 != *s2)
 420             return (*s1 - *s2);
 421         ++s1, ++s2;
 422         if (s1 == e1 && s2 == e2)
 423             return (0);
 424         else if (s1 == e1)
 425             return (*s2);
 426         else if (s2 == e2)
 427             return (*s1);
 428     }
 429 }
 430
 431 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 432  * '|' delimited (possibly empty) strings in which case search for a match
 433  * within the alternatives proceeds left to right.  Return 0 for success,
 434  * non-zero otherwise.
 435  */
 436 static int altcmp(const char *s, const char *e, const char *altstr)
 437 {
 438     const char *p, *q;
 439
 440     for (q = p = altstr; ; ) {
 441         while (*p && *p != '|')
 442             ++p;
 443         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 444             return (0);
 445         if (!*p)
 446             return (1);
 447         else
 448             q = ++p;
 449     }
 450 }
 451
 452 /* search featureset for flag *[s..e), if found set corresponding bit in
 453  * *pval and return true, otherwise return false
 454  */
 455 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 456                            const char **featureset)
 457 {
 458     uint32_t mask;
 459     const char **ppc;
 460     bool found = false;
 461
 462     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 463         if (*ppc && !altcmp(s, e, *ppc)) {
 464             *pval |= mask;
 465             found = true;
 466         }
 467     }
 468     return found;
 469 }
 470
 471 static void add_flagname_to_bitmaps(const char *flagname,
 472                                     FeatureWordArray words)
 473 {
 474     FeatureWord w;
 475     for (w = 0; w < FEATURE_WORDS; w++) {
 476         FeatureWordInfo *wi = &feature_word_info[w];
 477         if (wi->feat_names &&
 478             lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
 479             break;
 480         }
 481     }
 482     if (w == FEATURE_WORDS) {
 483         fprintf(stderr, "CPU feature %s not found\n", flagname);
 484     }
 485 }
 486
 487 typedef struct X86CPUDefinition {
 488     const char *name;
 489     uint32_t level;
 490     uint32_t xlevel;
 491     uint32_t xlevel2;
 492     /* vendor is zero-terminated, 12 character ASCII string */
 493     char vendor[CPUID_VENDOR_SZ + 1];
 494     int family;
 495     int model;
 496     int stepping;
 497     FeatureWordArray features;
 498     char model_id[48];
 499     bool cache_info_passthrough;
 500 } X86CPUDefinition;
 501
 502 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 503 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 504           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 505 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 506           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 507           CPUID_PSE36 | CPUID_FXSR)
 508 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 509 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 510           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 511           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 512           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 513
 514 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 515           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 516           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 517           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 518           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
 519           /* partly implemented:
 520           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
 521           CPUID_PSE36 (needed for Solaris) */
 522           /* missing:
 523           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 524 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 525           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 526           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 527           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
 528           /* missing:
 529           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 530           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 531           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 532           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
 533           CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
 534           CPUID_EXT_RDRAND */
 535 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 536           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 537           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
 538           /* missing:
 539           CPUID_EXT2_PDPE1GB */
 540 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 541           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 542 #define TCG_SVM_FEATURES 0
 543 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
 544           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
 545           /* missing:
 546           CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 547           CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 548           CPUID_7_0_EBX_RDSEED */
 549
 550 /* built-in CPU model definitions
 551  */
 552 static X86CPUDefinition builtin_x86_defs[] = {
 553     {
 554         .name = "qemu64",
 555         .level = 4,
 556         .vendor = CPUID_VENDOR_AMD,
 557         .family = 6,
 558         .model = 6,
 559         .stepping = 3,
 560         .features[FEAT_1_EDX] =
 561             PPRO_FEATURES |
 562             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 563             CPUID_PSE36,
 564         .features[FEAT_1_ECX] =
 565             CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
 566         .features[FEAT_8000_0001_EDX] =
 567             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 568             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 569         .features[FEAT_8000_0001_ECX] =
 570             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 571             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 572         .xlevel = 0x8000000A,
 573     },
 574     {
 575         .name = "phenom",
 576         .level = 5,
 577         .vendor = CPUID_VENDOR_AMD,
 578         .family = 16,
 579         .model = 2,
 580         .stepping = 3,
 581         .features[FEAT_1_EDX] =
 582             PPRO_FEATURES |
 583             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 584             CPUID_PSE36 | CPUID_VME | CPUID_HT,
 585         .features[FEAT_1_ECX] =
 586             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 587             CPUID_EXT_POPCNT,
 588         .features[FEAT_8000_0001_EDX] =
 589             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 590             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 591             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 592             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 593         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 594                     CPUID_EXT3_CR8LEG,
 595                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 596                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 597         .features[FEAT_8000_0001_ECX] =
 598             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 599             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 600         .features[FEAT_SVM] =
 601             CPUID_SVM_NPT | CPUID_SVM_LBRV,
 602         .xlevel = 0x8000001A,
 603         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 604     },
 605     {
 606         .name = "core2duo",
 607         .level = 10,
 608         .vendor = CPUID_VENDOR_INTEL,
 609         .family = 6,
 610         .model = 15,
 611         .stepping = 11,
 612         .features[FEAT_1_EDX] =
 613             PPRO_FEATURES |
 614             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 615             CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
 616             CPUID_HT | CPUID_TM | CPUID_PBE,
 617         .features[FEAT_1_ECX] =
 618             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 619             CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
 620             CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 621         .features[FEAT_8000_0001_EDX] =
 622             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 623         .features[FEAT_8000_0001_ECX] =
 624             CPUID_EXT3_LAHF_LM,
 625         .xlevel = 0x80000008,
 626         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 627     },
 628     {
 629         .name = "kvm64",
 630         .level = 5,
 631         .vendor = CPUID_VENDOR_INTEL,
 632         .family = 15,
 633         .model = 6,
 634         .stepping = 1,
 635         /* Missing: CPUID_VME, CPUID_HT */
 636         .features[FEAT_1_EDX] =
 637             PPRO_FEATURES |
 638             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 639             CPUID_PSE36,
 640         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 641         .features[FEAT_1_ECX] =
 642             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 643         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 644         .features[FEAT_8000_0001_EDX] =
 645             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 646             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 647         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 648                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 649                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 650                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 651         .features[FEAT_8000_0001_ECX] =
 652             0,
 653         .xlevel = 0x80000008,
 654         .model_id = "Common KVM processor"
 655     },
 656     {
 657         .name = "qemu32",
 658         .level = 4,
 659         .vendor = CPUID_VENDOR_INTEL,
 660         .family = 6,
 661         .model = 6,
 662         .stepping = 3,
 663         .features[FEAT_1_EDX] =
 664             PPRO_FEATURES,
 665         .features[FEAT_1_ECX] =
 666             CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
 667         .xlevel = 0x80000004,
 668     },
 669     {
 670         .name = "kvm32",
 671         .level = 5,
 672         .vendor = CPUID_VENDOR_INTEL,
 673         .family = 15,
 674         .model = 6,
 675         .stepping = 1,
 676         .features[FEAT_1_EDX] =
 677             PPRO_FEATURES |
 678             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 679         .features[FEAT_1_ECX] =
 680             CPUID_EXT_SSE3,
 681         .features[FEAT_8000_0001_EDX] =
 682             PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
 683         .features[FEAT_8000_0001_ECX] =
 684             0,
 685         .xlevel = 0x80000008,
 686         .model_id = "Common 32-bit KVM processor"
 687     },
 688     {
 689         .name = "coreduo",
 690         .level = 10,
 691         .vendor = CPUID_VENDOR_INTEL,
 692         .family = 6,
 693         .model = 14,
 694         .stepping = 8,
 695         .features[FEAT_1_EDX] =
 696             PPRO_FEATURES | CPUID_VME |
 697             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
 698             CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 699         .features[FEAT_1_ECX] =
 700             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
 701             CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 702         .features[FEAT_8000_0001_EDX] =
 703             CPUID_EXT2_NX,
 704         .xlevel = 0x80000008,
 705         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 706     },
 707     {
 708         .name = "486",
 709         .level = 1,
 710         .vendor = CPUID_VENDOR_INTEL,
 711         .family = 4,
 712         .model = 8,
 713         .stepping = 0,
 714         .features[FEAT_1_EDX] =
 715             I486_FEATURES,
 716         .xlevel = 0,
 717     },
 718     {
 719         .name = "pentium",
 720         .level = 1,
 721         .vendor = CPUID_VENDOR_INTEL,
 722         .family = 5,
 723         .model = 4,
 724         .stepping = 3,
 725         .features[FEAT_1_EDX] =
 726             PENTIUM_FEATURES,
 727         .xlevel = 0,
 728     },
 729     {
 730         .name = "pentium2",
 731         .level = 2,
 732         .vendor = CPUID_VENDOR_INTEL,
 733         .family = 6,
 734         .model = 5,
 735         .stepping = 2,
 736         .features[FEAT_1_EDX] =
 737             PENTIUM2_FEATURES,
 738         .xlevel = 0,
 739     },
 740     {
 741         .name = "pentium3",
 742         .level = 2,
 743         .vendor = CPUID_VENDOR_INTEL,
 744         .family = 6,
 745         .model = 7,
 746         .stepping = 3,
 747         .features[FEAT_1_EDX] =
 748             PENTIUM3_FEATURES,
 749         .xlevel = 0,
 750     },
 751     {
 752         .name = "athlon",
 753         .level = 2,
 754         .vendor = CPUID_VENDOR_AMD,
 755         .family = 6,
 756         .model = 2,
 757         .stepping = 3,
 758         .features[FEAT_1_EDX] =
 759             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 760             CPUID_MCA,
 761         .features[FEAT_8000_0001_EDX] =
 762             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 763             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 764         .xlevel = 0x80000008,
 765     },
 766     {
 767         .name = "n270",
 768         /* original is on level 10 */
 769         .level = 5,
 770         .vendor = CPUID_VENDOR_INTEL,
 771         .family = 6,
 772         .model = 28,
 773         .stepping = 2,
 774         .features[FEAT_1_EDX] =
 775             PPRO_FEATURES |
 776             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
 777             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 778             /* Some CPUs got no CPUID_SEP */
 779         .features[FEAT_1_ECX] =
 780             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 781             CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
 782             CPUID_EXT_MOVBE,
 783         .features[FEAT_8000_0001_EDX] =
 784             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 785             CPUID_EXT2_NX,
 786         .features[FEAT_8000_0001_ECX] =
 787             CPUID_EXT3_LAHF_LM,
 788         .xlevel = 0x8000000A,
 789         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 790     },
 791     {
 792         .name = "Conroe",
 793         .level = 4,
 794         .vendor = CPUID_VENDOR_INTEL,
 795         .family = 6,
 796         .model = 15,
 797         .stepping = 3,
 798         .features[FEAT_1_EDX] =
 799             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 800              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 801              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 802              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 803              CPUID_DE | CPUID_FP87,
 804         .features[FEAT_1_ECX] =
 805             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 806         .features[FEAT_8000_0001_EDX] =
 807             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 808         .features[FEAT_8000_0001_ECX] =
 809             CPUID_EXT3_LAHF_LM,
 810         .xlevel = 0x8000000A,
 811         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 812     },
 813     {
 814         .name = "Penryn",
 815         .level = 4,
 816         .vendor = CPUID_VENDOR_INTEL,
 817         .family = 6,
 818         .model = 23,
 819         .stepping = 3,
 820         .features[FEAT_1_EDX] =
 821             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 822              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 823              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 824              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 825              CPUID_DE | CPUID_FP87,
 826         .features[FEAT_1_ECX] =
 827             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 828              CPUID_EXT_SSE3,
 829         .features[FEAT_8000_0001_EDX] =
 830             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 831         .features[FEAT_8000_0001_ECX] =
 832             CPUID_EXT3_LAHF_LM,
 833         .xlevel = 0x8000000A,
 834         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 835     },
 836     {
 837         .name = "Nehalem",
 838         .level = 4,
 839         .vendor = CPUID_VENDOR_INTEL,
 840         .family = 6,
 841         .model = 26,
 842         .stepping = 3,
 843         .features[FEAT_1_EDX] =
 844             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 845              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 846              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 847              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 848              CPUID_DE | CPUID_FP87,
 849         .features[FEAT_1_ECX] =
 850             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 851              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 852         .features[FEAT_8000_0001_EDX] =
 853             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 854         .features[FEAT_8000_0001_ECX] =
 855             CPUID_EXT3_LAHF_LM,
 856         .xlevel = 0x8000000A,
 857         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 858     },
 859     {
 860         .name = "Westmere",
 861         .level = 11,
 862         .vendor = CPUID_VENDOR_INTEL,
 863         .family = 6,
 864         .model = 44,
 865         .stepping = 1,
 866         .features[FEAT_1_EDX] =
 867             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 868              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 869              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 870              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 871              CPUID_DE | CPUID_FP87,
 872         .features[FEAT_1_ECX] =
 873             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 874              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 875              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 876         .features[FEAT_8000_0001_EDX] =
 877             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 878         .features[FEAT_8000_0001_ECX] =
 879             CPUID_EXT3_LAHF_LM,
 880         .xlevel = 0x8000000A,
 881         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 882     },
 883     {
 884         .name = "SandyBridge",
 885         .level = 0xd,
 886         .vendor = CPUID_VENDOR_INTEL,
 887         .family = 6,
 888         .model = 42,
 889         .stepping = 1,
 890         .features[FEAT_1_EDX] =
 891             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 892              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 893              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 894              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 895              CPUID_DE | CPUID_FP87,
 896         .features[FEAT_1_ECX] =
 897             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 898              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
 899              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 900              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 901              CPUID_EXT_SSE3,
 902         .features[FEAT_8000_0001_EDX] =
 903             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 904              CPUID_EXT2_SYSCALL,
 905         .features[FEAT_8000_0001_ECX] =
 906             CPUID_EXT3_LAHF_LM,
 907         .xlevel = 0x8000000A,
 908         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
 909     },
 910     {
 911         .name = "Haswell",
 912         .level = 0xd,
 913         .vendor = CPUID_VENDOR_INTEL,
 914         .family = 6,
 915         .model = 60,
 916         .stepping = 1,
 917         .features[FEAT_1_EDX] =
 918             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 919              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 920              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 921              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 922              CPUID_DE | CPUID_FP87,
 923         .features[FEAT_1_ECX] =
 924             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 925              CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
 926              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 927              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
 928              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
 929              CPUID_EXT_PCID,
 930         .features[FEAT_8000_0001_EDX] =
 931             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 932              CPUID_EXT2_SYSCALL,
 933         .features[FEAT_8000_0001_ECX] =
 934             CPUID_EXT3_LAHF_LM,
 935         .features[FEAT_7_0_EBX] =
 936             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
 937             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
 938             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
 939             CPUID_7_0_EBX_RTM,
 940         .xlevel = 0x8000000A,
 941         .model_id = "Intel Core Processor (Haswell)",
 942     },
 943     {
 944         .name = "Opteron_G1",
 945         .level = 5,
 946         .vendor = CPUID_VENDOR_AMD,
 947         .family = 15,
 948         .model = 6,
 949         .stepping = 1,
 950         .features[FEAT_1_EDX] =
 951             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 952              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 953              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 954              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 955              CPUID_DE | CPUID_FP87,
 956         .features[FEAT_1_ECX] =
 957             CPUID_EXT_SSE3,
 958         .features[FEAT_8000_0001_EDX] =
 959             CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 960              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 961              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 962              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 963              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 964              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 965         .xlevel = 0x80000008,
 966         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
 967     },
 968     {
 969         .name = "Opteron_G2",
 970         .level = 5,
 971         .vendor = CPUID_VENDOR_AMD,
 972         .family = 15,
 973         .model = 6,
 974         .stepping = 1,
 975         .features[FEAT_1_EDX] =
 976             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 977              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 978              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 979              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 980              CPUID_DE | CPUID_FP87,
 981         .features[FEAT_1_ECX] =
 982             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
 983         .features[FEAT_8000_0001_EDX] =
 984             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 985              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 986              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 987              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 988              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 989              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 990              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 991         .features[FEAT_8000_0001_ECX] =
 992             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 993         .xlevel = 0x80000008,
 994         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
 995     },
 996     {
 997         .name = "Opteron_G3",
 998         .level = 5,
 999         .vendor = CPUID_VENDOR_AMD,
1000         .family = 15,
1001         .model = 6,
1002         .stepping = 1,
1003         .features[FEAT_1_EDX] =
1004             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1005              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1006              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1007              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1008              CPUID_DE | CPUID_FP87,
1009         .features[FEAT_1_ECX] =
1010             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1011              CPUID_EXT_SSE3,
1012         .features[FEAT_8000_0001_EDX] =
1013             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1014              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1015              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1016              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1017              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1018              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1019              CPUID_EXT2_DE | CPUID_EXT2_FPU,
1020         .features[FEAT_8000_0001_ECX] =
1021             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1022              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1023         .xlevel = 0x80000008,
1024         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1025     },
1026     {
1027         .name = "Opteron_G4",
1028         .level = 0xd,
1029         .vendor = CPUID_VENDOR_AMD,
1030         .family = 21,
1031         .model = 1,
1032         .stepping = 2,
1033         .features[FEAT_1_EDX] =
1034             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1035              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1036              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1037              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1038              CPUID_DE | CPUID_FP87,
1039         .features[FEAT_1_ECX] =
1040             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1041              CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1042              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1043              CPUID_EXT_SSE3,
1044         .features[FEAT_8000_0001_EDX] =
1045             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1046              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1047              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1048              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1049              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1050              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1051              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1052         .features[FEAT_8000_0001_ECX] =
1053             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1054              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1055              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1056              CPUID_EXT3_LAHF_LM,
1057         .xlevel = 0x8000001A,
1058         .model_id = "AMD Opteron 62xx class CPU",
1059     },
1060     {
1061         .name = "Opteron_G5",
1062         .level = 0xd,
1063         .vendor = CPUID_VENDOR_AMD,
1064         .family = 21,
1065         .model = 2,
1066         .stepping = 0,
1067         .features[FEAT_1_EDX] =
1068             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1069              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1070              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1071              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1072              CPUID_DE | CPUID_FP87,
1073         .features[FEAT_1_ECX] =
1074             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1075              CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1076              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1077              CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1078         .features[FEAT_8000_0001_EDX] =
1079             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1080              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1081              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1082              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1083              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1084              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1085              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1086         .features[FEAT_8000_0001_ECX] =
1087             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1088              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1089              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1090              CPUID_EXT3_LAHF_LM,
1091         .xlevel = 0x8000001A,
1092         .model_id = "AMD Opteron 63xx class CPU",
1093     },
1094 };
1095
1096 /**
1097  * x86_cpu_compat_set_features:
1098  * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1099  * @w: Identifies the feature word to be changed.
1100  * @feat_add: Feature bits to be added to feature word
1101  * @feat_remove: Feature bits to be removed from feature word
1102  *
1103  * Change CPU model feature bits for compatibility.
1104  *
1105  * This function may be used by machine-type compatibility functions
1106  * to enable or disable feature bits on specific CPU models.
1107  */
1108 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1109                                  uint32_t feat_add, uint32_t feat_remove)
1110 {
1111     X86CPUDefinition *def;
1112     int i;
1113     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1114         def = &builtin_x86_defs[i];
1115         if (!cpu_model || !strcmp(cpu_model, def->name)) {
1116             def->features[w] |= feat_add;
1117             def->features[w] &= ~feat_remove;
1118         }
1119     }
1120 }
1121
1122 static int cpu_x86_fill_model_id(char *str)
1123 {
1124     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1125     int i;
1126
1127     for (i = 0; i < 3; i++) {
1128         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1129         memcpy(str + i * 16 +  0, &eax, 4);
1130         memcpy(str + i * 16 +  4, &ebx, 4);
1131         memcpy(str + i * 16 +  8, &ecx, 4);
1132         memcpy(str + i * 16 + 12, &edx, 4);
1133     }
1134     return 0;
1135 }
1136
1137 /* Fill a X86CPUDefinition struct with information about the host CPU, and
1138  * the CPU features supported by the host hardware + host kernel
1139  *
1140  * This function may be called only if KVM is enabled.
1141  */
1142 static void kvm_cpu_fill_host(X86CPUDefinition *x86_cpu_def)
1143 {
1144     KVMState *s = kvm_state;
1145     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1146
1147     assert(kvm_enabled());
1148
1149     x86_cpu_def->name = "host";
1150     x86_cpu_def->cache_info_passthrough = true;
1151     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1152     x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1153
1154     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1155     x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1156     x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1157     x86_cpu_def->stepping = eax & 0x0F;
1158
1159     x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1160     x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1161     x86_cpu_def->xlevel2 =
1162         kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1163
1164     cpu_x86_fill_model_id(x86_cpu_def->model_id);
1165
1166     FeatureWord w;
1167     for (w = 0; w < FEATURE_WORDS; w++) {
1168         FeatureWordInfo *wi = &feature_word_info[w];
1169         x86_cpu_def->features[w] =
1170             kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1171                                          wi->cpuid_reg);
1172     }
1173 }
1174
1175 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1176 {
1177     int i;
1178
1179     for (i = 0; i < 32; ++i)
1180         if (1 << i & mask) {
1181             const char *reg = get_register_name_32(f->cpuid_reg);
1182             assert(reg);
1183             fprintf(stderr, "warning: host doesn't support requested feature: "
1184                 "CPUID.%02XH:%s%s%s [bit %d]\n",
1185                 f->cpuid_eax, reg,
1186                 f->feat_names[i] ? "." : "",
1187                 f->feat_names[i] ? f->feat_names[i] : "", i);
1188             break;
1189         }
1190     return 0;
1191 }
1192
1193 /* Check if all requested cpu flags are making their way to the guest
1194  *
1195  * Returns 0 if all flags are supported by the host, non-zero otherwise.
1196  *
1197  * This function may be called only if KVM is enabled.
1198  */
1199 static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
1200 {
1201     CPUX86State *env = &cpu->env;
1202     int rv = 0;
1203     FeatureWord w;
1204
1205     assert(kvm_enabled());
1206
1207     for (w = 0; w < FEATURE_WORDS; w++) {
1208         FeatureWordInfo *wi = &feature_word_info[w];
1209         uint32_t guest_feat = env->features[w];
1210         uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1211                                                              wi->cpuid_ecx,
1212                                                              wi->cpuid_reg);
1213         uint32_t mask;
1214         for (mask = 1; mask; mask <<= 1) {
1215             if (guest_feat & mask && !(host_feat & mask)) {
1216                 unavailable_host_feature(wi, mask);
1217                 rv = 1;
1218             }
1219         }
1220     }
1221     return rv;
1222 }
1223
1224 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1225                                          const char *name, Error **errp)
1226 {
1227     X86CPU *cpu = X86_CPU(obj);
1228     CPUX86State *env = &cpu->env;
1229     int64_t value;
1230
1231     value = (env->cpuid_version >> 8) & 0xf;
1232     if (value == 0xf) {
1233         value += (env->cpuid_version >> 20) & 0xff;
1234     }
1235     visit_type_int(v, &value, name, errp);
1236 }
1237
1238 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1239                                          const char *name, Error **errp)
1240 {
1241     X86CPU *cpu = X86_CPU(obj);
1242     CPUX86State *env = &cpu->env;
1243     const int64_t min = 0;
1244     const int64_t max = 0xff + 0xf;
1245     int64_t value;
1246
1247     visit_type_int(v, &value, name, errp);
1248     if (error_is_set(errp)) {
1249         return;
1250     }
1251     if (value < min || value > max) {
1252         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1253                   name ? name : "null", value, min, max);
1254         return;
1255     }
1256
1257     env->cpuid_version &= ~0xff00f00;
1258     if (value > 0x0f) {
1259         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1260     } else {
1261         env->cpuid_version |= value << 8;
1262     }
1263 }
1264
1265 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1266                                         const char *name, Error **errp)
1267 {
1268     X86CPU *cpu = X86_CPU(obj);
1269     CPUX86State *env = &cpu->env;
1270     int64_t value;
1271
1272     value = (env->cpuid_version >> 4) & 0xf;
1273     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1274     visit_type_int(v, &value, name, errp);
1275 }
1276
1277 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1278                                         const char *name, Error **errp)
1279 {
1280     X86CPU *cpu = X86_CPU(obj);
1281     CPUX86State *env = &cpu->env;
1282     const int64_t min = 0;
1283     const int64_t max = 0xff;
1284     int64_t value;
1285
1286     visit_type_int(v, &value, name, errp);
1287     if (error_is_set(errp)) {
1288         return;
1289     }
1290     if (value < min || value > max) {
1291         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1292                   name ? name : "null", value, min, max);
1293         return;
1294     }
1295
1296     env->cpuid_version &= ~0xf00f0;
1297     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1298 }
1299
1300 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1301                                            void *opaque, const char *name,
1302                                            Error **errp)
1303 {
1304     X86CPU *cpu = X86_CPU(obj);
1305     CPUX86State *env = &cpu->env;
1306     int64_t value;
1307
1308     value = env->cpuid_version & 0xf;
1309     visit_type_int(v, &value, name, errp);
1310 }
1311
1312 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1313                                            void *opaque, const char *name,
1314                                            Error **errp)
1315 {
1316     X86CPU *cpu = X86_CPU(obj);
1317     CPUX86State *env = &cpu->env;
1318     const int64_t min = 0;
1319     const int64_t max = 0xf;
1320     int64_t value;
1321
1322     visit_type_int(v, &value, name, errp);
1323     if (error_is_set(errp)) {
1324         return;
1325     }
1326     if (value < min || value > max) {
1327         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1328                   name ? name : "null", value, min, max);
1329         return;
1330     }
1331
1332     env->cpuid_version &= ~0xf;
1333     env->cpuid_version |= value & 0xf;
1334 }
1335
1336 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1337                                 const char *name, Error **errp)
1338 {
1339     X86CPU *cpu = X86_CPU(obj);
1340
1341     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1342 }
1343
1344 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1345                                 const char *name, Error **errp)
1346 {
1347     X86CPU *cpu = X86_CPU(obj);
1348
1349     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1350 }
1351
1352 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1353                                  const char *name, Error **errp)
1354 {
1355     X86CPU *cpu = X86_CPU(obj);
1356
1357     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1358 }
1359
1360 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1361                                  const char *name, Error **errp)
1362 {
1363     X86CPU *cpu = X86_CPU(obj);
1364
1365     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1366 }
1367
1368 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1369 {
1370     X86CPU *cpu = X86_CPU(obj);
1371     CPUX86State *env = &cpu->env;
1372     char *value;
1373
1374     value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1375     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1376                              env->cpuid_vendor3);
1377     return value;
1378 }
1379
1380 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1381                                  Error **errp)
1382 {
1383     X86CPU *cpu = X86_CPU(obj);
1384     CPUX86State *env = &cpu->env;
1385     int i;
1386
1387     if (strlen(value) != CPUID_VENDOR_SZ) {
1388         error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1389                   "vendor", value);
1390         return;
1391     }
1392
1393     env->cpuid_vendor1 = 0;
1394     env->cpuid_vendor2 = 0;
1395     env->cpuid_vendor3 = 0;
1396     for (i = 0; i < 4; i++) {
1397         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1398         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1399         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1400     }
1401 }
1402
1403 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1404 {
1405     X86CPU *cpu = X86_CPU(obj);
1406     CPUX86State *env = &cpu->env;
1407     char *value;
1408     int i;
1409
1410     value = g_malloc(48 + 1);
1411     for (i = 0; i < 48; i++) {
1412         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1413     }
1414     value[48] = '\0';
1415     return value;
1416 }
1417
1418 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1419                                    Error **errp)
1420 {
1421     X86CPU *cpu = X86_CPU(obj);
1422     CPUX86State *env = &cpu->env;
1423     int c, len, i;
1424
1425     if (model_id == NULL) {
1426         model_id = "";
1427     }
1428     len = strlen(model_id);
1429     memset(env->cpuid_model, 0, 48);
1430     for (i = 0; i < 48; i++) {
1431         if (i >= len) {
1432             c = '\0';
1433         } else {
1434             c = (uint8_t)model_id[i];
1435         }
1436         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1437     }
1438 }
1439
1440 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1441                                    const char *name, Error **errp)
1442 {
1443     X86CPU *cpu = X86_CPU(obj);
1444     int64_t value;
1445
1446     value = cpu->env.tsc_khz * 1000;
1447     visit_type_int(v, &value, name, errp);
1448 }
1449
1450 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1451                                    const char *name, Error **errp)
1452 {
1453     X86CPU *cpu = X86_CPU(obj);
1454     const int64_t min = 0;
1455     const int64_t max = INT64_MAX;
1456     int64_t value;
1457
1458     visit_type_int(v, &value, name, errp);
1459     if (error_is_set(errp)) {
1460         return;
1461     }
1462     if (value < min || value > max) {
1463         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1464                   name ? name : "null", value, min, max);
1465         return;
1466     }
1467
1468     cpu->env.tsc_khz = value / 1000;
1469 }
1470
1471 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1472                                   const char *name, Error **errp)
1473 {
1474     X86CPU *cpu = X86_CPU(obj);
1475     int64_t value = cpu->env.cpuid_apic_id;
1476
1477     visit_type_int(v, &value, name, errp);
1478 }
1479
1480 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1481                                   const char *name, Error **errp)
1482 {
1483     X86CPU *cpu = X86_CPU(obj);
1484     DeviceState *dev = DEVICE(obj);
1485     const int64_t min = 0;
1486     const int64_t max = UINT32_MAX;
1487     Error *error = NULL;
1488     int64_t value;
1489
1490     if (dev->realized) {
1491         error_setg(errp, "Attempt to set property '%s' on '%s' after "
1492                    "it was realized", name, object_get_typename(obj));
1493         return;
1494     }
1495
1496     visit_type_int(v, &value, name, &error);
1497     if (error) {
1498         error_propagate(errp, error);
1499         return;
1500     }
1501     if (value < min || value > max) {
1502         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1503                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1504                    object_get_typename(obj), name, value, min, max);
1505         return;
1506     }
1507
1508     if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1509         error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1510         return;
1511     }
1512     cpu->env.cpuid_apic_id = value;
1513 }
1514
1515 /* Generic getter for "feature-words" and "filtered-features" properties */
1516 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1517                                       const char *name, Error **errp)
1518 {
1519     uint32_t *array = (uint32_t *)opaque;
1520     FeatureWord w;
1521     Error *err = NULL;
1522     X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1523     X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1524     X86CPUFeatureWordInfoList *list = NULL;
1525
1526     for (w = 0; w < FEATURE_WORDS; w++) {
1527         FeatureWordInfo *wi = &feature_word_info[w];
1528         X86CPUFeatureWordInfo *qwi = &word_infos[w];
1529         qwi->cpuid_input_eax = wi->cpuid_eax;
1530         qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1531         qwi->cpuid_input_ecx = wi->cpuid_ecx;
1532         qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1533         qwi->features = array[w];
1534
1535         /* List will be in reverse order, but order shouldn't matter */
1536         list_entries[w].next = list;
1537         list_entries[w].value = &word_infos[w];
1538         list = &list_entries[w];
1539     }
1540
1541     visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1542     error_propagate(errp, err);
1543 }
1544
1545 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1546                                  const char *name, Error **errp)
1547 {
1548     X86CPU *cpu = X86_CPU(obj);
1549     int64_t value = cpu->hyperv_spinlock_attempts;
1550
1551     visit_type_int(v, &value, name, errp);
1552 }
1553
1554 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1555                                  const char *name, Error **errp)
1556 {
1557     const int64_t min = 0xFFF;
1558     const int64_t max = UINT_MAX;
1559     X86CPU *cpu = X86_CPU(obj);
1560     Error *err = NULL;
1561     int64_t value;
1562
1563     visit_type_int(v, &value, name, &err);
1564     if (err) {
1565         error_propagate(errp, err);
1566         return;
1567     }
1568
1569     if (value < min || value > max) {
1570         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1571                   " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1572                   object_get_typename(obj), name ? name : "null",
1573                   value, min, max);
1574         return;
1575     }
1576     cpu->hyperv_spinlock_attempts = value;
1577 }
1578
1579 static PropertyInfo qdev_prop_spinlocks = {
1580     .name  = "int",
1581     .get   = x86_get_hv_spinlocks,
1582     .set   = x86_set_hv_spinlocks,
1583 };
1584
1585 static int cpu_x86_find_by_name(X86CPU *cpu, X86CPUDefinition *x86_cpu_def,
1586                                 const char *name)
1587 {
1588     X86CPUDefinition *def;
1589     int i;
1590
1591     if (name == NULL) {
1592         return -1;
1593     }
1594     if (kvm_enabled() && strcmp(name, "host") == 0) {
1595         kvm_cpu_fill_host(x86_cpu_def);
1596         object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1597         return 0;
1598     }
1599
1600     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1601         def = &builtin_x86_defs[i];
1602         if (strcmp(name, def->name) == 0) {
1603             memcpy(x86_cpu_def, def, sizeof(*def));
1604             return 0;
1605         }
1606     }
1607
1608     return -1;
1609 }
1610
1611 /* Convert all '_' in a feature string option name to '-', to make feature
1612  * name conform to QOM property naming rule, which uses '-' instead of '_'.
1613  */
1614 static inline void feat2prop(char *s)
1615 {
1616     while ((s = strchr(s, '_'))) {
1617         *s = '-';
1618     }
1619 }
1620
1621 /* Parse "+feature,-feature,feature=foo" CPU feature string
1622  */
1623 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1624 {
1625     char *featurestr; /* Single 'key=value" string being parsed */
1626     /* Features to be added */
1627     FeatureWordArray plus_features = { 0 };
1628     /* Features to be removed */
1629     FeatureWordArray minus_features = { 0 };
1630     uint32_t numvalue;
1631     CPUX86State *env = &cpu->env;
1632
1633     featurestr = features ? strtok(features, ",") : NULL;
1634
1635     while (featurestr) {
1636         char *val;
1637         if (featurestr[0] == '+') {
1638             add_flagname_to_bitmaps(featurestr + 1, plus_features);
1639         } else if (featurestr[0] == '-') {
1640             add_flagname_to_bitmaps(featurestr + 1, minus_features);
1641         } else if ((val = strchr(featurestr, '='))) {
1642             *val = 0; val++;
1643             feat2prop(featurestr);
1644             if (!strcmp(featurestr, "xlevel")) {
1645                 char *err;
1646                 char num[32];
1647
1648                 numvalue = strtoul(val, &err, 0);
1649                 if (!*val || *err) {
1650                     error_setg(errp, "bad numerical value %s", val);
1651                     goto out;
1652                 }
1653                 if (numvalue < 0x80000000) {
1654                     fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1655                             ", fixup will be removed in future versions\n");
1656                     numvalue += 0x80000000;
1657                 }
1658                 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1659                 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1660             } else if (!strcmp(featurestr, "tsc-freq")) {
1661                 int64_t tsc_freq;
1662                 char *err;
1663                 char num[32];
1664
1665                 tsc_freq = strtosz_suffix_unit(val, &err,
1666                                                STRTOSZ_DEFSUFFIX_B, 1000);
1667                 if (tsc_freq < 0 || *err) {
1668                     error_setg(errp, "bad numerical value %s", val);
1669                     goto out;
1670                 }
1671                 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1672                 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1673             } else if (!strcmp(featurestr, "hv-spinlocks")) {
1674                 char *err;
1675                 const int min = 0xFFF;
1676                 char num[32];
1677                 numvalue = strtoul(val, &err, 0);
1678                 if (!*val || *err) {
1679                     error_setg(errp, "bad numerical value %s", val);
1680                     goto out;
1681                 }
1682                 if (numvalue < min) {
1683                     fprintf(stderr, "hv-spinlocks value shall always be >= 0x%x"
1684                             ", fixup will be removed in future versions\n",
1685                             min);
1686                     numvalue = min;
1687                 }
1688                 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1689                 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1690             } else {
1691                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1692             }
1693         } else {
1694             feat2prop(featurestr);
1695             object_property_parse(OBJECT(cpu), "on", featurestr, errp);
1696         }
1697         if (error_is_set(errp)) {
1698             goto out;
1699         }
1700         featurestr = strtok(NULL, ",");
1701     }
1702     env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1703     env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1704     env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1705     env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1706     env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1707     env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1708     env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1709     env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1710     env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1711     env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1712     env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1713     env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1714     env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1715     env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1716     env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1717     env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1718
1719 out:
1720     return;
1721 }
1722
1723 /* generate a composite string into buf of all cpuid names in featureset
1724  * selected by fbits.  indicate truncation at bufsize in the event of overflow.
1725  * if flags, suppress names undefined in featureset.
1726  */
1727 static void listflags(char *buf, int bufsize, uint32_t fbits,
1728     const char **featureset, uint32_t flags)
1729 {
1730     const char **p = &featureset[31];
1731     char *q, *b, bit;
1732     int nc;
1733
1734     b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1735     *buf = '\0';
1736     for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1737         if (fbits & 1 << bit && (*p || !flags)) {
1738             if (*p)
1739                 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1740             else
1741                 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1742             if (bufsize <= nc) {
1743                 if (b) {
1744                     memcpy(b, "...", sizeof("..."));
1745                 }
1746                 return;
1747             }
1748             q += nc;
1749             bufsize -= nc;
1750         }
1751 }
1752
1753 /* generate CPU information. */
1754 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1755 {
1756     X86CPUDefinition *def;
1757     char buf[256];
1758     int i;
1759
1760     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1761         def = &builtin_x86_defs[i];
1762         snprintf(buf, sizeof(buf), "%s", def->name);
1763         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1764     }
1765 #ifdef CONFIG_KVM
1766     (*cpu_fprintf)(f, "x86 %16s  %-48s\n", "host",
1767                    "KVM processor with all supported host features "
1768                    "(only available in KVM mode)");
1769 #endif
1770
1771     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1772     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1773         FeatureWordInfo *fw = &feature_word_info[i];
1774
1775         listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1776         (*cpu_fprintf)(f, "  %s\n", buf);
1777     }
1778 }
1779
1780 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1781 {
1782     CpuDefinitionInfoList *cpu_list = NULL;
1783     X86CPUDefinition *def;
1784     int i;
1785
1786     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1787         CpuDefinitionInfoList *entry;
1788         CpuDefinitionInfo *info;
1789
1790         def = &builtin_x86_defs[i];
1791         info = g_malloc0(sizeof(*info));
1792         info->name = g_strdup(def->name);
1793
1794         entry = g_malloc0(sizeof(*entry));
1795         entry->value = info;
1796         entry->next = cpu_list;
1797         cpu_list = entry;
1798     }
1799
1800     return cpu_list;
1801 }
1802
1803 static void filter_features_for_kvm(X86CPU *cpu)
1804 {
1805     CPUX86State *env = &cpu->env;
1806     KVMState *s = kvm_state;
1807     FeatureWord w;
1808
1809     for (w = 0; w < FEATURE_WORDS; w++) {
1810         FeatureWordInfo *wi = &feature_word_info[w];
1811         uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1812                                                              wi->cpuid_ecx,
1813                                                              wi->cpuid_reg);
1814         uint32_t requested_features = env->features[w];
1815         env->features[w] &= host_feat;
1816         cpu->filtered_features[w] = requested_features & ~env->features[w];
1817     }
1818 }
1819
1820 /* Load CPU definition for a given CPU model name
1821  */
1822 static void x86_cpu_load_def(X86CPU *cpu, const char *name, Error **errp)
1823 {
1824     CPUX86State *env = &cpu->env;
1825     X86CPUDefinition def1, *def = &def1;
1826
1827     memset(def, 0, sizeof(*def));
1828
1829     if (cpu_x86_find_by_name(cpu, def, name) < 0) {
1830         error_setg(errp, "Unable to find CPU definition: %s", name);
1831         return;
1832     }
1833
1834     object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1835     object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1836     object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1837     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1838     env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1839     env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1840     env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1841     env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1842     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1843     env->features[FEAT_KVM] = def->features[FEAT_KVM];
1844     env->features[FEAT_SVM] = def->features[FEAT_SVM];
1845     env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1846     env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1847     env->cpuid_xlevel2 = def->xlevel2;
1848     cpu->cache_info_passthrough = def->cache_info_passthrough;
1849
1850     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1851
1852     /* Special cases not set in the X86CPUDefinition structs: */
1853     if (kvm_enabled()) {
1854         env->features[FEAT_KVM] |= kvm_default_features;
1855     }
1856     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1857
1858     /* sysenter isn't supported in compatibility mode on AMD,
1859      * syscall isn't supported in compatibility mode on Intel.
1860      * Normally we advertise the actual CPU vendor, but you can
1861      * override this using the 'vendor' property if you want to use
1862      * KVM's sysenter/syscall emulation in compatibility mode and
1863      * when doing cross vendor migration
1864      */
1865     const char *vendor = def->vendor;
1866     char host_vendor[CPUID_VENDOR_SZ + 1];
1867     if (kvm_enabled()) {
1868         uint32_t  ebx = 0, ecx = 0, edx = 0;
1869         host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1870         x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1871         vendor = host_vendor;
1872     }
1873
1874     object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1875
1876 }
1877
1878 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1879                        Error **errp)
1880 {
1881     X86CPU *cpu = NULL;
1882     gchar **model_pieces;
1883     char *name, *features;
1884     char *typename;
1885     Error *error = NULL;
1886
1887     model_pieces = g_strsplit(cpu_model, ",", 2);
1888     if (!model_pieces[0]) {
1889         error_setg(&error, "Invalid/empty CPU model name");
1890         goto out;
1891     }
1892     name = model_pieces[0];
1893     features = model_pieces[1];
1894
1895     cpu = X86_CPU(object_new(TYPE_X86_CPU));
1896     x86_cpu_load_def(cpu, name, &error);
1897     if (error) {
1898         goto out;
1899     }
1900
1901 #ifndef CONFIG_USER_ONLY
1902     if (icc_bridge == NULL) {
1903         error_setg(&error, "Invalid icc-bridge value");
1904         goto out;
1905     }
1906     qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1907     object_unref(OBJECT(cpu));
1908 #endif
1909
1910     /* Emulate per-model subclasses for global properties */
1911     typename = g_strdup_printf("%s-" TYPE_X86_CPU, name);
1912     qdev_prop_set_globals_for_type(DEVICE(cpu), typename, &error);
1913     g_free(typename);
1914     if (error) {
1915         goto out;
1916     }
1917
1918     cpu_x86_parse_featurestr(cpu, features, &error);
1919     if (error) {
1920         goto out;
1921     }
1922
1923 out:
1924     if (error != NULL) {
1925         error_propagate(errp, error);
1926         object_unref(OBJECT(cpu));
1927         cpu = NULL;
1928     }
1929     g_strfreev(model_pieces);
1930     return cpu;
1931 }
1932
1933 X86CPU *cpu_x86_init(const char *cpu_model)
1934 {
1935     Error *error = NULL;
1936     X86CPU *cpu;
1937
1938     cpu = cpu_x86_create(cpu_model, NULL, &error);
1939     if (error) {
1940         goto out;
1941     }
1942
1943     object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1944
1945 out:
1946     if (error) {
1947         error_report("%s", error_get_pretty(error));
1948         error_free(error);
1949         if (cpu != NULL) {
1950             object_unref(OBJECT(cpu));
1951             cpu = NULL;
1952         }
1953     }
1954     return cpu;
1955 }
1956
1957 #if !defined(CONFIG_USER_ONLY)
1958
1959 void cpu_clear_apic_feature(CPUX86State *env)
1960 {
1961     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
1962 }
1963
1964 #endif /* !CONFIG_USER_ONLY */
1965
1966 /* Initialize list of CPU models, filling some non-static fields if necessary
1967  */
1968 void x86_cpudef_setup(void)
1969 {
1970     int i, j;
1971     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1972
1973     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1974         X86CPUDefinition *def = &builtin_x86_defs[i];
1975
1976         /* Look for specific "cpudef" models that */
1977         /* have the QEMU version in .model_id */
1978         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1979             if (strcmp(model_with_versions[j], def->name) == 0) {
1980                 pstrcpy(def->model_id, sizeof(def->model_id),
1981                         "QEMU Virtual CPU version ");
1982                 pstrcat(def->model_id, sizeof(def->model_id),
1983                         qemu_get_version());
1984                 break;
1985             }
1986         }
1987     }
1988 }
1989
1990 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1991                              uint32_t *ecx, uint32_t *edx)
1992 {
1993     *ebx = env->cpuid_vendor1;
1994     *edx = env->cpuid_vendor2;
1995     *ecx = env->cpuid_vendor3;
1996 }
1997
1998 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1999                    uint32_t *eax, uint32_t *ebx,
2000                    uint32_t *ecx, uint32_t *edx)
2001 {
2002     X86CPU *cpu = x86_env_get_cpu(env);
2003     CPUState *cs = CPU(cpu);
2004
2005     /* test if maximum index reached */
2006     if (index & 0x80000000) {
2007         if (index > env->cpuid_xlevel) {
2008             if (env->cpuid_xlevel2 > 0) {
2009                 /* Handle the Centaur's CPUID instruction. */
2010                 if (index > env->cpuid_xlevel2) {
2011                     index = env->cpuid_xlevel2;
2012                 } else if (index < 0xC0000000) {
2013                     index = env->cpuid_xlevel;
2014                 }
2015             } else {
2016                 /* Intel documentation states that invalid EAX input will
2017                  * return the same information as EAX=cpuid_level
2018                  * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2019                  */
2020                 index =  env->cpuid_level;
2021             }
2022         }
2023     } else {
2024         if (index > env->cpuid_level)
2025             index = env->cpuid_level;
2026     }
2027
2028     switch(index) {
2029     case 0:
2030         *eax = env->cpuid_level;
2031         get_cpuid_vendor(env, ebx, ecx, edx);
2032         break;
2033     case 1:
2034         *eax = env->cpuid_version;
2035         *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2036         *ecx = env->features[FEAT_1_ECX];
2037         *edx = env->features[FEAT_1_EDX];
2038         if (cs->nr_cores * cs->nr_threads > 1) {
2039             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2040             *edx |= 1 << 28;    /* HTT bit */
2041         }
2042         break;
2043     case 2:
2044         /* cache info: needed for Pentium Pro compatibility */
2045         if (cpu->cache_info_passthrough) {
2046             host_cpuid(index, 0, eax, ebx, ecx, edx);
2047             break;
2048         }
2049         *eax = 1; /* Number of CPUID[EAX=2] calls required */
2050         *ebx = 0;
2051         *ecx = 0;
2052         *edx = (L1D_DESCRIPTOR << 16) | \
2053                (L1I_DESCRIPTOR <<  8) | \
2054                (L2_DESCRIPTOR);
2055         break;
2056     case 4:
2057         /* cache info: needed for Core compatibility */
2058         if (cpu->cache_info_passthrough) {
2059             host_cpuid(index, count, eax, ebx, ecx, edx);
2060             *eax &= ~0xFC000000;
2061         } else {
2062             *eax = 0;
2063             switch (count) {
2064             case 0: /* L1 dcache info */
2065                 *eax |= CPUID_4_TYPE_DCACHE | \
2066                         CPUID_4_LEVEL(1) | \
2067                         CPUID_4_SELF_INIT_LEVEL;
2068                 *ebx = (L1D_LINE_SIZE - 1) | \
2069                        ((L1D_PARTITIONS - 1) << 12) | \
2070                        ((L1D_ASSOCIATIVITY - 1) << 22);
2071                 *ecx = L1D_SETS - 1;
2072                 *edx = CPUID_4_NO_INVD_SHARING;
2073                 break;
2074             case 1: /* L1 icache info */
2075                 *eax |= CPUID_4_TYPE_ICACHE | \
2076                         CPUID_4_LEVEL(1) | \
2077                         CPUID_4_SELF_INIT_LEVEL;
2078                 *ebx = (L1I_LINE_SIZE - 1) | \
2079                        ((L1I_PARTITIONS - 1) << 12) | \
2080                        ((L1I_ASSOCIATIVITY - 1) << 22);
2081                 *ecx = L1I_SETS - 1;
2082                 *edx = CPUID_4_NO_INVD_SHARING;
2083                 break;
2084             case 2: /* L2 cache info */
2085                 *eax |= CPUID_4_TYPE_UNIFIED | \
2086                         CPUID_4_LEVEL(2) | \
2087                         CPUID_4_SELF_INIT_LEVEL;
2088                 if (cs->nr_threads > 1) {
2089                     *eax |= (cs->nr_threads - 1) << 14;
2090                 }
2091                 *ebx = (L2_LINE_SIZE - 1) | \
2092                        ((L2_PARTITIONS - 1) << 12) | \
2093                        ((L2_ASSOCIATIVITY - 1) << 22);
2094                 *ecx = L2_SETS - 1;
2095                 *edx = CPUID_4_NO_INVD_SHARING;
2096                 break;
2097             default: /* end of info */
2098                 *eax = 0;
2099                 *ebx = 0;
2100                 *ecx = 0;
2101                 *edx = 0;
2102                 break;
2103             }
2104         }
2105
2106         /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  */
2107         if ((*eax & 31) && cs->nr_cores > 1) {
2108             *eax |= (cs->nr_cores - 1) << 26;
2109         }
2110         break;
2111     case 5:
2112         /* mwait info: needed for Core compatibility */
2113         *eax = 0; /* Smallest monitor-line size in bytes */
2114         *ebx = 0; /* Largest monitor-line size in bytes */
2115         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2116         *edx = 0;
2117         break;
2118     case 6:
2119         /* Thermal and Power Leaf */
2120         *eax = 0;
2121         *ebx = 0;
2122         *ecx = 0;
2123         *edx = 0;
2124         break;
2125     case 7:
2126         /* Structured Extended Feature Flags Enumeration Leaf */
2127         if (count == 0) {
2128             *eax = 0; /* Maximum ECX value for sub-leaves */
2129             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2130             *ecx = 0; /* Reserved */
2131             *edx = 0; /* Reserved */
2132         } else {
2133             *eax = 0;
2134             *ebx = 0;
2135             *ecx = 0;
2136             *edx = 0;
2137         }
2138         break;
2139     case 9:
2140         /* Direct Cache Access Information Leaf */
2141         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2142         *ebx = 0;
2143         *ecx = 0;
2144         *edx = 0;
2145         break;
2146     case 0xA:
2147         /* Architectural Performance Monitoring Leaf */
2148         if (kvm_enabled() && cpu->enable_pmu) {
2149             KVMState *s = cs->kvm_state;
2150
2151             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2152             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2153             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2154             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2155         } else {
2156             *eax = 0;
2157             *ebx = 0;
2158             *ecx = 0;
2159             *edx = 0;
2160         }
2161         break;
2162     case 0xD: {
2163         KVMState *s = cs->kvm_state;
2164         uint64_t kvm_mask;
2165         int i;
2166
2167         /* Processor Extended State */
2168         *eax = 0;
2169         *ebx = 0;
2170         *ecx = 0;
2171         *edx = 0;
2172         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2173             break;
2174         }
2175         kvm_mask =
2176             kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2177             ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2178
2179         if (count == 0) {
2180             *ecx = 0x240;
2181             for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2182                 const ExtSaveArea *esa = &ext_save_areas[i];
2183                 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2184                     (kvm_mask & (1 << i)) != 0) {
2185                     if (i < 32) {
2186                         *eax |= 1 << i;
2187                     } else {
2188                         *edx |= 1 << (i - 32);
2189                     }
2190                     *ecx = MAX(*ecx, esa->offset + esa->size);
2191                 }
2192             }
2193             *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2194             *ebx = *ecx;
2195         } else if (count == 1) {
2196             *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2197         } else if (count < ARRAY_SIZE(ext_save_areas)) {
2198             const ExtSaveArea *esa = &ext_save_areas[count];
2199             if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2200                 (kvm_mask & (1 << count)) != 0) {
2201                 *eax = esa->size;
2202                 *ebx = esa->offset;
2203             }
2204         }
2205         break;
2206     }
2207     case 0x80000000:
2208         *eax = env->cpuid_xlevel;
2209         *ebx = env->cpuid_vendor1;
2210         *edx = env->cpuid_vendor2;
2211         *ecx = env->cpuid_vendor3;
2212         break;
2213     case 0x80000001:
2214         *eax = env->cpuid_version;
2215         *ebx = 0;
2216         *ecx = env->features[FEAT_8000_0001_ECX];
2217         *edx = env->features[FEAT_8000_0001_EDX];
2218
2219         /* The Linux kernel checks for the CMPLegacy bit and
2220          * discards multiple thread information if it is set.
2221          * So dont set it here for Intel to make Linux guests happy.
2222          */
2223         if (cs->nr_cores * cs->nr_threads > 1) {
2224             uint32_t tebx, tecx, tedx;
2225             get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2226             if (tebx != CPUID_VENDOR_INTEL_1 ||
2227                 tedx != CPUID_VENDOR_INTEL_2 ||
2228                 tecx != CPUID_VENDOR_INTEL_3) {
2229                 *ecx |= 1 << 1;    /* CmpLegacy bit */
2230             }
2231         }
2232         break;
2233     case 0x80000002:
2234     case 0x80000003:
2235     case 0x80000004:
2236         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2237         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2238         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2239         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2240         break;
2241     case 0x80000005:
2242         /* cache info (L1 cache) */
2243         if (cpu->cache_info_passthrough) {
2244             host_cpuid(index, 0, eax, ebx, ecx, edx);
2245             break;
2246         }
2247         *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2248                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
2249         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2250                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
2251         *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2252                (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2253         *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2254                (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2255         break;
2256     case 0x80000006:
2257         /* cache info (L2 cache) */
2258         if (cpu->cache_info_passthrough) {
2259             host_cpuid(index, 0, eax, ebx, ecx, edx);
2260             break;
2261         }
2262         *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2263                (L2_DTLB_2M_ENTRIES << 16) | \
2264                (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2265                (L2_ITLB_2M_ENTRIES);
2266         *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2267                (L2_DTLB_4K_ENTRIES << 16) | \
2268                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2269                (L2_ITLB_4K_ENTRIES);
2270         *ecx = (L2_SIZE_KB_AMD << 16) | \
2271                (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2272                (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2273         *edx = ((L3_SIZE_KB/512) << 18) | \
2274                (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2275                (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2276         break;
2277     case 0x80000008:
2278         /* virtual & phys address size in low 2 bytes. */
2279 /* XXX: This value must match the one used in the MMU code. */
2280         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2281             /* 64 bit processor */
2282 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2283             *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2284         } else {
2285             if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2286                 *eax = 0x00000024; /* 36 bits physical */
2287             } else {
2288                 *eax = 0x00000020; /* 32 bits physical */
2289             }
2290         }
2291         *ebx = 0;
2292         *ecx = 0;
2293         *edx = 0;
2294         if (cs->nr_cores * cs->nr_threads > 1) {
2295             *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2296         }
2297         break;
2298     case 0x8000000A:
2299         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2300             *eax = 0x00000001; /* SVM Revision */
2301             *ebx = 0x00000010; /* nr of ASIDs */
2302             *ecx = 0;
2303             *edx = env->features[FEAT_SVM]; /* optional features */
2304         } else {
2305             *eax = 0;
2306             *ebx = 0;
2307             *ecx = 0;
2308             *edx = 0;
2309         }
2310         break;
2311     case 0xC0000000:
2312         *eax = env->cpuid_xlevel2;
2313         *ebx = 0;
2314         *ecx = 0;
2315         *edx = 0;
2316         break;
2317     case 0xC0000001:
2318         /* Support for VIA CPU's CPUID instruction */
2319         *eax = env->cpuid_version;
2320         *ebx = 0;
2321         *ecx = 0;
2322         *edx = env->features[FEAT_C000_0001_EDX];
2323         break;
2324     case 0xC0000002:
2325     case 0xC0000003:
2326     case 0xC0000004:
2327         /* Reserved for the future, and now filled with zero */
2328         *eax = 0;
2329         *ebx = 0;
2330         *ecx = 0;
2331         *edx = 0;
2332         break;
2333     default:
2334         /* reserved values: zero */
2335         *eax = 0;
2336         *ebx = 0;
2337         *ecx = 0;
2338         *edx = 0;
2339         break;
2340     }
2341 }
2342
2343 /* CPUClass::reset() */
2344 static void x86_cpu_reset(CPUState *s)
2345 {
2346     X86CPU *cpu = X86_CPU(s);
2347     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2348     CPUX86State *env = &cpu->env;
2349     int i;
2350
2351     xcc->parent_reset(s);
2352
2353
2354     memset(env, 0, offsetof(CPUX86State, breakpoints));
2355
2356     tlb_flush(env, 1);
2357
2358     env->old_exception = -1;
2359
2360     /* init to reset state */
2361
2362 #ifdef CONFIG_SOFTMMU
2363     env->hflags |= HF_SOFTMMU_MASK;
2364 #endif
2365     env->hflags2 |= HF2_GIF_MASK;
2366
2367     cpu_x86_update_cr0(env, 0x60000010);
2368     env->a20_mask = ~0x0;
2369     env->smbase = 0x30000;
2370
2371     env->idt.limit = 0xffff;
2372     env->gdt.limit = 0xffff;
2373     env->ldt.limit = 0xffff;
2374     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2375     env->tr.limit = 0xffff;
2376     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2377
2378     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2379                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2380                            DESC_R_MASK | DESC_A_MASK);
2381     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2382                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2383                            DESC_A_MASK);
2384     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2385                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2386                            DESC_A_MASK);
2387     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2388                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2389                            DESC_A_MASK);
2390     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2391                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2392                            DESC_A_MASK);
2393     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2394                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2395                            DESC_A_MASK);
2396
2397     env->eip = 0xfff0;
2398     env->regs[R_EDX] = env->cpuid_version;
2399
2400     env->eflags = 0x2;
2401
2402     /* FPU init */
2403     for (i = 0; i < 8; i++) {
2404         env->fptags[i] = 1;
2405     }
2406     env->fpuc = 0x37f;
2407
2408     env->mxcsr = 0x1f80;
2409     env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2410
2411     env->pat = 0x0007040600070406ULL;
2412     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2413
2414     memset(env->dr, 0, sizeof(env->dr));
2415     env->dr[6] = DR6_FIXED_1;
2416     env->dr[7] = DR7_FIXED_1;
2417     cpu_breakpoint_remove_all(env, BP_CPU);
2418     cpu_watchpoint_remove_all(env, BP_CPU);
2419
2420     env->tsc_adjust = 0;
2421     env->tsc = 0;
2422
2423 #if !defined(CONFIG_USER_ONLY)
2424     /* We hard-wire the BSP to the first CPU. */
2425     if (s->cpu_index == 0) {
2426         apic_designate_bsp(cpu->apic_state);
2427     }
2428
2429     s->halted = !cpu_is_bsp(cpu);
2430 #endif
2431 }
2432
2433 #ifndef CONFIG_USER_ONLY
2434 bool cpu_is_bsp(X86CPU *cpu)
2435 {
2436     return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2437 }
2438
2439 /* TODO: remove me, when reset over QOM tree is implemented */
2440 static void x86_cpu_machine_reset_cb(void *opaque)
2441 {
2442     X86CPU *cpu = opaque;
2443     cpu_reset(CPU(cpu));
2444 }
2445 #endif
2446
2447 static void mce_init(X86CPU *cpu)
2448 {
2449     CPUX86State *cenv = &cpu->env;
2450     unsigned int bank;
2451
2452     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2453         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2454             (CPUID_MCE | CPUID_MCA)) {
2455         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2456         cenv->mcg_ctl = ~(uint64_t)0;
2457         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2458             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2459         }
2460     }
2461 }
2462
2463 #ifndef CONFIG_USER_ONLY
2464 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2465 {
2466     CPUX86State *env = &cpu->env;
2467     DeviceState *dev = DEVICE(cpu);
2468     APICCommonState *apic;
2469     const char *apic_type = "apic";
2470
2471     if (kvm_irqchip_in_kernel()) {
2472         apic_type = "kvm-apic";
2473     } else if (xen_enabled()) {
2474         apic_type = "xen-apic";
2475     }
2476
2477     cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2478     if (cpu->apic_state == NULL) {
2479         error_setg(errp, "APIC device '%s' could not be created", apic_type);
2480         return;
2481     }
2482
2483     object_property_add_child(OBJECT(cpu), "apic",
2484                               OBJECT(cpu->apic_state), NULL);
2485     qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2486     /* TODO: convert to link<> */
2487     apic = APIC_COMMON(cpu->apic_state);
2488     apic->cpu = cpu;
2489 }
2490
2491 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2492 {
2493     if (cpu->apic_state == NULL) {
2494         return;
2495     }
2496
2497     if (qdev_init(cpu->apic_state)) {
2498         error_setg(errp, "APIC device '%s' could not be initialized",
2499                    object_get_typename(OBJECT(cpu->apic_state)));
2500         return;
2501     }
2502 }
2503 #else
2504 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2505 {
2506 }
2507 #endif
2508
2509 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2510 {
2511     CPUState *cs = CPU(dev);
2512     X86CPU *cpu = X86_CPU(dev);
2513     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2514     CPUX86State *env = &cpu->env;
2515     Error *local_err = NULL;
2516
2517     if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2518         env->cpuid_level = 7;
2519     }
2520
2521     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2522      * CPUID[1].EDX.
2523      */
2524     if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2525         env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2526         env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2527         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2528         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2529            & CPUID_EXT2_AMD_ALIASES);
2530     }
2531
2532     if (!kvm_enabled()) {
2533         env->features[FEAT_1_EDX] &= TCG_FEATURES;
2534         env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2535         env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2536 #ifdef TARGET_X86_64
2537             | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2538 #endif
2539             );
2540         env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2541         env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2542     } else {
2543         KVMState *s = kvm_state;
2544         if ((cpu->check_cpuid || cpu->enforce_cpuid)
2545             && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
2546             error_setg(&local_err,
2547                        "Host's CPU doesn't support requested features");
2548             goto out;
2549         }
2550         filter_features_for_kvm(cpu);
2551     }
2552
2553 #ifndef CONFIG_USER_ONLY
2554     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2555
2556     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2557         x86_cpu_apic_create(cpu, &local_err);
2558         if (local_err != NULL) {
2559             goto out;
2560         }
2561     }
2562 #endif
2563
2564     mce_init(cpu);
2565     qemu_init_vcpu(cs);
2566
2567     x86_cpu_apic_realize(cpu, &local_err);
2568     if (local_err != NULL) {
2569         goto out;
2570     }
2571     cpu_reset(cs);
2572
2573     xcc->parent_realize(dev, &local_err);
2574 out:
2575     if (local_err != NULL) {
2576         error_propagate(errp, local_err);
2577         return;
2578     }
2579 }
2580
2581 /* Enables contiguous-apic-ID mode, for compatibility */
2582 static bool compat_apic_id_mode;
2583
2584 void enable_compat_apic_id_mode(void)
2585 {
2586     compat_apic_id_mode = true;
2587 }
2588
2589 /* Calculates initial APIC ID for a specific CPU index
2590  *
2591  * Currently we need to be able to calculate the APIC ID from the CPU index
2592  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2593  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2594  * all CPUs up to max_cpus.
2595  */
2596 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2597 {
2598     uint32_t correct_id;
2599     static bool warned;
2600
2601     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2602     if (compat_apic_id_mode) {
2603         if (cpu_index != correct_id && !warned) {
2604             error_report("APIC IDs set in compatibility mode, "
2605                          "CPU topology won't match the configuration");
2606             warned = true;
2607         }
2608         return cpu_index;
2609     } else {
2610         return correct_id;
2611     }
2612 }
2613
2614 static void x86_cpu_initfn(Object *obj)
2615 {
2616     CPUState *cs = CPU(obj);
2617     X86CPU *cpu = X86_CPU(obj);
2618     CPUX86State *env = &cpu->env;
2619     static int inited;
2620
2621     cs->env_ptr = env;
2622     cpu_exec_init(env);
2623
2624     object_property_add(obj, "family", "int",
2625                         x86_cpuid_version_get_family,
2626                         x86_cpuid_version_set_family, NULL, NULL, NULL);
2627     object_property_add(obj, "model", "int",
2628                         x86_cpuid_version_get_model,
2629                         x86_cpuid_version_set_model, NULL, NULL, NULL);
2630     object_property_add(obj, "stepping", "int",
2631                         x86_cpuid_version_get_stepping,
2632                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2633     object_property_add(obj, "level", "int",
2634                         x86_cpuid_get_level,
2635                         x86_cpuid_set_level, NULL, NULL, NULL);
2636     object_property_add(obj, "xlevel", "int",
2637                         x86_cpuid_get_xlevel,
2638                         x86_cpuid_set_xlevel, NULL, NULL, NULL);
2639     object_property_add_str(obj, "vendor",
2640                             x86_cpuid_get_vendor,
2641                             x86_cpuid_set_vendor, NULL);
2642     object_property_add_str(obj, "model-id",
2643                             x86_cpuid_get_model_id,
2644                             x86_cpuid_set_model_id, NULL);
2645     object_property_add(obj, "tsc-frequency", "int",
2646                         x86_cpuid_get_tsc_freq,
2647                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2648     object_property_add(obj, "apic-id", "int",
2649                         x86_cpuid_get_apic_id,
2650                         x86_cpuid_set_apic_id, NULL, NULL, NULL);
2651     object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2652                         x86_cpu_get_feature_words,
2653                         NULL, NULL, (void *)env->features, NULL);
2654     object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2655                         x86_cpu_get_feature_words,
2656                         NULL, NULL, (void *)cpu->filtered_features, NULL);
2657
2658     cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2659     env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2660
2661     /* init various static tables used in TCG mode */
2662     if (tcg_enabled() && !inited) {
2663         inited = 1;
2664         optimize_flags_init();
2665 #ifndef CONFIG_USER_ONLY
2666         cpu_set_debug_excp_handler(breakpoint_handler);
2667 #endif
2668     }
2669 }
2670
2671 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2672 {
2673     X86CPU *cpu = X86_CPU(cs);
2674     CPUX86State *env = &cpu->env;
2675
2676     return env->cpuid_apic_id;
2677 }
2678
2679 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2680 {
2681     X86CPU *cpu = X86_CPU(cs);
2682
2683     return cpu->env.cr[0] & CR0_PG_MASK;
2684 }
2685
2686 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2687 {
2688     X86CPU *cpu = X86_CPU(cs);
2689
2690     cpu->env.eip = value;
2691 }
2692
2693 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2694 {
2695     X86CPU *cpu = X86_CPU(cs);
2696
2697     cpu->env.eip = tb->pc - tb->cs_base;
2698 }
2699
2700 static bool x86_cpu_has_work(CPUState *cs)
2701 {
2702     X86CPU *cpu = X86_CPU(cs);
2703     CPUX86State *env = &cpu->env;
2704
2705     return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2706                                       CPU_INTERRUPT_POLL)) &&
2707             (env->eflags & IF_MASK)) ||
2708            (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2709                                      CPU_INTERRUPT_INIT |
2710                                      CPU_INTERRUPT_SIPI |
2711                                      CPU_INTERRUPT_MCE));
2712 }
2713
2714 static Property x86_cpu_properties[] = {
2715     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2716     { .name  = "hv-spinlocks", .info  = &qdev_prop_spinlocks },
2717     DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2718     DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2719     DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2720     DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2721     DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2722     DEFINE_PROP_END_OF_LIST()
2723 };
2724
2725 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2726 {
2727     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2728     CPUClass *cc = CPU_CLASS(oc);
2729     DeviceClass *dc = DEVICE_CLASS(oc);
2730
2731     xcc->parent_realize = dc->realize;
2732     dc->realize = x86_cpu_realizefn;
2733     dc->bus_type = TYPE_ICC_BUS;
2734     dc->props = x86_cpu_properties;
2735
2736     xcc->parent_reset = cc->reset;
2737     cc->reset = x86_cpu_reset;
2738     cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2739
2740     cc->has_work = x86_cpu_has_work;
2741     cc->do_interrupt = x86_cpu_do_interrupt;
2742     cc->dump_state = x86_cpu_dump_state;
2743     cc->set_pc = x86_cpu_set_pc;
2744     cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2745     cc->gdb_read_register = x86_cpu_gdb_read_register;
2746     cc->gdb_write_register = x86_cpu_gdb_write_register;
2747     cc->get_arch_id = x86_cpu_get_arch_id;
2748     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2749 #ifndef CONFIG_USER_ONLY
2750     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2751     cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2752     cc->write_elf64_note = x86_cpu_write_elf64_note;
2753     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2754     cc->write_elf32_note = x86_cpu_write_elf32_note;
2755     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2756     cc->vmsd = &vmstate_x86_cpu;
2757 #endif
2758     cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2759 }
2760
2761 static const TypeInfo x86_cpu_type_info = {
2762     .name = TYPE_X86_CPU,
2763     .parent = TYPE_CPU,
2764     .instance_size = sizeof(X86CPU),
2765     .instance_init = x86_cpu_initfn,
2766     .abstract = false,
2767     .class_size = sizeof(X86CPUClass),
2768     .class_init = x86_cpu_common_class_init,
2769 };
2770
2771 static void x86_cpu_register_types(void)
2772 {
2773     type_register_static(&x86_cpu_type_info);
2774 }
2775
2776 type_init(x86_cpu_register_types)