hw/ppce500_mpc8544ds.c

   1 /*
   2  * Qemu PowerPC MPC8544DS board emualtion
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <[email protected]>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "net.h"
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "pci.h"
  23 #include "boards.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_ppc.h"
  27 #include "device_tree.h"
  28 #include "openpic.h"
  29 #include "ppc.h"
  30 #include "loader.h"
  31 #include "elf.h"
  32 #include "sysbus.h"
  33
  34 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  35 #define UIMAGE_LOAD_BASE           0
  36 #define DTC_LOAD_PAD               0x500000
  37 #define DTC_PAD_MASK               0xFFFFF
  38 #define INITRD_LOAD_PAD            0x2000000
  39 #define INITRD_PAD_MASK            0xFFFFFF
  40
  41 #define RAM_SIZES_ALIGN            (64UL << 20)
  42
  43 #define MPC8544_CCSRBAR_BASE       0xE0000000
  44 #define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000)
  45 #define MPC8544_SERIAL0_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4500)
  46 #define MPC8544_SERIAL1_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4600)
  47 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + 0x8000)
  48 #define MPC8544_PCI_REGS_SIZE      0x1000
  49 #define MPC8544_PCI_IO             0xE1000000
  50 #define MPC8544_PCI_IOLEN          0x10000
  51 #define MPC8544_UTIL_BASE          (MPC8544_CCSRBAR_BASE + 0xe0000)
  52 #define MPC8544_SPIN_BASE          0xEF000000
  53
  54 struct boot_info
  55 {
  56     uint32_t dt_base;
  57     uint32_t entry;
  58 };
  59
  60 static int mpc8544_load_device_tree(CPUState *env,
  61                                     target_phys_addr_t addr,
  62                                     uint32_t ramsize,
  63                                     target_phys_addr_t initrd_base,
  64                                     target_phys_addr_t initrd_size,
  65                                     const char *kernel_cmdline)
  66 {
  67     int ret = -1;
  68 #ifdef CONFIG_FDT
  69     uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
  70     char *filename;
  71     int fdt_size;
  72     void *fdt;
  73     uint8_t hypercall[16];
  74     uint32_t clock_freq = 400000000;
  75     uint32_t tb_freq = 400000000;
  76     int i;
  77
  78     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
  79     if (!filename) {
  80         goto out;
  81     }
  82     fdt = load_device_tree(filename, &fdt_size);
  83     g_free(filename);
  84     if (fdt == NULL) {
  85         goto out;
  86     }
  87
  88     /* Manipulate device tree in memory. */
  89     ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
  90                                sizeof(mem_reg_property));
  91     if (ret < 0)
  92         fprintf(stderr, "couldn't set /memory/reg\n");
  93
  94     if (initrd_size) {
  95         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
  96                                         initrd_base);
  97         if (ret < 0) {
  98             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
  99         }
 100
 101         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 102                                         (initrd_base + initrd_size));
 103         if (ret < 0) {
 104             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 105         }
 106     }
 107
 108     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 109                                       kernel_cmdline);
 110     if (ret < 0)
 111         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 112
 113     if (kvm_enabled()) {
 114         /* Read out host's frequencies */
 115         clock_freq = kvmppc_get_clockfreq();
 116         tb_freq = kvmppc_get_tbfreq();
 117
 118         /* indicate KVM hypercall interface */
 119         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 120                                     "linux,kvm");
 121         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 122         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 123                              hypercall, sizeof(hypercall));
 124     }
 125
 126     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 127        the first node as boot node and be happy */
 128     for (i = smp_cpus - 1; i >= 0; i--) {
 129         char cpu_name[128];
 130         uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20));
 131
 132         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 133             if (env->cpu_index == i) {
 134                 break;
 135             }
 136         }
 137
 138         if (!env) {
 139             continue;
 140         }
 141
 142         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
 143         qemu_devtree_add_subnode(fdt, cpu_name);
 144         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 145         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 146         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 147         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
 148         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 149                                   env->dcache_line_size);
 150         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 151                                   env->icache_line_size);
 152         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 153         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 154         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 155         if (env->cpu_index) {
 156             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 157             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 158             qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr",
 159                                  &cpu_release_addr, sizeof(cpu_release_addr));
 160         } else {
 161             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 162         }
 163     }
 164
 165     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 166     g_free(fdt);
 167
 168 out:
 169 #endif
 170
 171     return ret;
 172 }
 173
 174 /* Create -kernel TLB entries for BookE, linearly spanning 256MB.  */
 175 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
 176 {
 177     return (ffs(size >> 10) - 1) >> 1;
 178 }
 179
 180 static void mmubooke_create_initial_mapping(CPUState *env,
 181                                      target_ulong va,
 182                                      target_phys_addr_t pa)
 183 {
 184     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 185     target_phys_addr_t size;
 186
 187     size = (booke206_page_size_to_tlb(256 * 1024 * 1024) << MAS1_TSIZE_SHIFT);
 188     tlb->mas1 = MAS1_VALID | size;
 189     tlb->mas2 = va & TARGET_PAGE_MASK;
 190     tlb->mas7_3 = pa & TARGET_PAGE_MASK;
 191     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 192
 193     env->tlb_dirty = true;
 194 }
 195
 196 static void mpc8544ds_cpu_reset_sec(void *opaque)
 197 {
 198     CPUState *env = opaque;
 199
 200     cpu_reset(env);
 201
 202     /* Secondary CPU starts in halted state for now. Needs to change when
 203        implementing non-kernel boot. */
 204     env->halted = 1;
 205     env->exception_index = EXCP_HLT;
 206 }
 207
 208 static void mpc8544ds_cpu_reset(void *opaque)
 209 {
 210     CPUState *env = opaque;
 211     struct boot_info *bi = env->load_info;
 212
 213     cpu_reset(env);
 214
 215     /* Set initial guest state. */
 216     env->halted = 0;
 217     env->gpr[1] = (16<<20) - 8;
 218     env->gpr[3] = bi->dt_base;
 219     env->nip = bi->entry;
 220     mmubooke_create_initial_mapping(env, 0, 0);
 221 }
 222
 223 static void mpc8544ds_init(ram_addr_t ram_size,
 224                          const char *boot_device,
 225                          const char *kernel_filename,
 226                          const char *kernel_cmdline,
 227                          const char *initrd_filename,
 228                          const char *cpu_model)
 229 {
 230     PCIBus *pci_bus;
 231     CPUState *env = NULL;
 232     uint64_t elf_entry;
 233     uint64_t elf_lowaddr;
 234     target_phys_addr_t entry=0;
 235     target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
 236     target_long kernel_size=0;
 237     target_ulong dt_base = 0;
 238     target_ulong initrd_base = 0;
 239     target_long initrd_size=0;
 240     int i=0;
 241     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 242     qemu_irq **irqs, *mpic;
 243     DeviceState *dev;
 244     CPUState *firstenv = NULL;
 245
 246     /* Setup CPUs */
 247     if (cpu_model == NULL) {
 248         cpu_model = "e500v2_v30";
 249     }
 250
 251     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 252     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 253     for (i = 0; i < smp_cpus; i++) {
 254         qemu_irq *input;
 255         env = cpu_ppc_init(cpu_model);
 256         if (!env) {
 257             fprintf(stderr, "Unable to initialize CPU!\n");
 258             exit(1);
 259         }
 260
 261         if (!firstenv) {
 262             firstenv = env;
 263         }
 264
 265         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 266         input = (qemu_irq *)env->irq_inputs;
 267         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 268         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 269         env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
 270
 271         /* XXX register timer? */
 272         ppc_emb_timers_init(env, 400000000, PPC_INTERRUPT_DECR);
 273         ppc_dcr_init(env, NULL, NULL);
 274         /* XXX Enable DEC interrupts - probably wrong in the backend */
 275         env->spr[SPR_40x_TCR] = 1 << 26;
 276
 277         /* Register reset handler */
 278         if (!i) {
 279             /* Primary CPU */
 280             struct boot_info *boot_info;
 281             boot_info = g_malloc0(sizeof(struct boot_info));
 282             qemu_register_reset(mpc8544ds_cpu_reset, env);
 283             env->load_info = boot_info;
 284         } else {
 285             /* Secondary CPUs */
 286             qemu_register_reset(mpc8544ds_cpu_reset_sec, env);
 287         }
 288     }
 289
 290     env = firstenv;
 291
 292     /* Fixup Memory size on a alignment boundary */
 293     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 294
 295     /* Register Memory */
 296     cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL,
 297                                  "mpc8544ds.ram", ram_size));
 298
 299     /* MPIC */
 300     mpic = mpic_init(MPC8544_MPIC_REGS_BASE, smp_cpus, irqs, NULL);
 301
 302     if (!mpic) {
 303         cpu_abort(env, "MPIC failed to initialize\n");
 304     }
 305
 306     /* Serial */
 307     if (serial_hds[0]) {
 308         serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
 309                        0, mpic[12+26], 399193,
 310                        serial_hds[0], 1, 1);
 311     }
 312
 313     if (serial_hds[1]) {
 314         serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
 315                        0, mpic[12+26], 399193,
 316                        serial_hds[0], 1, 1);
 317     }
 318
 319     /* General Utility device */
 320     sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
 321
 322     /* PCI */
 323     dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
 324                                 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
 325                                 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
 326                                 NULL);
 327     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 328     if (!pci_bus)
 329         printf("couldn't create PCI controller!\n");
 330
 331     isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
 332
 333     if (pci_bus) {
 334         /* Register network interfaces. */
 335         for (i = 0; i < nb_nics; i++) {
 336             pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
 337         }
 338     }
 339
 340     /* Register spinning region */
 341     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 342
 343     /* Load kernel. */
 344     if (kernel_filename) {
 345         kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
 346         if (kernel_size < 0) {
 347             kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
 348                                    &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
 349             entry = elf_entry;
 350             loadaddr = elf_lowaddr;
 351         }
 352         /* XXX try again as binary */
 353         if (kernel_size < 0) {
 354             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 355                     kernel_filename);
 356             exit(1);
 357         }
 358     }
 359
 360     /* Load initrd. */
 361     if (initrd_filename) {
 362         initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 363         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 364                                           ram_size - initrd_base);
 365
 366         if (initrd_size < 0) {
 367             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 368                     initrd_filename);
 369             exit(1);
 370         }
 371     }
 372
 373     /* If we're loading a kernel directly, we must load the device tree too. */
 374     if (kernel_filename) {
 375         struct boot_info *boot_info;
 376
 377 #ifndef CONFIG_FDT
 378         cpu_abort(env, "Compiled without FDT support - can't load kernel\n");
 379 #endif
 380         dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 381         if (mpc8544_load_device_tree(env, dt_base, ram_size,
 382                     initrd_base, initrd_size, kernel_cmdline) < 0) {
 383             fprintf(stderr, "couldn't load device tree\n");
 384             exit(1);
 385         }
 386
 387         boot_info = env->load_info;
 388         boot_info->entry = entry;
 389         boot_info->dt_base = dt_base;
 390     }
 391
 392     if (kvm_enabled()) {
 393         kvmppc_init();
 394     }
 395 }
 396
 397 static QEMUMachine mpc8544ds_machine = {
 398     .name = "mpc8544ds",
 399     .desc = "mpc8544ds",
 400     .init = mpc8544ds_init,
 401     .max_cpus = 15,
 402 };
 403
 404 static void mpc8544ds_machine_init(void)
 405 {
 406     qemu_register_machine(&mpc8544ds_machine);
 407 }
 408
 409 machine_init(mpc8544ds_machine_init);