hw/sm501.c

   1 /*
   2  * QEMU SM501 Device
   3  *
   4  * Copyright (c) 2008 Shin-ichiro KAWASAKI
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include <stdio.h>
  26 #include <assert.h>
  27 #include "hw.h"
  28 #include "pc.h"
  29 #include "console.h"
  30
  31 /*
  32  * Status: 2008/11/02
  33  *   - Minimum implementation for Linux console : mmio regs and CRT layer.
  34  *   - Always updates full screen.
  35  *
  36  * TODO:
  37  *   - Panel support
  38  *   - Hardware cursor support
  39  *   - Touch panel support
  40  *   - USB support
  41  *   - UART support
  42  *   - Performance tuning
  43  */
  44
  45 //#define DEBUG_SM501
  46 //#define DEBUG_BITBLT
  47
  48 #ifdef DEBUG_SM501
  49 #define SM501_DPRINTF(fmt...) printf(fmt)
  50 #else
  51 #define SM501_DPRINTF(fmt...) do {} while(0)
  52 #endif
  53
  54
  55 #define MMIO_BASE_OFFSET 0x3e00000
  56
  57 /* SM501 register definitions taken from "linux/include/linux/sm501-regs.h" */
  58
  59 /* System Configuration area */
  60 /* System config base */
  61 #define SM501_SYS_CONFIG                (0x000000)
  62
  63 /* config 1 */
  64 #define SM501_SYSTEM_CONTROL            (0x000000)
  65
  66 #define SM501_SYSCTRL_PANEL_TRISTATE    (1<<0)
  67 #define SM501_SYSCTRL_MEM_TRISTATE      (1<<1)
  68 #define SM501_SYSCTRL_CRT_TRISTATE      (1<<2)
  69
  70 #define SM501_SYSCTRL_PCI_SLAVE_BURST_MASK (3<<4)
  71 #define SM501_SYSCTRL_PCI_SLAVE_BURST_1 (0<<4)
  72 #define SM501_SYSCTRL_PCI_SLAVE_BURST_2 (1<<4)
  73 #define SM501_SYSCTRL_PCI_SLAVE_BURST_4 (2<<4)
  74 #define SM501_SYSCTRL_PCI_SLAVE_BURST_8 (3<<4)
  75
  76 #define SM501_SYSCTRL_PCI_CLOCK_RUN_EN  (1<<6)
  77 #define SM501_SYSCTRL_PCI_RETRY_DISABLE (1<<7)
  78 #define SM501_SYSCTRL_PCI_SUBSYS_LOCK   (1<<11)
  79 #define SM501_SYSCTRL_PCI_BURST_READ_EN (1<<15)
  80
  81 /* miscellaneous control */
  82
  83 #define SM501_MISC_CONTROL              (0x000004)
  84
  85 #define SM501_MISC_BUS_SH               (0x0)
  86 #define SM501_MISC_BUS_PCI              (0x1)
  87 #define SM501_MISC_BUS_XSCALE           (0x2)
  88 #define SM501_MISC_BUS_NEC              (0x6)
  89 #define SM501_MISC_BUS_MASK             (0x7)
  90
  91 #define SM501_MISC_VR_62MB              (1<<3)
  92 #define SM501_MISC_CDR_RESET            (1<<7)
  93 #define SM501_MISC_USB_LB               (1<<8)
  94 #define SM501_MISC_USB_SLAVE            (1<<9)
  95 #define SM501_MISC_BL_1                 (1<<10)
  96 #define SM501_MISC_MC                   (1<<11)
  97 #define SM501_MISC_DAC_POWER            (1<<12)
  98 #define SM501_MISC_IRQ_INVERT           (1<<16)
  99 #define SM501_MISC_SH                   (1<<17)
 100
 101 #define SM501_MISC_HOLD_EMPTY           (0<<18)
 102 #define SM501_MISC_HOLD_8               (1<<18)
 103 #define SM501_MISC_HOLD_16              (2<<18)
 104 #define SM501_MISC_HOLD_24              (3<<18)
 105 #define SM501_MISC_HOLD_32              (4<<18)
 106 #define SM501_MISC_HOLD_MASK            (7<<18)
 107
 108 #define SM501_MISC_FREQ_12              (1<<24)
 109 #define SM501_MISC_PNL_24BIT            (1<<25)
 110 #define SM501_MISC_8051_LE              (1<<26)
 111
 112
 113
 114 #define SM501_GPIO31_0_CONTROL          (0x000008)
 115 #define SM501_GPIO63_32_CONTROL         (0x00000C)
 116 #define SM501_DRAM_CONTROL              (0x000010)
 117
 118 /* command list */
 119 #define SM501_ARBTRTN_CONTROL           (0x000014)
 120
 121 /* command list */
 122 #define SM501_COMMAND_LIST_STATUS       (0x000024)
 123
 124 /* interrupt debug */
 125 #define SM501_RAW_IRQ_STATUS            (0x000028)
 126 #define SM501_RAW_IRQ_CLEAR             (0x000028)
 127 #define SM501_IRQ_STATUS                (0x00002C)
 128 #define SM501_IRQ_MASK                  (0x000030)
 129 #define SM501_DEBUG_CONTROL             (0x000034)
 130
 131 /* power management */
 132 #define SM501_POWERMODE_P2X_SRC         (1<<29)
 133 #define SM501_POWERMODE_V2X_SRC         (1<<20)
 134 #define SM501_POWERMODE_M_SRC           (1<<12)
 135 #define SM501_POWERMODE_M1_SRC          (1<<4)
 136
 137 #define SM501_CURRENT_GATE              (0x000038)
 138 #define SM501_CURRENT_CLOCK             (0x00003C)
 139 #define SM501_POWER_MODE_0_GATE         (0x000040)
 140 #define SM501_POWER_MODE_0_CLOCK        (0x000044)
 141 #define SM501_POWER_MODE_1_GATE         (0x000048)
 142 #define SM501_POWER_MODE_1_CLOCK        (0x00004C)
 143 #define SM501_SLEEP_MODE_GATE           (0x000050)
 144 #define SM501_POWER_MODE_CONTROL        (0x000054)
 145
 146 /* power gates for units within the 501 */
 147 #define SM501_GATE_HOST                 (0)
 148 #define SM501_GATE_MEMORY               (1)
 149 #define SM501_GATE_DISPLAY              (2)
 150 #define SM501_GATE_2D_ENGINE            (3)
 151 #define SM501_GATE_CSC                  (4)
 152 #define SM501_GATE_ZVPORT               (5)
 153 #define SM501_GATE_GPIO                 (6)
 154 #define SM501_GATE_UART0                (7)
 155 #define SM501_GATE_UART1                (8)
 156 #define SM501_GATE_SSP                  (10)
 157 #define SM501_GATE_USB_HOST             (11)
 158 #define SM501_GATE_USB_GADGET           (12)
 159 #define SM501_GATE_UCONTROLLER          (17)
 160 #define SM501_GATE_AC97                 (18)
 161
 162 /* panel clock */
 163 #define SM501_CLOCK_P2XCLK              (24)
 164 /* crt clock */
 165 #define SM501_CLOCK_V2XCLK              (16)
 166 /* main clock */
 167 #define SM501_CLOCK_MCLK                (8)
 168 /* SDRAM controller clock */
 169 #define SM501_CLOCK_M1XCLK              (0)
 170
 171 /* config 2 */
 172 #define SM501_PCI_MASTER_BASE           (0x000058)
 173 #define SM501_ENDIAN_CONTROL            (0x00005C)
 174 #define SM501_DEVICEID                  (0x000060)
 175 /* 0x050100A0 */
 176
 177 #define SM501_DEVICEID_SM501            (0x05010000)
 178 #define SM501_DEVICEID_IDMASK           (0xffff0000)
 179 #define SM501_DEVICEID_REVMASK          (0x000000ff)
 180
 181 #define SM501_PLLCLOCK_COUNT            (0x000064)
 182 #define SM501_MISC_TIMING               (0x000068)
 183 #define SM501_CURRENT_SDRAM_CLOCK       (0x00006C)
 184
 185 #define SM501_PROGRAMMABLE_PLL_CONTROL  (0x000074)
 186
 187 /* GPIO base */
 188 #define SM501_GPIO                      (0x010000)
 189 #define SM501_GPIO_DATA_LOW             (0x00)
 190 #define SM501_GPIO_DATA_HIGH            (0x04)
 191 #define SM501_GPIO_DDR_LOW              (0x08)
 192 #define SM501_GPIO_DDR_HIGH             (0x0C)
 193 #define SM501_GPIO_IRQ_SETUP            (0x10)
 194 #define SM501_GPIO_IRQ_STATUS           (0x14)
 195 #define SM501_GPIO_IRQ_RESET            (0x14)
 196
 197 /* I2C controller base */
 198 #define SM501_I2C                       (0x010040)
 199 #define SM501_I2C_BYTE_COUNT            (0x00)
 200 #define SM501_I2C_CONTROL               (0x01)
 201 #define SM501_I2C_STATUS                (0x02)
 202 #define SM501_I2C_RESET                 (0x02)
 203 #define SM501_I2C_SLAVE_ADDRESS         (0x03)
 204 #define SM501_I2C_DATA                  (0x04)
 205
 206 /* SSP base */
 207 #define SM501_SSP                       (0x020000)
 208
 209 /* Uart 0 base */
 210 #define SM501_UART0                     (0x030000)
 211
 212 /* Uart 1 base */
 213 #define SM501_UART1                     (0x030020)
 214
 215 /* USB host port base */
 216 #define SM501_USB_HOST                  (0x040000)
 217
 218 /* USB slave/gadget base */
 219 #define SM501_USB_GADGET                (0x060000)
 220
 221 /* USB slave/gadget data port base */
 222 #define SM501_USB_GADGET_DATA           (0x070000)
 223
 224 /* Display controller/video engine base */
 225 #define SM501_DC                        (0x080000)
 226
 227 /* common defines for the SM501 address registers */
 228 #define SM501_ADDR_FLIP                 (1<<31)
 229 #define SM501_ADDR_EXT                  (1<<27)
 230 #define SM501_ADDR_CS1                  (1<<26)
 231 #define SM501_ADDR_MASK                 (0x3f << 26)
 232
 233 #define SM501_FIFO_MASK                 (0x3 << 16)
 234 #define SM501_FIFO_1                    (0x0 << 16)
 235 #define SM501_FIFO_3                    (0x1 << 16)
 236 #define SM501_FIFO_7                    (0x2 << 16)
 237 #define SM501_FIFO_11                   (0x3 << 16)
 238
 239 /* common registers for panel and the crt */
 240 #define SM501_OFF_DC_H_TOT              (0x000)
 241 #define SM501_OFF_DC_V_TOT              (0x008)
 242 #define SM501_OFF_DC_H_SYNC             (0x004)
 243 #define SM501_OFF_DC_V_SYNC             (0x00C)
 244
 245 #define SM501_DC_PANEL_CONTROL          (0x000)
 246
 247 #define SM501_DC_PANEL_CONTROL_FPEN     (1<<27)
 248 #define SM501_DC_PANEL_CONTROL_BIAS     (1<<26)
 249 #define SM501_DC_PANEL_CONTROL_DATA     (1<<25)
 250 #define SM501_DC_PANEL_CONTROL_VDD      (1<<24)
 251 #define SM501_DC_PANEL_CONTROL_DP       (1<<23)
 252
 253 #define SM501_DC_PANEL_CONTROL_TFT_888  (0<<21)
 254 #define SM501_DC_PANEL_CONTROL_TFT_333  (1<<21)
 255 #define SM501_DC_PANEL_CONTROL_TFT_444  (2<<21)
 256
 257 #define SM501_DC_PANEL_CONTROL_DE       (1<<20)
 258
 259 #define SM501_DC_PANEL_CONTROL_LCD_TFT  (0<<18)
 260 #define SM501_DC_PANEL_CONTROL_LCD_STN8 (1<<18)
 261 #define SM501_DC_PANEL_CONTROL_LCD_STN12 (2<<18)
 262
 263 #define SM501_DC_PANEL_CONTROL_CP       (1<<14)
 264 #define SM501_DC_PANEL_CONTROL_VSP      (1<<13)
 265 #define SM501_DC_PANEL_CONTROL_HSP      (1<<12)
 266 #define SM501_DC_PANEL_CONTROL_CK       (1<<9)
 267 #define SM501_DC_PANEL_CONTROL_TE       (1<<8)
 268 #define SM501_DC_PANEL_CONTROL_VPD      (1<<7)
 269 #define SM501_DC_PANEL_CONTROL_VP       (1<<6)
 270 #define SM501_DC_PANEL_CONTROL_HPD      (1<<5)
 271 #define SM501_DC_PANEL_CONTROL_HP       (1<<4)
 272 #define SM501_DC_PANEL_CONTROL_GAMMA    (1<<3)
 273 #define SM501_DC_PANEL_CONTROL_EN       (1<<2)
 274
 275 #define SM501_DC_PANEL_CONTROL_8BPP     (0<<0)
 276 #define SM501_DC_PANEL_CONTROL_16BPP    (1<<0)
 277 #define SM501_DC_PANEL_CONTROL_32BPP    (2<<0)
 278
 279
 280 #define SM501_DC_PANEL_PANNING_CONTROL  (0x004)
 281 #define SM501_DC_PANEL_COLOR_KEY        (0x008)
 282 #define SM501_DC_PANEL_FB_ADDR          (0x00C)
 283 #define SM501_DC_PANEL_FB_OFFSET        (0x010)
 284 #define SM501_DC_PANEL_FB_WIDTH         (0x014)
 285 #define SM501_DC_PANEL_FB_HEIGHT        (0x018)
 286 #define SM501_DC_PANEL_TL_LOC           (0x01C)
 287 #define SM501_DC_PANEL_BR_LOC           (0x020)
 288 #define SM501_DC_PANEL_H_TOT            (0x024)
 289 #define SM501_DC_PANEL_H_SYNC           (0x028)
 290 #define SM501_DC_PANEL_V_TOT            (0x02C)
 291 #define SM501_DC_PANEL_V_SYNC           (0x030)
 292 #define SM501_DC_PANEL_CUR_LINE         (0x034)
 293
 294 #define SM501_DC_VIDEO_CONTROL          (0x040)
 295 #define SM501_DC_VIDEO_FB0_ADDR         (0x044)
 296 #define SM501_DC_VIDEO_FB_WIDTH         (0x048)
 297 #define SM501_DC_VIDEO_FB0_LAST_ADDR    (0x04C)
 298 #define SM501_DC_VIDEO_TL_LOC           (0x050)
 299 #define SM501_DC_VIDEO_BR_LOC           (0x054)
 300 #define SM501_DC_VIDEO_SCALE            (0x058)
 301 #define SM501_DC_VIDEO_INIT_SCALE       (0x05C)
 302 #define SM501_DC_VIDEO_YUV_CONSTANTS    (0x060)
 303 #define SM501_DC_VIDEO_FB1_ADDR         (0x064)
 304 #define SM501_DC_VIDEO_FB1_LAST_ADDR    (0x068)
 305
 306 #define SM501_DC_VIDEO_ALPHA_CONTROL    (0x080)
 307 #define SM501_DC_VIDEO_ALPHA_FB_ADDR    (0x084)
 308 #define SM501_DC_VIDEO_ALPHA_FB_OFFSET  (0x088)
 309 #define SM501_DC_VIDEO_ALPHA_FB_LAST_ADDR       (0x08C)
 310 #define SM501_DC_VIDEO_ALPHA_TL_LOC     (0x090)
 311 #define SM501_DC_VIDEO_ALPHA_BR_LOC     (0x094)
 312 #define SM501_DC_VIDEO_ALPHA_SCALE      (0x098)
 313 #define SM501_DC_VIDEO_ALPHA_INIT_SCALE (0x09C)
 314 #define SM501_DC_VIDEO_ALPHA_CHROMA_KEY (0x0A0)
 315 #define SM501_DC_VIDEO_ALPHA_COLOR_LOOKUP       (0x0A4)
 316
 317 #define SM501_DC_PANEL_HWC_BASE         (0x0F0)
 318 #define SM501_DC_PANEL_HWC_ADDR         (0x0F0)
 319 #define SM501_DC_PANEL_HWC_LOC          (0x0F4)
 320 #define SM501_DC_PANEL_HWC_COLOR_1_2    (0x0F8)
 321 #define SM501_DC_PANEL_HWC_COLOR_3      (0x0FC)
 322
 323 #define SM501_HWC_EN                    (1<<31)
 324
 325 #define SM501_OFF_HWC_ADDR              (0x00)
 326 #define SM501_OFF_HWC_LOC               (0x04)
 327 #define SM501_OFF_HWC_COLOR_1_2         (0x08)
 328 #define SM501_OFF_HWC_COLOR_3           (0x0C)
 329
 330 #define SM501_DC_ALPHA_CONTROL          (0x100)
 331 #define SM501_DC_ALPHA_FB_ADDR          (0x104)
 332 #define SM501_DC_ALPHA_FB_OFFSET        (0x108)
 333 #define SM501_DC_ALPHA_TL_LOC           (0x10C)
 334 #define SM501_DC_ALPHA_BR_LOC           (0x110)
 335 #define SM501_DC_ALPHA_CHROMA_KEY       (0x114)
 336 #define SM501_DC_ALPHA_COLOR_LOOKUP     (0x118)
 337
 338 #define SM501_DC_CRT_CONTROL            (0x200)
 339
 340 #define SM501_DC_CRT_CONTROL_TVP        (1<<15)
 341 #define SM501_DC_CRT_CONTROL_CP         (1<<14)
 342 #define SM501_DC_CRT_CONTROL_VSP        (1<<13)
 343 #define SM501_DC_CRT_CONTROL_HSP        (1<<12)
 344 #define SM501_DC_CRT_CONTROL_VS         (1<<11)
 345 #define SM501_DC_CRT_CONTROL_BLANK      (1<<10)
 346 #define SM501_DC_CRT_CONTROL_SEL        (1<<9)
 347 #define SM501_DC_CRT_CONTROL_TE         (1<<8)
 348 #define SM501_DC_CRT_CONTROL_PIXEL_MASK (0xF << 4)
 349 #define SM501_DC_CRT_CONTROL_GAMMA      (1<<3)
 350 #define SM501_DC_CRT_CONTROL_ENABLE     (1<<2)
 351
 352 #define SM501_DC_CRT_CONTROL_8BPP       (0<<0)
 353 #define SM501_DC_CRT_CONTROL_16BPP      (1<<0)
 354 #define SM501_DC_CRT_CONTROL_32BPP      (2<<0)
 355
 356 #define SM501_DC_CRT_FB_ADDR            (0x204)
 357 #define SM501_DC_CRT_FB_OFFSET          (0x208)
 358 #define SM501_DC_CRT_H_TOT              (0x20C)
 359 #define SM501_DC_CRT_H_SYNC             (0x210)
 360 #define SM501_DC_CRT_V_TOT              (0x214)
 361 #define SM501_DC_CRT_V_SYNC             (0x218)
 362 #define SM501_DC_CRT_SIGNATURE_ANALYZER (0x21C)
 363 #define SM501_DC_CRT_CUR_LINE           (0x220)
 364 #define SM501_DC_CRT_MONITOR_DETECT     (0x224)
 365
 366 #define SM501_DC_CRT_HWC_BASE           (0x230)
 367 #define SM501_DC_CRT_HWC_ADDR           (0x230)
 368 #define SM501_DC_CRT_HWC_LOC            (0x234)
 369 #define SM501_DC_CRT_HWC_COLOR_1_2      (0x238)
 370 #define SM501_DC_CRT_HWC_COLOR_3        (0x23C)
 371
 372 #define SM501_DC_PANEL_PALETTE          (0x400)
 373
 374 #define SM501_DC_VIDEO_PALETTE          (0x800)
 375
 376 #define SM501_DC_CRT_PALETTE            (0xC00)
 377
 378 /* Zoom Video port base */
 379 #define SM501_ZVPORT                    (0x090000)
 380
 381 /* AC97/I2S base */
 382 #define SM501_AC97                      (0x0A0000)
 383
 384 /* 8051 micro controller base */
 385 #define SM501_UCONTROLLER               (0x0B0000)
 386
 387 /* 8051 micro controller SRAM base */
 388 #define SM501_UCONTROLLER_SRAM          (0x0C0000)
 389
 390 /* DMA base */
 391 #define SM501_DMA                       (0x0D0000)
 392
 393 /* 2d engine base */
 394 #define SM501_2D_ENGINE                 (0x100000)
 395 #define SM501_2D_SOURCE                 (0x00)
 396 #define SM501_2D_DESTINATION            (0x04)
 397 #define SM501_2D_DIMENSION              (0x08)
 398 #define SM501_2D_CONTROL                (0x0C)
 399 #define SM501_2D_PITCH                  (0x10)
 400 #define SM501_2D_FOREGROUND             (0x14)
 401 #define SM501_2D_BACKGROUND             (0x18)
 402 #define SM501_2D_STRETCH                (0x1C)
 403 #define SM501_2D_COLOR_COMPARE          (0x20)
 404 #define SM501_2D_COLOR_COMPARE_MASK     (0x24)
 405 #define SM501_2D_MASK                   (0x28)
 406 #define SM501_2D_CLIP_TL                (0x2C)
 407 #define SM501_2D_CLIP_BR                (0x30)
 408 #define SM501_2D_MONO_PATTERN_LOW       (0x34)
 409 #define SM501_2D_MONO_PATTERN_HIGH      (0x38)
 410 #define SM501_2D_WINDOW_WIDTH           (0x3C)
 411 #define SM501_2D_SOURCE_BASE            (0x40)
 412 #define SM501_2D_DESTINATION_BASE       (0x44)
 413 #define SM501_2D_ALPHA                  (0x48)
 414 #define SM501_2D_WRAP                   (0x4C)
 415 #define SM501_2D_STATUS                 (0x50)
 416
 417 #define SM501_CSC_Y_SOURCE_BASE         (0xC8)
 418 #define SM501_CSC_CONSTANTS             (0xCC)
 419 #define SM501_CSC_Y_SOURCE_X            (0xD0)
 420 #define SM501_CSC_Y_SOURCE_Y            (0xD4)
 421 #define SM501_CSC_U_SOURCE_BASE         (0xD8)
 422 #define SM501_CSC_V_SOURCE_BASE         (0xDC)
 423 #define SM501_CSC_SOURCE_DIMENSION      (0xE0)
 424 #define SM501_CSC_SOURCE_PITCH          (0xE4)
 425 #define SM501_CSC_DESTINATION           (0xE8)
 426 #define SM501_CSC_DESTINATION_DIMENSION (0xEC)
 427 #define SM501_CSC_DESTINATION_PITCH     (0xF0)
 428 #define SM501_CSC_SCALE_FACTOR          (0xF4)
 429 #define SM501_CSC_DESTINATION_BASE      (0xF8)
 430 #define SM501_CSC_CONTROL               (0xFC)
 431
 432 /* 2d engine data port base */
 433 #define SM501_2D_ENGINE_DATA            (0x110000)
 434
 435 /* end of register definitions */
 436
 437
 438 /* SM501 local memory size taken from "linux/drivers/mfd/sm501.c" */
 439 static const uint32_t sm501_mem_local_size[] = {
 440         [0]     = 4*1024*1024,
 441         [1]     = 8*1024*1024,
 442         [2]     = 16*1024*1024,
 443         [3]     = 32*1024*1024,
 444         [4]     = 64*1024*1024,
 445         [5]     = 2*1024*1024,
 446 };
 447 #define get_local_mem_size(s) sm501_mem_local_size[(s)->local_mem_size_index]
 448
 449 typedef struct SM501State {
 450     /* graphic console status */
 451     DisplayState *ds;
 452     QEMUConsole *console;
 453
 454     /* status & internal resources */
 455     target_phys_addr_t base;
 456     uint32_t local_mem_size_index;
 457     uint8_t * local_mem;
 458     uint32_t last_width;
 459     uint32_t last_height;
 460
 461     /* mmio registers */
 462     uint32_t system_control;
 463     uint32_t misc_control;
 464     uint32_t gpio_31_0_control;
 465     uint32_t gpio_63_32_control;
 466     uint32_t dram_control;
 467     uint32_t irq_mask;
 468     uint32_t misc_timing;
 469     uint32_t power_mode_control;
 470
 471     uint32_t uart0_ier;
 472     uint32_t uart0_lcr;
 473     uint32_t uart0_mcr;
 474     uint32_t uart0_scr;
 475
 476     uint8_t dc_palette[0x400 * 3];
 477
 478     uint32_t dc_panel_control;
 479     uint32_t dc_panel_panning_control;
 480     uint32_t dc_panel_fb_addr;
 481     uint32_t dc_panel_fb_offset;
 482     uint32_t dc_panel_fb_width;
 483     uint32_t dc_panel_fb_height;
 484     uint32_t dc_panel_tl_location;
 485     uint32_t dc_panel_br_location;
 486     uint32_t dc_panel_h_total;
 487     uint32_t dc_panel_h_sync;
 488     uint32_t dc_panel_v_total;
 489     uint32_t dc_panel_v_sync;
 490
 491     uint32_t dc_panel_hwc_addr;
 492     uint32_t dc_panel_hwc_location;
 493     uint32_t dc_panel_hwc_color_1_2;
 494     uint32_t dc_panel_hwc_color_3;
 495
 496     uint32_t dc_crt_control;
 497     uint32_t dc_crt_fb_addr;
 498     uint32_t dc_crt_fb_offset;
 499     uint32_t dc_crt_h_total;
 500     uint32_t dc_crt_h_sync;
 501     uint32_t dc_crt_v_total;
 502     uint32_t dc_crt_v_sync;
 503
 504     uint32_t dc_crt_hwc_addr;
 505     uint32_t dc_crt_hwc_location;
 506     uint32_t dc_crt_hwc_color_1_2;
 507     uint32_t dc_crt_hwc_color_3;
 508
 509 } SM501State;
 510
 511 static uint32_t get_local_mem_size_index(uint32_t size)
 512 {
 513     uint32_t norm_size = 0;
 514     int i, index = 0;
 515
 516     for (i = 0; i < sizeof(sm501_mem_local_size)/sizeof(uint32_t); i++) {
 517         uint32_t new_size = sm501_mem_local_size[i];
 518         if (new_size >= size) {
 519             if (norm_size == 0 || norm_size > new_size) {
 520                 norm_size = new_size;
 521                 index = i;
 522             }
 523         }
 524     }
 525
 526     return index;
 527 }
 528
 529 static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr)
 530 {
 531     SM501State * s = (SM501State *)opaque;
 532     uint32_t ret = 0;
 533     SM501_DPRINTF("sm501 system config regs : read addr=%x\n", (int)addr);
 534
 535     switch(addr) {
 536     case SM501_SYSTEM_CONTROL:
 537         ret = s->system_control;
 538         break;
 539     case SM501_MISC_CONTROL:
 540         ret = s->misc_control;
 541         break;
 542     case SM501_GPIO31_0_CONTROL:
 543         ret = s->gpio_31_0_control;
 544         break;
 545     case SM501_GPIO63_32_CONTROL:
 546         ret = s->gpio_63_32_control;
 547         break;
 548     case SM501_DEVICEID:
 549         ret = 0x050100A0;
 550         break;
 551     case SM501_DRAM_CONTROL:
 552         ret = (s->dram_control & 0x07F107C0) | s->local_mem_size_index << 13;
 553         break;
 554     case SM501_IRQ_MASK:
 555         ret = s->irq_mask;
 556         break;
 557     case SM501_MISC_TIMING:
 558         /* TODO : simulate gate control */
 559         ret = s->misc_timing;
 560         break;
 561     case SM501_CURRENT_GATE:
 562         /* TODO : simulate gate control */
 563         ret = 0x00021807;
 564         break;
 565     case SM501_CURRENT_CLOCK:
 566         ret = 0x2A1A0A09;
 567         break;
 568     case SM501_POWER_MODE_CONTROL:
 569         ret = s->power_mode_control;
 570         break;
 571
 572     default:
 573         printf("sm501 system config : not implemented register read."
 574                " addr=%x\n", (int)addr);
 575         assert(0);
 576     }
 577
 578     return ret;
 579 }
 580
 581 static void sm501_system_config_write(void *opaque,
 582                                       target_phys_addr_t addr, uint32_t value)
 583 {
 584     SM501State * s = (SM501State *)opaque;
 585     SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n",
 586                   addr, value);
 587
 588     switch(addr) {
 589     case SM501_SYSTEM_CONTROL:
 590         s->system_control = value & 0xE300B8F7;
 591         break;
 592     case SM501_MISC_CONTROL:
 593         s->misc_control = value & 0xFF7FFF20;
 594         break;
 595     case SM501_GPIO31_0_CONTROL:
 596         s->gpio_31_0_control = value;
 597         break;
 598     case SM501_GPIO63_32_CONTROL:
 599         s->gpio_63_32_control = value;
 600         break;
 601     case SM501_DRAM_CONTROL:
 602         s->local_mem_size_index = (value >> 13) & 0x7;
 603         /* rODO : check validity of size change */
 604         s->dram_control |=  value & 0x7FFFFFC3;
 605         break;
 606     case SM501_IRQ_MASK:
 607         s->irq_mask = value;
 608         break;
 609     case SM501_MISC_TIMING:
 610         s->misc_timing = value & 0xF31F1FFF;
 611         break;
 612     case SM501_POWER_MODE_0_GATE:
 613     case SM501_POWER_MODE_1_GATE:
 614     case SM501_POWER_MODE_0_CLOCK:
 615     case SM501_POWER_MODE_1_CLOCK:
 616         /* TODO : simulate gate & clock control */
 617         break;
 618     case SM501_POWER_MODE_CONTROL:
 619         s->power_mode_control = value & 0x00000003;
 620         break;
 621
 622     default:
 623         printf("sm501 system config : not implemented register write."
 624                " addr=%x, val=%x\n", (int)addr, value);
 625         assert(0);
 626     }
 627 }
 628
 629 static CPUReadMemoryFunc *sm501_system_config_readfn[] = {
 630     NULL,
 631     NULL,
 632     &sm501_system_config_read,
 633 };
 634
 635 static CPUWriteMemoryFunc *sm501_system_config_writefn[] = {
 636     NULL,
 637     NULL,
 638     &sm501_system_config_write,
 639 };
 640
 641 static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr)
 642 {
 643     SM501State * s = (SM501State *)opaque;
 644     uint32_t ret = 0;
 645     SM501_DPRINTF("sm501 disp ctrl regs : read addr=%x\n", (int)addr);
 646
 647     switch(addr) {
 648
 649     case SM501_DC_PANEL_CONTROL:
 650         ret = s->dc_panel_control;
 651         break;
 652     case SM501_DC_PANEL_PANNING_CONTROL:
 653         ret = s->dc_panel_panning_control;
 654         break;
 655     case SM501_DC_PANEL_FB_ADDR:
 656         ret = s->dc_panel_fb_addr;
 657         break;
 658     case SM501_DC_PANEL_FB_OFFSET:
 659         ret = s->dc_panel_fb_offset;
 660         break;
 661     case SM501_DC_PANEL_FB_WIDTH:
 662         ret = s->dc_panel_fb_width;
 663         break;
 664     case SM501_DC_PANEL_FB_HEIGHT:
 665         ret = s->dc_panel_fb_height;
 666         break;
 667     case SM501_DC_PANEL_TL_LOC:
 668         ret = s->dc_panel_tl_location;
 669         break;
 670     case SM501_DC_PANEL_BR_LOC:
 671         ret = s->dc_panel_br_location;
 672         break;
 673
 674     case SM501_DC_PANEL_H_TOT:
 675         ret = s->dc_panel_h_total;
 676         break;
 677     case SM501_DC_PANEL_H_SYNC:
 678         ret = s->dc_panel_h_sync;
 679         break;
 680     case SM501_DC_PANEL_V_TOT:
 681         ret = s->dc_panel_v_total;
 682         break;
 683     case SM501_DC_PANEL_V_SYNC:
 684         ret = s->dc_panel_v_sync;
 685         break;
 686
 687     case SM501_DC_CRT_CONTROL:
 688         ret = s->dc_crt_control;
 689         break;
 690     case SM501_DC_CRT_FB_ADDR:
 691         ret = s->dc_crt_fb_addr;
 692         break;
 693     case SM501_DC_CRT_FB_OFFSET:
 694         ret = s->dc_crt_fb_offset;
 695         break;
 696     case SM501_DC_CRT_H_TOT:
 697         ret = s->dc_crt_h_total;
 698         break;
 699     case SM501_DC_CRT_H_SYNC:
 700         ret = s->dc_crt_h_sync;
 701         break;
 702     case SM501_DC_CRT_V_TOT:
 703         ret = s->dc_crt_v_total;
 704         break;
 705     case SM501_DC_CRT_V_SYNC:
 706         ret = s->dc_crt_v_sync;
 707         break;
 708
 709     case SM501_DC_CRT_HWC_ADDR:
 710         ret = s->dc_crt_hwc_addr;
 711         break;
 712     case SM501_DC_CRT_HWC_LOC:
 713         ret = s->dc_crt_hwc_addr;
 714         break;
 715     case SM501_DC_CRT_HWC_COLOR_1_2:
 716         ret = s->dc_crt_hwc_addr;
 717         break;
 718     case SM501_DC_CRT_HWC_COLOR_3:
 719         ret = s->dc_crt_hwc_addr;
 720         break;
 721
 722     default:
 723         printf("sm501 disp ctrl : not implemented register read."
 724                " addr=%x\n", (int)addr);
 725         assert(0);
 726     }
 727
 728     return ret;
 729 }
 730
 731 static void sm501_disp_ctrl_write(void *opaque,
 732                                            target_phys_addr_t addr,
 733                                            uint32_t value)
 734 {
 735     SM501State * s = (SM501State *)opaque;
 736     SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n",
 737                   addr, value);
 738
 739     switch(addr) {
 740     case SM501_DC_PANEL_CONTROL:
 741         s->dc_panel_control = value & 0x0FFF73FF;
 742         break;
 743     case SM501_DC_PANEL_PANNING_CONTROL:
 744         s->dc_panel_panning_control = value & 0xFF3FFF3F;
 745         break;
 746     case SM501_DC_PANEL_FB_ADDR:
 747         s->dc_panel_fb_addr = value & 0x8FFFFFF0;
 748         break;
 749     case SM501_DC_PANEL_FB_OFFSET:
 750         s->dc_panel_fb_offset = value & 0x3FF03FF0;
 751         break;
 752     case SM501_DC_PANEL_FB_WIDTH:
 753         s->dc_panel_fb_width = value & 0x0FFF0FFF;
 754         break;
 755     case SM501_DC_PANEL_FB_HEIGHT:
 756         s->dc_panel_fb_height = value & 0x0FFF0FFF;
 757         break;
 758     case SM501_DC_PANEL_TL_LOC:
 759         s->dc_panel_tl_location = value & 0x07FF07FF;
 760         break;
 761     case SM501_DC_PANEL_BR_LOC:
 762         s->dc_panel_br_location = value & 0x07FF07FF;
 763         break;
 764
 765     case SM501_DC_PANEL_H_TOT:
 766         s->dc_panel_h_total = value & 0x0FFF0FFF;
 767         break;
 768     case SM501_DC_PANEL_H_SYNC:
 769         s->dc_panel_h_sync = value & 0x00FF0FFF;
 770         break;
 771     case SM501_DC_PANEL_V_TOT:
 772         s->dc_panel_v_total = value & 0x0FFF0FFF;
 773         break;
 774     case SM501_DC_PANEL_V_SYNC:
 775         s->dc_panel_v_sync = value & 0x003F0FFF;
 776         break;
 777
 778     case SM501_DC_PANEL_HWC_ADDR:
 779         s->dc_panel_hwc_addr = value & 0x8FFFFFF0;
 780         break;
 781     case SM501_DC_PANEL_HWC_LOC:
 782         s->dc_panel_hwc_addr = value & 0x0FFF0FFF;
 783         break;
 784     case SM501_DC_PANEL_HWC_COLOR_1_2:
 785         s->dc_panel_hwc_addr = value;
 786         break;
 787     case SM501_DC_PANEL_HWC_COLOR_3:
 788         s->dc_panel_hwc_addr = value & 0x0000FFFF;
 789         break;
 790
 791     case SM501_DC_CRT_CONTROL:
 792         s->dc_crt_control = value & 0x0003FFFF;
 793         break;
 794     case SM501_DC_CRT_FB_ADDR:
 795         s->dc_crt_fb_addr = value & 0x8FFFFFF0;
 796         break;
 797     case SM501_DC_CRT_FB_OFFSET:
 798         s->dc_crt_fb_offset = value & 0x3FF03FF0;
 799         break;
 800     case SM501_DC_CRT_H_TOT:
 801         s->dc_crt_h_total = value & 0x0FFF0FFF;
 802         break;
 803     case SM501_DC_CRT_H_SYNC:
 804         s->dc_crt_h_sync = value & 0x00FF0FFF;
 805         break;
 806     case SM501_DC_CRT_V_TOT:
 807         s->dc_crt_v_total = value & 0x0FFF0FFF;
 808         break;
 809     case SM501_DC_CRT_V_SYNC:
 810         s->dc_crt_v_sync = value & 0x003F0FFF;
 811         break;
 812
 813     case SM501_DC_CRT_HWC_ADDR:
 814         s->dc_crt_hwc_addr = value & 0x8FFFFFF0;
 815         break;
 816     case SM501_DC_CRT_HWC_LOC:
 817         s->dc_crt_hwc_addr = value & 0x0FFF0FFF;
 818         break;
 819     case SM501_DC_CRT_HWC_COLOR_1_2:
 820         s->dc_crt_hwc_addr = value;
 821         break;
 822     case SM501_DC_CRT_HWC_COLOR_3:
 823         s->dc_crt_hwc_addr = value & 0x0000FFFF;
 824         break;
 825
 826     default:
 827         printf("sm501 disp ctrl : not implemented register write."
 828                " addr=%x, val=%x\n", (int)addr, value);
 829         assert(0);
 830     }
 831 }
 832
 833 static CPUReadMemoryFunc *sm501_disp_ctrl_readfn[] = {
 834     NULL,
 835     NULL,
 836     &sm501_disp_ctrl_read,
 837 };
 838
 839 static CPUWriteMemoryFunc *sm501_disp_ctrl_writefn[] = {
 840     NULL,
 841     NULL,
 842     &sm501_disp_ctrl_write,
 843 };
 844
 845 static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr)
 846 {
 847     SM501State * s = (SM501State *)opaque;
 848     SM501_DPRINTF("sm501 palette read addr=%x\n", (int)addr);
 849
 850     /* TODO : consider BYTE/WORD access */
 851     /* TODO : consider endian */
 852
 853     assert(0 <= addr && addr < 0x400 * 3);
 854     return *(uint32_t*)&s->dc_palette[addr];
 855 }
 856
 857 static void sm501_palette_write(void *opaque,
 858                                 target_phys_addr_t addr, uint32_t value)
 859 {
 860     SM501State * s = (SM501State *)opaque;
 861     SM501_DPRINTF("sm501 palette write addr=%x, val=%x\n",
 862                   (int)addr, value);
 863
 864     /* TODO : consider BYTE/WORD access */
 865     /* TODO : consider endian */
 866
 867     assert(0 <= addr && addr < 0x400 * 3);
 868     *(uint32_t*)&s->dc_palette[addr] = value;
 869 }
 870
 871 static CPUReadMemoryFunc *sm501_palette_readfn[] = {
 872     &sm501_palette_read,
 873     &sm501_palette_read,
 874     &sm501_palette_read,
 875 };
 876
 877 static CPUWriteMemoryFunc *sm501_palette_writefn[] = {
 878     &sm501_palette_write,
 879     &sm501_palette_write,
 880     &sm501_palette_write,
 881 };
 882
 883
 884 /* draw line functions for all console modes */
 885
 886 #include "pixel_ops.h"
 887
 888 typedef void draw_line_func(uint8_t *d, const uint8_t *s,
 889                             int width, const uint32_t *pal);
 890
 891 #define DEPTH 8
 892 #include "sm501_template.h"
 893
 894 #define DEPTH 15
 895 #include "sm501_template.h"
 896
 897 #define BGR_FORMAT
 898 #define DEPTH 15
 899 #include "sm501_template.h"
 900
 901 #define DEPTH 16
 902 #include "sm501_template.h"
 903
 904 #define BGR_FORMAT
 905 #define DEPTH 16
 906 #include "sm501_template.h"
 907
 908 #define DEPTH 32
 909 #include "sm501_template.h"
 910
 911 #define BGR_FORMAT
 912 #define DEPTH 32
 913 #include "sm501_template.h"
 914
 915 static draw_line_func * draw_line8_funcs[] = {
 916     draw_line8_8,
 917     draw_line8_15,
 918     draw_line8_16,
 919     draw_line8_32,
 920     draw_line8_32bgr,
 921     draw_line8_15bgr,
 922     draw_line8_16bgr,
 923 };
 924
 925 static draw_line_func * draw_line16_funcs[] = {
 926     draw_line16_8,
 927     draw_line16_15,
 928     draw_line16_16,
 929     draw_line16_32,
 930     draw_line16_32bgr,
 931     draw_line16_15bgr,
 932     draw_line16_16bgr,
 933 };
 934
 935 static draw_line_func * draw_line32_funcs[] = {
 936     draw_line32_8,
 937     draw_line32_15,
 938     draw_line32_16,
 939     draw_line32_32,
 940     draw_line32_32bgr,
 941     draw_line32_15bgr,
 942     draw_line32_16bgr,
 943 };
 944
 945 static inline int get_depth_index(DisplayState *s)
 946 {
 947     switch(s->depth) {
 948     default:
 949     case 8:
 950         return 0;
 951     case 15:
 952         if (s->bgr)
 953             return 5;
 954         else
 955             return 1;
 956     case 16:
 957         if (s->bgr)
 958             return 6;
 959         else
 960             return 2;
 961     case 32:
 962         if (s->bgr)
 963             return 4;
 964         else
 965             return 3;
 966     }
 967 }
 968
 969 static void sm501_draw_crt(SM501State * s)
 970 {
 971     int y;
 972     int width = (s->dc_crt_h_total & 0x00000FFF) + 1;
 973     int height = (s->dc_crt_v_total & 0x00000FFF) + 1;
 974
 975     uint8_t  * src = s->local_mem;
 976     int src_bpp = 0;
 977     int dst_bpp = s->ds->depth / 8 + (s->ds->depth % 8 ? 1 : 0);
 978     uint32_t * palette = (uint32_t *)&s->dc_palette[SM501_DC_CRT_PALETTE
 979                                                     - SM501_DC_PANEL_PALETTE];
 980     int ds_depth_index = get_depth_index(s->ds);
 981     draw_line_func * draw_line = NULL;
 982     int full_update = 0;
 983     int y_start = -1;
 984     int page_min = 0x7fffffff;
 985     int page_max = -1;
 986
 987     /* choose draw_line function */
 988     switch (s->dc_crt_control & 3) {
 989     case SM501_DC_CRT_CONTROL_8BPP:
 990         src_bpp = 1;
 991         draw_line = draw_line8_funcs[ds_depth_index];
 992         break;
 993     case SM501_DC_CRT_CONTROL_16BPP:
 994         src_bpp = 2;
 995         draw_line = draw_line16_funcs[ds_depth_index];
 996         break;
 997     case SM501_DC_CRT_CONTROL_32BPP:
 998         src_bpp = 4;
 999         draw_line = draw_line32_funcs[ds_depth_index];
1000         break;
1001     default:
1002         printf("sm501 draw crt : invalid DC_CRT_CONTROL=%x.\n",
1003                s->dc_crt_control);
1004         assert(0);
1005         break;
1006     }
1007
1008     /* adjust console size */
1009     if (s->last_width != width || s->last_height != height) {
1010         qemu_console_resize(s->console, width, height);
1011         s->last_width = width;
1012         s->last_height = height;
1013         full_update = 1;
1014     }
1015
1016     /* draw each line according to conditions */
1017     for (y = 0; y < height; y++) {
1018         int update = full_update;
1019         uint8_t * line_end = &src[width * src_bpp - 1];
1020         int page0 = (src - phys_ram_base) & TARGET_PAGE_MASK;
1021         int page1 = (line_end - phys_ram_base) & TARGET_PAGE_MASK;
1022         int page;
1023
1024         /* check dirty flags for each line */
1025         for (page = page0; page <= page1; page += TARGET_PAGE_SIZE)
1026             if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG))
1027                 update = 1;
1028
1029         /* draw line and change status */
1030         if (update) {
1031             draw_line(&s->ds->data[y * width * dst_bpp], src, width, palette);
1032             if (y_start < 0)
1033                 y_start = y;
1034             if (page0 < page_min)
1035                 page_min = page0;
1036             if (page1 > page_max)
1037                 page_max = page1;
1038         } else {
1039             if (y_start >= 0) {
1040                 /* flush to display */
1041                 dpy_update(s->ds, 0, y_start, width, y - y_start);
1042                 y_start = -1;
1043             }
1044         }
1045
1046         src += width * src_bpp;
1047     }
1048
1049     /* complete flush to display */
1050     if (y_start >= 0)
1051         dpy_update(s->ds, 0, y_start, width, y - y_start);
1052
1053     /* clear dirty flags */
1054     if (page_max != -1)
1055         cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1056                                         VGA_DIRTY_FLAG);
1057 }
1058
1059 static void sm501_update_display(void *opaque)
1060 {
1061     SM501State * s = (SM501State *)opaque;
1062
1063     if (s->dc_crt_control & SM501_DC_CRT_CONTROL_ENABLE)
1064         sm501_draw_crt(s);
1065 }
1066
1067 void sm501_init(DisplayState *ds, uint32_t base, unsigned long local_mem_base,
1068                 uint32_t local_mem_bytes, CharDriverState *chr)
1069 {
1070     SM501State * s;
1071     int sm501_system_config_index;
1072     int sm501_disp_ctrl_index;
1073     int sm501_palette_index;
1074
1075     /* allocate management data region */
1076     s = (SM501State *)qemu_mallocz(sizeof(SM501State));
1077     s->base = base;
1078     s->local_mem_size_index
1079         = get_local_mem_size_index(local_mem_bytes);
1080     SM501_DPRINTF("local mem size=%x. index=%d\n", get_local_mem_size(s),
1081                   s->local_mem_size_index);
1082     s->system_control = 0x00100000;
1083     s->misc_control = 0x00001000; /* assumes SH, active=low */
1084     s->dc_panel_control = 0x00010000;
1085     s->dc_crt_control = 0x00010000;
1086     s->ds = ds;
1087
1088     /* allocate local memory */
1089     s->local_mem = (uint8 *)phys_ram_base + local_mem_base;
1090     cpu_register_physical_memory(base, local_mem_bytes, local_mem_base);
1091
1092     /* map mmio */
1093     sm501_system_config_index
1094         = cpu_register_io_memory(0, sm501_system_config_readfn,
1095                                  sm501_system_config_writefn, s);
1096     cpu_register_physical_memory(base + MMIO_BASE_OFFSET,
1097                                  0x6c, sm501_system_config_index);
1098     sm501_disp_ctrl_index = cpu_register_io_memory(0, sm501_disp_ctrl_readfn,
1099                                                    sm501_disp_ctrl_writefn, s);
1100     cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC,
1101                                  0x400, sm501_disp_ctrl_index);
1102
1103     sm501_palette_index = cpu_register_io_memory(0, sm501_palette_readfn,
1104                                                    sm501_palette_writefn, s);
1105     cpu_register_physical_memory(base + MMIO_BASE_OFFSET
1106                                  + SM501_DC + SM501_DC_PANEL_PALETTE,
1107                                  0x400 * 3, sm501_palette_index);
1108
1109     /* bridge to serial emulation module */
1110     if (chr)
1111         serial_mm_init(base + MMIO_BASE_OFFSET + SM501_UART0, 2,
1112                        0, /* TODO : chain irq to IRL */
1113                        115200, chr, 1);
1114
1115     /* create qemu graphic console */
1116     s->console = graphic_console_init(s->ds, sm501_update_display, NULL,
1117                                       NULL, NULL, s);
1118 }