tests/q35-test.c

   1 /*
   2  * QTest testcase for Q35 northbridge
   3  *
   4  * Copyright (c) 2015 Red Hat, Inc.
   5  *
   6  * Author: Gerd Hoffmann <[email protected]>
   7  *
   8  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   9  * See the COPYING file in the top-level directory.
  10  */
  11
  12 #include "qemu/osdep.h"
  13 #include "libqtest.h"
  14 #include "libqos/pci.h"
  15 #include "libqos/pci-pc.h"
  16 #include "hw/pci-host/q35.h"
  17 #include "qapi/qmp/qdict.h"
  18
  19 #define TSEG_SIZE_TEST_GUEST_RAM_MBYTES 128
  20
  21 /* @esmramc_tseg_sz: ESMRAMC.TSEG_SZ bitmask for selecting the requested TSEG
  22  *                   size. Must be a subset of
  23  *                   MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK.
  24  *
  25  * @extended_tseg_mbytes: Size of the extended TSEG. Only consulted if
  26  *                        @esmramc_tseg_sz equals
  27  *                        MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK precisely.
  28  *
  29  * @expected_tseg_mbytes: Expected guest-visible TSEG size in megabytes,
  30  *                        matching @esmramc_tseg_sz and @extended_tseg_mbytes
  31  *                        above.
  32  */
  33 struct TsegSizeArgs {
  34     uint8_t esmramc_tseg_sz;
  35     uint16_t extended_tseg_mbytes;
  36     uint16_t expected_tseg_mbytes;
  37 };
  38 typedef struct TsegSizeArgs TsegSizeArgs;
  39
  40 static const TsegSizeArgs tseg_1mb = {
  41     .esmramc_tseg_sz      = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB,
  42     .extended_tseg_mbytes = 0,
  43     .expected_tseg_mbytes = 1,
  44 };
  45 static const TsegSizeArgs tseg_2mb = {
  46     .esmramc_tseg_sz      = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB,
  47     .extended_tseg_mbytes = 0,
  48     .expected_tseg_mbytes = 2,
  49 };
  50 static const TsegSizeArgs tseg_8mb = {
  51     .esmramc_tseg_sz      = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB,
  52     .extended_tseg_mbytes = 0,
  53     .expected_tseg_mbytes = 8,
  54 };
  55 static const TsegSizeArgs tseg_ext_16mb = {
  56     .esmramc_tseg_sz      = MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK,
  57     .extended_tseg_mbytes = 16,
  58     .expected_tseg_mbytes = 16,
  59 };
  60
  61 static void smram_set_bit(QPCIDevice *pcidev, uint8_t mask, bool enabled)
  62 {
  63     uint8_t smram;
  64
  65     smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
  66     if (enabled) {
  67         smram |= mask;
  68     } else {
  69         smram &= ~mask;
  70     }
  71     qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram);
  72 }
  73
  74 static bool smram_test_bit(QPCIDevice *pcidev, uint8_t mask)
  75 {
  76     uint8_t smram;
  77
  78     smram = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
  79     return smram & mask;
  80 }
  81
  82 static void test_smram_lock(void)
  83 {
  84     QPCIBus *pcibus;
  85     QPCIDevice *pcidev;
  86     QDict *response;
  87
  88     qtest_start("-M q35");
  89
  90     pcibus = qpci_init_pc(global_qtest, NULL);
  91     g_assert(pcibus != NULL);
  92
  93     pcidev = qpci_device_find(pcibus, 0);
  94     g_assert(pcidev != NULL);
  95
  96     /* check open is settable */
  97     smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
  98     g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
  99     smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
 100     g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
 101
 102     /* lock, check open is cleared & not settable */
 103     smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_LCK, true);
 104     g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
 105     smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
 106     g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
 107
 108     /* reset */
 109     response = qmp("{'execute': 'system_reset', 'arguments': {} }");
 110     g_assert(response);
 111     g_assert(!qdict_haskey(response, "error"));
 112     qobject_unref(response);
 113
 114     /* check open is settable again */
 115     smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, false);
 116     g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == false);
 117     smram_set_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN, true);
 118     g_assert(smram_test_bit(pcidev, MCH_HOST_BRIDGE_SMRAM_D_OPEN) == true);
 119
 120     g_free(pcidev);
 121     qpci_free_pc(pcibus);
 122
 123     qtest_end();
 124 }
 125
 126 static void test_tseg_size(const void *data)
 127 {
 128     const TsegSizeArgs *args = data;
 129     char *cmdline;
 130     QPCIBus *pcibus;
 131     QPCIDevice *pcidev;
 132     uint8_t smram_val;
 133     uint8_t esmramc_val;
 134     uint32_t ram_offs;
 135
 136     if (args->esmramc_tseg_sz == MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) {
 137         cmdline = g_strdup_printf("-M q35 -m %uM "
 138                                   "-global mch.extended-tseg-mbytes=%u",
 139                                   TSEG_SIZE_TEST_GUEST_RAM_MBYTES,
 140                                   args->extended_tseg_mbytes);
 141     } else {
 142         cmdline = g_strdup_printf("-M q35 -m %uM",
 143                                   TSEG_SIZE_TEST_GUEST_RAM_MBYTES);
 144     }
 145     qtest_start(cmdline);
 146     g_free(cmdline);
 147
 148     /* locate the DRAM controller */
 149     pcibus = qpci_init_pc(global_qtest, NULL);
 150     g_assert(pcibus != NULL);
 151     pcidev = qpci_device_find(pcibus, 0);
 152     g_assert(pcidev != NULL);
 153
 154     /* Set TSEG size. Restrict TSEG visibility to SMM by setting T_EN. */
 155     esmramc_val = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_ESMRAMC);
 156     esmramc_val &= ~MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK;
 157     esmramc_val |= args->esmramc_tseg_sz;
 158     esmramc_val |= MCH_HOST_BRIDGE_ESMRAMC_T_EN;
 159     qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_ESMRAMC, esmramc_val);
 160
 161     /* Enable TSEG by setting G_SMRAME. Close TSEG by setting D_CLS. */
 162     smram_val = qpci_config_readb(pcidev, MCH_HOST_BRIDGE_SMRAM);
 163     smram_val &= ~(MCH_HOST_BRIDGE_SMRAM_D_OPEN |
 164                    MCH_HOST_BRIDGE_SMRAM_D_LCK);
 165     smram_val |= (MCH_HOST_BRIDGE_SMRAM_D_CLS |
 166                   MCH_HOST_BRIDGE_SMRAM_G_SMRAME);
 167     qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val);
 168
 169     /* lock TSEG */
 170     smram_val |= MCH_HOST_BRIDGE_SMRAM_D_LCK;
 171     qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_SMRAM, smram_val);
 172
 173     /* Now check that the byte right before the TSEG is r/w, and that the first
 174      * byte in the TSEG always reads as 0xff.
 175      */
 176     ram_offs = (TSEG_SIZE_TEST_GUEST_RAM_MBYTES - args->expected_tseg_mbytes) *
 177                1024 * 1024 - 1;
 178     g_assert_cmpint(readb(ram_offs), ==, 0);
 179     writeb(ram_offs, 1);
 180     g_assert_cmpint(readb(ram_offs), ==, 1);
 181
 182     ram_offs++;
 183     g_assert_cmpint(readb(ram_offs), ==, 0xff);
 184     writeb(ram_offs, 1);
 185     g_assert_cmpint(readb(ram_offs), ==, 0xff);
 186
 187     g_free(pcidev);
 188     qpci_free_pc(pcibus);
 189     qtest_end();
 190 }
 191
 192 int main(int argc, char **argv)
 193 {
 194     g_test_init(&argc, &argv, NULL);
 195
 196     qtest_add_func("/q35/smram/lock", test_smram_lock);
 197
 198     qtest_add_data_func("/q35/tseg-size/1mb", &tseg_1mb, test_tseg_size);
 199     qtest_add_data_func("/q35/tseg-size/2mb", &tseg_2mb, test_tseg_size);
 200     qtest_add_data_func("/q35/tseg-size/8mb", &tseg_8mb, test_tseg_size);
 201     qtest_add_data_func("/q35/tseg-size/ext/16mb", &tseg_ext_16mb,
 202                         test_tseg_size);
 203     return g_test_run();
 204 }