target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "sysemu/kvm.h"
  26 #include "sysemu/cpus.h"
  27 #include "kvm_i386.h"
  28 #include "topology.h"
  29
  30 #include "qemu/option.h"
  31 #include "qemu/config-file.h"
  32 #include "qapi/qmp/qerror.h"
  33
  34 #include "qapi-types.h"
  35 #include "qapi-visit.h"
  36 #include "qapi/visitor.h"
  37 #include "sysemu/arch_init.h"
  38
  39 #include "hw/hw.h"
  40 #if defined(CONFIG_KVM)
  41 #include <linux/kvm_para.h>
  42 #endif
  43
  44 #include "sysemu/sysemu.h"
  45 #include "hw/qdev-properties.h"
  46 #include "hw/cpu/icc_bus.h"
  47 #ifndef CONFIG_USER_ONLY
  48 #include "hw/xen/xen.h"
  49 #include "hw/i386/apic_internal.h"
  50 #endif
  51
  52
  53 /* Cache topology CPUID constants: */
  54
  55 /* CPUID Leaf 2 Descriptors */
  56
  57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
  58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
  59 #define CPUID_2_L2_2MB_8WAY_64B   0x7d
  60
  61
  62 /* CPUID Leaf 4 constants: */
  63
  64 /* EAX: */
  65 #define CPUID_4_TYPE_DCACHE  1
  66 #define CPUID_4_TYPE_ICACHE  2
  67 #define CPUID_4_TYPE_UNIFIED 3
  68
  69 #define CPUID_4_LEVEL(l)          ((l) << 5)
  70
  71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
  72 #define CPUID_4_FULLY_ASSOC     (1 << 9)
  73
  74 /* EDX: */
  75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
  76 #define CPUID_4_INCLUSIVE       (1 << 1)
  77 #define CPUID_4_COMPLEX_IDX     (1 << 2)
  78
  79 #define ASSOC_FULL 0xFF
  80
  81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
  82 #define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
  83                           a ==   2 ? 0x2 : \
  84                           a ==   4 ? 0x4 : \
  85                           a ==   8 ? 0x6 : \
  86                           a ==  16 ? 0x8 : \
  87                           a ==  32 ? 0xA : \
  88                           a ==  48 ? 0xB : \
  89                           a ==  64 ? 0xC : \
  90                           a ==  96 ? 0xD : \
  91                           a == 128 ? 0xE : \
  92                           a == ASSOC_FULL ? 0xF : \
  93                           0 /* invalid value */)
  94
  95
  96 /* Definitions of the hardcoded cache entries we expose: */
  97
  98 /* L1 data cache: */
  99 #define L1D_LINE_SIZE         64
 100 #define L1D_ASSOCIATIVITY      8
 101 #define L1D_SETS              64
 102 #define L1D_PARTITIONS         1
 103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
 105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 106 #define L1D_LINES_PER_TAG      1
 107 #define L1D_SIZE_KB_AMD       64
 108 #define L1D_ASSOCIATIVITY_AMD  2
 109
 110 /* L1 instruction cache: */
 111 #define L1I_LINE_SIZE         64
 112 #define L1I_ASSOCIATIVITY      8
 113 #define L1I_SETS              64
 114 #define L1I_PARTITIONS         1
 115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
 117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 118 #define L1I_LINES_PER_TAG      1
 119 #define L1I_SIZE_KB_AMD       64
 120 #define L1I_ASSOCIATIVITY_AMD  2
 121
 122 /* Level 2 unified cache: */
 123 #define L2_LINE_SIZE          64
 124 #define L2_ASSOCIATIVITY      16
 125 #define L2_SETS             4096
 126 #define L2_PARTITIONS          1
 127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
 128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
 129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
 130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
 131 #define L2_LINES_PER_TAG       1
 132 #define L2_SIZE_KB_AMD       512
 133
 134 /* No L3 cache: */
 135 #define L3_SIZE_KB             0 /* disabled */
 136 #define L3_ASSOCIATIVITY       0 /* disabled */
 137 #define L3_LINES_PER_TAG       0 /* disabled */
 138 #define L3_LINE_SIZE           0 /* disabled */
 139
 140 /* TLB definitions: */
 141
 142 #define L1_DTLB_2M_ASSOC       1
 143 #define L1_DTLB_2M_ENTRIES   255
 144 #define L1_DTLB_4K_ASSOC       1
 145 #define L1_DTLB_4K_ENTRIES   255
 146
 147 #define L1_ITLB_2M_ASSOC       1
 148 #define L1_ITLB_2M_ENTRIES   255
 149 #define L1_ITLB_4K_ASSOC       1
 150 #define L1_ITLB_4K_ENTRIES   255
 151
 152 #define L2_DTLB_2M_ASSOC       0 /* disabled */
 153 #define L2_DTLB_2M_ENTRIES     0 /* disabled */
 154 #define L2_DTLB_4K_ASSOC       4
 155 #define L2_DTLB_4K_ENTRIES   512
 156
 157 #define L2_ITLB_2M_ASSOC       0 /* disabled */
 158 #define L2_ITLB_2M_ENTRIES     0 /* disabled */
 159 #define L2_ITLB_4K_ASSOC       4
 160 #define L2_ITLB_4K_ENTRIES   512
 161
 162
 163
 164 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 165                                      uint32_t vendor2, uint32_t vendor3)
 166 {
 167     int i;
 168     for (i = 0; i < 4; i++) {
 169         dst[i] = vendor1 >> (8 * i);
 170         dst[i + 4] = vendor2 >> (8 * i);
 171         dst[i + 8] = vendor3 >> (8 * i);
 172     }
 173     dst[CPUID_VENDOR_SZ] = '\0';
 174 }
 175
 176 /* feature flags taken from "Intel Processor Identification and the CPUID
 177  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
 178  * between feature naming conventions, aliases may be added.
 179  */
 180 static const char *feature_name[] = {
 181     "fpu", "vme", "de", "pse",
 182     "tsc", "msr", "pae", "mce",
 183     "cx8", "apic", NULL, "sep",
 184     "mtrr", "pge", "mca", "cmov",
 185     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
 186     NULL, "ds" /* Intel dts */, "acpi", "mmx",
 187     "fxsr", "sse", "sse2", "ss",
 188     "ht" /* Intel htt */, "tm", "ia64", "pbe",
 189 };
 190 static const char *ext_feature_name[] = {
 191     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
 192     "ds_cpl", "vmx", "smx", "est",
 193     "tm2", "ssse3", "cid", NULL,
 194     "fma", "cx16", "xtpr", "pdcm",
 195     NULL, "pcid", "dca", "sse4.1|sse4_1",
 196     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
 197     "tsc-deadline", "aes", "xsave", "osxsave",
 198     "avx", "f16c", "rdrand", "hypervisor",
 199 };
 200 /* Feature names that are already defined on feature_name[] but are set on
 201  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
 202  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
 203  * if and only if CPU vendor is AMD.
 204  */
 205 static const char *ext2_feature_name[] = {
 206     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
 207     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
 208     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
 209     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
 210     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
 211     "nx|xd", NULL, "mmxext", NULL /* mmx */,
 212     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
 213     NULL, "lm|i64", "3dnowext", "3dnow",
 214 };
 215 static const char *ext3_feature_name[] = {
 216     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
 217     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
 218     "3dnowprefetch", "osvw", "ibs", "xop",
 219     "skinit", "wdt", NULL, "lwp",
 220     "fma4", "tce", NULL, "nodeid_msr",
 221     NULL, "tbm", "topoext", "perfctr_core",
 222     "perfctr_nb", NULL, NULL, NULL,
 223     NULL, NULL, NULL, NULL,
 224 };
 225
 226 static const char *ext4_feature_name[] = {
 227     NULL, NULL, "xstore", "xstore-en",
 228     NULL, NULL, "xcrypt", "xcrypt-en",
 229     "ace2", "ace2-en", "phe", "phe-en",
 230     "pmm", "pmm-en", NULL, NULL,
 231     NULL, NULL, NULL, NULL,
 232     NULL, NULL, NULL, NULL,
 233     NULL, NULL, NULL, NULL,
 234     NULL, NULL, NULL, NULL,
 235 };
 236
 237 static const char *kvm_feature_name[] = {
 238     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 239     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
 240     NULL, NULL, NULL, NULL,
 241     NULL, NULL, NULL, NULL,
 242     NULL, NULL, NULL, NULL,
 243     NULL, NULL, NULL, NULL,
 244     NULL, NULL, NULL, NULL,
 245     NULL, NULL, NULL, NULL,
 246 };
 247
 248 static const char *svm_feature_name[] = {
 249     "npt", "lbrv", "svm_lock", "nrip_save",
 250     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 251     NULL, NULL, "pause_filter", NULL,
 252     "pfthreshold", NULL, NULL, NULL,
 253     NULL, NULL, NULL, NULL,
 254     NULL, NULL, NULL, NULL,
 255     NULL, NULL, NULL, NULL,
 256     NULL, NULL, NULL, NULL,
 257 };
 258
 259 static const char *cpuid_7_0_ebx_feature_name[] = {
 260     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
 261     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
 262     NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
 263     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 264 };
 265
 266 typedef struct FeatureWordInfo {
 267     const char **feat_names;
 268     uint32_t cpuid_eax;   /* Input EAX for CPUID */
 269     bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
 270     uint32_t cpuid_ecx;   /* Input ECX value for CPUID */
 271     int cpuid_reg;        /* output register (R_* constant) */
 272 } FeatureWordInfo;
 273
 274 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 275     [FEAT_1_EDX] = {
 276         .feat_names = feature_name,
 277         .cpuid_eax = 1, .cpuid_reg = R_EDX,
 278     },
 279     [FEAT_1_ECX] = {
 280         .feat_names = ext_feature_name,
 281         .cpuid_eax = 1, .cpuid_reg = R_ECX,
 282     },
 283     [FEAT_8000_0001_EDX] = {
 284         .feat_names = ext2_feature_name,
 285         .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
 286     },
 287     [FEAT_8000_0001_ECX] = {
 288         .feat_names = ext3_feature_name,
 289         .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
 290     },
 291     [FEAT_C000_0001_EDX] = {
 292         .feat_names = ext4_feature_name,
 293         .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
 294     },
 295     [FEAT_KVM] = {
 296         .feat_names = kvm_feature_name,
 297         .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
 298     },
 299     [FEAT_SVM] = {
 300         .feat_names = svm_feature_name,
 301         .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
 302     },
 303     [FEAT_7_0_EBX] = {
 304         .feat_names = cpuid_7_0_ebx_feature_name,
 305         .cpuid_eax = 7,
 306         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
 307         .cpuid_reg = R_EBX,
 308     },
 309 };
 310
 311 typedef struct X86RegisterInfo32 {
 312     /* Name of register */
 313     const char *name;
 314     /* QAPI enum value register */
 315     X86CPURegister32 qapi_enum;
 316 } X86RegisterInfo32;
 317
 318 #define REGISTER(reg) \
 319     [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
 320 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
 321     REGISTER(EAX),
 322     REGISTER(ECX),
 323     REGISTER(EDX),
 324     REGISTER(EBX),
 325     REGISTER(ESP),
 326     REGISTER(EBP),
 327     REGISTER(ESI),
 328     REGISTER(EDI),
 329 };
 330 #undef REGISTER
 331
 332 typedef struct ExtSaveArea {
 333     uint32_t feature, bits;
 334     uint32_t offset, size;
 335 } ExtSaveArea;
 336
 337 static const ExtSaveArea ext_save_areas[] = {
 338     [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
 339             .offset = 0x240, .size = 0x100 },
 340     [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 341             .offset = 0x3c0, .size = 0x40  },
 342     [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 343             .offset = 0x400, .size = 0x40  },
 344 };
 345
 346 const char *get_register_name_32(unsigned int reg)
 347 {
 348     if (reg >= CPU_NB_REGS32) {
 349         return NULL;
 350     }
 351     return x86_reg_info_32[reg].name;
 352 }
 353
 354 /* collects per-function cpuid data
 355  */
 356 typedef struct model_features_t {
 357     uint32_t *guest_feat;
 358     uint32_t *host_feat;
 359     FeatureWord feat_word;
 360 } model_features_t;
 361
 362 /* KVM-specific features that are automatically added to all CPU models
 363  * when KVM is enabled.
 364  */
 365 static uint32_t kvm_default_features[FEATURE_WORDS] = {
 366     [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
 367         (1 << KVM_FEATURE_NOP_IO_DELAY) |
 368         (1 << KVM_FEATURE_CLOCKSOURCE2) |
 369         (1 << KVM_FEATURE_ASYNC_PF) |
 370         (1 << KVM_FEATURE_STEAL_TIME) |
 371         (1 << KVM_FEATURE_PV_EOI) |
 372         (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
 373     [FEAT_1_ECX] = CPUID_EXT_X2APIC,
 374 };
 375
 376 /* Features that are not added by default to any CPU model when KVM is enabled.
 377  */
 378 static uint32_t kvm_default_unset_features[FEATURE_WORDS] = {
 379     [FEAT_1_ECX] = CPUID_EXT_MONITOR,
 380 };
 381
 382 void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
 383 {
 384     kvm_default_features[w] &= ~features;
 385 }
 386
 387 void host_cpuid(uint32_t function, uint32_t count,
 388                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 389 {
 390     uint32_t vec[4];
 391
 392 #ifdef __x86_64__
 393     asm volatile("cpuid"
 394                  : "=a"(vec[0]), "=b"(vec[1]),
 395                    "=c"(vec[2]), "=d"(vec[3])
 396                  : "0"(function), "c"(count) : "cc");
 397 #elif defined(__i386__)
 398     asm volatile("pusha \n\t"
 399                  "cpuid \n\t"
 400                  "mov %%eax, 0(%2) \n\t"
 401                  "mov %%ebx, 4(%2) \n\t"
 402                  "mov %%ecx, 8(%2) \n\t"
 403                  "mov %%edx, 12(%2) \n\t"
 404                  "popa"
 405                  : : "a"(function), "c"(count), "S"(vec)
 406                  : "memory", "cc");
 407 #else
 408     abort();
 409 #endif
 410
 411     if (eax)
 412         *eax = vec[0];
 413     if (ebx)
 414         *ebx = vec[1];
 415     if (ecx)
 416         *ecx = vec[2];
 417     if (edx)
 418         *edx = vec[3];
 419 }
 420
 421 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 422
 423 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 424  * a substring.  ex if !NULL points to the first char after a substring,
 425  * otherwise the string is assumed to sized by a terminating nul.
 426  * Return lexical ordering of *s1:*s2.
 427  */
 428 static int sstrcmp(const char *s1, const char *e1, const char *s2,
 429     const char *e2)
 430 {
 431     for (;;) {
 432         if (!*s1 || !*s2 || *s1 != *s2)
 433             return (*s1 - *s2);
 434         ++s1, ++s2;
 435         if (s1 == e1 && s2 == e2)
 436             return (0);
 437         else if (s1 == e1)
 438             return (*s2);
 439         else if (s2 == e2)
 440             return (*s1);
 441     }
 442 }
 443
 444 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 445  * '|' delimited (possibly empty) strings in which case search for a match
 446  * within the alternatives proceeds left to right.  Return 0 for success,
 447  * non-zero otherwise.
 448  */
 449 static int altcmp(const char *s, const char *e, const char *altstr)
 450 {
 451     const char *p, *q;
 452
 453     for (q = p = altstr; ; ) {
 454         while (*p && *p != '|')
 455             ++p;
 456         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 457             return (0);
 458         if (!*p)
 459             return (1);
 460         else
 461             q = ++p;
 462     }
 463 }
 464
 465 /* search featureset for flag *[s..e), if found set corresponding bit in
 466  * *pval and return true, otherwise return false
 467  */
 468 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 469                            const char **featureset)
 470 {
 471     uint32_t mask;
 472     const char **ppc;
 473     bool found = false;
 474
 475     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 476         if (*ppc && !altcmp(s, e, *ppc)) {
 477             *pval |= mask;
 478             found = true;
 479         }
 480     }
 481     return found;
 482 }
 483
 484 static void add_flagname_to_bitmaps(const char *flagname,
 485                                     FeatureWordArray words)
 486 {
 487     FeatureWord w;
 488     for (w = 0; w < FEATURE_WORDS; w++) {
 489         FeatureWordInfo *wi = &feature_word_info[w];
 490         if (wi->feat_names &&
 491             lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
 492             break;
 493         }
 494     }
 495     if (w == FEATURE_WORDS) {
 496         fprintf(stderr, "CPU feature %s not found\n", flagname);
 497     }
 498 }
 499
 500 /* CPU class name definitions: */
 501
 502 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
 503 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 504
 505 /* Return type name for a given CPU model name
 506  * Caller is responsible for freeing the returned string.
 507  */
 508 static char *x86_cpu_type_name(const char *model_name)
 509 {
 510     return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
 511 }
 512
 513 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
 514 {
 515     ObjectClass *oc;
 516     char *typename;
 517
 518     if (cpu_model == NULL) {
 519         return NULL;
 520     }
 521
 522     typename = x86_cpu_type_name(cpu_model);
 523     oc = object_class_by_name(typename);
 524     g_free(typename);
 525     return oc;
 526 }
 527
 528 struct X86CPUDefinition {
 529     const char *name;
 530     uint32_t level;
 531     uint32_t xlevel;
 532     uint32_t xlevel2;
 533     /* vendor is zero-terminated, 12 character ASCII string */
 534     char vendor[CPUID_VENDOR_SZ + 1];
 535     int family;
 536     int model;
 537     int stepping;
 538     FeatureWordArray features;
 539     char model_id[48];
 540     bool cache_info_passthrough;
 541 };
 542
 543 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 544 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 545           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 546 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 547           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 548           CPUID_PSE36 | CPUID_FXSR)
 549 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 550 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 551           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 552           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 553           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 554
 555 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 556           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 557           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 558           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 559           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
 560           /* partly implemented:
 561           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
 562           /* missing:
 563           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 564 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 565           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 566           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 567           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
 568           /* missing:
 569           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 570           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 571           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 572           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
 573           CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
 574           CPUID_EXT_RDRAND */
 575
 576 #ifdef TARGET_X86_64
 577 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
 578 #else
 579 #define TCG_EXT2_X86_64_FEATURES 0
 580 #endif
 581
 582 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 583           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 584           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
 585           TCG_EXT2_X86_64_FEATURES)
 586 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 587           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 588 #define TCG_EXT4_FEATURES 0
 589 #define TCG_SVM_FEATURES 0
 590 #define TCG_KVM_FEATURES 0
 591 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
 592           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
 593           /* missing:
 594           CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 595           CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 596           CPUID_7_0_EBX_RDSEED */
 597
 598 static X86CPUDefinition builtin_x86_defs[] = {
 599     {
 600         .name = "qemu64",
 601         .level = 4,
 602         .vendor = CPUID_VENDOR_AMD,
 603         .family = 6,
 604         .model = 6,
 605         .stepping = 3,
 606         .features[FEAT_1_EDX] =
 607             PPRO_FEATURES |
 608             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 609             CPUID_PSE36,
 610         .features[FEAT_1_ECX] =
 611             CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
 612         .features[FEAT_8000_0001_EDX] =
 613             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 614             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 615         .features[FEAT_8000_0001_ECX] =
 616             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 617             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 618         .xlevel = 0x8000000A,
 619     },
 620     {
 621         .name = "phenom",
 622         .level = 5,
 623         .vendor = CPUID_VENDOR_AMD,
 624         .family = 16,
 625         .model = 2,
 626         .stepping = 3,
 627         .features[FEAT_1_EDX] =
 628             PPRO_FEATURES |
 629             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 630             CPUID_PSE36 | CPUID_VME | CPUID_HT,
 631         .features[FEAT_1_ECX] =
 632             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 633             CPUID_EXT_POPCNT,
 634         .features[FEAT_8000_0001_EDX] =
 635             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 636             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 637             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 638             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 639         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 640                     CPUID_EXT3_CR8LEG,
 641                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 642                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 643         .features[FEAT_8000_0001_ECX] =
 644             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 645             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 646         .features[FEAT_SVM] =
 647             CPUID_SVM_NPT | CPUID_SVM_LBRV,
 648         .xlevel = 0x8000001A,
 649         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 650     },
 651     {
 652         .name = "core2duo",
 653         .level = 10,
 654         .vendor = CPUID_VENDOR_INTEL,
 655         .family = 6,
 656         .model = 15,
 657         .stepping = 11,
 658         .features[FEAT_1_EDX] =
 659             PPRO_FEATURES |
 660             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 661             CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
 662             CPUID_HT | CPUID_TM | CPUID_PBE,
 663         .features[FEAT_1_ECX] =
 664             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 665             CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
 666             CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 667         .features[FEAT_8000_0001_EDX] =
 668             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 669         .features[FEAT_8000_0001_ECX] =
 670             CPUID_EXT3_LAHF_LM,
 671         .xlevel = 0x80000008,
 672         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 673     },
 674     {
 675         .name = "kvm64",
 676         .level = 5,
 677         .vendor = CPUID_VENDOR_INTEL,
 678         .family = 15,
 679         .model = 6,
 680         .stepping = 1,
 681         /* Missing: CPUID_VME, CPUID_HT */
 682         .features[FEAT_1_EDX] =
 683             PPRO_FEATURES |
 684             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 685             CPUID_PSE36,
 686         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 687         .features[FEAT_1_ECX] =
 688             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 689         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 690         .features[FEAT_8000_0001_EDX] =
 691             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 692             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 693         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 694                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 695                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 696                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 697         .features[FEAT_8000_0001_ECX] =
 698             0,
 699         .xlevel = 0x80000008,
 700         .model_id = "Common KVM processor"
 701     },
 702     {
 703         .name = "qemu32",
 704         .level = 4,
 705         .vendor = CPUID_VENDOR_INTEL,
 706         .family = 6,
 707         .model = 6,
 708         .stepping = 3,
 709         .features[FEAT_1_EDX] =
 710             PPRO_FEATURES,
 711         .features[FEAT_1_ECX] =
 712             CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
 713         .xlevel = 0x80000004,
 714     },
 715     {
 716         .name = "kvm32",
 717         .level = 5,
 718         .vendor = CPUID_VENDOR_INTEL,
 719         .family = 15,
 720         .model = 6,
 721         .stepping = 1,
 722         .features[FEAT_1_EDX] =
 723             PPRO_FEATURES |
 724             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 725         .features[FEAT_1_ECX] =
 726             CPUID_EXT_SSE3,
 727         .features[FEAT_8000_0001_EDX] =
 728             PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
 729         .features[FEAT_8000_0001_ECX] =
 730             0,
 731         .xlevel = 0x80000008,
 732         .model_id = "Common 32-bit KVM processor"
 733     },
 734     {
 735         .name = "coreduo",
 736         .level = 10,
 737         .vendor = CPUID_VENDOR_INTEL,
 738         .family = 6,
 739         .model = 14,
 740         .stepping = 8,
 741         .features[FEAT_1_EDX] =
 742             PPRO_FEATURES | CPUID_VME |
 743             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
 744             CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 745         .features[FEAT_1_ECX] =
 746             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
 747             CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 748         .features[FEAT_8000_0001_EDX] =
 749             CPUID_EXT2_NX,
 750         .xlevel = 0x80000008,
 751         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 752     },
 753     {
 754         .name = "486",
 755         .level = 1,
 756         .vendor = CPUID_VENDOR_INTEL,
 757         .family = 4,
 758         .model = 8,
 759         .stepping = 0,
 760         .features[FEAT_1_EDX] =
 761             I486_FEATURES,
 762         .xlevel = 0,
 763     },
 764     {
 765         .name = "pentium",
 766         .level = 1,
 767         .vendor = CPUID_VENDOR_INTEL,
 768         .family = 5,
 769         .model = 4,
 770         .stepping = 3,
 771         .features[FEAT_1_EDX] =
 772             PENTIUM_FEATURES,
 773         .xlevel = 0,
 774     },
 775     {
 776         .name = "pentium2",
 777         .level = 2,
 778         .vendor = CPUID_VENDOR_INTEL,
 779         .family = 6,
 780         .model = 5,
 781         .stepping = 2,
 782         .features[FEAT_1_EDX] =
 783             PENTIUM2_FEATURES,
 784         .xlevel = 0,
 785     },
 786     {
 787         .name = "pentium3",
 788         .level = 2,
 789         .vendor = CPUID_VENDOR_INTEL,
 790         .family = 6,
 791         .model = 7,
 792         .stepping = 3,
 793         .features[FEAT_1_EDX] =
 794             PENTIUM3_FEATURES,
 795         .xlevel = 0,
 796     },
 797     {
 798         .name = "athlon",
 799         .level = 2,
 800         .vendor = CPUID_VENDOR_AMD,
 801         .family = 6,
 802         .model = 2,
 803         .stepping = 3,
 804         .features[FEAT_1_EDX] =
 805             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 806             CPUID_MCA,
 807         .features[FEAT_8000_0001_EDX] =
 808             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 809             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 810         .xlevel = 0x80000008,
 811     },
 812     {
 813         .name = "n270",
 814         /* original is on level 10 */
 815         .level = 5,
 816         .vendor = CPUID_VENDOR_INTEL,
 817         .family = 6,
 818         .model = 28,
 819         .stepping = 2,
 820         .features[FEAT_1_EDX] =
 821             PPRO_FEATURES |
 822             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
 823             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 824             /* Some CPUs got no CPUID_SEP */
 825         .features[FEAT_1_ECX] =
 826             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 827             CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
 828             CPUID_EXT_MOVBE,
 829         .features[FEAT_8000_0001_EDX] =
 830             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 831             CPUID_EXT2_NX,
 832         .features[FEAT_8000_0001_ECX] =
 833             CPUID_EXT3_LAHF_LM,
 834         .xlevel = 0x8000000A,
 835         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 836     },
 837     {
 838         .name = "Conroe",
 839         .level = 4,
 840         .vendor = CPUID_VENDOR_INTEL,
 841         .family = 6,
 842         .model = 15,
 843         .stepping = 3,
 844         .features[FEAT_1_EDX] =
 845             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 846              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 847              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 848              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 849              CPUID_DE | CPUID_FP87,
 850         .features[FEAT_1_ECX] =
 851             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 852         .features[FEAT_8000_0001_EDX] =
 853             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 854         .features[FEAT_8000_0001_ECX] =
 855             CPUID_EXT3_LAHF_LM,
 856         .xlevel = 0x8000000A,
 857         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 858     },
 859     {
 860         .name = "Penryn",
 861         .level = 4,
 862         .vendor = CPUID_VENDOR_INTEL,
 863         .family = 6,
 864         .model = 23,
 865         .stepping = 3,
 866         .features[FEAT_1_EDX] =
 867             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 868              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 869              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 870              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 871              CPUID_DE | CPUID_FP87,
 872         .features[FEAT_1_ECX] =
 873             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 874              CPUID_EXT_SSE3,
 875         .features[FEAT_8000_0001_EDX] =
 876             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 877         .features[FEAT_8000_0001_ECX] =
 878             CPUID_EXT3_LAHF_LM,
 879         .xlevel = 0x8000000A,
 880         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 881     },
 882     {
 883         .name = "Nehalem",
 884         .level = 4,
 885         .vendor = CPUID_VENDOR_INTEL,
 886         .family = 6,
 887         .model = 26,
 888         .stepping = 3,
 889         .features[FEAT_1_EDX] =
 890             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 891              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 892              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 893              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 894              CPUID_DE | CPUID_FP87,
 895         .features[FEAT_1_ECX] =
 896             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 897              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 898         .features[FEAT_8000_0001_EDX] =
 899             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 900         .features[FEAT_8000_0001_ECX] =
 901             CPUID_EXT3_LAHF_LM,
 902         .xlevel = 0x8000000A,
 903         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 904     },
 905     {
 906         .name = "Westmere",
 907         .level = 11,
 908         .vendor = CPUID_VENDOR_INTEL,
 909         .family = 6,
 910         .model = 44,
 911         .stepping = 1,
 912         .features[FEAT_1_EDX] =
 913             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 914              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 915              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 916              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 917              CPUID_DE | CPUID_FP87,
 918         .features[FEAT_1_ECX] =
 919             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 920              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 921              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 922         .features[FEAT_8000_0001_EDX] =
 923             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 924         .features[FEAT_8000_0001_ECX] =
 925             CPUID_EXT3_LAHF_LM,
 926         .xlevel = 0x8000000A,
 927         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 928     },
 929     {
 930         .name = "SandyBridge",
 931         .level = 0xd,
 932         .vendor = CPUID_VENDOR_INTEL,
 933         .family = 6,
 934         .model = 42,
 935         .stepping = 1,
 936         .features[FEAT_1_EDX] =
 937             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 938              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 939              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 940              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 941              CPUID_DE | CPUID_FP87,
 942         .features[FEAT_1_ECX] =
 943             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 944              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
 945              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 946              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 947              CPUID_EXT_SSE3,
 948         .features[FEAT_8000_0001_EDX] =
 949             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 950              CPUID_EXT2_SYSCALL,
 951         .features[FEAT_8000_0001_ECX] =
 952             CPUID_EXT3_LAHF_LM,
 953         .xlevel = 0x8000000A,
 954         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
 955     },
 956     {
 957         .name = "Haswell",
 958         .level = 0xd,
 959         .vendor = CPUID_VENDOR_INTEL,
 960         .family = 6,
 961         .model = 60,
 962         .stepping = 1,
 963         .features[FEAT_1_EDX] =
 964             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 965              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 966              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 967              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 968              CPUID_DE | CPUID_FP87,
 969         .features[FEAT_1_ECX] =
 970             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 971              CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
 972              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 973              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
 974              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
 975              CPUID_EXT_PCID,
 976         .features[FEAT_8000_0001_EDX] =
 977             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 978              CPUID_EXT2_SYSCALL,
 979         .features[FEAT_8000_0001_ECX] =
 980             CPUID_EXT3_LAHF_LM,
 981         .features[FEAT_7_0_EBX] =
 982             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
 983             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
 984             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
 985             CPUID_7_0_EBX_RTM,
 986         .xlevel = 0x8000000A,
 987         .model_id = "Intel Core Processor (Haswell)",
 988     },
 989     {
 990         .name = "Opteron_G1",
 991         .level = 5,
 992         .vendor = CPUID_VENDOR_AMD,
 993         .family = 15,
 994         .model = 6,
 995         .stepping = 1,
 996         .features[FEAT_1_EDX] =
 997             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 998              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 999              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1000              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1001              CPUID_DE | CPUID_FP87,
1002         .features[FEAT_1_ECX] =
1003             CPUID_EXT_SSE3,
1004         .features[FEAT_8000_0001_EDX] =
1005             CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1006              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1007              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1008              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1009              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1010              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1011         .xlevel = 0x80000008,
1012         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1013     },
1014     {
1015         .name = "Opteron_G2",
1016         .level = 5,
1017         .vendor = CPUID_VENDOR_AMD,
1018         .family = 15,
1019         .model = 6,
1020         .stepping = 1,
1021         .features[FEAT_1_EDX] =
1022             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1023              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1024              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1025              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1026              CPUID_DE | CPUID_FP87,
1027         .features[FEAT_1_ECX] =
1028             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1029         .features[FEAT_8000_0001_EDX] =
1030             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1031              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1032              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1033              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1034              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1035              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1036              CPUID_EXT2_DE | CPUID_EXT2_FPU,
1037         .features[FEAT_8000_0001_ECX] =
1038             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1039         .xlevel = 0x80000008,
1040         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1041     },
1042     {
1043         .name = "Opteron_G3",
1044         .level = 5,
1045         .vendor = CPUID_VENDOR_AMD,
1046         .family = 15,
1047         .model = 6,
1048         .stepping = 1,
1049         .features[FEAT_1_EDX] =
1050             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1051              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1052              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1053              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1054              CPUID_DE | CPUID_FP87,
1055         .features[FEAT_1_ECX] =
1056             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1057              CPUID_EXT_SSE3,
1058         .features[FEAT_8000_0001_EDX] =
1059             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1060              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1061              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1062              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1063              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1064              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1065              CPUID_EXT2_DE | CPUID_EXT2_FPU,
1066         .features[FEAT_8000_0001_ECX] =
1067             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1068              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1069         .xlevel = 0x80000008,
1070         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1071     },
1072     {
1073         .name = "Opteron_G4",
1074         .level = 0xd,
1075         .vendor = CPUID_VENDOR_AMD,
1076         .family = 21,
1077         .model = 1,
1078         .stepping = 2,
1079         .features[FEAT_1_EDX] =
1080             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1081              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1082              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1083              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1084              CPUID_DE | CPUID_FP87,
1085         .features[FEAT_1_ECX] =
1086             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1087              CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1088              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1089              CPUID_EXT_SSE3,
1090         .features[FEAT_8000_0001_EDX] =
1091             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1092              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1093              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1094              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1095              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1096              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1097              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1098         .features[FEAT_8000_0001_ECX] =
1099             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1100              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1101              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1102              CPUID_EXT3_LAHF_LM,
1103         .xlevel = 0x8000001A,
1104         .model_id = "AMD Opteron 62xx class CPU",
1105     },
1106     {
1107         .name = "Opteron_G5",
1108         .level = 0xd,
1109         .vendor = CPUID_VENDOR_AMD,
1110         .family = 21,
1111         .model = 2,
1112         .stepping = 0,
1113         .features[FEAT_1_EDX] =
1114             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1115              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1116              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1117              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1118              CPUID_DE | CPUID_FP87,
1119         .features[FEAT_1_ECX] =
1120             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1121              CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1122              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1123              CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1124         .features[FEAT_8000_0001_EDX] =
1125             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1126              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1127              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1128              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1129              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1130              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1131              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1132         .features[FEAT_8000_0001_ECX] =
1133             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1134              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1135              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1136              CPUID_EXT3_LAHF_LM,
1137         .xlevel = 0x8000001A,
1138         .model_id = "AMD Opteron 63xx class CPU",
1139     },
1140 };
1141
1142 /**
1143  * x86_cpu_compat_set_features:
1144  * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1145  * @w: Identifies the feature word to be changed.
1146  * @feat_add: Feature bits to be added to feature word
1147  * @feat_remove: Feature bits to be removed from feature word
1148  *
1149  * Change CPU model feature bits for compatibility.
1150  *
1151  * This function may be used by machine-type compatibility functions
1152  * to enable or disable feature bits on specific CPU models.
1153  */
1154 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1155                                  uint32_t feat_add, uint32_t feat_remove)
1156 {
1157     X86CPUDefinition *def;
1158     int i;
1159     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1160         def = &builtin_x86_defs[i];
1161         if (!cpu_model || !strcmp(cpu_model, def->name)) {
1162             def->features[w] |= feat_add;
1163             def->features[w] &= ~feat_remove;
1164         }
1165     }
1166 }
1167
1168 #ifdef CONFIG_KVM
1169
1170 static int cpu_x86_fill_model_id(char *str)
1171 {
1172     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1173     int i;
1174
1175     for (i = 0; i < 3; i++) {
1176         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1177         memcpy(str + i * 16 +  0, &eax, 4);
1178         memcpy(str + i * 16 +  4, &ebx, 4);
1179         memcpy(str + i * 16 +  8, &ecx, 4);
1180         memcpy(str + i * 16 + 12, &edx, 4);
1181     }
1182     return 0;
1183 }
1184
1185 static X86CPUDefinition host_cpudef;
1186
1187 /* class_init for the "host" CPU model
1188  *
1189  * This function may be called before KVM is initialized.
1190  */
1191 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1192 {
1193     X86CPUClass *xcc = X86_CPU_CLASS(oc);
1194     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1195
1196     xcc->kvm_required = true;
1197
1198     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1199     x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1200
1201     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1202     host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1203     host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1204     host_cpudef.stepping = eax & 0x0F;
1205
1206     cpu_x86_fill_model_id(host_cpudef.model_id);
1207
1208     xcc->cpu_def = &host_cpudef;
1209     host_cpudef.cache_info_passthrough = true;
1210
1211     /* level, xlevel, xlevel2, and the feature words are initialized on
1212      * instance_init, because they require KVM to be initialized.
1213      */
1214 }
1215
1216 static void host_x86_cpu_initfn(Object *obj)
1217 {
1218     X86CPU *cpu = X86_CPU(obj);
1219     CPUX86State *env = &cpu->env;
1220     KVMState *s = kvm_state;
1221     FeatureWord w;
1222
1223     assert(kvm_enabled());
1224
1225     env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1226     env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1227     env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1228
1229     for (w = 0; w < FEATURE_WORDS; w++) {
1230         FeatureWordInfo *wi = &feature_word_info[w];
1231         env->features[w] =
1232             kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1233                                          wi->cpuid_reg);
1234     }
1235     object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1236 }
1237
1238 static const TypeInfo host_x86_cpu_type_info = {
1239     .name = X86_CPU_TYPE_NAME("host"),
1240     .parent = TYPE_X86_CPU,
1241     .instance_init = host_x86_cpu_initfn,
1242     .class_init = host_x86_cpu_class_init,
1243 };
1244
1245 #endif
1246
1247 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1248 {
1249     FeatureWordInfo *f = &feature_word_info[w];
1250     int i;
1251
1252     for (i = 0; i < 32; ++i) {
1253         if (1 << i & mask) {
1254             const char *reg = get_register_name_32(f->cpuid_reg);
1255             assert(reg);
1256             fprintf(stderr, "warning: host doesn't support requested feature: "
1257                 "CPUID.%02XH:%s%s%s [bit %d]\n",
1258                 f->cpuid_eax, reg,
1259                 f->feat_names[i] ? "." : "",
1260                 f->feat_names[i] ? f->feat_names[i] : "", i);
1261         }
1262     }
1263 }
1264
1265 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1266                                          const char *name, Error **errp)
1267 {
1268     X86CPU *cpu = X86_CPU(obj);
1269     CPUX86State *env = &cpu->env;
1270     int64_t value;
1271
1272     value = (env->cpuid_version >> 8) & 0xf;
1273     if (value == 0xf) {
1274         value += (env->cpuid_version >> 20) & 0xff;
1275     }
1276     visit_type_int(v, &value, name, errp);
1277 }
1278
1279 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1280                                          const char *name, Error **errp)
1281 {
1282     X86CPU *cpu = X86_CPU(obj);
1283     CPUX86State *env = &cpu->env;
1284     const int64_t min = 0;
1285     const int64_t max = 0xff + 0xf;
1286     Error *local_err = NULL;
1287     int64_t value;
1288
1289     visit_type_int(v, &value, name, &local_err);
1290     if (local_err) {
1291         error_propagate(errp, local_err);
1292         return;
1293     }
1294     if (value < min || value > max) {
1295         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1296                   name ? name : "null", value, min, max);
1297         return;
1298     }
1299
1300     env->cpuid_version &= ~0xff00f00;
1301     if (value > 0x0f) {
1302         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1303     } else {
1304         env->cpuid_version |= value << 8;
1305     }
1306 }
1307
1308 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1309                                         const char *name, Error **errp)
1310 {
1311     X86CPU *cpu = X86_CPU(obj);
1312     CPUX86State *env = &cpu->env;
1313     int64_t value;
1314
1315     value = (env->cpuid_version >> 4) & 0xf;
1316     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1317     visit_type_int(v, &value, name, errp);
1318 }
1319
1320 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1321                                         const char *name, Error **errp)
1322 {
1323     X86CPU *cpu = X86_CPU(obj);
1324     CPUX86State *env = &cpu->env;
1325     const int64_t min = 0;
1326     const int64_t max = 0xff;
1327     Error *local_err = NULL;
1328     int64_t value;
1329
1330     visit_type_int(v, &value, name, &local_err);
1331     if (local_err) {
1332         error_propagate(errp, local_err);
1333         return;
1334     }
1335     if (value < min || value > max) {
1336         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1337                   name ? name : "null", value, min, max);
1338         return;
1339     }
1340
1341     env->cpuid_version &= ~0xf00f0;
1342     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1343 }
1344
1345 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1346                                            void *opaque, const char *name,
1347                                            Error **errp)
1348 {
1349     X86CPU *cpu = X86_CPU(obj);
1350     CPUX86State *env = &cpu->env;
1351     int64_t value;
1352
1353     value = env->cpuid_version & 0xf;
1354     visit_type_int(v, &value, name, errp);
1355 }
1356
1357 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1358                                            void *opaque, const char *name,
1359                                            Error **errp)
1360 {
1361     X86CPU *cpu = X86_CPU(obj);
1362     CPUX86State *env = &cpu->env;
1363     const int64_t min = 0;
1364     const int64_t max = 0xf;
1365     Error *local_err = NULL;
1366     int64_t value;
1367
1368     visit_type_int(v, &value, name, &local_err);
1369     if (local_err) {
1370         error_propagate(errp, local_err);
1371         return;
1372     }
1373     if (value < min || value > max) {
1374         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1375                   name ? name : "null", value, min, max);
1376         return;
1377     }
1378
1379     env->cpuid_version &= ~0xf;
1380     env->cpuid_version |= value & 0xf;
1381 }
1382
1383 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1384                                 const char *name, Error **errp)
1385 {
1386     X86CPU *cpu = X86_CPU(obj);
1387
1388     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1389 }
1390
1391 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1392                                 const char *name, Error **errp)
1393 {
1394     X86CPU *cpu = X86_CPU(obj);
1395
1396     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1397 }
1398
1399 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1400                                  const char *name, Error **errp)
1401 {
1402     X86CPU *cpu = X86_CPU(obj);
1403
1404     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1405 }
1406
1407 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1408                                  const char *name, Error **errp)
1409 {
1410     X86CPU *cpu = X86_CPU(obj);
1411
1412     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1413 }
1414
1415 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1416 {
1417     X86CPU *cpu = X86_CPU(obj);
1418     CPUX86State *env = &cpu->env;
1419     char *value;
1420
1421     value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1422     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1423                              env->cpuid_vendor3);
1424     return value;
1425 }
1426
1427 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1428                                  Error **errp)
1429 {
1430     X86CPU *cpu = X86_CPU(obj);
1431     CPUX86State *env = &cpu->env;
1432     int i;
1433
1434     if (strlen(value) != CPUID_VENDOR_SZ) {
1435         error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1436                   "vendor", value);
1437         return;
1438     }
1439
1440     env->cpuid_vendor1 = 0;
1441     env->cpuid_vendor2 = 0;
1442     env->cpuid_vendor3 = 0;
1443     for (i = 0; i < 4; i++) {
1444         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1445         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1446         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1447     }
1448 }
1449
1450 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1451 {
1452     X86CPU *cpu = X86_CPU(obj);
1453     CPUX86State *env = &cpu->env;
1454     char *value;
1455     int i;
1456
1457     value = g_malloc(48 + 1);
1458     for (i = 0; i < 48; i++) {
1459         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1460     }
1461     value[48] = '\0';
1462     return value;
1463 }
1464
1465 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1466                                    Error **errp)
1467 {
1468     X86CPU *cpu = X86_CPU(obj);
1469     CPUX86State *env = &cpu->env;
1470     int c, len, i;
1471
1472     if (model_id == NULL) {
1473         model_id = "";
1474     }
1475     len = strlen(model_id);
1476     memset(env->cpuid_model, 0, 48);
1477     for (i = 0; i < 48; i++) {
1478         if (i >= len) {
1479             c = '\0';
1480         } else {
1481             c = (uint8_t)model_id[i];
1482         }
1483         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1484     }
1485 }
1486
1487 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1488                                    const char *name, Error **errp)
1489 {
1490     X86CPU *cpu = X86_CPU(obj);
1491     int64_t value;
1492
1493     value = cpu->env.tsc_khz * 1000;
1494     visit_type_int(v, &value, name, errp);
1495 }
1496
1497 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1498                                    const char *name, Error **errp)
1499 {
1500     X86CPU *cpu = X86_CPU(obj);
1501     const int64_t min = 0;
1502     const int64_t max = INT64_MAX;
1503     Error *local_err = NULL;
1504     int64_t value;
1505
1506     visit_type_int(v, &value, name, &local_err);
1507     if (local_err) {
1508         error_propagate(errp, local_err);
1509         return;
1510     }
1511     if (value < min || value > max) {
1512         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1513                   name ? name : "null", value, min, max);
1514         return;
1515     }
1516
1517     cpu->env.tsc_khz = value / 1000;
1518 }
1519
1520 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1521                                   const char *name, Error **errp)
1522 {
1523     X86CPU *cpu = X86_CPU(obj);
1524     int64_t value = cpu->env.cpuid_apic_id;
1525
1526     visit_type_int(v, &value, name, errp);
1527 }
1528
1529 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1530                                   const char *name, Error **errp)
1531 {
1532     X86CPU *cpu = X86_CPU(obj);
1533     DeviceState *dev = DEVICE(obj);
1534     const int64_t min = 0;
1535     const int64_t max = UINT32_MAX;
1536     Error *error = NULL;
1537     int64_t value;
1538
1539     if (dev->realized) {
1540         error_setg(errp, "Attempt to set property '%s' on '%s' after "
1541                    "it was realized", name, object_get_typename(obj));
1542         return;
1543     }
1544
1545     visit_type_int(v, &value, name, &error);
1546     if (error) {
1547         error_propagate(errp, error);
1548         return;
1549     }
1550     if (value < min || value > max) {
1551         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1552                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1553                    object_get_typename(obj), name, value, min, max);
1554         return;
1555     }
1556
1557     if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1558         error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1559         return;
1560     }
1561     cpu->env.cpuid_apic_id = value;
1562 }
1563
1564 /* Generic getter for "feature-words" and "filtered-features" properties */
1565 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1566                                       const char *name, Error **errp)
1567 {
1568     uint32_t *array = (uint32_t *)opaque;
1569     FeatureWord w;
1570     Error *err = NULL;
1571     X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1572     X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1573     X86CPUFeatureWordInfoList *list = NULL;
1574
1575     for (w = 0; w < FEATURE_WORDS; w++) {
1576         FeatureWordInfo *wi = &feature_word_info[w];
1577         X86CPUFeatureWordInfo *qwi = &word_infos[w];
1578         qwi->cpuid_input_eax = wi->cpuid_eax;
1579         qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1580         qwi->cpuid_input_ecx = wi->cpuid_ecx;
1581         qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1582         qwi->features = array[w];
1583
1584         /* List will be in reverse order, but order shouldn't matter */
1585         list_entries[w].next = list;
1586         list_entries[w].value = &word_infos[w];
1587         list = &list_entries[w];
1588     }
1589
1590     visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1591     error_propagate(errp, err);
1592 }
1593
1594 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1595                                  const char *name, Error **errp)
1596 {
1597     X86CPU *cpu = X86_CPU(obj);
1598     int64_t value = cpu->hyperv_spinlock_attempts;
1599
1600     visit_type_int(v, &value, name, errp);
1601 }
1602
1603 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1604                                  const char *name, Error **errp)
1605 {
1606     const int64_t min = 0xFFF;
1607     const int64_t max = UINT_MAX;
1608     X86CPU *cpu = X86_CPU(obj);
1609     Error *err = NULL;
1610     int64_t value;
1611
1612     visit_type_int(v, &value, name, &err);
1613     if (err) {
1614         error_propagate(errp, err);
1615         return;
1616     }
1617
1618     if (value < min || value > max) {
1619         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1620                   " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1621                   object_get_typename(obj), name ? name : "null",
1622                   value, min, max);
1623         return;
1624     }
1625     cpu->hyperv_spinlock_attempts = value;
1626 }
1627
1628 static PropertyInfo qdev_prop_spinlocks = {
1629     .name  = "int",
1630     .get   = x86_get_hv_spinlocks,
1631     .set   = x86_set_hv_spinlocks,
1632 };
1633
1634 /* Convert all '_' in a feature string option name to '-', to make feature
1635  * name conform to QOM property naming rule, which uses '-' instead of '_'.
1636  */
1637 static inline void feat2prop(char *s)
1638 {
1639     while ((s = strchr(s, '_'))) {
1640         *s = '-';
1641     }
1642 }
1643
1644 /* Parse "+feature,-feature,feature=foo" CPU feature string
1645  */
1646 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1647                                      Error **errp)
1648 {
1649     X86CPU *cpu = X86_CPU(cs);
1650     char *featurestr; /* Single 'key=value" string being parsed */
1651     /* Features to be added */
1652     FeatureWordArray plus_features = { 0 };
1653     /* Features to be removed */
1654     FeatureWordArray minus_features = { 0 };
1655     uint32_t numvalue;
1656     CPUX86State *env = &cpu->env;
1657     Error *local_err = NULL;
1658
1659     featurestr = features ? strtok(features, ",") : NULL;
1660
1661     while (featurestr) {
1662         char *val;
1663         if (featurestr[0] == '+') {
1664             add_flagname_to_bitmaps(featurestr + 1, plus_features);
1665         } else if (featurestr[0] == '-') {
1666             add_flagname_to_bitmaps(featurestr + 1, minus_features);
1667         } else if ((val = strchr(featurestr, '='))) {
1668             *val = 0; val++;
1669             feat2prop(featurestr);
1670             if (!strcmp(featurestr, "xlevel")) {
1671                 char *err;
1672                 char num[32];
1673
1674                 numvalue = strtoul(val, &err, 0);
1675                 if (!*val || *err) {
1676                     error_setg(errp, "bad numerical value %s", val);
1677                     return;
1678                 }
1679                 if (numvalue < 0x80000000) {
1680                     error_report("xlevel value shall always be >= 0x80000000"
1681                                  ", fixup will be removed in future versions");
1682                     numvalue += 0x80000000;
1683                 }
1684                 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1685                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1686             } else if (!strcmp(featurestr, "tsc-freq")) {
1687                 int64_t tsc_freq;
1688                 char *err;
1689                 char num[32];
1690
1691                 tsc_freq = strtosz_suffix_unit(val, &err,
1692                                                STRTOSZ_DEFSUFFIX_B, 1000);
1693                 if (tsc_freq < 0 || *err) {
1694                     error_setg(errp, "bad numerical value %s", val);
1695                     return;
1696                 }
1697                 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1698                 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1699                                       &local_err);
1700             } else if (!strcmp(featurestr, "hv-spinlocks")) {
1701                 char *err;
1702                 const int min = 0xFFF;
1703                 char num[32];
1704                 numvalue = strtoul(val, &err, 0);
1705                 if (!*val || *err) {
1706                     error_setg(errp, "bad numerical value %s", val);
1707                     return;
1708                 }
1709                 if (numvalue < min) {
1710                     error_report("hv-spinlocks value shall always be >= 0x%x"
1711                             ", fixup will be removed in future versions",
1712                             min);
1713                     numvalue = min;
1714                 }
1715                 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1716                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1717             } else {
1718                 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1719             }
1720         } else {
1721             feat2prop(featurestr);
1722             object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1723         }
1724         if (local_err) {
1725             error_propagate(errp, local_err);
1726             return;
1727         }
1728         featurestr = strtok(NULL, ",");
1729     }
1730     env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1731     env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1732     env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1733     env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1734     env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1735     env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1736     env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1737     env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1738     env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1739     env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1740     env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1741     env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1742     env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1743     env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1744     env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1745     env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1746 }
1747
1748 /* generate a composite string into buf of all cpuid names in featureset
1749  * selected by fbits.  indicate truncation at bufsize in the event of overflow.
1750  * if flags, suppress names undefined in featureset.
1751  */
1752 static void listflags(char *buf, int bufsize, uint32_t fbits,
1753     const char **featureset, uint32_t flags)
1754 {
1755     const char **p = &featureset[31];
1756     char *q, *b, bit;
1757     int nc;
1758
1759     b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1760     *buf = '\0';
1761     for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1762         if (fbits & 1 << bit && (*p || !flags)) {
1763             if (*p)
1764                 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1765             else
1766                 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1767             if (bufsize <= nc) {
1768                 if (b) {
1769                     memcpy(b, "...", sizeof("..."));
1770                 }
1771                 return;
1772             }
1773             q += nc;
1774             bufsize -= nc;
1775         }
1776 }
1777
1778 /* generate CPU information. */
1779 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1780 {
1781     X86CPUDefinition *def;
1782     char buf[256];
1783     int i;
1784
1785     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1786         def = &builtin_x86_defs[i];
1787         snprintf(buf, sizeof(buf), "%s", def->name);
1788         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1789     }
1790 #ifdef CONFIG_KVM
1791     (*cpu_fprintf)(f, "x86 %16s  %-48s\n", "host",
1792                    "KVM processor with all supported host features "
1793                    "(only available in KVM mode)");
1794 #endif
1795
1796     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1797     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1798         FeatureWordInfo *fw = &feature_word_info[i];
1799
1800         listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1801         (*cpu_fprintf)(f, "  %s\n", buf);
1802     }
1803 }
1804
1805 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1806 {
1807     CpuDefinitionInfoList *cpu_list = NULL;
1808     X86CPUDefinition *def;
1809     int i;
1810
1811     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1812         CpuDefinitionInfoList *entry;
1813         CpuDefinitionInfo *info;
1814
1815         def = &builtin_x86_defs[i];
1816         info = g_malloc0(sizeof(*info));
1817         info->name = g_strdup(def->name);
1818
1819         entry = g_malloc0(sizeof(*entry));
1820         entry->value = info;
1821         entry->next = cpu_list;
1822         cpu_list = entry;
1823     }
1824
1825     return cpu_list;
1826 }
1827
1828 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w)
1829 {
1830     FeatureWordInfo *wi = &feature_word_info[w];
1831
1832     assert(kvm_enabled());
1833     return kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
1834                                                    wi->cpuid_ecx,
1835                                                    wi->cpuid_reg);
1836 }
1837
1838 /*
1839  * Filters CPU feature words based on host availability of each feature.
1840  *
1841  * This function may be called only if KVM is enabled.
1842  *
1843  * Returns: 0 if all flags are supported by the host, non-zero otherwise.
1844  */
1845 static int x86_cpu_filter_features(X86CPU *cpu)
1846 {
1847     CPUX86State *env = &cpu->env;
1848     FeatureWord w;
1849     int rv = 0;
1850
1851     for (w = 0; w < FEATURE_WORDS; w++) {
1852         uint32_t host_feat = x86_cpu_get_supported_feature_word(w);
1853         uint32_t requested_features = env->features[w];
1854         env->features[w] &= host_feat;
1855         cpu->filtered_features[w] = requested_features & ~env->features[w];
1856         if (cpu->filtered_features[w]) {
1857             if (cpu->check_cpuid || cpu->enforce_cpuid) {
1858                 report_unavailable_features(w, cpu->filtered_features[w]);
1859             }
1860             rv = 1;
1861         }
1862     }
1863
1864     return rv;
1865 }
1866
1867 /* Load data from X86CPUDefinition
1868  */
1869 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1870 {
1871     CPUX86State *env = &cpu->env;
1872     const char *vendor;
1873     char host_vendor[CPUID_VENDOR_SZ + 1];
1874
1875     object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1876     object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1877     object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1878     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1879     env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1880     env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1881     env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1882     env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1883     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1884     env->features[FEAT_KVM] = def->features[FEAT_KVM];
1885     env->features[FEAT_SVM] = def->features[FEAT_SVM];
1886     env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1887     env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1888     env->cpuid_xlevel2 = def->xlevel2;
1889     cpu->cache_info_passthrough = def->cache_info_passthrough;
1890
1891     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1892
1893     /* Special cases not set in the X86CPUDefinition structs: */
1894     if (kvm_enabled()) {
1895         FeatureWord w;
1896         for (w = 0; w < FEATURE_WORDS; w++) {
1897             env->features[w] |= kvm_default_features[w];
1898             env->features[w] &= ~kvm_default_unset_features[w];
1899         }
1900     }
1901
1902     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1903
1904     /* sysenter isn't supported in compatibility mode on AMD,
1905      * syscall isn't supported in compatibility mode on Intel.
1906      * Normally we advertise the actual CPU vendor, but you can
1907      * override this using the 'vendor' property if you want to use
1908      * KVM's sysenter/syscall emulation in compatibility mode and
1909      * when doing cross vendor migration
1910      */
1911     vendor = def->vendor;
1912     if (kvm_enabled()) {
1913         uint32_t  ebx = 0, ecx = 0, edx = 0;
1914         host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1915         x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1916         vendor = host_vendor;
1917     }
1918
1919     object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1920
1921 }
1922
1923 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1924                        Error **errp)
1925 {
1926     X86CPU *cpu = NULL;
1927     X86CPUClass *xcc;
1928     ObjectClass *oc;
1929     gchar **model_pieces;
1930     char *name, *features;
1931     Error *error = NULL;
1932
1933     model_pieces = g_strsplit(cpu_model, ",", 2);
1934     if (!model_pieces[0]) {
1935         error_setg(&error, "Invalid/empty CPU model name");
1936         goto out;
1937     }
1938     name = model_pieces[0];
1939     features = model_pieces[1];
1940
1941     oc = x86_cpu_class_by_name(name);
1942     if (oc == NULL) {
1943         error_setg(&error, "Unable to find CPU definition: %s", name);
1944         goto out;
1945     }
1946     xcc = X86_CPU_CLASS(oc);
1947
1948     if (xcc->kvm_required && !kvm_enabled()) {
1949         error_setg(&error, "CPU model '%s' requires KVM", name);
1950         goto out;
1951     }
1952
1953     cpu = X86_CPU(object_new(object_class_get_name(oc)));
1954
1955 #ifndef CONFIG_USER_ONLY
1956     if (icc_bridge == NULL) {
1957         error_setg(&error, "Invalid icc-bridge value");
1958         goto out;
1959     }
1960     qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1961     object_unref(OBJECT(cpu));
1962 #endif
1963
1964     x86_cpu_parse_featurestr(CPU(cpu), features, &error);
1965     if (error) {
1966         goto out;
1967     }
1968
1969 out:
1970     if (error != NULL) {
1971         error_propagate(errp, error);
1972         if (cpu) {
1973             object_unref(OBJECT(cpu));
1974             cpu = NULL;
1975         }
1976     }
1977     g_strfreev(model_pieces);
1978     return cpu;
1979 }
1980
1981 X86CPU *cpu_x86_init(const char *cpu_model)
1982 {
1983     Error *error = NULL;
1984     X86CPU *cpu;
1985
1986     cpu = cpu_x86_create(cpu_model, NULL, &error);
1987     if (error) {
1988         goto out;
1989     }
1990
1991     object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1992
1993 out:
1994     if (error) {
1995         error_report("%s", error_get_pretty(error));
1996         error_free(error);
1997         if (cpu != NULL) {
1998             object_unref(OBJECT(cpu));
1999             cpu = NULL;
2000         }
2001     }
2002     return cpu;
2003 }
2004
2005 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2006 {
2007     X86CPUDefinition *cpudef = data;
2008     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2009
2010     xcc->cpu_def = cpudef;
2011 }
2012
2013 static void x86_register_cpudef_type(X86CPUDefinition *def)
2014 {
2015     char *typename = x86_cpu_type_name(def->name);
2016     TypeInfo ti = {
2017         .name = typename,
2018         .parent = TYPE_X86_CPU,
2019         .class_init = x86_cpu_cpudef_class_init,
2020         .class_data = def,
2021     };
2022
2023     type_register(&ti);
2024     g_free(typename);
2025 }
2026
2027 #if !defined(CONFIG_USER_ONLY)
2028
2029 void cpu_clear_apic_feature(CPUX86State *env)
2030 {
2031     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2032 }
2033
2034 #endif /* !CONFIG_USER_ONLY */
2035
2036 /* Initialize list of CPU models, filling some non-static fields if necessary
2037  */
2038 void x86_cpudef_setup(void)
2039 {
2040     int i, j;
2041     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2042
2043     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2044         X86CPUDefinition *def = &builtin_x86_defs[i];
2045
2046         /* Look for specific "cpudef" models that */
2047         /* have the QEMU version in .model_id */
2048         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2049             if (strcmp(model_with_versions[j], def->name) == 0) {
2050                 pstrcpy(def->model_id, sizeof(def->model_id),
2051                         "QEMU Virtual CPU version ");
2052                 pstrcat(def->model_id, sizeof(def->model_id),
2053                         qemu_get_version());
2054                 break;
2055             }
2056         }
2057     }
2058 }
2059
2060 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2061                              uint32_t *ecx, uint32_t *edx)
2062 {
2063     *ebx = env->cpuid_vendor1;
2064     *edx = env->cpuid_vendor2;
2065     *ecx = env->cpuid_vendor3;
2066 }
2067
2068 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2069                    uint32_t *eax, uint32_t *ebx,
2070                    uint32_t *ecx, uint32_t *edx)
2071 {
2072     X86CPU *cpu = x86_env_get_cpu(env);
2073     CPUState *cs = CPU(cpu);
2074
2075     /* test if maximum index reached */
2076     if (index & 0x80000000) {
2077         if (index > env->cpuid_xlevel) {
2078             if (env->cpuid_xlevel2 > 0) {
2079                 /* Handle the Centaur's CPUID instruction. */
2080                 if (index > env->cpuid_xlevel2) {
2081                     index = env->cpuid_xlevel2;
2082                 } else if (index < 0xC0000000) {
2083                     index = env->cpuid_xlevel;
2084                 }
2085             } else {
2086                 /* Intel documentation states that invalid EAX input will
2087                  * return the same information as EAX=cpuid_level
2088                  * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2089                  */
2090                 index =  env->cpuid_level;
2091             }
2092         }
2093     } else {
2094         if (index > env->cpuid_level)
2095             index = env->cpuid_level;
2096     }
2097
2098     switch(index) {
2099     case 0:
2100         *eax = env->cpuid_level;
2101         get_cpuid_vendor(env, ebx, ecx, edx);
2102         break;
2103     case 1:
2104         *eax = env->cpuid_version;
2105         *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2106         *ecx = env->features[FEAT_1_ECX];
2107         *edx = env->features[FEAT_1_EDX];
2108         if (cs->nr_cores * cs->nr_threads > 1) {
2109             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2110             *edx |= 1 << 28;    /* HTT bit */
2111         }
2112         break;
2113     case 2:
2114         /* cache info: needed for Pentium Pro compatibility */
2115         if (cpu->cache_info_passthrough) {
2116             host_cpuid(index, 0, eax, ebx, ecx, edx);
2117             break;
2118         }
2119         *eax = 1; /* Number of CPUID[EAX=2] calls required */
2120         *ebx = 0;
2121         *ecx = 0;
2122         *edx = (L1D_DESCRIPTOR << 16) | \
2123                (L1I_DESCRIPTOR <<  8) | \
2124                (L2_DESCRIPTOR);
2125         break;
2126     case 4:
2127         /* cache info: needed for Core compatibility */
2128         if (cpu->cache_info_passthrough) {
2129             host_cpuid(index, count, eax, ebx, ecx, edx);
2130             *eax &= ~0xFC000000;
2131         } else {
2132             *eax = 0;
2133             switch (count) {
2134             case 0: /* L1 dcache info */
2135                 *eax |= CPUID_4_TYPE_DCACHE | \
2136                         CPUID_4_LEVEL(1) | \
2137                         CPUID_4_SELF_INIT_LEVEL;
2138                 *ebx = (L1D_LINE_SIZE - 1) | \
2139                        ((L1D_PARTITIONS - 1) << 12) | \
2140                        ((L1D_ASSOCIATIVITY - 1) << 22);
2141                 *ecx = L1D_SETS - 1;
2142                 *edx = CPUID_4_NO_INVD_SHARING;
2143                 break;
2144             case 1: /* L1 icache info */
2145                 *eax |= CPUID_4_TYPE_ICACHE | \
2146                         CPUID_4_LEVEL(1) | \
2147                         CPUID_4_SELF_INIT_LEVEL;
2148                 *ebx = (L1I_LINE_SIZE - 1) | \
2149                        ((L1I_PARTITIONS - 1) << 12) | \
2150                        ((L1I_ASSOCIATIVITY - 1) << 22);
2151                 *ecx = L1I_SETS - 1;
2152                 *edx = CPUID_4_NO_INVD_SHARING;
2153                 break;
2154             case 2: /* L2 cache info */
2155                 *eax |= CPUID_4_TYPE_UNIFIED | \
2156                         CPUID_4_LEVEL(2) | \
2157                         CPUID_4_SELF_INIT_LEVEL;
2158                 if (cs->nr_threads > 1) {
2159                     *eax |= (cs->nr_threads - 1) << 14;
2160                 }
2161                 *ebx = (L2_LINE_SIZE - 1) | \
2162                        ((L2_PARTITIONS - 1) << 12) | \
2163                        ((L2_ASSOCIATIVITY - 1) << 22);
2164                 *ecx = L2_SETS - 1;
2165                 *edx = CPUID_4_NO_INVD_SHARING;
2166                 break;
2167             default: /* end of info */
2168                 *eax = 0;
2169                 *ebx = 0;
2170                 *ecx = 0;
2171                 *edx = 0;
2172                 break;
2173             }
2174         }
2175
2176         /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  */
2177         if ((*eax & 31) && cs->nr_cores > 1) {
2178             *eax |= (cs->nr_cores - 1) << 26;
2179         }
2180         break;
2181     case 5:
2182         /* mwait info: needed for Core compatibility */
2183         *eax = 0; /* Smallest monitor-line size in bytes */
2184         *ebx = 0; /* Largest monitor-line size in bytes */
2185         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2186         *edx = 0;
2187         break;
2188     case 6:
2189         /* Thermal and Power Leaf */
2190         *eax = 0;
2191         *ebx = 0;
2192         *ecx = 0;
2193         *edx = 0;
2194         break;
2195     case 7:
2196         /* Structured Extended Feature Flags Enumeration Leaf */
2197         if (count == 0) {
2198             *eax = 0; /* Maximum ECX value for sub-leaves */
2199             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2200             *ecx = 0; /* Reserved */
2201             *edx = 0; /* Reserved */
2202         } else {
2203             *eax = 0;
2204             *ebx = 0;
2205             *ecx = 0;
2206             *edx = 0;
2207         }
2208         break;
2209     case 9:
2210         /* Direct Cache Access Information Leaf */
2211         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2212         *ebx = 0;
2213         *ecx = 0;
2214         *edx = 0;
2215         break;
2216     case 0xA:
2217         /* Architectural Performance Monitoring Leaf */
2218         if (kvm_enabled() && cpu->enable_pmu) {
2219             KVMState *s = cs->kvm_state;
2220
2221             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2222             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2223             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2224             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2225         } else {
2226             *eax = 0;
2227             *ebx = 0;
2228             *ecx = 0;
2229             *edx = 0;
2230         }
2231         break;
2232     case 0xD: {
2233         KVMState *s = cs->kvm_state;
2234         uint64_t kvm_mask;
2235         int i;
2236
2237         /* Processor Extended State */
2238         *eax = 0;
2239         *ebx = 0;
2240         *ecx = 0;
2241         *edx = 0;
2242         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2243             break;
2244         }
2245         kvm_mask =
2246             kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2247             ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2248
2249         if (count == 0) {
2250             *ecx = 0x240;
2251             for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2252                 const ExtSaveArea *esa = &ext_save_areas[i];
2253                 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2254                     (kvm_mask & (1 << i)) != 0) {
2255                     if (i < 32) {
2256                         *eax |= 1 << i;
2257                     } else {
2258                         *edx |= 1 << (i - 32);
2259                     }
2260                     *ecx = MAX(*ecx, esa->offset + esa->size);
2261                 }
2262             }
2263             *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2264             *ebx = *ecx;
2265         } else if (count == 1) {
2266             *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2267         } else if (count < ARRAY_SIZE(ext_save_areas)) {
2268             const ExtSaveArea *esa = &ext_save_areas[count];
2269             if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2270                 (kvm_mask & (1 << count)) != 0) {
2271                 *eax = esa->size;
2272                 *ebx = esa->offset;
2273             }
2274         }
2275         break;
2276     }
2277     case 0x80000000:
2278         *eax = env->cpuid_xlevel;
2279         *ebx = env->cpuid_vendor1;
2280         *edx = env->cpuid_vendor2;
2281         *ecx = env->cpuid_vendor3;
2282         break;
2283     case 0x80000001:
2284         *eax = env->cpuid_version;
2285         *ebx = 0;
2286         *ecx = env->features[FEAT_8000_0001_ECX];
2287         *edx = env->features[FEAT_8000_0001_EDX];
2288
2289         /* The Linux kernel checks for the CMPLegacy bit and
2290          * discards multiple thread information if it is set.
2291          * So dont set it here for Intel to make Linux guests happy.
2292          */
2293         if (cs->nr_cores * cs->nr_threads > 1) {
2294             uint32_t tebx, tecx, tedx;
2295             get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2296             if (tebx != CPUID_VENDOR_INTEL_1 ||
2297                 tedx != CPUID_VENDOR_INTEL_2 ||
2298                 tecx != CPUID_VENDOR_INTEL_3) {
2299                 *ecx |= 1 << 1;    /* CmpLegacy bit */
2300             }
2301         }
2302         break;
2303     case 0x80000002:
2304     case 0x80000003:
2305     case 0x80000004:
2306         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2307         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2308         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2309         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2310         break;
2311     case 0x80000005:
2312         /* cache info (L1 cache) */
2313         if (cpu->cache_info_passthrough) {
2314             host_cpuid(index, 0, eax, ebx, ecx, edx);
2315             break;
2316         }
2317         *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2318                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
2319         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2320                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
2321         *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2322                (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2323         *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2324                (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2325         break;
2326     case 0x80000006:
2327         /* cache info (L2 cache) */
2328         if (cpu->cache_info_passthrough) {
2329             host_cpuid(index, 0, eax, ebx, ecx, edx);
2330             break;
2331         }
2332         *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2333                (L2_DTLB_2M_ENTRIES << 16) | \
2334                (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2335                (L2_ITLB_2M_ENTRIES);
2336         *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2337                (L2_DTLB_4K_ENTRIES << 16) | \
2338                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2339                (L2_ITLB_4K_ENTRIES);
2340         *ecx = (L2_SIZE_KB_AMD << 16) | \
2341                (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2342                (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2343         *edx = ((L3_SIZE_KB/512) << 18) | \
2344                (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2345                (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2346         break;
2347     case 0x80000008:
2348         /* virtual & phys address size in low 2 bytes. */
2349 /* XXX: This value must match the one used in the MMU code. */
2350         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2351             /* 64 bit processor */
2352 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2353             *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2354         } else {
2355             if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2356                 *eax = 0x00000024; /* 36 bits physical */
2357             } else {
2358                 *eax = 0x00000020; /* 32 bits physical */
2359             }
2360         }
2361         *ebx = 0;
2362         *ecx = 0;
2363         *edx = 0;
2364         if (cs->nr_cores * cs->nr_threads > 1) {
2365             *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2366         }
2367         break;
2368     case 0x8000000A:
2369         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2370             *eax = 0x00000001; /* SVM Revision */
2371             *ebx = 0x00000010; /* nr of ASIDs */
2372             *ecx = 0;
2373             *edx = env->features[FEAT_SVM]; /* optional features */
2374         } else {
2375             *eax = 0;
2376             *ebx = 0;
2377             *ecx = 0;
2378             *edx = 0;
2379         }
2380         break;
2381     case 0xC0000000:
2382         *eax = env->cpuid_xlevel2;
2383         *ebx = 0;
2384         *ecx = 0;
2385         *edx = 0;
2386         break;
2387     case 0xC0000001:
2388         /* Support for VIA CPU's CPUID instruction */
2389         *eax = env->cpuid_version;
2390         *ebx = 0;
2391         *ecx = 0;
2392         *edx = env->features[FEAT_C000_0001_EDX];
2393         break;
2394     case 0xC0000002:
2395     case 0xC0000003:
2396     case 0xC0000004:
2397         /* Reserved for the future, and now filled with zero */
2398         *eax = 0;
2399         *ebx = 0;
2400         *ecx = 0;
2401         *edx = 0;
2402         break;
2403     default:
2404         /* reserved values: zero */
2405         *eax = 0;
2406         *ebx = 0;
2407         *ecx = 0;
2408         *edx = 0;
2409         break;
2410     }
2411 }
2412
2413 /* CPUClass::reset() */
2414 static void x86_cpu_reset(CPUState *s)
2415 {
2416     X86CPU *cpu = X86_CPU(s);
2417     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2418     CPUX86State *env = &cpu->env;
2419     int i;
2420
2421     xcc->parent_reset(s);
2422
2423     memset(env, 0, offsetof(CPUX86State, cpuid_level));
2424
2425     tlb_flush(s, 1);
2426
2427     env->old_exception = -1;
2428
2429     /* init to reset state */
2430
2431 #ifdef CONFIG_SOFTMMU
2432     env->hflags |= HF_SOFTMMU_MASK;
2433 #endif
2434     env->hflags2 |= HF2_GIF_MASK;
2435
2436     cpu_x86_update_cr0(env, 0x60000010);
2437     env->a20_mask = ~0x0;
2438     env->smbase = 0x30000;
2439
2440     env->idt.limit = 0xffff;
2441     env->gdt.limit = 0xffff;
2442     env->ldt.limit = 0xffff;
2443     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2444     env->tr.limit = 0xffff;
2445     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2446
2447     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2448                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2449                            DESC_R_MASK | DESC_A_MASK);
2450     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2451                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2452                            DESC_A_MASK);
2453     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2454                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2455                            DESC_A_MASK);
2456     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2457                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2458                            DESC_A_MASK);
2459     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2460                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2461                            DESC_A_MASK);
2462     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2463                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2464                            DESC_A_MASK);
2465
2466     env->eip = 0xfff0;
2467     env->regs[R_EDX] = env->cpuid_version;
2468
2469     env->eflags = 0x2;
2470
2471     /* FPU init */
2472     for (i = 0; i < 8; i++) {
2473         env->fptags[i] = 1;
2474     }
2475     env->fpuc = 0x37f;
2476
2477     env->mxcsr = 0x1f80;
2478     env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2479
2480     env->pat = 0x0007040600070406ULL;
2481     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2482
2483     memset(env->dr, 0, sizeof(env->dr));
2484     env->dr[6] = DR6_FIXED_1;
2485     env->dr[7] = DR7_FIXED_1;
2486     cpu_breakpoint_remove_all(s, BP_CPU);
2487     cpu_watchpoint_remove_all(s, BP_CPU);
2488
2489     env->xcr0 = 1;
2490
2491 #if !defined(CONFIG_USER_ONLY)
2492     /* We hard-wire the BSP to the first CPU. */
2493     if (s->cpu_index == 0) {
2494         apic_designate_bsp(cpu->apic_state);
2495     }
2496
2497     s->halted = !cpu_is_bsp(cpu);
2498
2499     if (kvm_enabled()) {
2500         kvm_arch_reset_vcpu(cpu);
2501     }
2502 #endif
2503 }
2504
2505 #ifndef CONFIG_USER_ONLY
2506 bool cpu_is_bsp(X86CPU *cpu)
2507 {
2508     return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2509 }
2510
2511 /* TODO: remove me, when reset over QOM tree is implemented */
2512 static void x86_cpu_machine_reset_cb(void *opaque)
2513 {
2514     X86CPU *cpu = opaque;
2515     cpu_reset(CPU(cpu));
2516 }
2517 #endif
2518
2519 static void mce_init(X86CPU *cpu)
2520 {
2521     CPUX86State *cenv = &cpu->env;
2522     unsigned int bank;
2523
2524     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2525         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2526             (CPUID_MCE | CPUID_MCA)) {
2527         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2528         cenv->mcg_ctl = ~(uint64_t)0;
2529         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2530             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2531         }
2532     }
2533 }
2534
2535 #ifndef CONFIG_USER_ONLY
2536 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2537 {
2538     CPUX86State *env = &cpu->env;
2539     DeviceState *dev = DEVICE(cpu);
2540     APICCommonState *apic;
2541     const char *apic_type = "apic";
2542
2543     if (kvm_irqchip_in_kernel()) {
2544         apic_type = "kvm-apic";
2545     } else if (xen_enabled()) {
2546         apic_type = "xen-apic";
2547     }
2548
2549     cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2550     if (cpu->apic_state == NULL) {
2551         error_setg(errp, "APIC device '%s' could not be created", apic_type);
2552         return;
2553     }
2554
2555     object_property_add_child(OBJECT(cpu), "apic",
2556                               OBJECT(cpu->apic_state), NULL);
2557     qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2558     /* TODO: convert to link<> */
2559     apic = APIC_COMMON(cpu->apic_state);
2560     apic->cpu = cpu;
2561 }
2562
2563 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2564 {
2565     if (cpu->apic_state == NULL) {
2566         return;
2567     }
2568
2569     if (qdev_init(cpu->apic_state)) {
2570         error_setg(errp, "APIC device '%s' could not be initialized",
2571                    object_get_typename(OBJECT(cpu->apic_state)));
2572         return;
2573     }
2574 }
2575 #else
2576 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2577 {
2578 }
2579 #endif
2580
2581 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2582 {
2583     CPUState *cs = CPU(dev);
2584     X86CPU *cpu = X86_CPU(dev);
2585     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2586     CPUX86State *env = &cpu->env;
2587     Error *local_err = NULL;
2588
2589     if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2590         env->cpuid_level = 7;
2591     }
2592
2593     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2594      * CPUID[1].EDX.
2595      */
2596     if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2597         env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2598         env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2599         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2600         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2601            & CPUID_EXT2_AMD_ALIASES);
2602     }
2603
2604     if (!kvm_enabled()) {
2605         env->features[FEAT_1_EDX] &= TCG_FEATURES;
2606         env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2607         env->features[FEAT_7_0_EBX] &= TCG_7_0_EBX_FEATURES;
2608         env->features[FEAT_8000_0001_EDX] &= TCG_EXT2_FEATURES;
2609         env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2610         env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2611         env->features[FEAT_KVM] &= TCG_KVM_FEATURES;
2612         env->features[FEAT_C000_0001_EDX] &= TCG_EXT4_FEATURES;
2613     } else {
2614         if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
2615             error_setg(&local_err,
2616                        "Host's CPU doesn't support requested features");
2617             goto out;
2618         }
2619     }
2620
2621 #ifndef CONFIG_USER_ONLY
2622     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2623
2624     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2625         x86_cpu_apic_create(cpu, &local_err);
2626         if (local_err != NULL) {
2627             goto out;
2628         }
2629     }
2630 #endif
2631
2632     mce_init(cpu);
2633     qemu_init_vcpu(cs);
2634
2635     x86_cpu_apic_realize(cpu, &local_err);
2636     if (local_err != NULL) {
2637         goto out;
2638     }
2639     cpu_reset(cs);
2640
2641     xcc->parent_realize(dev, &local_err);
2642 out:
2643     if (local_err != NULL) {
2644         error_propagate(errp, local_err);
2645         return;
2646     }
2647 }
2648
2649 /* Enables contiguous-apic-ID mode, for compatibility */
2650 static bool compat_apic_id_mode;
2651
2652 void enable_compat_apic_id_mode(void)
2653 {
2654     compat_apic_id_mode = true;
2655 }
2656
2657 /* Calculates initial APIC ID for a specific CPU index
2658  *
2659  * Currently we need to be able to calculate the APIC ID from the CPU index
2660  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2661  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2662  * all CPUs up to max_cpus.
2663  */
2664 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2665 {
2666     uint32_t correct_id;
2667     static bool warned;
2668
2669     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2670     if (compat_apic_id_mode) {
2671         if (cpu_index != correct_id && !warned) {
2672             error_report("APIC IDs set in compatibility mode, "
2673                          "CPU topology won't match the configuration");
2674             warned = true;
2675         }
2676         return cpu_index;
2677     } else {
2678         return correct_id;
2679     }
2680 }
2681
2682 static void x86_cpu_initfn(Object *obj)
2683 {
2684     CPUState *cs = CPU(obj);
2685     X86CPU *cpu = X86_CPU(obj);
2686     X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2687     CPUX86State *env = &cpu->env;
2688     static int inited;
2689
2690     cs->env_ptr = env;
2691     cpu_exec_init(env);
2692
2693     object_property_add(obj, "family", "int",
2694                         x86_cpuid_version_get_family,
2695                         x86_cpuid_version_set_family, NULL, NULL, NULL);
2696     object_property_add(obj, "model", "int",
2697                         x86_cpuid_version_get_model,
2698                         x86_cpuid_version_set_model, NULL, NULL, NULL);
2699     object_property_add(obj, "stepping", "int",
2700                         x86_cpuid_version_get_stepping,
2701                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2702     object_property_add(obj, "level", "int",
2703                         x86_cpuid_get_level,
2704                         x86_cpuid_set_level, NULL, NULL, NULL);
2705     object_property_add(obj, "xlevel", "int",
2706                         x86_cpuid_get_xlevel,
2707                         x86_cpuid_set_xlevel, NULL, NULL, NULL);
2708     object_property_add_str(obj, "vendor",
2709                             x86_cpuid_get_vendor,
2710                             x86_cpuid_set_vendor, NULL);
2711     object_property_add_str(obj, "model-id",
2712                             x86_cpuid_get_model_id,
2713                             x86_cpuid_set_model_id, NULL);
2714     object_property_add(obj, "tsc-frequency", "int",
2715                         x86_cpuid_get_tsc_freq,
2716                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2717     object_property_add(obj, "apic-id", "int",
2718                         x86_cpuid_get_apic_id,
2719                         x86_cpuid_set_apic_id, NULL, NULL, NULL);
2720     object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2721                         x86_cpu_get_feature_words,
2722                         NULL, NULL, (void *)env->features, NULL);
2723     object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2724                         x86_cpu_get_feature_words,
2725                         NULL, NULL, (void *)cpu->filtered_features, NULL);
2726
2727     cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2728     env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2729
2730     x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2731
2732     /* init various static tables used in TCG mode */
2733     if (tcg_enabled() && !inited) {
2734         inited = 1;
2735         optimize_flags_init();
2736 #ifndef CONFIG_USER_ONLY
2737         cpu_set_debug_excp_handler(breakpoint_handler);
2738 #endif
2739     }
2740 }
2741
2742 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2743 {
2744     X86CPU *cpu = X86_CPU(cs);
2745     CPUX86State *env = &cpu->env;
2746
2747     return env->cpuid_apic_id;
2748 }
2749
2750 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2751 {
2752     X86CPU *cpu = X86_CPU(cs);
2753
2754     return cpu->env.cr[0] & CR0_PG_MASK;
2755 }
2756
2757 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2758 {
2759     X86CPU *cpu = X86_CPU(cs);
2760
2761     cpu->env.eip = value;
2762 }
2763
2764 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2765 {
2766     X86CPU *cpu = X86_CPU(cs);
2767
2768     cpu->env.eip = tb->pc - tb->cs_base;
2769 }
2770
2771 static bool x86_cpu_has_work(CPUState *cs)
2772 {
2773     X86CPU *cpu = X86_CPU(cs);
2774     CPUX86State *env = &cpu->env;
2775
2776     return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2777                                       CPU_INTERRUPT_POLL)) &&
2778             (env->eflags & IF_MASK)) ||
2779            (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2780                                      CPU_INTERRUPT_INIT |
2781                                      CPU_INTERRUPT_SIPI |
2782                                      CPU_INTERRUPT_MCE));
2783 }
2784
2785 static Property x86_cpu_properties[] = {
2786     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2787     { .name  = "hv-spinlocks", .info  = &qdev_prop_spinlocks },
2788     DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2789     DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2790     DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2791     DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2792     DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2793     DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
2794     DEFINE_PROP_END_OF_LIST()
2795 };
2796
2797 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2798 {
2799     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2800     CPUClass *cc = CPU_CLASS(oc);
2801     DeviceClass *dc = DEVICE_CLASS(oc);
2802
2803     xcc->parent_realize = dc->realize;
2804     dc->realize = x86_cpu_realizefn;
2805     dc->bus_type = TYPE_ICC_BUS;
2806     dc->props = x86_cpu_properties;
2807
2808     xcc->parent_reset = cc->reset;
2809     cc->reset = x86_cpu_reset;
2810     cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2811
2812     cc->class_by_name = x86_cpu_class_by_name;
2813     cc->parse_features = x86_cpu_parse_featurestr;
2814     cc->has_work = x86_cpu_has_work;
2815     cc->do_interrupt = x86_cpu_do_interrupt;
2816     cc->dump_state = x86_cpu_dump_state;
2817     cc->set_pc = x86_cpu_set_pc;
2818     cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2819     cc->gdb_read_register = x86_cpu_gdb_read_register;
2820     cc->gdb_write_register = x86_cpu_gdb_write_register;
2821     cc->get_arch_id = x86_cpu_get_arch_id;
2822     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2823 #ifdef CONFIG_USER_ONLY
2824     cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2825 #else
2826     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2827     cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2828     cc->write_elf64_note = x86_cpu_write_elf64_note;
2829     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2830     cc->write_elf32_note = x86_cpu_write_elf32_note;
2831     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2832     cc->vmsd = &vmstate_x86_cpu;
2833 #endif
2834     cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2835 }
2836
2837 static const TypeInfo x86_cpu_type_info = {
2838     .name = TYPE_X86_CPU,
2839     .parent = TYPE_CPU,
2840     .instance_size = sizeof(X86CPU),
2841     .instance_init = x86_cpu_initfn,
2842     .abstract = true,
2843     .class_size = sizeof(X86CPUClass),
2844     .class_init = x86_cpu_common_class_init,
2845 };
2846
2847 static void x86_cpu_register_types(void)
2848 {
2849     int i;
2850
2851     type_register_static(&x86_cpu_type_info);
2852     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2853         x86_register_cpudef_type(&builtin_x86_defs[i]);
2854     }
2855 #ifdef CONFIG_KVM
2856     type_register_static(&host_x86_cpu_type_info);
2857 #endif
2858 }
2859
2860 type_init(x86_cpu_register_types)