4 /* CPU interfaces that are target independent. */
6 #ifndef CONFIG_USER_ONLY
7 #include "exec/hwaddr.h"
10 #include "qemu/bswap.h"
11 #include "qemu/queue.h"
13 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */
14 void qemu_init_cpu_list(void);
15 void cpu_list_lock(void);
16 void cpu_list_unlock(void);
18 void tcg_flush_softmmu_tlb(CPUState *cs);
20 #if !defined(CONFIG_USER_ONLY)
28 #if defined(HOST_WORDS_BIGENDIAN)
29 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN
31 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN
34 /* address in the RAM (different from a physical address) */
35 #if defined(CONFIG_XEN_BACKEND)
36 typedef uint64_t ram_addr_t;
37 # define RAM_ADDR_MAX UINT64_MAX
38 # define RAM_ADDR_FMT "%" PRIx64
40 typedef uintptr_t ram_addr_t;
41 # define RAM_ADDR_MAX UINTPTR_MAX
42 # define RAM_ADDR_FMT "%" PRIxPTR
45 extern ram_addr_t ram_size;
49 typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
50 typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
52 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
53 /* This should not be used by devices. */
54 ram_addr_t qemu_ram_addr_from_host(void *ptr);
55 RAMBlock *qemu_ram_block_by_name(const char *name);
56 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
58 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host);
59 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev);
60 void qemu_ram_unset_idstr(RAMBlock *block);
61 const char *qemu_ram_get_idstr(RAMBlock *rb);
62 void *qemu_ram_get_host_addr(RAMBlock *rb);
63 ram_addr_t qemu_ram_get_offset(RAMBlock *rb);
64 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb);
65 bool qemu_ram_is_shared(RAMBlock *rb);
66 bool qemu_ram_is_uf_zeroable(RAMBlock *rb);
67 void qemu_ram_set_uf_zeroable(RAMBlock *rb);
68 bool qemu_ram_is_migratable(RAMBlock *rb);
69 void qemu_ram_set_migratable(RAMBlock *rb);
70 void qemu_ram_unset_migratable(RAMBlock *rb);
72 size_t qemu_ram_pagesize(RAMBlock *block);
73 size_t qemu_ram_pagesize_largest(void);
75 void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
76 hwaddr len, int is_write);
77 static inline void cpu_physical_memory_read(hwaddr addr,
78 void *buf, hwaddr len)
80 cpu_physical_memory_rw(addr, buf, len, 0);
82 static inline void cpu_physical_memory_write(hwaddr addr,
83 const void *buf, hwaddr len)
85 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
87 void *cpu_physical_memory_map(hwaddr addr,
90 void cpu_physical_memory_unmap(void *buffer, hwaddr len,
91 int is_write, hwaddr access_len);
92 void cpu_register_map_client(QEMUBH *bh);
93 void cpu_unregister_map_client(QEMUBH *bh);
95 bool cpu_physical_memory_is_io(hwaddr phys_addr);
97 /* Coalesced MMIO regions are areas where write operations can be reordered.
98 * This usually implies that write operations are side-effect free. This allows
99 * batching which can make a major impact on performance when using
102 void qemu_flush_coalesced_mmio_buffer(void);
104 void cpu_flush_icache_range(hwaddr start, hwaddr len);
106 extern struct MemoryRegion io_mem_rom;
107 extern struct MemoryRegion io_mem_notdirty;
109 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque);
111 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
112 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length);
116 #endif /* CPU_COMMON_H */