2 * QEMU PowerPC 405 embedded processors emulation
4 * Copyright (c) 2007 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/ppc405.h"
27 #include "hw/serial.h"
28 #include "qemu/timer.h"
29 #include "sysemu/sysemu.h"
31 #include "exec/address-spaces.h"
42 //#define DEBUG_CLOCKS_LL
44 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
50 /* We put the bd structure at the top of memory */
51 if (bd->bi_memsize >= 0x01000000UL)
52 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
54 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
55 stl_be_phys(bdloc + 0x00, bd->bi_memstart);
56 stl_be_phys(bdloc + 0x04, bd->bi_memsize);
57 stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
58 stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
59 stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);
60 stl_be_phys(bdloc + 0x14, bd->bi_sramstart);
61 stl_be_phys(bdloc + 0x18, bd->bi_sramsize);
62 stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);
63 stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);
64 for (i = 0; i < 6; i++) {
65 stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
67 stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
68 stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);
69 stl_be_phys(bdloc + 0x30, bd->bi_busfreq);
70 stl_be_phys(bdloc + 0x34, bd->bi_baudrate);
71 for (i = 0; i < 4; i++) {
72 stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
74 for (i = 0; i < 32; i++) {
75 stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
77 stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
78 stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);
79 for (i = 0; i < 6; i++) {
80 stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
83 if (flags & 0x00000001) {
84 for (i = 0; i < 6; i++)
85 stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
87 stl_be_phys(bdloc + n, bd->bi_opbfreq);
89 for (i = 0; i < 2; i++) {
90 stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);
97 /*****************************************************************************/
98 /* Shared peripherals */
100 /*****************************************************************************/
101 /* Peripheral local bus arbitrer */
108 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
109 struct ppc4xx_plb_t {
115 static uint32_t dcr_read_plb (void *opaque, int dcrn)
132 /* Avoid gcc warning */
140 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
147 /* We don't care about the actual parameters written as
148 * we don't manage any priorities on the bus
150 plb->acr = val & 0xF8000000;
162 static void ppc4xx_plb_reset (void *opaque)
167 plb->acr = 0x00000000;
168 plb->bear = 0x00000000;
169 plb->besr = 0x00000000;
172 static void ppc4xx_plb_init(CPUPPCState *env)
176 plb = g_malloc0(sizeof(ppc4xx_plb_t));
177 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
178 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
179 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
180 qemu_register_reset(ppc4xx_plb_reset, plb);
183 /*****************************************************************************/
184 /* PLB to OPB bridge */
191 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
192 struct ppc4xx_pob_t {
198 static uint32_t dcr_read_pob (void *opaque, int dcrn)
215 /* Avoid gcc warning */
223 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
243 static void ppc4xx_pob_reset (void *opaque)
249 pob->bear = 0x00000000;
250 pob->besr0 = 0x0000000;
251 pob->besr1 = 0x0000000;
254 static void ppc4xx_pob_init(CPUPPCState *env)
258 pob = g_malloc0(sizeof(ppc4xx_pob_t));
259 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
260 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
261 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
262 qemu_register_reset(ppc4xx_pob_reset, pob);
265 /*****************************************************************************/
267 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
268 struct ppc4xx_opba_t {
274 static uint32_t opba_readb (void *opaque, hwaddr addr)
280 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
298 static void opba_writeb (void *opaque,
299 hwaddr addr, uint32_t value)
304 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
310 opba->cr = value & 0xF8;
313 opba->pr = value & 0xFF;
320 static uint32_t opba_readw (void *opaque, hwaddr addr)
325 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
327 ret = opba_readb(opaque, addr) << 8;
328 ret |= opba_readb(opaque, addr + 1);
333 static void opba_writew (void *opaque,
334 hwaddr addr, uint32_t value)
337 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
340 opba_writeb(opaque, addr, value >> 8);
341 opba_writeb(opaque, addr + 1, value);
344 static uint32_t opba_readl (void *opaque, hwaddr addr)
349 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
351 ret = opba_readb(opaque, addr) << 24;
352 ret |= opba_readb(opaque, addr + 1) << 16;
357 static void opba_writel (void *opaque,
358 hwaddr addr, uint32_t value)
361 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
364 opba_writeb(opaque, addr, value >> 24);
365 opba_writeb(opaque, addr + 1, value >> 16);
368 static const MemoryRegionOps opba_ops = {
370 .read = { opba_readb, opba_readw, opba_readl, },
371 .write = { opba_writeb, opba_writew, opba_writel, },
373 .endianness = DEVICE_NATIVE_ENDIAN,
376 static void ppc4xx_opba_reset (void *opaque)
381 opba->cr = 0x00; /* No dynamic priorities - park disabled */
385 static void ppc4xx_opba_init(hwaddr base)
389 opba = g_malloc0(sizeof(ppc4xx_opba_t));
391 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
393 memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
394 memory_region_add_subregion(get_system_memory(), base, &opba->io);
395 qemu_register_reset(ppc4xx_opba_reset, opba);
398 /*****************************************************************************/
399 /* Code decompression controller */
402 /*****************************************************************************/
403 /* Peripheral controller */
404 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
405 struct ppc4xx_ebc_t {
416 EBC0_CFGADDR = 0x012,
417 EBC0_CFGDATA = 0x013,
420 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
432 case 0x00: /* B0CR */
435 case 0x01: /* B1CR */
438 case 0x02: /* B2CR */
441 case 0x03: /* B3CR */
444 case 0x04: /* B4CR */
447 case 0x05: /* B5CR */
450 case 0x06: /* B6CR */
453 case 0x07: /* B7CR */
456 case 0x10: /* B0AP */
459 case 0x11: /* B1AP */
462 case 0x12: /* B2AP */
465 case 0x13: /* B3AP */
468 case 0x14: /* B4AP */
471 case 0x15: /* B5AP */
474 case 0x16: /* B6AP */
477 case 0x17: /* B7AP */
480 case 0x20: /* BEAR */
483 case 0x21: /* BESR0 */
486 case 0x22: /* BESR1 */
505 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
516 case 0x00: /* B0CR */
518 case 0x01: /* B1CR */
520 case 0x02: /* B2CR */
522 case 0x03: /* B3CR */
524 case 0x04: /* B4CR */
526 case 0x05: /* B5CR */
528 case 0x06: /* B6CR */
530 case 0x07: /* B7CR */
532 case 0x10: /* B0AP */
534 case 0x11: /* B1AP */
536 case 0x12: /* B2AP */
538 case 0x13: /* B3AP */
540 case 0x14: /* B4AP */
542 case 0x15: /* B5AP */
544 case 0x16: /* B6AP */
546 case 0x17: /* B7AP */
548 case 0x20: /* BEAR */
550 case 0x21: /* BESR0 */
552 case 0x22: /* BESR1 */
565 static void ebc_reset (void *opaque)
571 ebc->addr = 0x00000000;
572 ebc->bap[0] = 0x7F8FFE80;
573 ebc->bcr[0] = 0xFFE28000;
574 for (i = 0; i < 8; i++) {
575 ebc->bap[i] = 0x00000000;
576 ebc->bcr[i] = 0x00000000;
578 ebc->besr0 = 0x00000000;
579 ebc->besr1 = 0x00000000;
580 ebc->cfg = 0x80400000;
583 static void ppc405_ebc_init(CPUPPCState *env)
587 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
588 qemu_register_reset(&ebc_reset, ebc);
589 ppc_dcr_register(env, EBC0_CFGADDR,
590 ebc, &dcr_read_ebc, &dcr_write_ebc);
591 ppc_dcr_register(env, EBC0_CFGDATA,
592 ebc, &dcr_read_ebc, &dcr_write_ebc);
595 /*****************************************************************************/
624 typedef struct ppc405_dma_t ppc405_dma_t;
625 struct ppc405_dma_t {
638 static uint32_t dcr_read_dma (void *opaque, int dcrn)
643 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
647 static void ppc405_dma_reset (void *opaque)
653 for (i = 0; i < 4; i++) {
654 dma->cr[i] = 0x00000000;
655 dma->ct[i] = 0x00000000;
656 dma->da[i] = 0x00000000;
657 dma->sa[i] = 0x00000000;
658 dma->sg[i] = 0x00000000;
660 dma->sr = 0x00000000;
661 dma->sgc = 0x00000000;
662 dma->slp = 0x7C000000;
663 dma->pol = 0x00000000;
666 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
670 dma = g_malloc0(sizeof(ppc405_dma_t));
671 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
672 qemu_register_reset(&ppc405_dma_reset, dma);
673 ppc_dcr_register(env, DMA0_CR0,
674 dma, &dcr_read_dma, &dcr_write_dma);
675 ppc_dcr_register(env, DMA0_CT0,
676 dma, &dcr_read_dma, &dcr_write_dma);
677 ppc_dcr_register(env, DMA0_DA0,
678 dma, &dcr_read_dma, &dcr_write_dma);
679 ppc_dcr_register(env, DMA0_SA0,
680 dma, &dcr_read_dma, &dcr_write_dma);
681 ppc_dcr_register(env, DMA0_SG0,
682 dma, &dcr_read_dma, &dcr_write_dma);
683 ppc_dcr_register(env, DMA0_CR1,
684 dma, &dcr_read_dma, &dcr_write_dma);
685 ppc_dcr_register(env, DMA0_CT1,
686 dma, &dcr_read_dma, &dcr_write_dma);
687 ppc_dcr_register(env, DMA0_DA1,
688 dma, &dcr_read_dma, &dcr_write_dma);
689 ppc_dcr_register(env, DMA0_SA1,
690 dma, &dcr_read_dma, &dcr_write_dma);
691 ppc_dcr_register(env, DMA0_SG1,
692 dma, &dcr_read_dma, &dcr_write_dma);
693 ppc_dcr_register(env, DMA0_CR2,
694 dma, &dcr_read_dma, &dcr_write_dma);
695 ppc_dcr_register(env, DMA0_CT2,
696 dma, &dcr_read_dma, &dcr_write_dma);
697 ppc_dcr_register(env, DMA0_DA2,
698 dma, &dcr_read_dma, &dcr_write_dma);
699 ppc_dcr_register(env, DMA0_SA2,
700 dma, &dcr_read_dma, &dcr_write_dma);
701 ppc_dcr_register(env, DMA0_SG2,
702 dma, &dcr_read_dma, &dcr_write_dma);
703 ppc_dcr_register(env, DMA0_CR3,
704 dma, &dcr_read_dma, &dcr_write_dma);
705 ppc_dcr_register(env, DMA0_CT3,
706 dma, &dcr_read_dma, &dcr_write_dma);
707 ppc_dcr_register(env, DMA0_DA3,
708 dma, &dcr_read_dma, &dcr_write_dma);
709 ppc_dcr_register(env, DMA0_SA3,
710 dma, &dcr_read_dma, &dcr_write_dma);
711 ppc_dcr_register(env, DMA0_SG3,
712 dma, &dcr_read_dma, &dcr_write_dma);
713 ppc_dcr_register(env, DMA0_SR,
714 dma, &dcr_read_dma, &dcr_write_dma);
715 ppc_dcr_register(env, DMA0_SGC,
716 dma, &dcr_read_dma, &dcr_write_dma);
717 ppc_dcr_register(env, DMA0_SLP,
718 dma, &dcr_read_dma, &dcr_write_dma);
719 ppc_dcr_register(env, DMA0_POL,
720 dma, &dcr_read_dma, &dcr_write_dma);
723 /*****************************************************************************/
725 typedef struct ppc405_gpio_t ppc405_gpio_t;
726 struct ppc405_gpio_t {
741 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
744 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
750 static void ppc405_gpio_writeb (void *opaque,
751 hwaddr addr, uint32_t value)
754 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
759 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
762 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
768 static void ppc405_gpio_writew (void *opaque,
769 hwaddr addr, uint32_t value)
772 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
777 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
780 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
786 static void ppc405_gpio_writel (void *opaque,
787 hwaddr addr, uint32_t value)
790 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
795 static const MemoryRegionOps ppc405_gpio_ops = {
797 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
798 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
800 .endianness = DEVICE_NATIVE_ENDIAN,
803 static void ppc405_gpio_reset (void *opaque)
807 static void ppc405_gpio_init(hwaddr base)
811 gpio = g_malloc0(sizeof(ppc405_gpio_t));
813 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
815 memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
816 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
817 qemu_register_reset(&ppc405_gpio_reset, gpio);
820 /*****************************************************************************/
824 OCM0_ISACNTL = 0x019,
826 OCM0_DSACNTL = 0x01B,
829 typedef struct ppc405_ocm_t ppc405_ocm_t;
830 struct ppc405_ocm_t {
832 MemoryRegion isarc_ram;
833 MemoryRegion dsarc_ram;
840 static void ocm_update_mappings (ppc405_ocm_t *ocm,
841 uint32_t isarc, uint32_t isacntl,
842 uint32_t dsarc, uint32_t dsacntl)
845 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
846 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
847 " (%08" PRIx32 " %08" PRIx32 ")\n",
848 isarc, isacntl, dsarc, dsacntl,
849 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
851 if (ocm->isarc != isarc ||
852 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
853 if (ocm->isacntl & 0x80000000) {
854 /* Unmap previously assigned memory region */
855 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
856 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
858 if (isacntl & 0x80000000) {
859 /* Map new instruction memory region */
861 printf("OCM map ISA %08" PRIx32 "\n", isarc);
863 memory_region_add_subregion(get_system_memory(), isarc,
867 if (ocm->dsarc != dsarc ||
868 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
869 if (ocm->dsacntl & 0x80000000) {
870 /* Beware not to unmap the region we just mapped */
871 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
872 /* Unmap previously assigned memory region */
874 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
876 memory_region_del_subregion(get_system_memory(),
880 if (dsacntl & 0x80000000) {
881 /* Beware not to remap the region we just mapped */
882 if (!(isacntl & 0x80000000) || dsarc != isarc) {
883 /* Map new data memory region */
885 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
887 memory_region_add_subregion(get_system_memory(), dsarc,
894 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
921 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
924 uint32_t isarc, dsarc, isacntl, dsacntl;
929 isacntl = ocm->isacntl;
930 dsacntl = ocm->dsacntl;
933 isarc = val & 0xFC000000;
936 isacntl = val & 0xC0000000;
939 isarc = val & 0xFC000000;
942 isacntl = val & 0xC0000000;
945 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
948 ocm->isacntl = isacntl;
949 ocm->dsacntl = dsacntl;
952 static void ocm_reset (void *opaque)
955 uint32_t isarc, dsarc, isacntl, dsacntl;
959 isacntl = 0x00000000;
961 dsacntl = 0x00000000;
962 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
965 ocm->isacntl = isacntl;
966 ocm->dsacntl = dsacntl;
969 static void ppc405_ocm_init(CPUPPCState *env)
973 ocm = g_malloc0(sizeof(ppc405_ocm_t));
974 /* XXX: Size is 4096 or 0x04000000 */
975 memory_region_init_ram(&ocm->isarc_ram, "ppc405.ocm", 4096);
976 vmstate_register_ram_global(&ocm->isarc_ram);
977 memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
979 qemu_register_reset(&ocm_reset, ocm);
980 ppc_dcr_register(env, OCM0_ISARC,
981 ocm, &dcr_read_ocm, &dcr_write_ocm);
982 ppc_dcr_register(env, OCM0_ISACNTL,
983 ocm, &dcr_read_ocm, &dcr_write_ocm);
984 ppc_dcr_register(env, OCM0_DSARC,
985 ocm, &dcr_read_ocm, &dcr_write_ocm);
986 ppc_dcr_register(env, OCM0_DSACNTL,
987 ocm, &dcr_read_ocm, &dcr_write_ocm);
990 /*****************************************************************************/
992 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
993 struct ppc4xx_i2c_t {
1013 static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
1019 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1024 // i2c_readbyte(&i2c->mdata);
1064 ret = i2c->xtcntlss;
1067 ret = i2c->directcntl;
1074 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1080 static void ppc4xx_i2c_writeb (void *opaque,
1081 hwaddr addr, uint32_t value)
1086 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1093 // i2c_sendbyte(&i2c->mdata);
1108 i2c->mdcntl = value & 0xDF;
1111 i2c->sts &= ~(value & 0x0A);
1114 i2c->extsts &= ~(value & 0x8F);
1123 i2c->clkdiv = value;
1126 i2c->intrmsk = value;
1129 i2c->xfrcnt = value & 0x77;
1132 i2c->xtcntlss = value;
1135 i2c->directcntl = value & 0x7;
1140 static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
1145 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1147 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1148 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1153 static void ppc4xx_i2c_writew (void *opaque,
1154 hwaddr addr, uint32_t value)
1157 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1160 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1161 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1164 static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
1169 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1171 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1172 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1173 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1174 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1179 static void ppc4xx_i2c_writel (void *opaque,
1180 hwaddr addr, uint32_t value)
1183 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1186 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1187 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1188 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1189 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1192 static const MemoryRegionOps i2c_ops = {
1194 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1195 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1197 .endianness = DEVICE_NATIVE_ENDIAN,
1200 static void ppc4xx_i2c_reset (void *opaque)
1213 i2c->directcntl = 0x0F;
1216 static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
1220 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1223 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1225 memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
1226 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1227 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1230 /*****************************************************************************/
1231 /* General purpose timers */
1232 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1233 struct ppc4xx_gpt_t {
1237 struct QEMUTimer *timer;
1248 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1251 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1253 /* XXX: generate a bus fault */
1257 static void ppc4xx_gpt_writeb (void *opaque,
1258 hwaddr addr, uint32_t value)
1261 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1264 /* XXX: generate a bus fault */
1267 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1270 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1272 /* XXX: generate a bus fault */
1276 static void ppc4xx_gpt_writew (void *opaque,
1277 hwaddr addr, uint32_t value)
1280 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1283 /* XXX: generate a bus fault */
1286 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1292 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1297 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1303 for (i = 0; i < 5; i++) {
1304 if (gpt->oe & mask) {
1305 /* Output is enabled */
1306 if (ppc4xx_gpt_compare(gpt, i)) {
1307 /* Comparison is OK */
1308 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1310 /* Comparison is KO */
1311 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1318 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1324 for (i = 0; i < 5; i++) {
1325 if (gpt->is & gpt->im & mask)
1326 qemu_irq_raise(gpt->irqs[i]);
1328 qemu_irq_lower(gpt->irqs[i]);
1333 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1338 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1345 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1350 /* Time base counter */
1351 ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
1352 gpt->tb_freq, get_ticks_per_sec());
1363 /* Interrupt mask */
1368 /* Interrupt status */
1372 /* Interrupt enable */
1377 idx = (addr - 0x80) >> 2;
1378 ret = gpt->comp[idx];
1382 idx = (addr - 0xC0) >> 2;
1383 ret = gpt->mask[idx];
1393 static void ppc4xx_gpt_writel (void *opaque,
1394 hwaddr addr, uint32_t value)
1400 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1406 /* Time base counter */
1407 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1408 - qemu_get_clock_ns(vm_clock);
1409 ppc4xx_gpt_compute_timer(gpt);
1413 gpt->oe = value & 0xF8000000;
1414 ppc4xx_gpt_set_outputs(gpt);
1418 gpt->ol = value & 0xF8000000;
1419 ppc4xx_gpt_set_outputs(gpt);
1422 /* Interrupt mask */
1423 gpt->im = value & 0x0000F800;
1426 /* Interrupt status set */
1427 gpt->is |= value & 0x0000F800;
1428 ppc4xx_gpt_set_irqs(gpt);
1431 /* Interrupt status clear */
1432 gpt->is &= ~(value & 0x0000F800);
1433 ppc4xx_gpt_set_irqs(gpt);
1436 /* Interrupt enable */
1437 gpt->ie = value & 0x0000F800;
1438 ppc4xx_gpt_set_irqs(gpt);
1442 idx = (addr - 0x80) >> 2;
1443 gpt->comp[idx] = value & 0xF8000000;
1444 ppc4xx_gpt_compute_timer(gpt);
1448 idx = (addr - 0xC0) >> 2;
1449 gpt->mask[idx] = value & 0xF8000000;
1450 ppc4xx_gpt_compute_timer(gpt);
1455 static const MemoryRegionOps gpt_ops = {
1457 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1458 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1460 .endianness = DEVICE_NATIVE_ENDIAN,
1463 static void ppc4xx_gpt_cb (void *opaque)
1468 ppc4xx_gpt_set_irqs(gpt);
1469 ppc4xx_gpt_set_outputs(gpt);
1470 ppc4xx_gpt_compute_timer(gpt);
1473 static void ppc4xx_gpt_reset (void *opaque)
1479 qemu_del_timer(gpt->timer);
1480 gpt->oe = 0x00000000;
1481 gpt->ol = 0x00000000;
1482 gpt->im = 0x00000000;
1483 gpt->is = 0x00000000;
1484 gpt->ie = 0x00000000;
1485 for (i = 0; i < 5; i++) {
1486 gpt->comp[i] = 0x00000000;
1487 gpt->mask[i] = 0x00000000;
1491 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1496 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1497 for (i = 0; i < 5; i++) {
1498 gpt->irqs[i] = irqs[i];
1500 gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
1502 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1504 memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
1505 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1506 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1509 /*****************************************************************************/
1515 MAL0_TXCASR = 0x184,
1516 MAL0_TXCARR = 0x185,
1517 MAL0_TXEOBISR = 0x186,
1518 MAL0_TXDEIR = 0x187,
1519 MAL0_RXCASR = 0x190,
1520 MAL0_RXCARR = 0x191,
1521 MAL0_RXEOBISR = 0x192,
1522 MAL0_RXDEIR = 0x193,
1523 MAL0_TXCTP0R = 0x1A0,
1524 MAL0_TXCTP1R = 0x1A1,
1525 MAL0_TXCTP2R = 0x1A2,
1526 MAL0_TXCTP3R = 0x1A3,
1527 MAL0_RXCTP0R = 0x1C0,
1528 MAL0_RXCTP1R = 0x1C1,
1533 typedef struct ppc40x_mal_t ppc40x_mal_t;
1534 struct ppc40x_mal_t {
1552 static void ppc40x_mal_reset (void *opaque);
1554 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1577 ret = mal->txeobisr;
1589 ret = mal->rxeobisr;
1595 ret = mal->txctpr[0];
1598 ret = mal->txctpr[1];
1601 ret = mal->txctpr[2];
1604 ret = mal->txctpr[3];
1607 ret = mal->rxctpr[0];
1610 ret = mal->rxctpr[1];
1626 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1634 if (val & 0x80000000)
1635 ppc40x_mal_reset(mal);
1636 mal->cfg = val & 0x00FFC087;
1643 mal->ier = val & 0x0000001F;
1646 mal->txcasr = val & 0xF0000000;
1649 mal->txcarr = val & 0xF0000000;
1653 mal->txeobisr &= ~val;
1657 mal->txdeir &= ~val;
1660 mal->rxcasr = val & 0xC0000000;
1663 mal->rxcarr = val & 0xC0000000;
1667 mal->rxeobisr &= ~val;
1671 mal->rxdeir &= ~val;
1685 mal->txctpr[idx] = val;
1693 mal->rxctpr[idx] = val;
1697 goto update_rx_size;
1701 mal->rcbs[idx] = val & 0x000000FF;
1706 static void ppc40x_mal_reset (void *opaque)
1711 mal->cfg = 0x0007C000;
1712 mal->esr = 0x00000000;
1713 mal->ier = 0x00000000;
1714 mal->rxcasr = 0x00000000;
1715 mal->rxdeir = 0x00000000;
1716 mal->rxeobisr = 0x00000000;
1717 mal->txcasr = 0x00000000;
1718 mal->txdeir = 0x00000000;
1719 mal->txeobisr = 0x00000000;
1722 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
1727 mal = g_malloc0(sizeof(ppc40x_mal_t));
1728 for (i = 0; i < 4; i++)
1729 mal->irqs[i] = irqs[i];
1730 qemu_register_reset(&ppc40x_mal_reset, mal);
1731 ppc_dcr_register(env, MAL0_CFG,
1732 mal, &dcr_read_mal, &dcr_write_mal);
1733 ppc_dcr_register(env, MAL0_ESR,
1734 mal, &dcr_read_mal, &dcr_write_mal);
1735 ppc_dcr_register(env, MAL0_IER,
1736 mal, &dcr_read_mal, &dcr_write_mal);
1737 ppc_dcr_register(env, MAL0_TXCASR,
1738 mal, &dcr_read_mal, &dcr_write_mal);
1739 ppc_dcr_register(env, MAL0_TXCARR,
1740 mal, &dcr_read_mal, &dcr_write_mal);
1741 ppc_dcr_register(env, MAL0_TXEOBISR,
1742 mal, &dcr_read_mal, &dcr_write_mal);
1743 ppc_dcr_register(env, MAL0_TXDEIR,
1744 mal, &dcr_read_mal, &dcr_write_mal);
1745 ppc_dcr_register(env, MAL0_RXCASR,
1746 mal, &dcr_read_mal, &dcr_write_mal);
1747 ppc_dcr_register(env, MAL0_RXCARR,
1748 mal, &dcr_read_mal, &dcr_write_mal);
1749 ppc_dcr_register(env, MAL0_RXEOBISR,
1750 mal, &dcr_read_mal, &dcr_write_mal);
1751 ppc_dcr_register(env, MAL0_RXDEIR,
1752 mal, &dcr_read_mal, &dcr_write_mal);
1753 ppc_dcr_register(env, MAL0_TXCTP0R,
1754 mal, &dcr_read_mal, &dcr_write_mal);
1755 ppc_dcr_register(env, MAL0_TXCTP1R,
1756 mal, &dcr_read_mal, &dcr_write_mal);
1757 ppc_dcr_register(env, MAL0_TXCTP2R,
1758 mal, &dcr_read_mal, &dcr_write_mal);
1759 ppc_dcr_register(env, MAL0_TXCTP3R,
1760 mal, &dcr_read_mal, &dcr_write_mal);
1761 ppc_dcr_register(env, MAL0_RXCTP0R,
1762 mal, &dcr_read_mal, &dcr_write_mal);
1763 ppc_dcr_register(env, MAL0_RXCTP1R,
1764 mal, &dcr_read_mal, &dcr_write_mal);
1765 ppc_dcr_register(env, MAL0_RCBS0,
1766 mal, &dcr_read_mal, &dcr_write_mal);
1767 ppc_dcr_register(env, MAL0_RCBS1,
1768 mal, &dcr_read_mal, &dcr_write_mal);
1771 /*****************************************************************************/
1773 void ppc40x_core_reset(PowerPCCPU *cpu)
1775 CPUPPCState *env = &cpu->env;
1778 printf("Reset PowerPC core\n");
1779 cpu_interrupt(env, CPU_INTERRUPT_RESET);
1780 dbsr = env->spr[SPR_40x_DBSR];
1781 dbsr &= ~0x00000300;
1783 env->spr[SPR_40x_DBSR] = dbsr;
1786 void ppc40x_chip_reset(PowerPCCPU *cpu)
1788 CPUPPCState *env = &cpu->env;
1791 printf("Reset PowerPC chip\n");
1792 cpu_interrupt(env, CPU_INTERRUPT_RESET);
1793 /* XXX: TODO reset all internal peripherals */
1794 dbsr = env->spr[SPR_40x_DBSR];
1795 dbsr &= ~0x00000300;
1797 env->spr[SPR_40x_DBSR] = dbsr;
1800 void ppc40x_system_reset(PowerPCCPU *cpu)
1802 printf("Reset PowerPC system\n");
1803 qemu_system_reset_request();
1806 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1808 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1810 switch ((val >> 28) & 0x3) {
1816 ppc40x_core_reset(cpu);
1820 ppc40x_chip_reset(cpu);
1824 ppc40x_system_reset(cpu);
1829 /*****************************************************************************/
1832 PPC405CR_CPC0_PLLMR = 0x0B0,
1833 PPC405CR_CPC0_CR0 = 0x0B1,
1834 PPC405CR_CPC0_CR1 = 0x0B2,
1835 PPC405CR_CPC0_PSR = 0x0B4,
1836 PPC405CR_CPC0_JTAGID = 0x0B5,
1837 PPC405CR_CPC0_ER = 0x0B9,
1838 PPC405CR_CPC0_FR = 0x0BA,
1839 PPC405CR_CPC0_SR = 0x0BB,
1843 PPC405CR_CPU_CLK = 0,
1844 PPC405CR_TMR_CLK = 1,
1845 PPC405CR_PLB_CLK = 2,
1846 PPC405CR_SDRAM_CLK = 3,
1847 PPC405CR_OPB_CLK = 4,
1848 PPC405CR_EXT_CLK = 5,
1849 PPC405CR_UART_CLK = 6,
1850 PPC405CR_CLK_NB = 7,
1853 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1854 struct ppc405cr_cpc_t {
1855 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1866 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1868 uint64_t VCO_out, PLL_out;
1869 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1872 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1873 if (cpc->pllmr & 0x80000000) {
1874 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1875 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1877 VCO_out = cpc->sysclk * M;
1878 if (VCO_out < 400000000 || VCO_out > 800000000) {
1879 /* PLL cannot lock */
1880 cpc->pllmr &= ~0x80000000;
1883 PLL_out = VCO_out / D2;
1888 PLL_out = cpc->sysclk * M;
1891 if (cpc->cr1 & 0x00800000)
1892 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1895 PLB_clk = CPU_clk / D0;
1896 SDRAM_clk = PLB_clk;
1897 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1898 OPB_clk = PLB_clk / D0;
1899 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1900 EXT_clk = PLB_clk / D0;
1901 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1902 UART_clk = CPU_clk / D0;
1903 /* Setup CPU clocks */
1904 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1905 /* Setup time-base clock */
1906 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1907 /* Setup PLB clock */
1908 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1909 /* Setup SDRAM clock */
1910 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1911 /* Setup OPB clock */
1912 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1913 /* Setup external clock */
1914 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1915 /* Setup UART clock */
1916 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1919 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1921 ppc405cr_cpc_t *cpc;
1926 case PPC405CR_CPC0_PLLMR:
1929 case PPC405CR_CPC0_CR0:
1932 case PPC405CR_CPC0_CR1:
1935 case PPC405CR_CPC0_PSR:
1938 case PPC405CR_CPC0_JTAGID:
1941 case PPC405CR_CPC0_ER:
1944 case PPC405CR_CPC0_FR:
1947 case PPC405CR_CPC0_SR:
1948 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1951 /* Avoid gcc warning */
1959 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1961 ppc405cr_cpc_t *cpc;
1965 case PPC405CR_CPC0_PLLMR:
1966 cpc->pllmr = val & 0xFFF77C3F;
1968 case PPC405CR_CPC0_CR0:
1969 cpc->cr0 = val & 0x0FFFFFFE;
1971 case PPC405CR_CPC0_CR1:
1972 cpc->cr1 = val & 0x00800000;
1974 case PPC405CR_CPC0_PSR:
1977 case PPC405CR_CPC0_JTAGID:
1980 case PPC405CR_CPC0_ER:
1981 cpc->er = val & 0xBFFC0000;
1983 case PPC405CR_CPC0_FR:
1984 cpc->fr = val & 0xBFFC0000;
1986 case PPC405CR_CPC0_SR:
1992 static void ppc405cr_cpc_reset (void *opaque)
1994 ppc405cr_cpc_t *cpc;
1998 /* Compute PLLMR value from PSR settings */
1999 cpc->pllmr = 0x80000000;
2001 switch ((cpc->psr >> 30) & 3) {
2004 cpc->pllmr &= ~0x80000000;
2008 cpc->pllmr |= 5 << 16;
2012 cpc->pllmr |= 4 << 16;
2016 cpc->pllmr |= 2 << 16;
2020 D = (cpc->psr >> 28) & 3;
2021 cpc->pllmr |= (D + 1) << 20;
2023 D = (cpc->psr >> 25) & 7;
2038 D = (cpc->psr >> 23) & 3;
2039 cpc->pllmr |= D << 26;
2041 D = (cpc->psr >> 21) & 3;
2042 cpc->pllmr |= D << 10;
2044 D = (cpc->psr >> 17) & 3;
2045 cpc->pllmr |= D << 24;
2046 cpc->cr0 = 0x0000003C;
2047 cpc->cr1 = 0x2B0D8800;
2048 cpc->er = 0x00000000;
2049 cpc->fr = 0x00000000;
2050 ppc405cr_clk_setup(cpc);
2053 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2057 /* XXX: this should be read from IO pins */
2058 cpc->psr = 0x00000000; /* 8 bits ROM */
2060 D = 0x2; /* Divide by 4 */
2061 cpc->psr |= D << 30;
2063 D = 0x1; /* Divide by 2 */
2064 cpc->psr |= D << 28;
2066 D = 0x1; /* Divide by 2 */
2067 cpc->psr |= D << 23;
2069 D = 0x5; /* M = 16 */
2070 cpc->psr |= D << 25;
2072 D = 0x1; /* Divide by 2 */
2073 cpc->psr |= D << 21;
2075 D = 0x2; /* Divide by 4 */
2076 cpc->psr |= D << 17;
2079 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
2082 ppc405cr_cpc_t *cpc;
2084 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2085 memcpy(cpc->clk_setup, clk_setup,
2086 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2087 cpc->sysclk = sysclk;
2088 cpc->jtagid = 0x42051049;
2089 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2090 &dcr_read_crcpc, &dcr_write_crcpc);
2091 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2092 &dcr_read_crcpc, &dcr_write_crcpc);
2093 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2094 &dcr_read_crcpc, &dcr_write_crcpc);
2095 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2096 &dcr_read_crcpc, &dcr_write_crcpc);
2097 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2098 &dcr_read_crcpc, &dcr_write_crcpc);
2099 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2100 &dcr_read_crcpc, &dcr_write_crcpc);
2101 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2102 &dcr_read_crcpc, &dcr_write_crcpc);
2103 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2104 &dcr_read_crcpc, &dcr_write_crcpc);
2105 ppc405cr_clk_init(cpc);
2106 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2109 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
2110 MemoryRegion ram_memories[4],
2111 hwaddr ram_bases[4],
2112 hwaddr ram_sizes[4],
2113 uint32_t sysclk, qemu_irq **picp,
2116 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2117 qemu_irq dma_irqs[4];
2120 qemu_irq *pic, *irqs;
2122 memset(clk_setup, 0, sizeof(clk_setup));
2123 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2124 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2126 /* Memory mapped devices registers */
2128 ppc4xx_plb_init(env);
2129 /* PLB to OPB bridge */
2130 ppc4xx_pob_init(env);
2132 ppc4xx_opba_init(0xef600600);
2133 /* Universal interrupt controller */
2134 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2135 irqs[PPCUIC_OUTPUT_INT] =
2136 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2137 irqs[PPCUIC_OUTPUT_CINT] =
2138 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2139 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2141 /* SDRAM controller */
2142 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2143 ram_bases, ram_sizes, do_init);
2144 /* External bus controller */
2145 ppc405_ebc_init(env);
2146 /* DMA controller */
2147 dma_irqs[0] = pic[26];
2148 dma_irqs[1] = pic[25];
2149 dma_irqs[2] = pic[24];
2150 dma_irqs[3] = pic[23];
2151 ppc405_dma_init(env, dma_irqs);
2153 if (serial_hds[0] != NULL) {
2154 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2155 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2158 if (serial_hds[1] != NULL) {
2159 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2160 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2163 /* IIC controller */
2164 ppc405_i2c_init(0xef600500, pic[2]);
2166 ppc405_gpio_init(0xef600700);
2168 ppc405cr_cpc_init(env, clk_setup, sysclk);
2173 /*****************************************************************************/
2177 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2178 PPC405EP_CPC0_BOOT = 0x0F1,
2179 PPC405EP_CPC0_EPCTL = 0x0F3,
2180 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2181 PPC405EP_CPC0_UCR = 0x0F5,
2182 PPC405EP_CPC0_SRR = 0x0F6,
2183 PPC405EP_CPC0_JTAGID = 0x0F7,
2184 PPC405EP_CPC0_PCI = 0x0F9,
2186 PPC405EP_CPC0_ER = xxx,
2187 PPC405EP_CPC0_FR = xxx,
2188 PPC405EP_CPC0_SR = xxx,
2193 PPC405EP_CPU_CLK = 0,
2194 PPC405EP_PLB_CLK = 1,
2195 PPC405EP_OPB_CLK = 2,
2196 PPC405EP_EBC_CLK = 3,
2197 PPC405EP_MAL_CLK = 4,
2198 PPC405EP_PCI_CLK = 5,
2199 PPC405EP_UART0_CLK = 6,
2200 PPC405EP_UART1_CLK = 7,
2201 PPC405EP_CLK_NB = 8,
2204 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2205 struct ppc405ep_cpc_t {
2207 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2215 /* Clock and power management */
2221 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2223 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2224 uint32_t UART0_clk, UART1_clk;
2225 uint64_t VCO_out, PLL_out;
2229 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2230 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2231 #ifdef DEBUG_CLOCKS_LL
2232 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2234 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2235 #ifdef DEBUG_CLOCKS_LL
2236 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2238 VCO_out = cpc->sysclk * M * D;
2239 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2240 /* Error - unlock the PLL */
2241 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2243 cpc->pllmr[1] &= ~0x80000000;
2247 PLL_out = VCO_out / D;
2248 /* Pretend the PLL is locked */
2249 cpc->boot |= 0x00000001;
2254 PLL_out = cpc->sysclk;
2255 if (cpc->pllmr[1] & 0x40000000) {
2256 /* Pretend the PLL is not locked */
2257 cpc->boot &= ~0x00000001;
2260 /* Now, compute all other clocks */
2261 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2262 #ifdef DEBUG_CLOCKS_LL
2263 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2265 CPU_clk = PLL_out / D;
2266 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2267 #ifdef DEBUG_CLOCKS_LL
2268 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2270 PLB_clk = CPU_clk / D;
2271 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2272 #ifdef DEBUG_CLOCKS_LL
2273 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2275 OPB_clk = PLB_clk / D;
2276 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2277 #ifdef DEBUG_CLOCKS_LL
2278 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2280 EBC_clk = PLB_clk / D;
2281 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2282 #ifdef DEBUG_CLOCKS_LL
2283 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2285 MAL_clk = PLB_clk / D;
2286 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2287 #ifdef DEBUG_CLOCKS_LL
2288 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2290 PCI_clk = PLB_clk / D;
2291 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2292 #ifdef DEBUG_CLOCKS_LL
2293 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2295 UART0_clk = PLL_out / D;
2296 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2297 #ifdef DEBUG_CLOCKS_LL
2298 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2300 UART1_clk = PLL_out / D;
2302 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2303 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2304 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2305 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2306 " UART1 %" PRIu32 "\n",
2307 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2308 UART0_clk, UART1_clk);
2310 /* Setup CPU clocks */
2311 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2312 /* Setup PLB clock */
2313 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2314 /* Setup OPB clock */
2315 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2316 /* Setup external clock */
2317 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2318 /* Setup MAL clock */
2319 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2320 /* Setup PCI clock */
2321 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2322 /* Setup UART0 clock */
2323 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2324 /* Setup UART1 clock */
2325 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2328 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2330 ppc405ep_cpc_t *cpc;
2335 case PPC405EP_CPC0_BOOT:
2338 case PPC405EP_CPC0_EPCTL:
2341 case PPC405EP_CPC0_PLLMR0:
2342 ret = cpc->pllmr[0];
2344 case PPC405EP_CPC0_PLLMR1:
2345 ret = cpc->pllmr[1];
2347 case PPC405EP_CPC0_UCR:
2350 case PPC405EP_CPC0_SRR:
2353 case PPC405EP_CPC0_JTAGID:
2356 case PPC405EP_CPC0_PCI:
2360 /* Avoid gcc warning */
2368 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2370 ppc405ep_cpc_t *cpc;
2374 case PPC405EP_CPC0_BOOT:
2375 /* Read-only register */
2377 case PPC405EP_CPC0_EPCTL:
2378 /* Don't care for now */
2379 cpc->epctl = val & 0xC00000F3;
2381 case PPC405EP_CPC0_PLLMR0:
2382 cpc->pllmr[0] = val & 0x00633333;
2383 ppc405ep_compute_clocks(cpc);
2385 case PPC405EP_CPC0_PLLMR1:
2386 cpc->pllmr[1] = val & 0xC0F73FFF;
2387 ppc405ep_compute_clocks(cpc);
2389 case PPC405EP_CPC0_UCR:
2390 /* UART control - don't care for now */
2391 cpc->ucr = val & 0x003F7F7F;
2393 case PPC405EP_CPC0_SRR:
2396 case PPC405EP_CPC0_JTAGID:
2399 case PPC405EP_CPC0_PCI:
2405 static void ppc405ep_cpc_reset (void *opaque)
2407 ppc405ep_cpc_t *cpc = opaque;
2409 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2410 cpc->epctl = 0x00000000;
2411 cpc->pllmr[0] = 0x00011010;
2412 cpc->pllmr[1] = 0x40000000;
2413 cpc->ucr = 0x00000000;
2414 cpc->srr = 0x00040000;
2415 cpc->pci = 0x00000000;
2416 cpc->er = 0x00000000;
2417 cpc->fr = 0x00000000;
2418 cpc->sr = 0x00000000;
2419 ppc405ep_compute_clocks(cpc);
2422 /* XXX: sysclk should be between 25 and 100 MHz */
2423 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
2426 ppc405ep_cpc_t *cpc;
2428 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2429 memcpy(cpc->clk_setup, clk_setup,
2430 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2431 cpc->jtagid = 0x20267049;
2432 cpc->sysclk = sysclk;
2433 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2434 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2435 &dcr_read_epcpc, &dcr_write_epcpc);
2436 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2437 &dcr_read_epcpc, &dcr_write_epcpc);
2438 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2439 &dcr_read_epcpc, &dcr_write_epcpc);
2440 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2441 &dcr_read_epcpc, &dcr_write_epcpc);
2442 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2443 &dcr_read_epcpc, &dcr_write_epcpc);
2444 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2445 &dcr_read_epcpc, &dcr_write_epcpc);
2446 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2447 &dcr_read_epcpc, &dcr_write_epcpc);
2448 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2449 &dcr_read_epcpc, &dcr_write_epcpc);
2451 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2452 &dcr_read_epcpc, &dcr_write_epcpc);
2453 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2454 &dcr_read_epcpc, &dcr_write_epcpc);
2455 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2456 &dcr_read_epcpc, &dcr_write_epcpc);
2460 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
2461 MemoryRegion ram_memories[2],
2462 hwaddr ram_bases[2],
2463 hwaddr ram_sizes[2],
2464 uint32_t sysclk, qemu_irq **picp,
2467 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2468 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2471 qemu_irq *pic, *irqs;
2473 memset(clk_setup, 0, sizeof(clk_setup));
2475 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2476 &tlb_clk_setup, sysclk);
2478 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2479 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2480 /* Internal devices init */
2481 /* Memory mapped devices registers */
2483 ppc4xx_plb_init(env);
2484 /* PLB to OPB bridge */
2485 ppc4xx_pob_init(env);
2487 ppc4xx_opba_init(0xef600600);
2488 /* Initialize timers */
2489 ppc_booke_timers_init(cpu, sysclk, 0);
2490 /* Universal interrupt controller */
2491 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2492 irqs[PPCUIC_OUTPUT_INT] =
2493 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2494 irqs[PPCUIC_OUTPUT_CINT] =
2495 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2496 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2498 /* SDRAM controller */
2499 /* XXX 405EP has no ECC interrupt */
2500 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2501 ram_bases, ram_sizes, do_init);
2502 /* External bus controller */
2503 ppc405_ebc_init(env);
2504 /* DMA controller */
2505 dma_irqs[0] = pic[5];
2506 dma_irqs[1] = pic[6];
2507 dma_irqs[2] = pic[7];
2508 dma_irqs[3] = pic[8];
2509 ppc405_dma_init(env, dma_irqs);
2510 /* IIC controller */
2511 ppc405_i2c_init(0xef600500, pic[2]);
2513 ppc405_gpio_init(0xef600700);
2515 if (serial_hds[0] != NULL) {
2516 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2517 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2520 if (serial_hds[1] != NULL) {
2521 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2522 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2526 ppc405_ocm_init(env);
2528 gpt_irqs[0] = pic[19];
2529 gpt_irqs[1] = pic[20];
2530 gpt_irqs[2] = pic[21];
2531 gpt_irqs[3] = pic[22];
2532 gpt_irqs[4] = pic[23];
2533 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2535 /* Uses pic[3], pic[16], pic[18] */
2537 mal_irqs[0] = pic[11];
2538 mal_irqs[1] = pic[12];
2539 mal_irqs[2] = pic[13];
2540 mal_irqs[3] = pic[14];
2541 ppc405_mal_init(env, mal_irqs);
2543 /* Uses pic[9], pic[15], pic[17] */
2545 ppc405ep_cpc_init(env, clk_setup, sysclk);