hw/scsi/vmw_pvscsi.c

   1 /*
   2  * QEMU VMWARE PVSCSI paravirtual SCSI bus
   3  *
   4  * Copyright (c) 2012 Ravello Systems LTD (http://ravellosystems.com)
   5  *
   6  * Developed by Daynix Computing LTD (http://www.daynix.com)
   7  *
   8  * Based on implementation by Paolo Bonzini
   9  * http://lists.gnu.org/archive/html/qemu-devel/2011-08/msg00729.html
  10  *
  11  * Authors:
  12  * Paolo Bonzini <[email protected]>
  13  * Dmitry Fleytman <[email protected]>
  14  * Yan Vugenfirer <[email protected]>
  15  *
  16  * This work is licensed under the terms of the GNU GPL, version 2.
  17  * See the COPYING file in the top-level directory.
  18  *
  19  * NOTE about MSI-X:
  20  * MSI-X support has been removed for the moment because it leads Windows OS
  21  * to crash on startup. The crash happens because Windows driver requires
  22  * MSI-X shared memory to be part of the same BAR used for rings state
  23  * registers, etc. This is not supported by QEMU infrastructure so separate
  24  * BAR created from MSI-X purposes. Windows driver fails to deal with 2 BARs.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "hw/scsi/scsi.h"
  31 #include "block/scsi.h"
  32 #include "hw/pci/msi.h"
  33 #include "vmw_pvscsi.h"
  34 #include "trace.h"
  35
  36
  37 #define PVSCSI_USE_64BIT         (true)
  38 #define PVSCSI_PER_VECTOR_MASK   (false)
  39
  40 #define PVSCSI_MAX_DEVS                   (64)
  41 #define PVSCSI_MSIX_NUM_VECTORS           (1)
  42
  43 #define PVSCSI_MAX_SG_ELEM                2048
  44
  45 #define PVSCSI_MAX_CMD_DATA_WORDS \
  46     (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
  47
  48 #define RS_GET_FIELD(m, field) \
  49     (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
  50                  (m)->rs_pa + offsetof(struct PVSCSIRingsState, field)))
  51 #define RS_SET_FIELD(m, field, val) \
  52     (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
  53                  (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val))
  54
  55 typedef struct PVSCSIClass {
  56     PCIDeviceClass parent_class;
  57     DeviceRealize parent_dc_realize;
  58 } PVSCSIClass;
  59
  60 #define TYPE_PVSCSI "pvscsi"
  61 #define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
  62
  63 #define PVSCSI_DEVICE_CLASS(klass) \
  64     OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI)
  65 #define PVSCSI_DEVICE_GET_CLASS(obj) \
  66     OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI)
  67
  68 /* Compatibility flags for migration */
  69 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
  70 #define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
  71     (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
  72 #define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
  73 #define PVSCSI_COMPAT_DISABLE_PCIE \
  74     (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
  75
  76 #define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
  77     ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
  78 #define PVSCSI_MSI_OFFSET(s) \
  79     (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
  80 #define PVSCSI_EXP_EP_OFFSET (0x40)
  81
  82 typedef struct PVSCSIRingInfo {
  83     uint64_t            rs_pa;
  84     uint32_t            txr_len_mask;
  85     uint32_t            rxr_len_mask;
  86     uint32_t            msg_len_mask;
  87     uint64_t            req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
  88     uint64_t            cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
  89     uint64_t            msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
  90     uint64_t            consumed_ptr;
  91     uint64_t            filled_cmp_ptr;
  92     uint64_t            filled_msg_ptr;
  93 } PVSCSIRingInfo;
  94
  95 typedef struct PVSCSISGState {
  96     hwaddr elemAddr;
  97     hwaddr dataAddr;
  98     uint32_t resid;
  99 } PVSCSISGState;
 100
 101 typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
 102
 103 typedef struct {
 104     PCIDevice parent_obj;
 105     MemoryRegion io_space;
 106     SCSIBus bus;
 107     QEMUBH *completion_worker;
 108     PVSCSIRequestList pending_queue;
 109     PVSCSIRequestList completion_queue;
 110
 111     uint64_t reg_interrupt_status;        /* Interrupt status register value */
 112     uint64_t reg_interrupt_enabled;       /* Interrupt mask register value   */
 113     uint64_t reg_command_status;          /* Command status register value   */
 114
 115     /* Command data adoption mechanism */
 116     uint64_t curr_cmd;                   /* Last command arrived             */
 117     uint32_t curr_cmd_data_cntr;         /* Amount of data for last command  */
 118
 119     /* Collector for current command data */
 120     uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
 121
 122     uint8_t rings_info_valid;            /* Whether data rings initialized   */
 123     uint8_t msg_ring_info_valid;         /* Whether message ring initialized */
 124     uint8_t use_msg;                     /* Whether to use message ring      */
 125
 126     uint8_t msi_used;                    /* For migration compatibility      */
 127     PVSCSIRingInfo rings;                /* Data transfer rings manager      */
 128     uint32_t resetting;                  /* Reset in progress                */
 129
 130     uint32_t compat_flags;
 131 } PVSCSIState;
 132
 133 typedef struct PVSCSIRequest {
 134     SCSIRequest *sreq;
 135     PVSCSIState *dev;
 136     uint8_t sense_key;
 137     uint8_t completed;
 138     int lun;
 139     QEMUSGList sgl;
 140     PVSCSISGState sg;
 141     struct PVSCSIRingReqDesc req;
 142     struct PVSCSIRingCmpDesc cmp;
 143     QTAILQ_ENTRY(PVSCSIRequest) next;
 144 } PVSCSIRequest;
 145
 146 /* Integer binary logarithm */
 147 static int
 148 pvscsi_log2(uint32_t input)
 149 {
 150     int log = 0;
 151     assert(input > 0);
 152     while (input >> ++log) {
 153     }
 154     return log;
 155 }
 156
 157 static void
 158 pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
 159 {
 160     int i;
 161     uint32_t txr_len_log2, rxr_len_log2;
 162     uint32_t req_ring_size, cmp_ring_size;
 163     m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
 164
 165     req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 166     cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 167     txr_len_log2 = pvscsi_log2(req_ring_size - 1);
 168     rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
 169
 170     m->txr_len_mask = MASK(txr_len_log2);
 171     m->rxr_len_mask = MASK(rxr_len_log2);
 172
 173     m->consumed_ptr = 0;
 174     m->filled_cmp_ptr = 0;
 175
 176     for (i = 0; i < ri->reqRingNumPages; i++) {
 177         m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
 178     }
 179
 180     for (i = 0; i < ri->cmpRingNumPages; i++) {
 181         m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
 182     }
 183
 184     RS_SET_FIELD(m, reqProdIdx, 0);
 185     RS_SET_FIELD(m, reqConsIdx, 0);
 186     RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
 187
 188     RS_SET_FIELD(m, cmpProdIdx, 0);
 189     RS_SET_FIELD(m, cmpConsIdx, 0);
 190     RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
 191
 192     trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
 193
 194     /* Flush ring state page changes */
 195     smp_wmb();
 196 }
 197
 198 static int
 199 pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
 200 {
 201     int i;
 202     uint32_t len_log2;
 203     uint32_t ring_size;
 204
 205     if (ri->numPages > PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES) {
 206         return -1;
 207     }
 208     ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 209     len_log2 = pvscsi_log2(ring_size - 1);
 210
 211     m->msg_len_mask = MASK(len_log2);
 212
 213     m->filled_msg_ptr = 0;
 214
 215     for (i = 0; i < ri->numPages; i++) {
 216         m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
 217     }
 218
 219     RS_SET_FIELD(m, msgProdIdx, 0);
 220     RS_SET_FIELD(m, msgConsIdx, 0);
 221     RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
 222
 223     trace_pvscsi_ring_init_msg(len_log2);
 224
 225     /* Flush ring state page changes */
 226     smp_wmb();
 227
 228     return 0;
 229 }
 230
 231 static void
 232 pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
 233 {
 234     mgr->rs_pa = 0;
 235     mgr->txr_len_mask = 0;
 236     mgr->rxr_len_mask = 0;
 237     mgr->msg_len_mask = 0;
 238     mgr->consumed_ptr = 0;
 239     mgr->filled_cmp_ptr = 0;
 240     mgr->filled_msg_ptr = 0;
 241     memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
 242     memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
 243     memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
 244 }
 245
 246 static hwaddr
 247 pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
 248 {
 249     uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx);
 250
 251     if (ready_ptr != mgr->consumed_ptr) {
 252         uint32_t next_ready_ptr =
 253             mgr->consumed_ptr++ & mgr->txr_len_mask;
 254         uint32_t next_ready_page =
 255             next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 256         uint32_t inpage_idx =
 257             next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
 258
 259         return mgr->req_ring_pages_pa[next_ready_page] +
 260                inpage_idx * sizeof(PVSCSIRingReqDesc);
 261     } else {
 262         return 0;
 263     }
 264 }
 265
 266 static void
 267 pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
 268 {
 269     RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
 270 }
 271
 272 static hwaddr
 273 pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
 274 {
 275     /*
 276      * According to Linux driver code it explicitly verifies that number
 277      * of requests being processed by device is less then the size of
 278      * completion queue, so device may omit completion queue overflow
 279      * conditions check. We assume that this is true for other (Windows)
 280      * drivers as well.
 281      */
 282
 283     uint32_t free_cmp_ptr =
 284         mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
 285     uint32_t free_cmp_page =
 286         free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 287     uint32_t inpage_idx =
 288         free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
 289     return mgr->cmp_ring_pages_pa[free_cmp_page] +
 290            inpage_idx * sizeof(PVSCSIRingCmpDesc);
 291 }
 292
 293 static hwaddr
 294 pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
 295 {
 296     uint32_t free_msg_ptr =
 297         mgr->filled_msg_ptr++ & mgr->msg_len_mask;
 298     uint32_t free_msg_page =
 299         free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 300     uint32_t inpage_idx =
 301         free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
 302     return mgr->msg_ring_pages_pa[free_msg_page] +
 303            inpage_idx * sizeof(PVSCSIRingMsgDesc);
 304 }
 305
 306 static void
 307 pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
 308 {
 309     /* Flush descriptor changes */
 310     smp_wmb();
 311
 312     trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
 313
 314     RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
 315 }
 316
 317 static bool
 318 pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
 319 {
 320     uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx);
 321     uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx);
 322
 323     return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
 324 }
 325
 326 static void
 327 pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
 328 {
 329     /* Flush descriptor changes */
 330     smp_wmb();
 331
 332     trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
 333
 334     RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
 335 }
 336
 337 static void
 338 pvscsi_reset_state(PVSCSIState *s)
 339 {
 340     s->curr_cmd = PVSCSI_CMD_FIRST;
 341     s->curr_cmd_data_cntr = 0;
 342     s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 343     s->reg_interrupt_status = 0;
 344     pvscsi_ring_cleanup(&s->rings);
 345     s->rings_info_valid = FALSE;
 346     s->msg_ring_info_valid = FALSE;
 347     QTAILQ_INIT(&s->pending_queue);
 348     QTAILQ_INIT(&s->completion_queue);
 349 }
 350
 351 static void
 352 pvscsi_update_irq_status(PVSCSIState *s)
 353 {
 354     PCIDevice *d = PCI_DEVICE(s);
 355     bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
 356
 357     trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
 358                                   s->reg_interrupt_status);
 359
 360     if (msi_enabled(d)) {
 361         if (should_raise) {
 362             trace_pvscsi_update_irq_msi();
 363             msi_notify(d, PVSCSI_VECTOR_COMPLETION);
 364         }
 365         return;
 366     }
 367
 368     pci_set_irq(d, !!should_raise);
 369 }
 370
 371 static void
 372 pvscsi_raise_completion_interrupt(PVSCSIState *s)
 373 {
 374     s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
 375
 376     /* Memory barrier to flush interrupt status register changes*/
 377     smp_wmb();
 378
 379     pvscsi_update_irq_status(s);
 380 }
 381
 382 static void
 383 pvscsi_raise_message_interrupt(PVSCSIState *s)
 384 {
 385     s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
 386
 387     /* Memory barrier to flush interrupt status register changes*/
 388     smp_wmb();
 389
 390     pvscsi_update_irq_status(s);
 391 }
 392
 393 static void
 394 pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
 395 {
 396     hwaddr cmp_descr_pa;
 397
 398     cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
 399     trace_pvscsi_cmp_ring_put(cmp_descr_pa);
 400     cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc,
 401                               sizeof(*cmp_desc));
 402 }
 403
 404 static void
 405 pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
 406 {
 407     hwaddr msg_descr_pa;
 408
 409     msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
 410     trace_pvscsi_msg_ring_put(msg_descr_pa);
 411     cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc,
 412                               sizeof(*msg_desc));
 413 }
 414
 415 static void
 416 pvscsi_process_completion_queue(void *opaque)
 417 {
 418     PVSCSIState *s = opaque;
 419     PVSCSIRequest *pvscsi_req;
 420     bool has_completed = false;
 421
 422     while (!QTAILQ_EMPTY(&s->completion_queue)) {
 423         pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
 424         QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
 425         pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
 426         g_free(pvscsi_req);
 427         has_completed = true;
 428     }
 429
 430     if (has_completed) {
 431         pvscsi_ring_flush_cmp(&s->rings);
 432         pvscsi_raise_completion_interrupt(s);
 433     }
 434 }
 435
 436 static void
 437 pvscsi_reset_adapter(PVSCSIState *s)
 438 {
 439     s->resetting++;
 440     qbus_reset_all_fn(&s->bus);
 441     s->resetting--;
 442     pvscsi_process_completion_queue(s);
 443     assert(QTAILQ_EMPTY(&s->pending_queue));
 444     pvscsi_reset_state(s);
 445 }
 446
 447 static void
 448 pvscsi_schedule_completion_processing(PVSCSIState *s)
 449 {
 450     /* Try putting more complete requests on the ring. */
 451     if (!QTAILQ_EMPTY(&s->completion_queue)) {
 452         qemu_bh_schedule(s->completion_worker);
 453     }
 454 }
 455
 456 static void
 457 pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
 458 {
 459     assert(!r->completed);
 460
 461     trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
 462                                   r->sense_key);
 463     if (r->sreq != NULL) {
 464         scsi_req_unref(r->sreq);
 465         r->sreq = NULL;
 466     }
 467     r->completed = 1;
 468     QTAILQ_REMOVE(&s->pending_queue, r, next);
 469     QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
 470     pvscsi_schedule_completion_processing(s);
 471 }
 472
 473 static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
 474 {
 475     PVSCSIRequest *req = r->hba_private;
 476
 477     trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
 478
 479     return &req->sgl;
 480 }
 481
 482 static void
 483 pvscsi_get_next_sg_elem(PVSCSISGState *sg)
 484 {
 485     struct PVSCSISGElement elem;
 486
 487     cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem));
 488     if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
 489         /*
 490             * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in
 491             * header file but its value is unknown. This flag requires
 492             * additional processing, so we put warning here to catch it
 493             * some day and make proper implementation
 494             */
 495         trace_pvscsi_get_next_sg_elem(elem.flags);
 496     }
 497
 498     sg->elemAddr += sizeof(elem);
 499     sg->dataAddr = elem.addr;
 500     sg->resid = elem.length;
 501 }
 502
 503 static void
 504 pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
 505 {
 506     r->cmp.senseLen = MIN(r->req.senseLen, len);
 507     r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
 508     cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
 509 }
 510
 511 static void
 512 pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
 513 {
 514     PVSCSIRequest *pvscsi_req = req->hba_private;
 515     PVSCSIState *s;
 516
 517     if (!pvscsi_req) {
 518         trace_pvscsi_command_complete_not_found(req->tag);
 519         return;
 520     }
 521     s = pvscsi_req->dev;
 522
 523     if (resid) {
 524         /* Short transfer.  */
 525         trace_pvscsi_command_complete_data_run();
 526         pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
 527     }
 528
 529     pvscsi_req->cmp.scsiStatus = status;
 530     if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
 531         uint8_t sense[SCSI_SENSE_BUF_SIZE];
 532         int sense_len =
 533             scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
 534
 535         trace_pvscsi_command_complete_sense_len(sense_len);
 536         pvscsi_write_sense(pvscsi_req, sense, sense_len);
 537     }
 538     qemu_sglist_destroy(&pvscsi_req->sgl);
 539     pvscsi_complete_request(s, pvscsi_req);
 540 }
 541
 542 static void
 543 pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
 544 {
 545     if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
 546         PVSCSIMsgDescDevStatusChanged msg = {0};
 547
 548         msg.type = msg_type;
 549         msg.bus = dev->channel;
 550         msg.target = dev->id;
 551         msg.lun[1] = dev->lun;
 552
 553         pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
 554         pvscsi_ring_flush_msg(&s->rings);
 555         pvscsi_raise_message_interrupt(s);
 556     }
 557 }
 558
 559 static void
 560 pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
 561 {
 562     PVSCSIState *s = PVSCSI(hotplug_dev);
 563
 564     pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
 565 }
 566
 567 static void
 568 pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
 569 {
 570     PVSCSIState *s = PVSCSI(hotplug_dev);
 571
 572     pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
 573     qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
 574 }
 575
 576 static void
 577 pvscsi_request_cancelled(SCSIRequest *req)
 578 {
 579     PVSCSIRequest *pvscsi_req = req->hba_private;
 580     PVSCSIState *s = pvscsi_req->dev;
 581
 582     if (pvscsi_req->completed) {
 583         return;
 584     }
 585
 586    if (pvscsi_req->dev->resetting) {
 587        pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
 588     } else {
 589        pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
 590     }
 591
 592     pvscsi_complete_request(s, pvscsi_req);
 593 }
 594
 595 static SCSIDevice*
 596 pvscsi_device_find(PVSCSIState *s, int channel, int target,
 597                    uint8_t *requested_lun, uint8_t *target_lun)
 598 {
 599     if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
 600         requested_lun[4] || requested_lun[5] || requested_lun[6] ||
 601         requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
 602         return NULL;
 603     } else {
 604         *target_lun = requested_lun[1];
 605         return scsi_device_find(&s->bus, channel, target, *target_lun);
 606     }
 607 }
 608
 609 static PVSCSIRequest *
 610 pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
 611                                 struct PVSCSIRingReqDesc *descr)
 612 {
 613     PVSCSIRequest *pvscsi_req;
 614     uint8_t lun;
 615
 616     pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
 617     pvscsi_req->dev = s;
 618     pvscsi_req->req = *descr;
 619     pvscsi_req->cmp.context = pvscsi_req->req.context;
 620     QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
 621
 622     *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
 623     if (*d) {
 624         pvscsi_req->lun = lun;
 625     }
 626
 627     return pvscsi_req;
 628 }
 629
 630 static void
 631 pvscsi_convert_sglist(PVSCSIRequest *r)
 632 {
 633     uint32_t chunk_size, elmcnt = 0;
 634     uint64_t data_length = r->req.dataLen;
 635     PVSCSISGState sg = r->sg;
 636     while (data_length && elmcnt < PVSCSI_MAX_SG_ELEM) {
 637         while (!sg.resid && elmcnt++ < PVSCSI_MAX_SG_ELEM) {
 638             pvscsi_get_next_sg_elem(&sg);
 639             trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
 640                                         r->sg.resid);
 641         }
 642         chunk_size = MIN(data_length, sg.resid);
 643         if (chunk_size) {
 644             qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
 645         }
 646
 647         sg.dataAddr += chunk_size;
 648         data_length -= chunk_size;
 649         sg.resid -= chunk_size;
 650     }
 651 }
 652
 653 static void
 654 pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
 655 {
 656     PCIDevice *d = PCI_DEVICE(s);
 657
 658     pci_dma_sglist_init(&r->sgl, d, 1);
 659     if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
 660         pvscsi_convert_sglist(r);
 661     } else {
 662         qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
 663     }
 664 }
 665
 666 static void
 667 pvscsi_process_request_descriptor(PVSCSIState *s,
 668                                   struct PVSCSIRingReqDesc *descr)
 669 {
 670     SCSIDevice *d;
 671     PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
 672     int64_t n;
 673
 674     trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
 675
 676     if (!d) {
 677         r->cmp.hostStatus = BTSTAT_SELTIMEO;
 678         trace_pvscsi_process_req_descr_unknown_device();
 679         pvscsi_complete_request(s, r);
 680         return;
 681     }
 682
 683     if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
 684         r->sg.elemAddr = descr->dataAddr;
 685     }
 686
 687     r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r);
 688     if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
 689         (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
 690         r->cmp.hostStatus = BTSTAT_BADMSG;
 691         trace_pvscsi_process_req_descr_invalid_dir();
 692         scsi_req_cancel(r->sreq);
 693         return;
 694     }
 695     if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
 696         (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
 697         r->cmp.hostStatus = BTSTAT_BADMSG;
 698         trace_pvscsi_process_req_descr_invalid_dir();
 699         scsi_req_cancel(r->sreq);
 700         return;
 701     }
 702
 703     pvscsi_build_sglist(s, r);
 704     n = scsi_req_enqueue(r->sreq);
 705
 706     if (n) {
 707         scsi_req_continue(r->sreq);
 708     }
 709 }
 710
 711 static void
 712 pvscsi_process_io(PVSCSIState *s)
 713 {
 714     PVSCSIRingReqDesc descr;
 715     hwaddr next_descr_pa;
 716
 717     assert(s->rings_info_valid);
 718     while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
 719
 720         /* Only read after production index verification */
 721         smp_rmb();
 722
 723         trace_pvscsi_process_io(next_descr_pa);
 724         cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr));
 725         pvscsi_process_request_descriptor(s, &descr);
 726     }
 727
 728     pvscsi_ring_flush_req(&s->rings);
 729 }
 730
 731 static void
 732 pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
 733 {
 734     int i;
 735     trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
 736
 737     trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
 738     for (i = 0; i < rc->reqRingNumPages; i++) {
 739         trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
 740     }
 741
 742     trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
 743     for (i = 0; i < rc->cmpRingNumPages; i++) {
 744         trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->cmpRingPPNs[i]);
 745     }
 746 }
 747
 748 static uint64_t
 749 pvscsi_on_cmd_config(PVSCSIState *s)
 750 {
 751     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
 752     return PVSCSI_COMMAND_PROCESSING_FAILED;
 753 }
 754
 755 static uint64_t
 756 pvscsi_on_cmd_unplug(PVSCSIState *s)
 757 {
 758     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
 759     return PVSCSI_COMMAND_PROCESSING_FAILED;
 760 }
 761
 762 static uint64_t
 763 pvscsi_on_issue_scsi(PVSCSIState *s)
 764 {
 765     trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
 766     return PVSCSI_COMMAND_PROCESSING_FAILED;
 767 }
 768
 769 static uint64_t
 770 pvscsi_on_cmd_setup_rings(PVSCSIState *s)
 771 {
 772     PVSCSICmdDescSetupRings *rc =
 773         (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
 774
 775     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
 776
 777     if (!rc->reqRingNumPages
 778         || rc->reqRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES
 779         || !rc->cmpRingNumPages
 780         || rc->cmpRingNumPages > PVSCSI_SETUP_RINGS_MAX_NUM_PAGES) {
 781         return PVSCSI_COMMAND_PROCESSING_FAILED;
 782     }
 783
 784     pvscsi_dbg_dump_tx_rings_config(rc);
 785     pvscsi_ring_init_data(&s->rings, rc);
 786
 787     s->rings_info_valid = TRUE;
 788     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 789 }
 790
 791 static uint64_t
 792 pvscsi_on_cmd_abort(PVSCSIState *s)
 793 {
 794     PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
 795     PVSCSIRequest *r, *next;
 796
 797     trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
 798
 799     QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
 800         if (r->req.context == cmd->context) {
 801             break;
 802         }
 803     }
 804     if (r) {
 805         assert(!r->completed);
 806         r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
 807         scsi_req_cancel(r->sreq);
 808     }
 809
 810     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 811 }
 812
 813 static uint64_t
 814 pvscsi_on_cmd_unknown(PVSCSIState *s)
 815 {
 816     trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
 817     return PVSCSI_COMMAND_PROCESSING_FAILED;
 818 }
 819
 820 static uint64_t
 821 pvscsi_on_cmd_reset_device(PVSCSIState *s)
 822 {
 823     uint8_t target_lun = 0;
 824     struct PVSCSICmdDescResetDevice *cmd =
 825         (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
 826     SCSIDevice *sdev;
 827
 828     sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
 829
 830     trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
 831
 832     if (sdev != NULL) {
 833         s->resetting++;
 834         device_reset(&sdev->qdev);
 835         s->resetting--;
 836         return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 837     }
 838
 839     return PVSCSI_COMMAND_PROCESSING_FAILED;
 840 }
 841
 842 static uint64_t
 843 pvscsi_on_cmd_reset_bus(PVSCSIState *s)
 844 {
 845     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
 846
 847     s->resetting++;
 848     qbus_reset_all_fn(&s->bus);
 849     s->resetting--;
 850     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 851 }
 852
 853 static uint64_t
 854 pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
 855 {
 856     PVSCSICmdDescSetupMsgRing *rc =
 857         (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
 858
 859     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
 860
 861     if (!s->use_msg) {
 862         return PVSCSI_COMMAND_PROCESSING_FAILED;
 863     }
 864
 865     if (s->rings_info_valid) {
 866         if (pvscsi_ring_init_msg(&s->rings, rc) < 0) {
 867             return PVSCSI_COMMAND_PROCESSING_FAILED;
 868         }
 869         s->msg_ring_info_valid = TRUE;
 870     }
 871     return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
 872 }
 873
 874 static uint64_t
 875 pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
 876 {
 877     trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
 878
 879     pvscsi_reset_adapter(s);
 880     return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
 881 }
 882
 883 static const struct {
 884     int       data_size;
 885     uint64_t  (*handler_fn)(PVSCSIState *s);
 886 } pvscsi_commands[] = {
 887     [PVSCSI_CMD_FIRST] = {
 888         .data_size = 0,
 889         .handler_fn = pvscsi_on_cmd_unknown,
 890     },
 891
 892     /* Not implemented, data size defined based on what arrives on windows */
 893     [PVSCSI_CMD_CONFIG] = {
 894         .data_size = 6 * sizeof(uint32_t),
 895         .handler_fn = pvscsi_on_cmd_config,
 896     },
 897
 898     /* Command not implemented, data size is unknown */
 899     [PVSCSI_CMD_ISSUE_SCSI] = {
 900         .data_size = 0,
 901         .handler_fn = pvscsi_on_issue_scsi,
 902     },
 903
 904     /* Command not implemented, data size is unknown */
 905     [PVSCSI_CMD_DEVICE_UNPLUG] = {
 906         .data_size = 0,
 907         .handler_fn = pvscsi_on_cmd_unplug,
 908     },
 909
 910     [PVSCSI_CMD_SETUP_RINGS] = {
 911         .data_size = sizeof(PVSCSICmdDescSetupRings),
 912         .handler_fn = pvscsi_on_cmd_setup_rings,
 913     },
 914
 915     [PVSCSI_CMD_RESET_DEVICE] = {
 916         .data_size = sizeof(struct PVSCSICmdDescResetDevice),
 917         .handler_fn = pvscsi_on_cmd_reset_device,
 918     },
 919
 920     [PVSCSI_CMD_RESET_BUS] = {
 921         .data_size = 0,
 922         .handler_fn = pvscsi_on_cmd_reset_bus,
 923     },
 924
 925     [PVSCSI_CMD_SETUP_MSG_RING] = {
 926         .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
 927         .handler_fn = pvscsi_on_cmd_setup_msg_ring,
 928     },
 929
 930     [PVSCSI_CMD_ADAPTER_RESET] = {
 931         .data_size = 0,
 932         .handler_fn = pvscsi_on_cmd_adapter_reset,
 933     },
 934
 935     [PVSCSI_CMD_ABORT_CMD] = {
 936         .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
 937         .handler_fn = pvscsi_on_cmd_abort,
 938     },
 939 };
 940
 941 static void
 942 pvscsi_do_command_processing(PVSCSIState *s)
 943 {
 944     size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
 945
 946     assert(s->curr_cmd < PVSCSI_CMD_LAST);
 947     if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
 948         s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
 949         s->curr_cmd = PVSCSI_CMD_FIRST;
 950         s->curr_cmd_data_cntr   = 0;
 951     }
 952 }
 953
 954 static void
 955 pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
 956 {
 957     size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
 958
 959     assert(bytes_arrived < sizeof(s->curr_cmd_data));
 960     s->curr_cmd_data[s->curr_cmd_data_cntr++] = value;
 961
 962     pvscsi_do_command_processing(s);
 963 }
 964
 965 static void
 966 pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
 967 {
 968     if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
 969         s->curr_cmd = cmd_id;
 970     } else {
 971         s->curr_cmd = PVSCSI_CMD_FIRST;
 972         trace_pvscsi_on_cmd_unknown(cmd_id);
 973     }
 974
 975     s->curr_cmd_data_cntr = 0;
 976     s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
 977
 978     pvscsi_do_command_processing(s);
 979 }
 980
 981 static void
 982 pvscsi_io_write(void *opaque, hwaddr addr,
 983                 uint64_t val, unsigned size)
 984 {
 985     PVSCSIState *s = opaque;
 986
 987     switch (addr) {
 988     case PVSCSI_REG_OFFSET_COMMAND:
 989         pvscsi_on_command(s, val);
 990         break;
 991
 992     case PVSCSI_REG_OFFSET_COMMAND_DATA:
 993         pvscsi_on_command_data(s, (uint32_t) val);
 994         break;
 995
 996     case PVSCSI_REG_OFFSET_INTR_STATUS:
 997         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
 998         s->reg_interrupt_status &= ~val;
 999         pvscsi_update_irq_status(s);
1000         pvscsi_schedule_completion_processing(s);
1001         break;
1002
1003     case PVSCSI_REG_OFFSET_INTR_MASK:
1004         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
1005         s->reg_interrupt_enabled = val;
1006         pvscsi_update_irq_status(s);
1007         break;
1008
1009     case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
1010         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
1011         pvscsi_process_io(s);
1012         break;
1013
1014     case PVSCSI_REG_OFFSET_KICK_RW_IO:
1015         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
1016         pvscsi_process_io(s);
1017         break;
1018
1019     case PVSCSI_REG_OFFSET_DEBUG:
1020         trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1021         break;
1022
1023     default:
1024         trace_pvscsi_io_write_unknown(addr, size, val);
1025         break;
1026     }
1027
1028 }
1029
1030 static uint64_t
1031 pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1032 {
1033     PVSCSIState *s = opaque;
1034
1035     switch (addr) {
1036     case PVSCSI_REG_OFFSET_INTR_STATUS:
1037         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1038                              s->reg_interrupt_status);
1039         return s->reg_interrupt_status;
1040
1041     case PVSCSI_REG_OFFSET_INTR_MASK:
1042         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1043                              s->reg_interrupt_status);
1044         return s->reg_interrupt_enabled;
1045
1046     case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1047         trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1048                              s->reg_interrupt_status);
1049         return s->reg_command_status;
1050
1051     default:
1052         trace_pvscsi_io_read_unknown(addr, size);
1053         return 0;
1054     }
1055 }
1056
1057
1058 static void
1059 pvscsi_init_msi(PVSCSIState *s)
1060 {
1061     int res;
1062     PCIDevice *d = PCI_DEVICE(s);
1063
1064     res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
1065                    PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK, NULL);
1066     if (res < 0) {
1067         trace_pvscsi_init_msi_fail(res);
1068         s->msi_used = false;
1069     } else {
1070         s->msi_used = true;
1071     }
1072 }
1073
1074 static void
1075 pvscsi_cleanup_msi(PVSCSIState *s)
1076 {
1077     PCIDevice *d = PCI_DEVICE(s);
1078
1079     msi_uninit(d);
1080 }
1081
1082 static const MemoryRegionOps pvscsi_ops = {
1083         .read = pvscsi_io_read,
1084         .write = pvscsi_io_write,
1085         .endianness = DEVICE_LITTLE_ENDIAN,
1086         .impl = {
1087                 .min_access_size = 4,
1088                 .max_access_size = 4,
1089         },
1090 };
1091
1092 static const struct SCSIBusInfo pvscsi_scsi_info = {
1093         .tcq = true,
1094         .max_target = PVSCSI_MAX_DEVS,
1095         .max_channel = 0,
1096         .max_lun = 0,
1097
1098         .get_sg_list = pvscsi_get_sg_list,
1099         .complete = pvscsi_command_complete,
1100         .cancel = pvscsi_request_cancelled,
1101 };
1102
1103 static int
1104 pvscsi_init(PCIDevice *pci_dev)
1105 {
1106     PVSCSIState *s = PVSCSI(pci_dev);
1107
1108     trace_pvscsi_state("init");
1109
1110     /* PCI subsystem ID, subsystem vendor ID, revision */
1111     if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
1112         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
1113     } else {
1114         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1115                      PCI_VENDOR_ID_VMWARE);
1116         pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1117                      PCI_DEVICE_ID_VMWARE_PVSCSI);
1118         pci_config_set_revision(pci_dev->config, 0x2);
1119     }
1120
1121     /* PCI latency timer = 255 */
1122     pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1123
1124     /* Interrupt pin A */
1125     pci_config_set_interrupt_pin(pci_dev->config, 1);
1126
1127     memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1128                           "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1129     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1130
1131     pvscsi_init_msi(s);
1132
1133     if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
1134         pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1135     }
1136
1137     s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
1138     if (!s->completion_worker) {
1139         pvscsi_cleanup_msi(s);
1140         return -ENOMEM;
1141     }
1142
1143     scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
1144                  &pvscsi_scsi_info, NULL);
1145     /* override default SCSI bus hotplug-handler, with pvscsi's one */
1146     qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(s), &error_abort);
1147     pvscsi_reset_state(s);
1148
1149     return 0;
1150 }
1151
1152 static void
1153 pvscsi_uninit(PCIDevice *pci_dev)
1154 {
1155     PVSCSIState *s = PVSCSI(pci_dev);
1156
1157     trace_pvscsi_state("uninit");
1158     qemu_bh_delete(s->completion_worker);
1159
1160     pvscsi_cleanup_msi(s);
1161 }
1162
1163 static void
1164 pvscsi_reset(DeviceState *dev)
1165 {
1166     PCIDevice *d = PCI_DEVICE(dev);
1167     PVSCSIState *s = PVSCSI(d);
1168
1169     trace_pvscsi_state("reset");
1170     pvscsi_reset_adapter(s);
1171 }
1172
1173 static void
1174 pvscsi_pre_save(void *opaque)
1175 {
1176     PVSCSIState *s = (PVSCSIState *) opaque;
1177
1178     trace_pvscsi_state("presave");
1179
1180     assert(QTAILQ_EMPTY(&s->pending_queue));
1181     assert(QTAILQ_EMPTY(&s->completion_queue));
1182 }
1183
1184 static int
1185 pvscsi_post_load(void *opaque, int version_id)
1186 {
1187     trace_pvscsi_state("postload");
1188     return 0;
1189 }
1190
1191 static bool pvscsi_vmstate_need_pcie_device(void *opaque)
1192 {
1193     PVSCSIState *s = PVSCSI(opaque);
1194
1195     return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
1196 }
1197
1198 static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
1199 {
1200     return !pvscsi_vmstate_need_pcie_device(opaque);
1201 }
1202
1203 static const VMStateDescription vmstate_pvscsi_pcie_device = {
1204     .name = "pvscsi/pcie",
1205     .needed = pvscsi_vmstate_need_pcie_device,
1206     .fields = (VMStateField[]) {
1207         VMSTATE_PCIE_DEVICE(parent_obj, PVSCSIState),
1208         VMSTATE_END_OF_LIST()
1209     }
1210 };
1211
1212 static const VMStateDescription vmstate_pvscsi = {
1213     .name = "pvscsi",
1214     .version_id = 0,
1215     .minimum_version_id = 0,
1216     .pre_save = pvscsi_pre_save,
1217     .post_load = pvscsi_post_load,
1218     .fields = (VMStateField[]) {
1219         VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
1220                             pvscsi_vmstate_test_pci_device, 0,
1221                             vmstate_pci_device, PCIDevice),
1222         VMSTATE_UINT8(msi_used, PVSCSIState),
1223         VMSTATE_UINT32(resetting, PVSCSIState),
1224         VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1225         VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1226         VMSTATE_UINT64(reg_command_status, PVSCSIState),
1227         VMSTATE_UINT64(curr_cmd, PVSCSIState),
1228         VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1229         VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1230                              ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1231         VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1232         VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1233         VMSTATE_UINT8(use_msg, PVSCSIState),
1234
1235         VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1236         VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1237         VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1238         VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1239                              PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1240         VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1241                              PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1242         VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1243         VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1244
1245         VMSTATE_END_OF_LIST()
1246     },
1247     .subsections = (const VMStateDescription*[]) {
1248         &vmstate_pvscsi_pcie_device,
1249         NULL
1250     }
1251 };
1252
1253 static Property pvscsi_properties[] = {
1254     DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1255     DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
1256                     PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
1257     DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
1258                     PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
1259     DEFINE_PROP_END_OF_LIST(),
1260 };
1261
1262 static void pvscsi_realize(DeviceState *qdev, Error **errp)
1263 {
1264     PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev);
1265     PCIDevice *pci_dev = PCI_DEVICE(qdev);
1266     PVSCSIState *s = PVSCSI(qdev);
1267
1268     if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
1269         pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1270     }
1271
1272     pvs_c->parent_dc_realize(qdev, errp);
1273 }
1274
1275 static void pvscsi_class_init(ObjectClass *klass, void *data)
1276 {
1277     DeviceClass *dc = DEVICE_CLASS(klass);
1278     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1279     PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass);
1280     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1281
1282     k->init = pvscsi_init;
1283     k->exit = pvscsi_uninit;
1284     k->vendor_id = PCI_VENDOR_ID_VMWARE;
1285     k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1286     k->class_id = PCI_CLASS_STORAGE_SCSI;
1287     k->subsystem_id = 0x1000;
1288     pvs_k->parent_dc_realize = dc->realize;
1289     dc->realize = pvscsi_realize;
1290     dc->reset = pvscsi_reset;
1291     dc->vmsd = &vmstate_pvscsi;
1292     dc->props = pvscsi_properties;
1293     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1294     hc->unplug = pvscsi_hot_unplug;
1295     hc->plug = pvscsi_hotplug;
1296 }
1297
1298 static const TypeInfo pvscsi_info = {
1299     .name          = TYPE_PVSCSI,
1300     .parent        = TYPE_PCI_DEVICE,
1301     .class_size    = sizeof(PVSCSIClass),
1302     .instance_size = sizeof(PVSCSIState),
1303     .class_init    = pvscsi_class_init,
1304     .interfaces = (InterfaceInfo[]) {
1305         { TYPE_HOTPLUG_HANDLER },
1306         { }
1307     }
1308 };
1309
1310 static void
1311 pvscsi_register_types(void)
1312 {
1313     type_register_static(&pvscsi_info);
1314 }
1315
1316 type_init(pvscsi_register_types);