hw/net/e1000e.c

   1 /*
   2 * QEMU INTEL 82574 GbE NIC emulation
   3 *
   4 * Software developer's manuals:
   5 * http://www.intel.com/content/dam/doc/datasheet/82574l-gbe-controller-datasheet.pdf
   6 *
   7 * Copyright (c) 2015 Ravello Systems LTD (http://ravellosystems.com)
   8 * Developed by Daynix Computing LTD (http://www.daynix.com)
   9 *
  10 * Authors:
  11 * Dmitry Fleytman <[email protected]>
  12 * Leonid Bloch <[email protected]>
  13 * Yan Vugenfirer <[email protected]>
  14 *
  15 * Based on work done by:
  16 * Nir Peleg, Tutis Systems Ltd. for Qumranet Inc.
  17 * Copyright (c) 2008 Qumranet
  18 * Based on work done by:
  19 * Copyright (c) 2007 Dan Aloni
  20 * Copyright (c) 2004 Antony T Curtis
  21 *
  22 * This library is free software; you can redistribute it and/or
  23 * modify it under the terms of the GNU Lesser General Public
  24 * License as published by the Free Software Foundation; either
  25 * version 2 of the License, or (at your option) any later version.
  26 *
  27 * This library is distributed in the hope that it will be useful,
  28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  30 * Lesser General Public License for more details.
  31 *
  32 * You should have received a copy of the GNU Lesser General Public
  33 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  34 */
  35
  36 #include "qemu/osdep.h"
  37 #include "qemu/units.h"
  38 #include "net/net.h"
  39 #include "net/tap.h"
  40 #include "qemu/module.h"
  41 #include "qemu/range.h"
  42 #include "sysemu/sysemu.h"
  43 #include "hw/hw.h"
  44 #include "hw/pci/msi.h"
  45 #include "hw/pci/msix.h"
  46 #include "hw/qdev-properties.h"
  47 #include "migration/vmstate.h"
  48
  49 #include "e1000_regs.h"
  50
  51 #include "e1000x_common.h"
  52 #include "e1000e_core.h"
  53
  54 #include "trace.h"
  55 #include "qapi/error.h"
  56 #include "qom/object.h"
  57
  58 #define TYPE_E1000E "e1000e"
  59 typedef struct E1000EState E1000EState;
  60 DECLARE_INSTANCE_CHECKER(E1000EState, E1000E,
  61                          TYPE_E1000E)
  62
  63 struct E1000EState {
  64     PCIDevice parent_obj;
  65     NICState *nic;
  66     NICConf conf;
  67
  68     MemoryRegion mmio;
  69     MemoryRegion flash;
  70     MemoryRegion io;
  71     MemoryRegion msix;
  72
  73     uint32_t ioaddr;
  74
  75     uint16_t subsys_ven;
  76     uint16_t subsys;
  77
  78     uint16_t subsys_ven_used;
  79     uint16_t subsys_used;
  80
  81     bool disable_vnet;
  82
  83     E1000ECore core;
  84
  85 };
  86
  87 #define E1000E_MMIO_IDX     0
  88 #define E1000E_FLASH_IDX    1
  89 #define E1000E_IO_IDX       2
  90 #define E1000E_MSIX_IDX     3
  91
  92 #define E1000E_MMIO_SIZE    (128 * KiB)
  93 #define E1000E_FLASH_SIZE   (128 * KiB)
  94 #define E1000E_IO_SIZE      (32)
  95 #define E1000E_MSIX_SIZE    (16 * KiB)
  96
  97 #define E1000E_MSIX_TABLE   (0x0000)
  98 #define E1000E_MSIX_PBA     (0x2000)
  99
 100 static uint64_t
 101 e1000e_mmio_read(void *opaque, hwaddr addr, unsigned size)
 102 {
 103     E1000EState *s = opaque;
 104     return e1000e_core_read(&s->core, addr, size);
 105 }
 106
 107 static void
 108 e1000e_mmio_write(void *opaque, hwaddr addr,
 109                    uint64_t val, unsigned size)
 110 {
 111     E1000EState *s = opaque;
 112     e1000e_core_write(&s->core, addr, val, size);
 113 }
 114
 115 static bool
 116 e1000e_io_get_reg_index(E1000EState *s, uint32_t *idx)
 117 {
 118     if (s->ioaddr < 0x1FFFF) {
 119         *idx = s->ioaddr;
 120         return true;
 121     }
 122
 123     if (s->ioaddr < 0x7FFFF) {
 124         trace_e1000e_wrn_io_addr_undefined(s->ioaddr);
 125         return false;
 126     }
 127
 128     if (s->ioaddr < 0xFFFFF) {
 129         trace_e1000e_wrn_io_addr_flash(s->ioaddr);
 130         return false;
 131     }
 132
 133     trace_e1000e_wrn_io_addr_unknown(s->ioaddr);
 134     return false;
 135 }
 136
 137 static uint64_t
 138 e1000e_io_read(void *opaque, hwaddr addr, unsigned size)
 139 {
 140     E1000EState *s = opaque;
 141     uint32_t idx = 0;
 142     uint64_t val;
 143
 144     switch (addr) {
 145     case E1000_IOADDR:
 146         trace_e1000e_io_read_addr(s->ioaddr);
 147         return s->ioaddr;
 148     case E1000_IODATA:
 149         if (e1000e_io_get_reg_index(s, &idx)) {
 150             val = e1000e_core_read(&s->core, idx, sizeof(val));
 151             trace_e1000e_io_read_data(idx, val);
 152             return val;
 153         }
 154         return 0;
 155     default:
 156         trace_e1000e_wrn_io_read_unknown(addr);
 157         return 0;
 158     }
 159 }
 160
 161 static void
 162 e1000e_io_write(void *opaque, hwaddr addr,
 163                 uint64_t val, unsigned size)
 164 {
 165     E1000EState *s = opaque;
 166     uint32_t idx = 0;
 167
 168     switch (addr) {
 169     case E1000_IOADDR:
 170         trace_e1000e_io_write_addr(val);
 171         s->ioaddr = (uint32_t) val;
 172         return;
 173     case E1000_IODATA:
 174         if (e1000e_io_get_reg_index(s, &idx)) {
 175             trace_e1000e_io_write_data(idx, val);
 176             e1000e_core_write(&s->core, idx, val, sizeof(val));
 177         }
 178         return;
 179     default:
 180         trace_e1000e_wrn_io_write_unknown(addr);
 181         return;
 182     }
 183 }
 184
 185 static const MemoryRegionOps mmio_ops = {
 186     .read = e1000e_mmio_read,
 187     .write = e1000e_mmio_write,
 188     .endianness = DEVICE_LITTLE_ENDIAN,
 189     .impl = {
 190         .min_access_size = 4,
 191         .max_access_size = 4,
 192     },
 193 };
 194
 195 static const MemoryRegionOps io_ops = {
 196     .read = e1000e_io_read,
 197     .write = e1000e_io_write,
 198     .endianness = DEVICE_LITTLE_ENDIAN,
 199     .impl = {
 200         .min_access_size = 4,
 201         .max_access_size = 4,
 202     },
 203 };
 204
 205 static bool
 206 e1000e_nc_can_receive(NetClientState *nc)
 207 {
 208     E1000EState *s = qemu_get_nic_opaque(nc);
 209     return e1000e_can_receive(&s->core);
 210 }
 211
 212 static ssize_t
 213 e1000e_nc_receive_iov(NetClientState *nc, const struct iovec *iov, int iovcnt)
 214 {
 215     E1000EState *s = qemu_get_nic_opaque(nc);
 216     return e1000e_receive_iov(&s->core, iov, iovcnt);
 217 }
 218
 219 static ssize_t
 220 e1000e_nc_receive(NetClientState *nc, const uint8_t *buf, size_t size)
 221 {
 222     E1000EState *s = qemu_get_nic_opaque(nc);
 223     return e1000e_receive(&s->core, buf, size);
 224 }
 225
 226 static void
 227 e1000e_set_link_status(NetClientState *nc)
 228 {
 229     E1000EState *s = qemu_get_nic_opaque(nc);
 230     e1000e_core_set_link_status(&s->core);
 231 }
 232
 233 static NetClientInfo net_e1000e_info = {
 234     .type = NET_CLIENT_DRIVER_NIC,
 235     .size = sizeof(NICState),
 236     .can_receive = e1000e_nc_can_receive,
 237     .receive = e1000e_nc_receive,
 238     .receive_iov = e1000e_nc_receive_iov,
 239     .link_status_changed = e1000e_set_link_status,
 240 };
 241
 242 /*
 243 * EEPROM (NVM) contents documented in Table 36, section 6.1
 244 * and generally 6.1.2 Software accessed words.
 245 */
 246 static const uint16_t e1000e_eeprom_template[64] = {
 247   /*        Address        |    Compat.    | ImVer |   Compat.     */
 248     0x0000, 0x0000, 0x0000, 0x0420, 0xf746, 0x2010, 0xffff, 0xffff,
 249   /*      PBA      |ICtrl1 | SSID  | SVID  | DevID |-------|ICtrl2 */
 250     0x0000, 0x0000, 0x026b, 0x0000, 0x8086, 0x0000, 0x0000, 0x8058,
 251   /*    NVM words 1,2,3    |-------------------------------|PCI-EID*/
 252     0x0000, 0x2001, 0x7e7c, 0xffff, 0x1000, 0x00c8, 0x0000, 0x2704,
 253   /* PCIe Init. Conf 1,2,3 |PCICtrl|PHY|LD1|-------| RevID | LD0,2 */
 254     0x6cc9, 0x3150, 0x070e, 0x460b, 0x2d84, 0x0100, 0xf000, 0x0706,
 255   /* FLPAR |FLANADD|LAN-PWR|FlVndr |ICtrl3 |APTSMBA|APTRxEP|APTSMBC*/
 256     0x6000, 0x0080, 0x0f04, 0x7fff, 0x4f01, 0xc600, 0x0000, 0x20ff,
 257   /* APTIF | APTMC |APTuCP |LSWFWID|MSWFWID|NC-SIMC|NC-SIC | VPDP  */
 258     0x0028, 0x0003, 0x0000, 0x0000, 0x0000, 0x0003, 0x0000, 0xffff,
 259   /*                            SW Section                         */
 260     0x0100, 0xc000, 0x121c, 0xc007, 0xffff, 0xffff, 0xffff, 0xffff,
 261   /*                      SW Section                       |CHKSUM */
 262     0xffff, 0xffff, 0xffff, 0xffff, 0x0000, 0x0120, 0xffff, 0x0000,
 263 };
 264
 265 static void e1000e_core_realize(E1000EState *s)
 266 {
 267     s->core.owner = &s->parent_obj;
 268     s->core.owner_nic = s->nic;
 269 }
 270
 271 static void
 272 e1000e_unuse_msix_vectors(E1000EState *s, int num_vectors)
 273 {
 274     int i;
 275     for (i = 0; i < num_vectors; i++) {
 276         msix_vector_unuse(PCI_DEVICE(s), i);
 277     }
 278 }
 279
 280 static bool
 281 e1000e_use_msix_vectors(E1000EState *s, int num_vectors)
 282 {
 283     int i;
 284     for (i = 0; i < num_vectors; i++) {
 285         int res = msix_vector_use(PCI_DEVICE(s), i);
 286         if (res < 0) {
 287             trace_e1000e_msix_use_vector_fail(i, res);
 288             e1000e_unuse_msix_vectors(s, i);
 289             return false;
 290         }
 291     }
 292     return true;
 293 }
 294
 295 static void
 296 e1000e_init_msix(E1000EState *s)
 297 {
 298     PCIDevice *d = PCI_DEVICE(s);
 299     int res = msix_init(PCI_DEVICE(s), E1000E_MSIX_VEC_NUM,
 300                         &s->msix,
 301                         E1000E_MSIX_IDX, E1000E_MSIX_TABLE,
 302                         &s->msix,
 303                         E1000E_MSIX_IDX, E1000E_MSIX_PBA,
 304                         0xA0, NULL);
 305
 306     if (res < 0) {
 307         trace_e1000e_msix_init_fail(res);
 308     } else {
 309         if (!e1000e_use_msix_vectors(s, E1000E_MSIX_VEC_NUM)) {
 310             msix_uninit(d, &s->msix, &s->msix);
 311         }
 312     }
 313 }
 314
 315 static void
 316 e1000e_cleanup_msix(E1000EState *s)
 317 {
 318     if (msix_present(PCI_DEVICE(s))) {
 319         e1000e_unuse_msix_vectors(s, E1000E_MSIX_VEC_NUM);
 320         msix_uninit(PCI_DEVICE(s), &s->msix, &s->msix);
 321     }
 322 }
 323
 324 static void
 325 e1000e_init_net_peer(E1000EState *s, PCIDevice *pci_dev, uint8_t *macaddr)
 326 {
 327     DeviceState *dev = DEVICE(pci_dev);
 328     NetClientState *nc;
 329     int i;
 330
 331     s->nic = qemu_new_nic(&net_e1000e_info, &s->conf,
 332         object_get_typename(OBJECT(s)), dev->id, s);
 333
 334     s->core.max_queue_num = s->conf.peers.queues ? s->conf.peers.queues - 1 : 0;
 335
 336     trace_e1000e_mac_set_permanent(MAC_ARG(macaddr));
 337     memcpy(s->core.permanent_mac, macaddr, sizeof(s->core.permanent_mac));
 338
 339     qemu_format_nic_info_str(qemu_get_queue(s->nic), macaddr);
 340
 341     /* Setup virtio headers */
 342     if (s->disable_vnet) {
 343         s->core.has_vnet = false;
 344         trace_e1000e_cfg_support_virtio(false);
 345         return;
 346     } else {
 347         s->core.has_vnet = true;
 348     }
 349
 350     for (i = 0; i < s->conf.peers.queues; i++) {
 351         nc = qemu_get_subqueue(s->nic, i);
 352         if (!nc->peer || !qemu_has_vnet_hdr(nc->peer)) {
 353             s->core.has_vnet = false;
 354             trace_e1000e_cfg_support_virtio(false);
 355             return;
 356         }
 357     }
 358
 359     trace_e1000e_cfg_support_virtio(true);
 360
 361     for (i = 0; i < s->conf.peers.queues; i++) {
 362         nc = qemu_get_subqueue(s->nic, i);
 363         qemu_set_vnet_hdr_len(nc->peer, sizeof(struct virtio_net_hdr));
 364         qemu_using_vnet_hdr(nc->peer, true);
 365     }
 366 }
 367
 368 static inline uint64_t
 369 e1000e_gen_dsn(uint8_t *mac)
 370 {
 371     return (uint64_t)(mac[5])        |
 372            (uint64_t)(mac[4])  << 8  |
 373            (uint64_t)(mac[3])  << 16 |
 374            (uint64_t)(0x00FF)  << 24 |
 375            (uint64_t)(0x00FF)  << 32 |
 376            (uint64_t)(mac[2])  << 40 |
 377            (uint64_t)(mac[1])  << 48 |
 378            (uint64_t)(mac[0])  << 56;
 379 }
 380
 381 static int
 382 e1000e_add_pm_capability(PCIDevice *pdev, uint8_t offset, uint16_t pmc)
 383 {
 384     Error *local_err = NULL;
 385     int ret = pci_add_capability(pdev, PCI_CAP_ID_PM, offset,
 386                                  PCI_PM_SIZEOF, &local_err);
 387
 388     if (local_err) {
 389         error_report_err(local_err);
 390         return ret;
 391     }
 392
 393     pci_set_word(pdev->config + offset + PCI_PM_PMC,
 394                  PCI_PM_CAP_VER_1_1 |
 395                  pmc);
 396
 397     pci_set_word(pdev->wmask + offset + PCI_PM_CTRL,
 398                  PCI_PM_CTRL_STATE_MASK |
 399                  PCI_PM_CTRL_PME_ENABLE |
 400                  PCI_PM_CTRL_DATA_SEL_MASK);
 401
 402     pci_set_word(pdev->w1cmask + offset + PCI_PM_CTRL,
 403                  PCI_PM_CTRL_PME_STATUS);
 404
 405     return ret;
 406 }
 407
 408 static void e1000e_write_config(PCIDevice *pci_dev, uint32_t address,
 409                                 uint32_t val, int len)
 410 {
 411     E1000EState *s = E1000E(pci_dev);
 412
 413     pci_default_write_config(pci_dev, address, val, len);
 414
 415     if (range_covers_byte(address, len, PCI_COMMAND) &&
 416         (pci_dev->config[PCI_COMMAND] & PCI_COMMAND_MASTER)) {
 417         e1000e_start_recv(&s->core);
 418     }
 419 }
 420
 421 static void e1000e_pci_realize(PCIDevice *pci_dev, Error **errp)
 422 {
 423     static const uint16_t e1000e_pmrb_offset = 0x0C8;
 424     static const uint16_t e1000e_pcie_offset = 0x0E0;
 425     static const uint16_t e1000e_aer_offset =  0x100;
 426     static const uint16_t e1000e_dsn_offset =  0x140;
 427     E1000EState *s = E1000E(pci_dev);
 428     uint8_t *macaddr;
 429     int ret;
 430
 431     trace_e1000e_cb_pci_realize();
 432
 433     pci_dev->config_write = e1000e_write_config;
 434
 435     pci_dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
 436     pci_dev->config[PCI_INTERRUPT_PIN] = 1;
 437
 438     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, s->subsys_ven);
 439     pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, s->subsys);
 440
 441     s->subsys_ven_used = s->subsys_ven;
 442     s->subsys_used = s->subsys;
 443
 444     /* Define IO/MMIO regions */
 445     memory_region_init_io(&s->mmio, OBJECT(s), &mmio_ops, s,
 446                           "e1000e-mmio", E1000E_MMIO_SIZE);
 447     pci_register_bar(pci_dev, E1000E_MMIO_IDX,
 448                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
 449
 450     /*
 451      * We provide a dummy implementation for the flash BAR
 452      * for drivers that may theoretically probe for its presence.
 453      */
 454     memory_region_init(&s->flash, OBJECT(s),
 455                        "e1000e-flash", E1000E_FLASH_SIZE);
 456     pci_register_bar(pci_dev, E1000E_FLASH_IDX,
 457                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->flash);
 458
 459     memory_region_init_io(&s->io, OBJECT(s), &io_ops, s,
 460                           "e1000e-io", E1000E_IO_SIZE);
 461     pci_register_bar(pci_dev, E1000E_IO_IDX,
 462                      PCI_BASE_ADDRESS_SPACE_IO, &s->io);
 463
 464     memory_region_init(&s->msix, OBJECT(s), "e1000e-msix",
 465                        E1000E_MSIX_SIZE);
 466     pci_register_bar(pci_dev, E1000E_MSIX_IDX,
 467                      PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix);
 468
 469     /* Create networking backend */
 470     qemu_macaddr_default_if_unset(&s->conf.macaddr);
 471     macaddr = s->conf.macaddr.a;
 472
 473     e1000e_init_msix(s);
 474
 475     if (pcie_endpoint_cap_v1_init(pci_dev, e1000e_pcie_offset) < 0) {
 476         hw_error("Failed to initialize PCIe capability");
 477     }
 478
 479     ret = msi_init(PCI_DEVICE(s), 0xD0, 1, true, false, NULL);
 480     if (ret) {
 481         trace_e1000e_msi_init_fail(ret);
 482     }
 483
 484     if (e1000e_add_pm_capability(pci_dev, e1000e_pmrb_offset,
 485                                   PCI_PM_CAP_DSI) < 0) {
 486         hw_error("Failed to initialize PM capability");
 487     }
 488
 489     if (pcie_aer_init(pci_dev, PCI_ERR_VER, e1000e_aer_offset,
 490                       PCI_ERR_SIZEOF, NULL) < 0) {
 491         hw_error("Failed to initialize AER capability");
 492     }
 493
 494     pcie_dev_ser_num_init(pci_dev, e1000e_dsn_offset,
 495                           e1000e_gen_dsn(macaddr));
 496
 497     e1000e_init_net_peer(s, pci_dev, macaddr);
 498
 499     /* Initialize core */
 500     e1000e_core_realize(s);
 501
 502     e1000e_core_pci_realize(&s->core,
 503                             e1000e_eeprom_template,
 504                             sizeof(e1000e_eeprom_template),
 505                             macaddr);
 506 }
 507
 508 static void e1000e_pci_uninit(PCIDevice *pci_dev)
 509 {
 510     E1000EState *s = E1000E(pci_dev);
 511
 512     trace_e1000e_cb_pci_uninit();
 513
 514     e1000e_core_pci_uninit(&s->core);
 515
 516     pcie_aer_exit(pci_dev);
 517     pcie_cap_exit(pci_dev);
 518
 519     qemu_del_nic(s->nic);
 520
 521     e1000e_cleanup_msix(s);
 522     msi_uninit(pci_dev);
 523 }
 524
 525 static void e1000e_qdev_reset(DeviceState *dev)
 526 {
 527     E1000EState *s = E1000E(dev);
 528
 529     trace_e1000e_cb_qdev_reset();
 530
 531     e1000e_core_reset(&s->core);
 532 }
 533
 534 static int e1000e_pre_save(void *opaque)
 535 {
 536     E1000EState *s = opaque;
 537
 538     trace_e1000e_cb_pre_save();
 539
 540     e1000e_core_pre_save(&s->core);
 541
 542     return 0;
 543 }
 544
 545 static int e1000e_post_load(void *opaque, int version_id)
 546 {
 547     E1000EState *s = opaque;
 548
 549     trace_e1000e_cb_post_load();
 550
 551     if ((s->subsys != s->subsys_used) ||
 552         (s->subsys_ven != s->subsys_ven_used)) {
 553         fprintf(stderr,
 554             "ERROR: Cannot migrate while device properties "
 555             "(subsys/subsys_ven) differ");
 556         return -1;
 557     }
 558
 559     return e1000e_core_post_load(&s->core);
 560 }
 561
 562 static const VMStateDescription e1000e_vmstate_tx = {
 563     .name = "e1000e-tx",
 564     .version_id = 1,
 565     .minimum_version_id = 1,
 566     .fields = (VMStateField[]) {
 567         VMSTATE_UINT8(sum_needed, struct e1000e_tx),
 568         VMSTATE_UINT8(props.ipcss, struct e1000e_tx),
 569         VMSTATE_UINT8(props.ipcso, struct e1000e_tx),
 570         VMSTATE_UINT16(props.ipcse, struct e1000e_tx),
 571         VMSTATE_UINT8(props.tucss, struct e1000e_tx),
 572         VMSTATE_UINT8(props.tucso, struct e1000e_tx),
 573         VMSTATE_UINT16(props.tucse, struct e1000e_tx),
 574         VMSTATE_UINT8(props.hdr_len, struct e1000e_tx),
 575         VMSTATE_UINT16(props.mss, struct e1000e_tx),
 576         VMSTATE_UINT32(props.paylen, struct e1000e_tx),
 577         VMSTATE_INT8(props.ip, struct e1000e_tx),
 578         VMSTATE_INT8(props.tcp, struct e1000e_tx),
 579         VMSTATE_BOOL(props.tse, struct e1000e_tx),
 580         VMSTATE_BOOL(cptse, struct e1000e_tx),
 581         VMSTATE_BOOL(skip_cp, struct e1000e_tx),
 582         VMSTATE_END_OF_LIST()
 583     }
 584 };
 585
 586 static const VMStateDescription e1000e_vmstate_intr_timer = {
 587     .name = "e1000e-intr-timer",
 588     .version_id = 1,
 589     .minimum_version_id = 1,
 590     .fields = (VMStateField[]) {
 591         VMSTATE_TIMER_PTR(timer, E1000IntrDelayTimer),
 592         VMSTATE_BOOL(running, E1000IntrDelayTimer),
 593         VMSTATE_END_OF_LIST()
 594     }
 595 };
 596
 597 #define VMSTATE_E1000E_INTR_DELAY_TIMER(_f, _s)                     \
 598     VMSTATE_STRUCT(_f, _s, 0,                                       \
 599                    e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
 600
 601 #define VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(_f, _s, _num)         \
 602     VMSTATE_STRUCT_ARRAY(_f, _s, _num, 0,                           \
 603                          e1000e_vmstate_intr_timer, E1000IntrDelayTimer)
 604
 605 static const VMStateDescription e1000e_vmstate = {
 606     .name = "e1000e",
 607     .version_id = 1,
 608     .minimum_version_id = 1,
 609     .pre_save = e1000e_pre_save,
 610     .post_load = e1000e_post_load,
 611     .fields = (VMStateField[]) {
 612         VMSTATE_PCI_DEVICE(parent_obj, E1000EState),
 613         VMSTATE_MSIX(parent_obj, E1000EState),
 614
 615         VMSTATE_UINT32(ioaddr, E1000EState),
 616         VMSTATE_UINT32(core.rxbuf_min_shift, E1000EState),
 617         VMSTATE_UINT8(core.rx_desc_len, E1000EState),
 618         VMSTATE_UINT32_ARRAY(core.rxbuf_sizes, E1000EState,
 619                              E1000_PSRCTL_BUFFS_PER_DESC),
 620         VMSTATE_UINT32(core.rx_desc_buf_size, E1000EState),
 621         VMSTATE_UINT16_ARRAY(core.eeprom, E1000EState, E1000E_EEPROM_SIZE),
 622         VMSTATE_UINT16_2DARRAY(core.phy, E1000EState,
 623                                E1000E_PHY_PAGES, E1000E_PHY_PAGE_SIZE),
 624         VMSTATE_UINT32_ARRAY(core.mac, E1000EState, E1000E_MAC_SIZE),
 625         VMSTATE_UINT8_ARRAY(core.permanent_mac, E1000EState, ETH_ALEN),
 626
 627         VMSTATE_UINT32(core.delayed_causes, E1000EState),
 628
 629         VMSTATE_UINT16(subsys, E1000EState),
 630         VMSTATE_UINT16(subsys_ven, E1000EState),
 631
 632         VMSTATE_E1000E_INTR_DELAY_TIMER(core.rdtr, E1000EState),
 633         VMSTATE_E1000E_INTR_DELAY_TIMER(core.radv, E1000EState),
 634         VMSTATE_E1000E_INTR_DELAY_TIMER(core.raid, E1000EState),
 635         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tadv, E1000EState),
 636         VMSTATE_E1000E_INTR_DELAY_TIMER(core.tidv, E1000EState),
 637
 638         VMSTATE_E1000E_INTR_DELAY_TIMER(core.itr, E1000EState),
 639         VMSTATE_BOOL(core.itr_intr_pending, E1000EState),
 640
 641         VMSTATE_E1000E_INTR_DELAY_TIMER_ARRAY(core.eitr, E1000EState,
 642                                               E1000E_MSIX_VEC_NUM),
 643         VMSTATE_BOOL_ARRAY(core.eitr_intr_pending, E1000EState,
 644                            E1000E_MSIX_VEC_NUM),
 645
 646         VMSTATE_UINT32(core.itr_guest_value, E1000EState),
 647         VMSTATE_UINT32_ARRAY(core.eitr_guest_value, E1000EState,
 648                              E1000E_MSIX_VEC_NUM),
 649
 650         VMSTATE_UINT16(core.vet, E1000EState),
 651
 652         VMSTATE_STRUCT_ARRAY(core.tx, E1000EState, E1000E_NUM_QUEUES, 0,
 653                              e1000e_vmstate_tx, struct e1000e_tx),
 654         VMSTATE_END_OF_LIST()
 655     }
 656 };
 657
 658 static PropertyInfo e1000e_prop_disable_vnet,
 659                     e1000e_prop_subsys_ven,
 660                     e1000e_prop_subsys;
 661
 662 static Property e1000e_properties[] = {
 663     DEFINE_NIC_PROPERTIES(E1000EState, conf),
 664     DEFINE_PROP_SIGNED("disable_vnet_hdr", E1000EState, disable_vnet, false,
 665                         e1000e_prop_disable_vnet, bool),
 666     DEFINE_PROP_SIGNED("subsys_ven", E1000EState, subsys_ven,
 667                         PCI_VENDOR_ID_INTEL,
 668                         e1000e_prop_subsys_ven, uint16_t),
 669     DEFINE_PROP_SIGNED("subsys", E1000EState, subsys, 0,
 670                         e1000e_prop_subsys, uint16_t),
 671     DEFINE_PROP_END_OF_LIST(),
 672 };
 673
 674 static void e1000e_class_init(ObjectClass *class, void *data)
 675 {
 676     DeviceClass *dc = DEVICE_CLASS(class);
 677     PCIDeviceClass *c = PCI_DEVICE_CLASS(class);
 678
 679     c->realize = e1000e_pci_realize;
 680     c->exit = e1000e_pci_uninit;
 681     c->vendor_id = PCI_VENDOR_ID_INTEL;
 682     c->device_id = E1000_DEV_ID_82574L;
 683     c->revision = 0;
 684     c->romfile = "efi-e1000e.rom";
 685     c->class_id = PCI_CLASS_NETWORK_ETHERNET;
 686
 687     dc->desc = "Intel 82574L GbE Controller";
 688     dc->reset = e1000e_qdev_reset;
 689     dc->vmsd = &e1000e_vmstate;
 690
 691     e1000e_prop_disable_vnet = qdev_prop_uint8;
 692     e1000e_prop_disable_vnet.description = "Do not use virtio headers, "
 693                                            "perform SW offloads emulation "
 694                                            "instead";
 695
 696     e1000e_prop_subsys_ven = qdev_prop_uint16;
 697     e1000e_prop_subsys_ven.description = "PCI device Subsystem Vendor ID";
 698
 699     e1000e_prop_subsys = qdev_prop_uint16;
 700     e1000e_prop_subsys.description = "PCI device Subsystem ID";
 701
 702     device_class_set_props(dc, e1000e_properties);
 703     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 704 }
 705
 706 static void e1000e_instance_init(Object *obj)
 707 {
 708     E1000EState *s = E1000E(obj);
 709     device_add_bootindex_property(obj, &s->conf.bootindex,
 710                                   "bootindex", "/ethernet-phy@0",
 711                                   DEVICE(obj));
 712 }
 713
 714 static const TypeInfo e1000e_info = {
 715     .name = TYPE_E1000E,
 716     .parent = TYPE_PCI_DEVICE,
 717     .instance_size = sizeof(E1000EState),
 718     .class_init = e1000e_class_init,
 719     .instance_init = e1000e_instance_init,
 720     .interfaces = (InterfaceInfo[]) {
 721         { INTERFACE_PCIE_DEVICE },
 722         { }
 723     },
 724 };
 725
 726 static void e1000e_register_types(void)
 727 {
 728     type_register_static(&e1000e_info);
 729 }
 730
 731 type_init(e1000e_register_types)