]> Git Repo - qemu.git/blob - hw/pci_bridge_dev.c
Merge commit '1dd3a74d2ee2d873cde0b390b536e45420b3fe05' into HEAD
[qemu.git] / hw / pci_bridge_dev.c
1 /*
2  * Standard PCI Bridge Device
3  *
4  * Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <[email protected]>
5  *
6  * http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, see <http://www.gnu.org/licenses/>.
20  */
21
22 #include "pci/pci_bridge.h"
23 #include "pci/pci_ids.h"
24 #include "pci/msi.h"
25 #include "pci/shpc.h"
26 #include "pci/slotid_cap.h"
27 #include "memory.h"
28 #include "pci/pci_bus.h"
29
30 #define REDHAT_PCI_VENDOR_ID 0x1b36
31 #define PCI_BRIDGE_DEV_VENDOR_ID REDHAT_PCI_VENDOR_ID
32 #define PCI_BRIDGE_DEV_DEVICE_ID 0x1
33
34 struct PCIBridgeDev {
35     PCIBridge bridge;
36     MemoryRegion bar;
37     uint8_t chassis_nr;
38 #define PCI_BRIDGE_DEV_F_MSI_REQ 0
39     uint32_t flags;
40 };
41 typedef struct PCIBridgeDev PCIBridgeDev;
42
43 /* Mapping mandated by PCI-to-PCI Bridge architecture specification,
44  * revision 1.2 */
45 /* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
46 static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
47 {
48     return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
49 }
50
51 static int pci_bridge_dev_initfn(PCIDevice *dev)
52 {
53     PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
54     PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
55     int err;
56
57     pci_bridge_map_irq(br, NULL, pci_bridge_dev_map_irq_fn);
58     err = pci_bridge_initfn(dev);
59     if (err) {
60         goto bridge_error;
61     }
62     memory_region_init(&bridge_dev->bar, "shpc-bar", shpc_bar_size(dev));
63     err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
64     if (err) {
65         goto shpc_error;
66     }
67     err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0);
68     if (err) {
69         goto slotid_error;
70     }
71     if ((bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_MSI_REQ)) &&
72         msi_supported) {
73         err = msi_init(dev, 0, 1, true, true);
74         if (err < 0) {
75             goto msi_error;
76         }
77     }
78     /* TODO: spec recommends using 64 bit prefetcheable BAR.
79      * Check whether that works well. */
80     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
81                      PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
82     dev->config[PCI_INTERRUPT_PIN] = 0x1;
83     return 0;
84 msi_error:
85     slotid_cap_cleanup(dev);
86 slotid_error:
87     shpc_cleanup(dev, &bridge_dev->bar);
88 shpc_error:
89     memory_region_destroy(&bridge_dev->bar);
90     pci_bridge_exitfn(dev);
91 bridge_error:
92     return err;
93 }
94
95 static void pci_bridge_dev_exitfn(PCIDevice *dev)
96 {
97     PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
98     PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
99     if (msi_present(dev)) {
100         msi_uninit(dev);
101     }
102     slotid_cap_cleanup(dev);
103     shpc_cleanup(dev, &bridge_dev->bar);
104     memory_region_destroy(&bridge_dev->bar);
105     pci_bridge_exitfn(dev);
106 }
107
108 static void pci_bridge_dev_write_config(PCIDevice *d,
109                                         uint32_t address, uint32_t val, int len)
110 {
111     pci_bridge_write_config(d, address, val, len);
112     if (msi_present(d)) {
113         msi_write_config(d, address, val, len);
114     }
115     shpc_cap_write_config(d, address, val, len);
116 }
117
118 static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
119 {
120     PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
121
122     pci_bridge_reset(qdev);
123     shpc_reset(dev);
124 }
125
126 static Property pci_bridge_dev_properties[] = {
127                     /* Note: 0 is not a legal chassis number. */
128     DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0),
129     DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true),
130     DEFINE_PROP_END_OF_LIST(),
131 };
132
133 static const VMStateDescription pci_bridge_dev_vmstate = {
134     .name = "pci_bridge",
135     .fields = (VMStateField[]) {
136         VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev),
137         SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev),
138         VMSTATE_END_OF_LIST()
139     }
140 };
141
142 static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
143 {
144     DeviceClass *dc = DEVICE_CLASS(klass);
145     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
146     k->init = pci_bridge_dev_initfn;
147     k->exit = pci_bridge_dev_exitfn;
148     k->config_write = pci_bridge_dev_write_config;
149     k->vendor_id = PCI_BRIDGE_DEV_VENDOR_ID;
150     k->device_id = PCI_BRIDGE_DEV_DEVICE_ID;
151     k->class_id = PCI_CLASS_BRIDGE_PCI;
152     k->is_bridge = 1,
153     dc->desc = "Standard PCI Bridge";
154     dc->reset = qdev_pci_bridge_dev_reset;
155     dc->props = pci_bridge_dev_properties;
156     dc->vmsd = &pci_bridge_dev_vmstate;
157 }
158
159 static TypeInfo pci_bridge_dev_info = {
160     .name = "pci-bridge",
161     .parent        = TYPE_PCI_DEVICE,
162     .instance_size = sizeof(PCIBridgeDev),
163     .class_init = pci_bridge_dev_class_init,
164 };
165
166 static void pci_bridge_dev_register(void)
167 {
168     type_register_static(&pci_bridge_dev_info);
169 }
170
171 type_init(pci_bridge_dev_register);
This page took 0.042544 seconds and 4 git commands to generate.