hw/audio/intel-hda.c

   1 /*
   2  * Copyright (C) 2010 Red Hat, Inc.
   3  *
   4  * written by Gerd Hoffmann <[email protected]>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "hw/hw.h"
  21 #include "hw/pci/pci.h"
  22 #include "hw/pci/msi.h"
  23 #include "qemu/timer.h"
  24 #include "hw/audio/audio.h"
  25 #include "intel-hda.h"
  26 #include "intel-hda-defs.h"
  27 #include "sysemu/dma.h"
  28
  29 /* --------------------------------------------------------------------- */
  30 /* hda bus                                                               */
  31
  32 static Property hda_props[] = {
  33     DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
  34     DEFINE_PROP_END_OF_LIST()
  35 };
  36
  37 static const TypeInfo hda_codec_bus_info = {
  38     .name = TYPE_HDA_BUS,
  39     .parent = TYPE_BUS,
  40     .instance_size = sizeof(HDACodecBus),
  41 };
  42
  43 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus, size_t bus_size,
  44                         hda_codec_response_func response,
  45                         hda_codec_xfer_func xfer)
  46 {
  47     qbus_create_inplace(bus, bus_size, TYPE_HDA_BUS, dev, NULL);
  48     bus->response = response;
  49     bus->xfer = xfer;
  50 }
  51
  52 static int hda_codec_dev_init(DeviceState *qdev)
  53 {
  54     HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
  55     HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
  56     HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
  57
  58     if (dev->cad == -1) {
  59         dev->cad = bus->next_cad;
  60     }
  61     if (dev->cad >= 15) {
  62         return -1;
  63     }
  64     bus->next_cad = dev->cad + 1;
  65     return cdc->init(dev);
  66 }
  67
  68 static int hda_codec_dev_exit(DeviceState *qdev)
  69 {
  70     HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
  71     HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
  72
  73     if (cdc->exit) {
  74         cdc->exit(dev);
  75     }
  76     return 0;
  77 }
  78
  79 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
  80 {
  81     BusChild *kid;
  82     HDACodecDevice *cdev;
  83
  84     QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
  85         DeviceState *qdev = kid->child;
  86         cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
  87         if (cdev->cad == cad) {
  88             return cdev;
  89         }
  90     }
  91     return NULL;
  92 }
  93
  94 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
  95 {
  96     HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
  97     bus->response(dev, solicited, response);
  98 }
  99
 100 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
 101                     uint8_t *buf, uint32_t len)
 102 {
 103     HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
 104     return bus->xfer(dev, stnr, output, buf, len);
 105 }
 106
 107 /* --------------------------------------------------------------------- */
 108 /* intel hda emulation                                                   */
 109
 110 typedef struct IntelHDAStream IntelHDAStream;
 111 typedef struct IntelHDAState IntelHDAState;
 112 typedef struct IntelHDAReg IntelHDAReg;
 113
 114 typedef struct bpl {
 115     uint64_t addr;
 116     uint32_t len;
 117     uint32_t flags;
 118 } bpl;
 119
 120 struct IntelHDAStream {
 121     /* registers */
 122     uint32_t ctl;
 123     uint32_t lpib;
 124     uint32_t cbl;
 125     uint32_t lvi;
 126     uint32_t fmt;
 127     uint32_t bdlp_lbase;
 128     uint32_t bdlp_ubase;
 129
 130     /* state */
 131     bpl      *bpl;
 132     uint32_t bentries;
 133     uint32_t bsize, be, bp;
 134 };
 135
 136 struct IntelHDAState {
 137     PCIDevice pci;
 138     const char *name;
 139     HDACodecBus codecs;
 140
 141     /* registers */
 142     uint32_t g_ctl;
 143     uint32_t wake_en;
 144     uint32_t state_sts;
 145     uint32_t int_ctl;
 146     uint32_t int_sts;
 147     uint32_t wall_clk;
 148
 149     uint32_t corb_lbase;
 150     uint32_t corb_ubase;
 151     uint32_t corb_rp;
 152     uint32_t corb_wp;
 153     uint32_t corb_ctl;
 154     uint32_t corb_sts;
 155     uint32_t corb_size;
 156
 157     uint32_t rirb_lbase;
 158     uint32_t rirb_ubase;
 159     uint32_t rirb_wp;
 160     uint32_t rirb_cnt;
 161     uint32_t rirb_ctl;
 162     uint32_t rirb_sts;
 163     uint32_t rirb_size;
 164
 165     uint32_t dp_lbase;
 166     uint32_t dp_ubase;
 167
 168     uint32_t icw;
 169     uint32_t irr;
 170     uint32_t ics;
 171
 172     /* streams */
 173     IntelHDAStream st[8];
 174
 175     /* state */
 176     MemoryRegion mmio;
 177     uint32_t rirb_count;
 178     int64_t wall_base_ns;
 179
 180     /* debug logging */
 181     const IntelHDAReg *last_reg;
 182     uint32_t last_val;
 183     uint32_t last_write;
 184     uint32_t last_sec;
 185     uint32_t repeat_count;
 186
 187     /* properties */
 188     uint32_t debug;
 189     uint32_t msi;
 190 };
 191
 192 #define TYPE_INTEL_HDA_GENERIC "intel-hda-generic"
 193
 194 #define INTEL_HDA(obj) \
 195     OBJECT_CHECK(IntelHDAState, (obj), TYPE_INTEL_HDA_GENERIC)
 196
 197 struct IntelHDAReg {
 198     const char *name;      /* register name */
 199     uint32_t   size;       /* size in bytes */
 200     uint32_t   reset;      /* reset value */
 201     uint32_t   wmask;      /* write mask */
 202     uint32_t   wclear;     /* write 1 to clear bits */
 203     uint32_t   offset;     /* location in IntelHDAState */
 204     uint32_t   shift;      /* byte access entries for dwords */
 205     uint32_t   stream;
 206     void       (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
 207     void       (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
 208 };
 209
 210 static void intel_hda_reset(DeviceState *dev);
 211
 212 /* --------------------------------------------------------------------- */
 213
 214 static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
 215 {
 216     hwaddr addr;
 217
 218     addr = ((uint64_t)ubase << 32) | lbase;
 219     return addr;
 220 }
 221
 222 static void intel_hda_update_int_sts(IntelHDAState *d)
 223 {
 224     uint32_t sts = 0;
 225     uint32_t i;
 226
 227     /* update controller status */
 228     if (d->rirb_sts & ICH6_RBSTS_IRQ) {
 229         sts |= (1 << 30);
 230     }
 231     if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
 232         sts |= (1 << 30);
 233     }
 234     if (d->state_sts & d->wake_en) {
 235         sts |= (1 << 30);
 236     }
 237
 238     /* update stream status */
 239     for (i = 0; i < 8; i++) {
 240         /* buffer completion interrupt */
 241         if (d->st[i].ctl & (1 << 26)) {
 242             sts |= (1 << i);
 243         }
 244     }
 245
 246     /* update global status */
 247     if (sts & d->int_ctl) {
 248         sts |= (1 << 31);
 249     }
 250
 251     d->int_sts = sts;
 252 }
 253
 254 static void intel_hda_update_irq(IntelHDAState *d)
 255 {
 256     int msi = d->msi && msi_enabled(&d->pci);
 257     int level;
 258
 259     intel_hda_update_int_sts(d);
 260     if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
 261         level = 1;
 262     } else {
 263         level = 0;
 264     }
 265     dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
 266            level, msi ? "msi" : "intx");
 267     if (msi) {
 268         if (level) {
 269             msi_notify(&d->pci, 0);
 270         }
 271     } else {
 272         pci_set_irq(&d->pci, level);
 273     }
 274 }
 275
 276 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
 277 {
 278     uint32_t cad, nid, data;
 279     HDACodecDevice *codec;
 280     HDACodecDeviceClass *cdc;
 281
 282     cad = (verb >> 28) & 0x0f;
 283     if (verb & (1 << 27)) {
 284         /* indirect node addressing, not specified in HDA 1.0 */
 285         dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
 286         return -1;
 287     }
 288     nid = (verb >> 20) & 0x7f;
 289     data = verb & 0xfffff;
 290
 291     codec = hda_codec_find(&d->codecs, cad);
 292     if (codec == NULL) {
 293         dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
 294         return -1;
 295     }
 296     cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
 297     cdc->command(codec, nid, data);
 298     return 0;
 299 }
 300
 301 static void intel_hda_corb_run(IntelHDAState *d)
 302 {
 303     hwaddr addr;
 304     uint32_t rp, verb;
 305
 306     if (d->ics & ICH6_IRS_BUSY) {
 307         dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
 308         intel_hda_send_command(d, d->icw);
 309         return;
 310     }
 311
 312     for (;;) {
 313         if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
 314             dprint(d, 2, "%s: !run\n", __FUNCTION__);
 315             return;
 316         }
 317         if ((d->corb_rp & 0xff) == d->corb_wp) {
 318             dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
 319             return;
 320         }
 321         if (d->rirb_count == d->rirb_cnt) {
 322             dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
 323             return;
 324         }
 325
 326         rp = (d->corb_rp + 1) & 0xff;
 327         addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
 328         verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
 329         d->corb_rp = rp;
 330
 331         dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
 332         intel_hda_send_command(d, verb);
 333     }
 334 }
 335
 336 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
 337 {
 338     HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
 339     IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
 340     hwaddr addr;
 341     uint32_t wp, ex;
 342
 343     if (d->ics & ICH6_IRS_BUSY) {
 344         dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
 345                __FUNCTION__, response, dev->cad);
 346         d->irr = response;
 347         d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
 348         d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
 349         return;
 350     }
 351
 352     if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
 353         dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
 354         return;
 355     }
 356
 357     ex = (solicited ? 0 : (1 << 4)) | dev->cad;
 358     wp = (d->rirb_wp + 1) & 0xff;
 359     addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
 360     stl_le_pci_dma(&d->pci, addr + 8*wp, response);
 361     stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
 362     d->rirb_wp = wp;
 363
 364     dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
 365            __FUNCTION__, wp, response, ex);
 366
 367     d->rirb_count++;
 368     if (d->rirb_count == d->rirb_cnt) {
 369         dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
 370         if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
 371             d->rirb_sts |= ICH6_RBSTS_IRQ;
 372             intel_hda_update_irq(d);
 373         }
 374     } else if ((d->corb_rp & 0xff) == d->corb_wp) {
 375         dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
 376                d->rirb_count, d->rirb_cnt);
 377         if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
 378             d->rirb_sts |= ICH6_RBSTS_IRQ;
 379             intel_hda_update_irq(d);
 380         }
 381     }
 382 }
 383
 384 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
 385                            uint8_t *buf, uint32_t len)
 386 {
 387     HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
 388     IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
 389     hwaddr addr;
 390     uint32_t s, copy, left;
 391     IntelHDAStream *st;
 392     bool irq = false;
 393
 394     st = output ? d->st + 4 : d->st;
 395     for (s = 0; s < 4; s++) {
 396         if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
 397             st = st + s;
 398             break;
 399         }
 400     }
 401     if (s == 4) {
 402         return false;
 403     }
 404     if (st->bpl == NULL) {
 405         return false;
 406     }
 407     if (st->ctl & (1 << 26)) {
 408         /*
 409          * Wait with the next DMA xfer until the guest
 410          * has acked the buffer completion interrupt
 411          */
 412         return false;
 413     }
 414
 415     left = len;
 416     while (left > 0) {
 417         copy = left;
 418         if (copy > st->bsize - st->lpib)
 419             copy = st->bsize - st->lpib;
 420         if (copy > st->bpl[st->be].len - st->bp)
 421             copy = st->bpl[st->be].len - st->bp;
 422
 423         dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
 424                st->be, st->bp, st->bpl[st->be].len, copy);
 425
 426         pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
 427         st->lpib += copy;
 428         st->bp += copy;
 429         buf += copy;
 430         left -= copy;
 431
 432         if (st->bpl[st->be].len == st->bp) {
 433             /* bpl entry filled */
 434             if (st->bpl[st->be].flags & 0x01) {
 435                 irq = true;
 436             }
 437             st->bp = 0;
 438             st->be++;
 439             if (st->be == st->bentries) {
 440                 /* bpl wrap around */
 441                 st->be = 0;
 442                 st->lpib = 0;
 443             }
 444         }
 445     }
 446     if (d->dp_lbase & 0x01) {
 447         s = st - d->st;
 448         addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
 449         stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
 450     }
 451     dprint(d, 3, "dma: --\n");
 452
 453     if (irq) {
 454         st->ctl |= (1 << 26); /* buffer completion interrupt */
 455         intel_hda_update_irq(d);
 456     }
 457     return true;
 458 }
 459
 460 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
 461 {
 462     hwaddr addr;
 463     uint8_t buf[16];
 464     uint32_t i;
 465
 466     addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
 467     st->bentries = st->lvi +1;
 468     g_free(st->bpl);
 469     st->bpl = g_malloc(sizeof(bpl) * st->bentries);
 470     for (i = 0; i < st->bentries; i++, addr += 16) {
 471         pci_dma_read(&d->pci, addr, buf, 16);
 472         st->bpl[i].addr  = le64_to_cpu(*(uint64_t *)buf);
 473         st->bpl[i].len   = le32_to_cpu(*(uint32_t *)(buf + 8));
 474         st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
 475         dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
 476                i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
 477     }
 478
 479     st->bsize = st->cbl;
 480     st->lpib  = 0;
 481     st->be    = 0;
 482     st->bp    = 0;
 483 }
 484
 485 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
 486 {
 487     BusChild *kid;
 488     HDACodecDevice *cdev;
 489
 490     QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
 491         DeviceState *qdev = kid->child;
 492         HDACodecDeviceClass *cdc;
 493
 494         cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
 495         cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
 496         if (cdc->stream) {
 497             cdc->stream(cdev, stream, running, output);
 498         }
 499     }
 500 }
 501
 502 /* --------------------------------------------------------------------- */
 503
 504 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 505 {
 506     if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
 507         intel_hda_reset(DEVICE(d));
 508     }
 509 }
 510
 511 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 512 {
 513     intel_hda_update_irq(d);
 514 }
 515
 516 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 517 {
 518     intel_hda_update_irq(d);
 519 }
 520
 521 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 522 {
 523     intel_hda_update_irq(d);
 524 }
 525
 526 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
 527 {
 528     int64_t ns;
 529
 530     ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - d->wall_base_ns;
 531     d->wall_clk = (uint32_t)(ns * 24 / 1000);  /* 24 MHz */
 532 }
 533
 534 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 535 {
 536     intel_hda_corb_run(d);
 537 }
 538
 539 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 540 {
 541     intel_hda_corb_run(d);
 542 }
 543
 544 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 545 {
 546     if (d->rirb_wp & ICH6_RIRBWP_RST) {
 547         d->rirb_wp = 0;
 548     }
 549 }
 550
 551 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 552 {
 553     intel_hda_update_irq(d);
 554
 555     if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
 556         /* cleared ICH6_RBSTS_IRQ */
 557         d->rirb_count = 0;
 558         intel_hda_corb_run(d);
 559     }
 560 }
 561
 562 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 563 {
 564     if (d->ics & ICH6_IRS_BUSY) {
 565         intel_hda_corb_run(d);
 566     }
 567 }
 568
 569 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
 570 {
 571     bool output = reg->stream >= 4;
 572     IntelHDAStream *st = d->st + reg->stream;
 573
 574     if (st->ctl & 0x01) {
 575         /* reset */
 576         dprint(d, 1, "st #%d: reset\n", reg->stream);
 577         st->ctl = 0;
 578     }
 579     if ((st->ctl & 0x02) != (old & 0x02)) {
 580         uint32_t stnr = (st->ctl >> 20) & 0x0f;
 581         /* run bit flipped */
 582         if (st->ctl & 0x02) {
 583             /* start */
 584             dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
 585                    reg->stream, stnr, st->cbl);
 586             intel_hda_parse_bdl(d, st);
 587             intel_hda_notify_codecs(d, stnr, true, output);
 588         } else {
 589             /* stop */
 590             dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
 591             intel_hda_notify_codecs(d, stnr, false, output);
 592         }
 593     }
 594     intel_hda_update_irq(d);
 595 }
 596
 597 /* --------------------------------------------------------------------- */
 598
 599 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
 600
 601 static const struct IntelHDAReg regtab[] = {
 602     /* global */
 603     [ ICH6_REG_GCAP ] = {
 604         .name     = "GCAP",
 605         .size     = 2,
 606         .reset    = 0x4401,
 607     },
 608     [ ICH6_REG_VMIN ] = {
 609         .name     = "VMIN",
 610         .size     = 1,
 611     },
 612     [ ICH6_REG_VMAJ ] = {
 613         .name     = "VMAJ",
 614         .size     = 1,
 615         .reset    = 1,
 616     },
 617     [ ICH6_REG_OUTPAY ] = {
 618         .name     = "OUTPAY",
 619         .size     = 2,
 620         .reset    = 0x3c,
 621     },
 622     [ ICH6_REG_INPAY ] = {
 623         .name     = "INPAY",
 624         .size     = 2,
 625         .reset    = 0x1d,
 626     },
 627     [ ICH6_REG_GCTL ] = {
 628         .name     = "GCTL",
 629         .size     = 4,
 630         .wmask    = 0x0103,
 631         .offset   = offsetof(IntelHDAState, g_ctl),
 632         .whandler = intel_hda_set_g_ctl,
 633     },
 634     [ ICH6_REG_WAKEEN ] = {
 635         .name     = "WAKEEN",
 636         .size     = 2,
 637         .wmask    = 0x7fff,
 638         .offset   = offsetof(IntelHDAState, wake_en),
 639         .whandler = intel_hda_set_wake_en,
 640     },
 641     [ ICH6_REG_STATESTS ] = {
 642         .name     = "STATESTS",
 643         .size     = 2,
 644         .wmask    = 0x7fff,
 645         .wclear   = 0x7fff,
 646         .offset   = offsetof(IntelHDAState, state_sts),
 647         .whandler = intel_hda_set_state_sts,
 648     },
 649
 650     /* interrupts */
 651     [ ICH6_REG_INTCTL ] = {
 652         .name     = "INTCTL",
 653         .size     = 4,
 654         .wmask    = 0xc00000ff,
 655         .offset   = offsetof(IntelHDAState, int_ctl),
 656         .whandler = intel_hda_set_int_ctl,
 657     },
 658     [ ICH6_REG_INTSTS ] = {
 659         .name     = "INTSTS",
 660         .size     = 4,
 661         .wmask    = 0xc00000ff,
 662         .wclear   = 0xc00000ff,
 663         .offset   = offsetof(IntelHDAState, int_sts),
 664     },
 665
 666     /* misc */
 667     [ ICH6_REG_WALLCLK ] = {
 668         .name     = "WALLCLK",
 669         .size     = 4,
 670         .offset   = offsetof(IntelHDAState, wall_clk),
 671         .rhandler = intel_hda_get_wall_clk,
 672     },
 673     [ ICH6_REG_WALLCLK + 0x2000 ] = {
 674         .name     = "WALLCLK(alias)",
 675         .size     = 4,
 676         .offset   = offsetof(IntelHDAState, wall_clk),
 677         .rhandler = intel_hda_get_wall_clk,
 678     },
 679
 680     /* dma engine */
 681     [ ICH6_REG_CORBLBASE ] = {
 682         .name     = "CORBLBASE",
 683         .size     = 4,
 684         .wmask    = 0xffffff80,
 685         .offset   = offsetof(IntelHDAState, corb_lbase),
 686     },
 687     [ ICH6_REG_CORBUBASE ] = {
 688         .name     = "CORBUBASE",
 689         .size     = 4,
 690         .wmask    = 0xffffffff,
 691         .offset   = offsetof(IntelHDAState, corb_ubase),
 692     },
 693     [ ICH6_REG_CORBWP ] = {
 694         .name     = "CORBWP",
 695         .size     = 2,
 696         .wmask    = 0xff,
 697         .offset   = offsetof(IntelHDAState, corb_wp),
 698         .whandler = intel_hda_set_corb_wp,
 699     },
 700     [ ICH6_REG_CORBRP ] = {
 701         .name     = "CORBRP",
 702         .size     = 2,
 703         .wmask    = 0x80ff,
 704         .offset   = offsetof(IntelHDAState, corb_rp),
 705     },
 706     [ ICH6_REG_CORBCTL ] = {
 707         .name     = "CORBCTL",
 708         .size     = 1,
 709         .wmask    = 0x03,
 710         .offset   = offsetof(IntelHDAState, corb_ctl),
 711         .whandler = intel_hda_set_corb_ctl,
 712     },
 713     [ ICH6_REG_CORBSTS ] = {
 714         .name     = "CORBSTS",
 715         .size     = 1,
 716         .wmask    = 0x01,
 717         .wclear   = 0x01,
 718         .offset   = offsetof(IntelHDAState, corb_sts),
 719     },
 720     [ ICH6_REG_CORBSIZE ] = {
 721         .name     = "CORBSIZE",
 722         .size     = 1,
 723         .reset    = 0x42,
 724         .offset   = offsetof(IntelHDAState, corb_size),
 725     },
 726     [ ICH6_REG_RIRBLBASE ] = {
 727         .name     = "RIRBLBASE",
 728         .size     = 4,
 729         .wmask    = 0xffffff80,
 730         .offset   = offsetof(IntelHDAState, rirb_lbase),
 731     },
 732     [ ICH6_REG_RIRBUBASE ] = {
 733         .name     = "RIRBUBASE",
 734         .size     = 4,
 735         .wmask    = 0xffffffff,
 736         .offset   = offsetof(IntelHDAState, rirb_ubase),
 737     },
 738     [ ICH6_REG_RIRBWP ] = {
 739         .name     = "RIRBWP",
 740         .size     = 2,
 741         .wmask    = 0x8000,
 742         .offset   = offsetof(IntelHDAState, rirb_wp),
 743         .whandler = intel_hda_set_rirb_wp,
 744     },
 745     [ ICH6_REG_RINTCNT ] = {
 746         .name     = "RINTCNT",
 747         .size     = 2,
 748         .wmask    = 0xff,
 749         .offset   = offsetof(IntelHDAState, rirb_cnt),
 750     },
 751     [ ICH6_REG_RIRBCTL ] = {
 752         .name     = "RIRBCTL",
 753         .size     = 1,
 754         .wmask    = 0x07,
 755         .offset   = offsetof(IntelHDAState, rirb_ctl),
 756     },
 757     [ ICH6_REG_RIRBSTS ] = {
 758         .name     = "RIRBSTS",
 759         .size     = 1,
 760         .wmask    = 0x05,
 761         .wclear   = 0x05,
 762         .offset   = offsetof(IntelHDAState, rirb_sts),
 763         .whandler = intel_hda_set_rirb_sts,
 764     },
 765     [ ICH6_REG_RIRBSIZE ] = {
 766         .name     = "RIRBSIZE",
 767         .size     = 1,
 768         .reset    = 0x42,
 769         .offset   = offsetof(IntelHDAState, rirb_size),
 770     },
 771
 772     [ ICH6_REG_DPLBASE ] = {
 773         .name     = "DPLBASE",
 774         .size     = 4,
 775         .wmask    = 0xffffff81,
 776         .offset   = offsetof(IntelHDAState, dp_lbase),
 777     },
 778     [ ICH6_REG_DPUBASE ] = {
 779         .name     = "DPUBASE",
 780         .size     = 4,
 781         .wmask    = 0xffffffff,
 782         .offset   = offsetof(IntelHDAState, dp_ubase),
 783     },
 784
 785     [ ICH6_REG_IC ] = {
 786         .name     = "ICW",
 787         .size     = 4,
 788         .wmask    = 0xffffffff,
 789         .offset   = offsetof(IntelHDAState, icw),
 790     },
 791     [ ICH6_REG_IR ] = {
 792         .name     = "IRR",
 793         .size     = 4,
 794         .offset   = offsetof(IntelHDAState, irr),
 795     },
 796     [ ICH6_REG_IRS ] = {
 797         .name     = "ICS",
 798         .size     = 2,
 799         .wmask    = 0x0003,
 800         .wclear   = 0x0002,
 801         .offset   = offsetof(IntelHDAState, ics),
 802         .whandler = intel_hda_set_ics,
 803     },
 804
 805 #define HDA_STREAM(_t, _i)                                            \
 806     [ ST_REG(_i, ICH6_REG_SD_CTL) ] = {                               \
 807         .stream   = _i,                                               \
 808         .name     = _t stringify(_i) " CTL",                          \
 809         .size     = 4,                                                \
 810         .wmask    = 0x1cff001f,                                       \
 811         .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
 812         .whandler = intel_hda_set_st_ctl,                             \
 813     },                                                                \
 814     [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = {                            \
 815         .stream   = _i,                                               \
 816         .name     = _t stringify(_i) " CTL(stnr)",                    \
 817         .size     = 1,                                                \
 818         .shift    = 16,                                               \
 819         .wmask    = 0x00ff0000,                                       \
 820         .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
 821         .whandler = intel_hda_set_st_ctl,                             \
 822     },                                                                \
 823     [ ST_REG(_i, ICH6_REG_SD_STS)] = {                                \
 824         .stream   = _i,                                               \
 825         .name     = _t stringify(_i) " CTL(sts)",                     \
 826         .size     = 1,                                                \
 827         .shift    = 24,                                               \
 828         .wmask    = 0x1c000000,                                       \
 829         .wclear   = 0x1c000000,                                       \
 830         .offset   = offsetof(IntelHDAState, st[_i].ctl),              \
 831         .whandler = intel_hda_set_st_ctl,                             \
 832     },                                                                \
 833     [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = {                              \
 834         .stream   = _i,                                               \
 835         .name     = _t stringify(_i) " LPIB",                         \
 836         .size     = 4,                                                \
 837         .offset   = offsetof(IntelHDAState, st[_i].lpib),             \
 838     },                                                                \
 839     [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = {                     \
 840         .stream   = _i,                                               \
 841         .name     = _t stringify(_i) " LPIB(alias)",                  \
 842         .size     = 4,                                                \
 843         .offset   = offsetof(IntelHDAState, st[_i].lpib),             \
 844     },                                                                \
 845     [ ST_REG(_i, ICH6_REG_SD_CBL) ] = {                               \
 846         .stream   = _i,                                               \
 847         .name     = _t stringify(_i) " CBL",                          \
 848         .size     = 4,                                                \
 849         .wmask    = 0xffffffff,                                       \
 850         .offset   = offsetof(IntelHDAState, st[_i].cbl),              \
 851     },                                                                \
 852     [ ST_REG(_i, ICH6_REG_SD_LVI) ] = {                               \
 853         .stream   = _i,                                               \
 854         .name     = _t stringify(_i) " LVI",                          \
 855         .size     = 2,                                                \
 856         .wmask    = 0x00ff,                                           \
 857         .offset   = offsetof(IntelHDAState, st[_i].lvi),              \
 858     },                                                                \
 859     [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = {                          \
 860         .stream   = _i,                                               \
 861         .name     = _t stringify(_i) " FIFOS",                        \
 862         .size     = 2,                                                \
 863         .reset    = HDA_BUFFER_SIZE,                                  \
 864     },                                                                \
 865     [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = {                            \
 866         .stream   = _i,                                               \
 867         .name     = _t stringify(_i) " FMT",                          \
 868         .size     = 2,                                                \
 869         .wmask    = 0x7f7f,                                           \
 870         .offset   = offsetof(IntelHDAState, st[_i].fmt),              \
 871     },                                                                \
 872     [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = {                             \
 873         .stream   = _i,                                               \
 874         .name     = _t stringify(_i) " BDLPL",                        \
 875         .size     = 4,                                                \
 876         .wmask    = 0xffffff80,                                       \
 877         .offset   = offsetof(IntelHDAState, st[_i].bdlp_lbase),       \
 878     },                                                                \
 879     [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = {                             \
 880         .stream   = _i,                                               \
 881         .name     = _t stringify(_i) " BDLPU",                        \
 882         .size     = 4,                                                \
 883         .wmask    = 0xffffffff,                                       \
 884         .offset   = offsetof(IntelHDAState, st[_i].bdlp_ubase),       \
 885     },                                                                \
 886
 887     HDA_STREAM("IN", 0)
 888     HDA_STREAM("IN", 1)
 889     HDA_STREAM("IN", 2)
 890     HDA_STREAM("IN", 3)
 891
 892     HDA_STREAM("OUT", 4)
 893     HDA_STREAM("OUT", 5)
 894     HDA_STREAM("OUT", 6)
 895     HDA_STREAM("OUT", 7)
 896
 897 };
 898
 899 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
 900 {
 901     const IntelHDAReg *reg;
 902
 903     if (addr >= ARRAY_SIZE(regtab)) {
 904         goto noreg;
 905     }
 906     reg = regtab+addr;
 907     if (reg->name == NULL) {
 908         goto noreg;
 909     }
 910     return reg;
 911
 912 noreg:
 913     dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
 914     return NULL;
 915 }
 916
 917 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
 918 {
 919     uint8_t *addr = (void*)d;
 920
 921     addr += reg->offset;
 922     return (uint32_t*)addr;
 923 }
 924
 925 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
 926                                 uint32_t wmask)
 927 {
 928     uint32_t *addr;
 929     uint32_t old;
 930
 931     if (!reg) {
 932         return;
 933     }
 934
 935     if (d->debug) {
 936         time_t now = time(NULL);
 937         if (d->last_write && d->last_reg == reg && d->last_val == val) {
 938             d->repeat_count++;
 939             if (d->last_sec != now) {
 940                 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
 941                 d->last_sec = now;
 942                 d->repeat_count = 0;
 943             }
 944         } else {
 945             if (d->repeat_count) {
 946                 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
 947             }
 948             dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
 949             d->last_write = 1;
 950             d->last_reg   = reg;
 951             d->last_val   = val;
 952             d->last_sec   = now;
 953             d->repeat_count = 0;
 954         }
 955     }
 956     assert(reg->offset != 0);
 957
 958     addr = intel_hda_reg_addr(d, reg);
 959     old = *addr;
 960
 961     if (reg->shift) {
 962         val <<= reg->shift;
 963         wmask <<= reg->shift;
 964     }
 965     wmask &= reg->wmask;
 966     *addr &= ~wmask;
 967     *addr |= wmask & val;
 968     *addr &= ~(val & reg->wclear);
 969
 970     if (reg->whandler) {
 971         reg->whandler(d, reg, old);
 972     }
 973 }
 974
 975 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
 976                                    uint32_t rmask)
 977 {
 978     uint32_t *addr, ret;
 979
 980     if (!reg) {
 981         return 0;
 982     }
 983
 984     if (reg->rhandler) {
 985         reg->rhandler(d, reg);
 986     }
 987
 988     if (reg->offset == 0) {
 989         /* constant read-only register */
 990         ret = reg->reset;
 991     } else {
 992         addr = intel_hda_reg_addr(d, reg);
 993         ret = *addr;
 994         if (reg->shift) {
 995             ret >>= reg->shift;
 996         }
 997         ret &= rmask;
 998     }
 999     if (d->debug) {
1000         time_t now = time(NULL);
1001         if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
1002             d->repeat_count++;
1003             if (d->last_sec != now) {
1004                 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1005                 d->last_sec = now;
1006                 d->repeat_count = 0;
1007             }
1008         } else {
1009             if (d->repeat_count) {
1010                 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1011             }
1012             dprint(d, 2, "read  %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1013             d->last_write = 0;
1014             d->last_reg   = reg;
1015             d->last_val   = ret;
1016             d->last_sec   = now;
1017             d->repeat_count = 0;
1018         }
1019     }
1020     return ret;
1021 }
1022
1023 static void intel_hda_regs_reset(IntelHDAState *d)
1024 {
1025     uint32_t *addr;
1026     int i;
1027
1028     for (i = 0; i < ARRAY_SIZE(regtab); i++) {
1029         if (regtab[i].name == NULL) {
1030             continue;
1031         }
1032         if (regtab[i].offset == 0) {
1033             continue;
1034         }
1035         addr = intel_hda_reg_addr(d, regtab + i);
1036         *addr = regtab[i].reset;
1037     }
1038 }
1039
1040 /* --------------------------------------------------------------------- */
1041
1042 static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
1043 {
1044     IntelHDAState *d = opaque;
1045     const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1046
1047     intel_hda_reg_write(d, reg, val, 0xff);
1048 }
1049
1050 static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
1051 {
1052     IntelHDAState *d = opaque;
1053     const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1054
1055     intel_hda_reg_write(d, reg, val, 0xffff);
1056 }
1057
1058 static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
1059 {
1060     IntelHDAState *d = opaque;
1061     const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1062
1063     intel_hda_reg_write(d, reg, val, 0xffffffff);
1064 }
1065
1066 static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
1067 {
1068     IntelHDAState *d = opaque;
1069     const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1070
1071     return intel_hda_reg_read(d, reg, 0xff);
1072 }
1073
1074 static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
1075 {
1076     IntelHDAState *d = opaque;
1077     const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1078
1079     return intel_hda_reg_read(d, reg, 0xffff);
1080 }
1081
1082 static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
1083 {
1084     IntelHDAState *d = opaque;
1085     const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1086
1087     return intel_hda_reg_read(d, reg, 0xffffffff);
1088 }
1089
1090 static const MemoryRegionOps intel_hda_mmio_ops = {
1091     .old_mmio = {
1092         .read = {
1093             intel_hda_mmio_readb,
1094             intel_hda_mmio_readw,
1095             intel_hda_mmio_readl,
1096         },
1097         .write = {
1098             intel_hda_mmio_writeb,
1099             intel_hda_mmio_writew,
1100             intel_hda_mmio_writel,
1101         },
1102     },
1103     .endianness = DEVICE_NATIVE_ENDIAN,
1104 };
1105
1106 /* --------------------------------------------------------------------- */
1107
1108 static void intel_hda_reset(DeviceState *dev)
1109 {
1110     BusChild *kid;
1111     IntelHDAState *d = INTEL_HDA(dev);
1112     HDACodecDevice *cdev;
1113
1114     intel_hda_regs_reset(d);
1115     d->wall_base_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1116
1117     /* reset codecs */
1118     QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1119         DeviceState *qdev = kid->child;
1120         cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
1121         device_reset(DEVICE(cdev));
1122         d->state_sts |= (1 << cdev->cad);
1123     }
1124     intel_hda_update_irq(d);
1125 }
1126
1127 static int intel_hda_init(PCIDevice *pci)
1128 {
1129     IntelHDAState *d = INTEL_HDA(pci);
1130     uint8_t *conf = d->pci.config;
1131
1132     d->name = object_get_typename(OBJECT(d));
1133
1134     pci_config_set_interrupt_pin(conf, 1);
1135
1136     /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1137     conf[0x40] = 0x01;
1138
1139     memory_region_init_io(&d->mmio, OBJECT(d), &intel_hda_mmio_ops, d,
1140                           "intel-hda", 0x4000);
1141     pci_register_bar(&d->pci, 0, 0, &d->mmio);
1142     if (d->msi) {
1143         msi_init(&d->pci, 0x50, 1, true, false);
1144     }
1145
1146     hda_codec_bus_init(DEVICE(pci), &d->codecs, sizeof(d->codecs),
1147                        intel_hda_response, intel_hda_xfer);
1148
1149     return 0;
1150 }
1151
1152 static void intel_hda_exit(PCIDevice *pci)
1153 {
1154     IntelHDAState *d = INTEL_HDA(pci);
1155
1156     msi_uninit(&d->pci);
1157     memory_region_destroy(&d->mmio);
1158 }
1159
1160 static int intel_hda_post_load(void *opaque, int version)
1161 {
1162     IntelHDAState* d = opaque;
1163     int i;
1164
1165     dprint(d, 1, "%s\n", __FUNCTION__);
1166     for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1167         if (d->st[i].ctl & 0x02) {
1168             intel_hda_parse_bdl(d, &d->st[i]);
1169         }
1170     }
1171     intel_hda_update_irq(d);
1172     return 0;
1173 }
1174
1175 static const VMStateDescription vmstate_intel_hda_stream = {
1176     .name = "intel-hda-stream",
1177     .version_id = 1,
1178     .fields = (VMStateField []) {
1179         VMSTATE_UINT32(ctl, IntelHDAStream),
1180         VMSTATE_UINT32(lpib, IntelHDAStream),
1181         VMSTATE_UINT32(cbl, IntelHDAStream),
1182         VMSTATE_UINT32(lvi, IntelHDAStream),
1183         VMSTATE_UINT32(fmt, IntelHDAStream),
1184         VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1185         VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1186         VMSTATE_END_OF_LIST()
1187     }
1188 };
1189
1190 static const VMStateDescription vmstate_intel_hda = {
1191     .name = "intel-hda",
1192     .version_id = 1,
1193     .post_load = intel_hda_post_load,
1194     .fields = (VMStateField []) {
1195         VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1196
1197         /* registers */
1198         VMSTATE_UINT32(g_ctl, IntelHDAState),
1199         VMSTATE_UINT32(wake_en, IntelHDAState),
1200         VMSTATE_UINT32(state_sts, IntelHDAState),
1201         VMSTATE_UINT32(int_ctl, IntelHDAState),
1202         VMSTATE_UINT32(int_sts, IntelHDAState),
1203         VMSTATE_UINT32(wall_clk, IntelHDAState),
1204         VMSTATE_UINT32(corb_lbase, IntelHDAState),
1205         VMSTATE_UINT32(corb_ubase, IntelHDAState),
1206         VMSTATE_UINT32(corb_rp, IntelHDAState),
1207         VMSTATE_UINT32(corb_wp, IntelHDAState),
1208         VMSTATE_UINT32(corb_ctl, IntelHDAState),
1209         VMSTATE_UINT32(corb_sts, IntelHDAState),
1210         VMSTATE_UINT32(corb_size, IntelHDAState),
1211         VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1212         VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1213         VMSTATE_UINT32(rirb_wp, IntelHDAState),
1214         VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1215         VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1216         VMSTATE_UINT32(rirb_sts, IntelHDAState),
1217         VMSTATE_UINT32(rirb_size, IntelHDAState),
1218         VMSTATE_UINT32(dp_lbase, IntelHDAState),
1219         VMSTATE_UINT32(dp_ubase, IntelHDAState),
1220         VMSTATE_UINT32(icw, IntelHDAState),
1221         VMSTATE_UINT32(irr, IntelHDAState),
1222         VMSTATE_UINT32(ics, IntelHDAState),
1223         VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1224                              vmstate_intel_hda_stream,
1225                              IntelHDAStream),
1226
1227         /* additional state info */
1228         VMSTATE_UINT32(rirb_count, IntelHDAState),
1229         VMSTATE_INT64(wall_base_ns, IntelHDAState),
1230
1231         VMSTATE_END_OF_LIST()
1232     }
1233 };
1234
1235 static Property intel_hda_properties[] = {
1236     DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1237     DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1238     DEFINE_PROP_END_OF_LIST(),
1239 };
1240
1241 static void intel_hda_class_init(ObjectClass *klass, void *data)
1242 {
1243     DeviceClass *dc = DEVICE_CLASS(klass);
1244     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1245
1246     k->init = intel_hda_init;
1247     k->exit = intel_hda_exit;
1248     k->vendor_id = PCI_VENDOR_ID_INTEL;
1249     k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
1250     dc->reset = intel_hda_reset;
1251     dc->vmsd = &vmstate_intel_hda;
1252     dc->props = intel_hda_properties;
1253 }
1254
1255 static void intel_hda_class_init_ich6(ObjectClass *klass, void *data)
1256 {
1257     DeviceClass *dc = DEVICE_CLASS(klass);
1258     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1259
1260     k->device_id = 0x2668;
1261     k->revision = 1;
1262     set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1263     dc->desc = "Intel HD Audio Controller (ich6)";
1264 }
1265
1266 static void intel_hda_class_init_ich9(ObjectClass *klass, void *data)
1267 {
1268     DeviceClass *dc = DEVICE_CLASS(klass);
1269     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1270
1271     k->device_id = 0x293e;
1272     k->revision = 3;
1273     set_bit(DEVICE_CATEGORY_SOUND, dc->categories);
1274     dc->desc = "Intel HD Audio Controller (ich9)";
1275 }
1276
1277 static const TypeInfo intel_hda_info = {
1278     .name          = TYPE_INTEL_HDA_GENERIC,
1279     .parent        = TYPE_PCI_DEVICE,
1280     .instance_size = sizeof(IntelHDAState),
1281     .class_init    = intel_hda_class_init,
1282     .abstract      = true,
1283 };
1284
1285 static const TypeInfo intel_hda_info_ich6 = {
1286     .name          = "intel-hda",
1287     .parent        = TYPE_INTEL_HDA_GENERIC,
1288     .class_init    = intel_hda_class_init_ich6,
1289 };
1290
1291 static const TypeInfo intel_hda_info_ich9 = {
1292     .name          = "ich9-intel-hda",
1293     .parent        = TYPE_INTEL_HDA_GENERIC,
1294     .class_init    = intel_hda_class_init_ich9,
1295 };
1296
1297 static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1298 {
1299     DeviceClass *k = DEVICE_CLASS(klass);
1300     k->init = hda_codec_dev_init;
1301     k->exit = hda_codec_dev_exit;
1302     set_bit(DEVICE_CATEGORY_SOUND, k->categories);
1303     k->bus_type = TYPE_HDA_BUS;
1304     k->props = hda_props;
1305 }
1306
1307 static const TypeInfo hda_codec_device_type_info = {
1308     .name = TYPE_HDA_CODEC_DEVICE,
1309     .parent = TYPE_DEVICE,
1310     .instance_size = sizeof(HDACodecDevice),
1311     .abstract = true,
1312     .class_size = sizeof(HDACodecDeviceClass),
1313     .class_init = hda_codec_device_class_init,
1314 };
1315
1316 /*
1317  * create intel hda controller with codec attached to it,
1318  * so '-soundhw hda' works.
1319  */
1320 static int intel_hda_and_codec_init(PCIBus *bus)
1321 {
1322     DeviceState *controller;
1323     BusState *hdabus;
1324     DeviceState *codec;
1325
1326     controller = DEVICE(pci_create_simple(bus, -1, "intel-hda"));
1327     hdabus = QLIST_FIRST(&controller->child_bus);
1328     codec = qdev_create(hdabus, "hda-duplex");
1329     qdev_init_nofail(codec);
1330     return 0;
1331 }
1332
1333 static void intel_hda_register_types(void)
1334 {
1335     type_register_static(&hda_codec_bus_info);
1336     type_register_static(&intel_hda_info);
1337     type_register_static(&intel_hda_info_ich6);
1338     type_register_static(&intel_hda_info_ich9);
1339     type_register_static(&hda_codec_device_type_info);
1340     pci_register_soundhw("hda", "Intel HD Audio", intel_hda_and_codec_init);
1341 }
1342
1343 type_init(intel_hda_register_types)