hw/timer/milkymist-sysctl.c

   1 /*
   2  *  QEMU model of the Milkymist System Controller.
   3  *
   4  *  Copyright (c) 2010-2012 Michael Walle <[email protected]>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/sysctl.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/irq.h"
  27 #include "hw/sysbus.h"
  28 #include "sysemu/sysemu.h"
  29 #include "trace.h"
  30 #include "qemu/timer.h"
  31 #include "hw/ptimer.h"
  32 #include "qemu/error-report.h"
  33 #include "qemu/module.h"
  34
  35 enum {
  36     CTRL_ENABLE      = (1<<0),
  37     CTRL_AUTORESTART = (1<<1),
  38 };
  39
  40 enum {
  41     ICAP_READY       = (1<<0),
  42 };
  43
  44 enum {
  45     R_GPIO_IN         = 0,
  46     R_GPIO_OUT,
  47     R_GPIO_INTEN,
  48     R_TIMER0_CONTROL  = 4,
  49     R_TIMER0_COMPARE,
  50     R_TIMER0_COUNTER,
  51     R_TIMER1_CONTROL  = 8,
  52     R_TIMER1_COMPARE,
  53     R_TIMER1_COUNTER,
  54     R_ICAP = 16,
  55     R_DBG_SCRATCHPAD  = 20,
  56     R_DBG_WRITE_LOCK,
  57     R_CLK_FREQUENCY   = 29,
  58     R_CAPABILITIES,
  59     R_SYSTEM_ID,
  60     R_MAX
  61 };
  62
  63 #define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
  64 #define MILKYMIST_SYSCTL(obj) \
  65     OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
  66
  67 struct MilkymistSysctlState {
  68     SysBusDevice parent_obj;
  69
  70     MemoryRegion regs_region;
  71
  72     QEMUBH *bh0;
  73     QEMUBH *bh1;
  74     ptimer_state *ptimer0;
  75     ptimer_state *ptimer1;
  76
  77     uint32_t freq_hz;
  78     uint32_t capabilities;
  79     uint32_t systemid;
  80     uint32_t strappings;
  81
  82     uint32_t regs[R_MAX];
  83
  84     qemu_irq gpio_irq;
  85     qemu_irq timer0_irq;
  86     qemu_irq timer1_irq;
  87 };
  88 typedef struct MilkymistSysctlState MilkymistSysctlState;
  89
  90 static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
  91 {
  92     trace_milkymist_sysctl_icap_write(value);
  93     switch (value & 0xffff) {
  94     case 0x000e:
  95         qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
  96         break;
  97     }
  98 }
  99
 100 static uint64_t sysctl_read(void *opaque, hwaddr addr,
 101                             unsigned size)
 102 {
 103     MilkymistSysctlState *s = opaque;
 104     uint32_t r = 0;
 105
 106     addr >>= 2;
 107     switch (addr) {
 108     case R_TIMER0_COUNTER:
 109         r = (uint32_t)ptimer_get_count(s->ptimer0);
 110         /* milkymist timer counts up */
 111         r = s->regs[R_TIMER0_COMPARE] - r;
 112         break;
 113     case R_TIMER1_COUNTER:
 114         r = (uint32_t)ptimer_get_count(s->ptimer1);
 115         /* milkymist timer counts up */
 116         r = s->regs[R_TIMER1_COMPARE] - r;
 117         break;
 118     case R_GPIO_IN:
 119     case R_GPIO_OUT:
 120     case R_GPIO_INTEN:
 121     case R_TIMER0_CONTROL:
 122     case R_TIMER0_COMPARE:
 123     case R_TIMER1_CONTROL:
 124     case R_TIMER1_COMPARE:
 125     case R_ICAP:
 126     case R_DBG_SCRATCHPAD:
 127     case R_DBG_WRITE_LOCK:
 128     case R_CLK_FREQUENCY:
 129     case R_CAPABILITIES:
 130     case R_SYSTEM_ID:
 131         r = s->regs[addr];
 132         break;
 133
 134     default:
 135         error_report("milkymist_sysctl: read access to unknown register 0x"
 136                 TARGET_FMT_plx, addr << 2);
 137         break;
 138     }
 139
 140     trace_milkymist_sysctl_memory_read(addr << 2, r);
 141
 142     return r;
 143 }
 144
 145 static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
 146                          unsigned size)
 147 {
 148     MilkymistSysctlState *s = opaque;
 149
 150     trace_milkymist_sysctl_memory_write(addr, value);
 151
 152     addr >>= 2;
 153     switch (addr) {
 154     case R_GPIO_OUT:
 155     case R_GPIO_INTEN:
 156     case R_TIMER0_COUNTER:
 157     case R_TIMER1_COUNTER:
 158     case R_DBG_SCRATCHPAD:
 159         s->regs[addr] = value;
 160         break;
 161     case R_TIMER0_COMPARE:
 162         ptimer_set_limit(s->ptimer0, value, 0);
 163         s->regs[addr] = value;
 164         break;
 165     case R_TIMER1_COMPARE:
 166         ptimer_set_limit(s->ptimer1, value, 0);
 167         s->regs[addr] = value;
 168         break;
 169     case R_TIMER0_CONTROL:
 170         s->regs[addr] = value;
 171         if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
 172             trace_milkymist_sysctl_start_timer0();
 173             ptimer_set_count(s->ptimer0,
 174                     s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
 175             ptimer_run(s->ptimer0, 0);
 176         } else {
 177             trace_milkymist_sysctl_stop_timer0();
 178             ptimer_stop(s->ptimer0);
 179         }
 180         break;
 181     case R_TIMER1_CONTROL:
 182         s->regs[addr] = value;
 183         if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
 184             trace_milkymist_sysctl_start_timer1();
 185             ptimer_set_count(s->ptimer1,
 186                     s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
 187             ptimer_run(s->ptimer1, 0);
 188         } else {
 189             trace_milkymist_sysctl_stop_timer1();
 190             ptimer_stop(s->ptimer1);
 191         }
 192         break;
 193     case R_ICAP:
 194         sysctl_icap_write(s, value);
 195         break;
 196     case R_DBG_WRITE_LOCK:
 197         s->regs[addr] = 1;
 198         break;
 199     case R_SYSTEM_ID:
 200         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 201         break;
 202
 203     case R_GPIO_IN:
 204     case R_CLK_FREQUENCY:
 205     case R_CAPABILITIES:
 206         error_report("milkymist_sysctl: write to read-only register 0x"
 207                 TARGET_FMT_plx, addr << 2);
 208         break;
 209
 210     default:
 211         error_report("milkymist_sysctl: write access to unknown register 0x"
 212                 TARGET_FMT_plx, addr << 2);
 213         break;
 214     }
 215 }
 216
 217 static const MemoryRegionOps sysctl_mmio_ops = {
 218     .read = sysctl_read,
 219     .write = sysctl_write,
 220     .valid = {
 221         .min_access_size = 4,
 222         .max_access_size = 4,
 223     },
 224     .endianness = DEVICE_NATIVE_ENDIAN,
 225 };
 226
 227 static void timer0_hit(void *opaque)
 228 {
 229     MilkymistSysctlState *s = opaque;
 230
 231     if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
 232         s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
 233         trace_milkymist_sysctl_stop_timer0();
 234         ptimer_stop(s->ptimer0);
 235     }
 236
 237     trace_milkymist_sysctl_pulse_irq_timer0();
 238     qemu_irq_pulse(s->timer0_irq);
 239 }
 240
 241 static void timer1_hit(void *opaque)
 242 {
 243     MilkymistSysctlState *s = opaque;
 244
 245     if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
 246         s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
 247         trace_milkymist_sysctl_stop_timer1();
 248         ptimer_stop(s->ptimer1);
 249     }
 250
 251     trace_milkymist_sysctl_pulse_irq_timer1();
 252     qemu_irq_pulse(s->timer1_irq);
 253 }
 254
 255 static void milkymist_sysctl_reset(DeviceState *d)
 256 {
 257     MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
 258     int i;
 259
 260     for (i = 0; i < R_MAX; i++) {
 261         s->regs[i] = 0;
 262     }
 263
 264     ptimer_stop(s->ptimer0);
 265     ptimer_stop(s->ptimer1);
 266
 267     /* defaults */
 268     s->regs[R_ICAP] = ICAP_READY;
 269     s->regs[R_SYSTEM_ID] = s->systemid;
 270     s->regs[R_CLK_FREQUENCY] = s->freq_hz;
 271     s->regs[R_CAPABILITIES] = s->capabilities;
 272     s->regs[R_GPIO_IN] = s->strappings;
 273 }
 274
 275 static void milkymist_sysctl_init(Object *obj)
 276 {
 277     MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
 278     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 279
 280     sysbus_init_irq(dev, &s->gpio_irq);
 281     sysbus_init_irq(dev, &s->timer0_irq);
 282     sysbus_init_irq(dev, &s->timer1_irq);
 283
 284     s->bh0 = qemu_bh_new(timer0_hit, s);
 285     s->bh1 = qemu_bh_new(timer1_hit, s);
 286     s->ptimer0 = ptimer_init(s->bh0, PTIMER_POLICY_DEFAULT);
 287     s->ptimer1 = ptimer_init(s->bh1, PTIMER_POLICY_DEFAULT);
 288
 289     memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
 290             "milkymist-sysctl", R_MAX * 4);
 291     sysbus_init_mmio(dev, &s->regs_region);
 292 }
 293
 294 static void milkymist_sysctl_realize(DeviceState *dev, Error **errp)
 295 {
 296     MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
 297
 298     ptimer_set_freq(s->ptimer0, s->freq_hz);
 299     ptimer_set_freq(s->ptimer1, s->freq_hz);
 300 }
 301
 302 static const VMStateDescription vmstate_milkymist_sysctl = {
 303     .name = "milkymist-sysctl",
 304     .version_id = 1,
 305     .minimum_version_id = 1,
 306     .fields = (VMStateField[]) {
 307         VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
 308         VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
 309         VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
 310         VMSTATE_END_OF_LIST()
 311     }
 312 };
 313
 314 static Property milkymist_sysctl_properties[] = {
 315     DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
 316     freq_hz, 80000000),
 317     DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
 318     capabilities, 0x00000000),
 319     DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
 320     systemid, 0x10014d31),
 321     DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
 322     strappings, 0x00000001),
 323     DEFINE_PROP_END_OF_LIST(),
 324 };
 325
 326 static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
 327 {
 328     DeviceClass *dc = DEVICE_CLASS(klass);
 329
 330     dc->realize = milkymist_sysctl_realize;
 331     dc->reset = milkymist_sysctl_reset;
 332     dc->vmsd = &vmstate_milkymist_sysctl;
 333     dc->props = milkymist_sysctl_properties;
 334 }
 335
 336 static const TypeInfo milkymist_sysctl_info = {
 337     .name          = TYPE_MILKYMIST_SYSCTL,
 338     .parent        = TYPE_SYS_BUS_DEVICE,
 339     .instance_size = sizeof(MilkymistSysctlState),
 340     .instance_init = milkymist_sysctl_init,
 341     .class_init    = milkymist_sysctl_class_init,
 342 };
 343
 344 static void milkymist_sysctl_register_types(void)
 345 {
 346     type_register_static(&milkymist_sysctl_info);
 347 }
 348
 349 type_init(milkymist_sysctl_register_types)