hw/i2c/exynos4210_i2c.c

   1 /*
   2  *  Exynos4210 I2C Bus Serial Interface Emulation
   3  *
   4  *  Copyright (C) 2012 Samsung Electronics Co Ltd.
   5  *    Maksim Kozlov, <[email protected]>
   6  *    Igor Mitsyanko, <[email protected]>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License as published by the
  10  *  Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16  *  for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License along
  19  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  20  *
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/module.h"
  25 #include "qemu/timer.h"
  26 #include "hw/sysbus.h"
  27 #include "hw/i2c/i2c.h"
  28 #include "hw/irq.h"
  29
  30 #ifndef EXYNOS4_I2C_DEBUG
  31 #define EXYNOS4_I2C_DEBUG                 0
  32 #endif
  33
  34 #define TYPE_EXYNOS4_I2C                  "exynos4210.i2c"
  35 #define EXYNOS4_I2C(obj)                  \
  36     OBJECT_CHECK(Exynos4210I2CState, (obj), TYPE_EXYNOS4_I2C)
  37
  38 /* Exynos4210 I2C memory map */
  39 #define EXYNOS4_I2C_MEM_SIZE              0x14
  40 #define I2CCON_ADDR                       0x00  /* control register */
  41 #define I2CSTAT_ADDR                      0x04  /* control/status register */
  42 #define I2CADD_ADDR                       0x08  /* address register */
  43 #define I2CDS_ADDR                        0x0c  /* data shift register */
  44 #define I2CLC_ADDR                        0x10  /* line control register */
  45
  46 #define I2CCON_ACK_GEN                    (1 << 7)
  47 #define I2CCON_INTRS_EN                   (1 << 5)
  48 #define I2CCON_INT_PEND                   (1 << 4)
  49
  50 #define EXYNOS4_I2C_MODE(reg)             (((reg) >> 6) & 3)
  51 #define I2C_IN_MASTER_MODE(reg)           (((reg) >> 6) & 2)
  52 #define I2CMODE_MASTER_Rx                 0x2
  53 #define I2CMODE_MASTER_Tx                 0x3
  54 #define I2CSTAT_LAST_BIT                  (1 << 0)
  55 #define I2CSTAT_OUTPUT_EN                 (1 << 4)
  56 #define I2CSTAT_START_BUSY                (1 << 5)
  57
  58
  59 #if EXYNOS4_I2C_DEBUG
  60 #define DPRINT(fmt, args...)              \
  61     do { fprintf(stderr, "QEMU I2C: "fmt, ## args); } while (0)
  62
  63 static const char *exynos4_i2c_get_regname(unsigned offset)
  64 {
  65     switch (offset) {
  66     case I2CCON_ADDR:
  67         return "I2CCON";
  68     case I2CSTAT_ADDR:
  69         return "I2CSTAT";
  70     case I2CADD_ADDR:
  71         return "I2CADD";
  72     case I2CDS_ADDR:
  73         return "I2CDS";
  74     case I2CLC_ADDR:
  75         return "I2CLC";
  76     default:
  77         return "[?]";
  78     }
  79 }
  80
  81 #else
  82 #define DPRINT(fmt, args...)              do { } while (0)
  83 #endif
  84
  85 typedef struct Exynos4210I2CState {
  86     SysBusDevice parent_obj;
  87
  88     MemoryRegion iomem;
  89     I2CBus *bus;
  90     qemu_irq irq;
  91
  92     uint8_t i2ccon;
  93     uint8_t i2cstat;
  94     uint8_t i2cadd;
  95     uint8_t i2cds;
  96     uint8_t i2clc;
  97     bool scl_free;
  98 } Exynos4210I2CState;
  99
 100 static inline void exynos4210_i2c_raise_interrupt(Exynos4210I2CState *s)
 101 {
 102     if (s->i2ccon & I2CCON_INTRS_EN) {
 103         s->i2ccon |= I2CCON_INT_PEND;
 104         qemu_irq_raise(s->irq);
 105     }
 106 }
 107
 108 static void exynos4210_i2c_data_receive(void *opaque)
 109 {
 110     Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
 111
 112     s->i2cstat &= ~I2CSTAT_LAST_BIT;
 113     s->scl_free = false;
 114     s->i2cds = i2c_recv(s->bus);
 115     exynos4210_i2c_raise_interrupt(s);
 116 }
 117
 118 static void exynos4210_i2c_data_send(void *opaque)
 119 {
 120     Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
 121
 122     s->i2cstat &= ~I2CSTAT_LAST_BIT;
 123     s->scl_free = false;
 124     if (i2c_send(s->bus, s->i2cds) < 0 && (s->i2ccon & I2CCON_ACK_GEN)) {
 125         s->i2cstat |= I2CSTAT_LAST_BIT;
 126     }
 127     exynos4210_i2c_raise_interrupt(s);
 128 }
 129
 130 static uint64_t exynos4210_i2c_read(void *opaque, hwaddr offset,
 131                                  unsigned size)
 132 {
 133     Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
 134     uint8_t value;
 135
 136     switch (offset) {
 137     case I2CCON_ADDR:
 138         value = s->i2ccon;
 139         break;
 140     case I2CSTAT_ADDR:
 141         value = s->i2cstat;
 142         break;
 143     case I2CADD_ADDR:
 144         value = s->i2cadd;
 145         break;
 146     case I2CDS_ADDR:
 147         value = s->i2cds;
 148         s->scl_free = true;
 149         if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Rx &&
 150                (s->i2cstat & I2CSTAT_START_BUSY) &&
 151                !(s->i2ccon & I2CCON_INT_PEND)) {
 152             exynos4210_i2c_data_receive(s);
 153         }
 154         break;
 155     case I2CLC_ADDR:
 156         value = s->i2clc;
 157         break;
 158     default:
 159         value = 0;
 160         DPRINT("ERROR: Bad read offset 0x%x\n", (unsigned int)offset);
 161         break;
 162     }
 163
 164     DPRINT("read %s [0x%02x] -> 0x%02x\n", exynos4_i2c_get_regname(offset),
 165             (unsigned int)offset, value);
 166     return value;
 167 }
 168
 169 static void exynos4210_i2c_write(void *opaque, hwaddr offset,
 170                               uint64_t value, unsigned size)
 171 {
 172     Exynos4210I2CState *s = (Exynos4210I2CState *)opaque;
 173     uint8_t v = value & 0xff;
 174
 175     DPRINT("write %s [0x%02x] <- 0x%02x\n", exynos4_i2c_get_regname(offset),
 176             (unsigned int)offset, v);
 177
 178     switch (offset) {
 179     case I2CCON_ADDR:
 180         s->i2ccon = (v & ~I2CCON_INT_PEND) | (s->i2ccon & I2CCON_INT_PEND);
 181         if ((s->i2ccon & I2CCON_INT_PEND) && !(v & I2CCON_INT_PEND)) {
 182             s->i2ccon &= ~I2CCON_INT_PEND;
 183             qemu_irq_lower(s->irq);
 184             if (!(s->i2ccon & I2CCON_INTRS_EN)) {
 185                 s->i2cstat &= ~I2CSTAT_START_BUSY;
 186             }
 187
 188             if (s->i2cstat & I2CSTAT_START_BUSY) {
 189                 if (s->scl_free) {
 190                     if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Tx) {
 191                         exynos4210_i2c_data_send(s);
 192                     } else if (EXYNOS4_I2C_MODE(s->i2cstat) ==
 193                             I2CMODE_MASTER_Rx) {
 194                         exynos4210_i2c_data_receive(s);
 195                     }
 196                 } else {
 197                     s->i2ccon |= I2CCON_INT_PEND;
 198                     qemu_irq_raise(s->irq);
 199                 }
 200             }
 201         }
 202         break;
 203     case I2CSTAT_ADDR:
 204         s->i2cstat =
 205                 (s->i2cstat & I2CSTAT_START_BUSY) | (v & ~I2CSTAT_START_BUSY);
 206
 207         if (!(s->i2cstat & I2CSTAT_OUTPUT_EN)) {
 208             s->i2cstat &= ~I2CSTAT_START_BUSY;
 209             s->scl_free = true;
 210             qemu_irq_lower(s->irq);
 211             break;
 212         }
 213
 214         /* Nothing to do if in i2c slave mode */
 215         if (!I2C_IN_MASTER_MODE(s->i2cstat)) {
 216             break;
 217         }
 218
 219         if (v & I2CSTAT_START_BUSY) {
 220             s->i2cstat &= ~I2CSTAT_LAST_BIT;
 221             s->i2cstat |= I2CSTAT_START_BUSY;    /* Line is busy */
 222             s->scl_free = false;
 223
 224             /* Generate start bit and send slave address */
 225             if (i2c_start_transfer(s->bus, s->i2cds >> 1, s->i2cds & 0x1) &&
 226                     (s->i2ccon & I2CCON_ACK_GEN)) {
 227                 s->i2cstat |= I2CSTAT_LAST_BIT;
 228             } else if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Rx) {
 229                 exynos4210_i2c_data_receive(s);
 230             }
 231             exynos4210_i2c_raise_interrupt(s);
 232         } else {
 233             i2c_end_transfer(s->bus);
 234             if (!(s->i2ccon & I2CCON_INT_PEND)) {
 235                 s->i2cstat &= ~I2CSTAT_START_BUSY;
 236             }
 237             s->scl_free = true;
 238         }
 239         break;
 240     case I2CADD_ADDR:
 241         if ((s->i2cstat & I2CSTAT_OUTPUT_EN) == 0) {
 242             s->i2cadd = v;
 243         }
 244         break;
 245     case I2CDS_ADDR:
 246         if (s->i2cstat & I2CSTAT_OUTPUT_EN) {
 247             s->i2cds = v;
 248             s->scl_free = true;
 249             if (EXYNOS4_I2C_MODE(s->i2cstat) == I2CMODE_MASTER_Tx &&
 250                     (s->i2cstat & I2CSTAT_START_BUSY) &&
 251                     !(s->i2ccon & I2CCON_INT_PEND)) {
 252                 exynos4210_i2c_data_send(s);
 253             }
 254         }
 255         break;
 256     case I2CLC_ADDR:
 257         s->i2clc = v;
 258         break;
 259     default:
 260         DPRINT("ERROR: Bad write offset 0x%x\n", (unsigned int)offset);
 261         break;
 262     }
 263 }
 264
 265 static const MemoryRegionOps exynos4210_i2c_ops = {
 266     .read = exynos4210_i2c_read,
 267     .write = exynos4210_i2c_write,
 268     .endianness = DEVICE_NATIVE_ENDIAN,
 269 };
 270
 271 static const VMStateDescription exynos4210_i2c_vmstate = {
 272     .name = "exynos4210.i2c",
 273     .version_id = 1,
 274     .minimum_version_id = 1,
 275     .fields = (VMStateField[]) {
 276         VMSTATE_UINT8(i2ccon, Exynos4210I2CState),
 277         VMSTATE_UINT8(i2cstat, Exynos4210I2CState),
 278         VMSTATE_UINT8(i2cds, Exynos4210I2CState),
 279         VMSTATE_UINT8(i2cadd, Exynos4210I2CState),
 280         VMSTATE_UINT8(i2clc, Exynos4210I2CState),
 281         VMSTATE_BOOL(scl_free, Exynos4210I2CState),
 282         VMSTATE_END_OF_LIST()
 283     }
 284 };
 285
 286 static void exynos4210_i2c_reset(DeviceState *d)
 287 {
 288     Exynos4210I2CState *s = EXYNOS4_I2C(d);
 289
 290     s->i2ccon  = 0x00;
 291     s->i2cstat = 0x00;
 292     s->i2cds   = 0xFF;
 293     s->i2clc   = 0x00;
 294     s->i2cadd  = 0xFF;
 295     s->scl_free = true;
 296 }
 297
 298 static void exynos4210_i2c_init(Object *obj)
 299 {
 300     DeviceState *dev = DEVICE(obj);
 301     Exynos4210I2CState *s = EXYNOS4_I2C(obj);
 302     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 303
 304     memory_region_init_io(&s->iomem, obj, &exynos4210_i2c_ops, s,
 305                           TYPE_EXYNOS4_I2C, EXYNOS4_I2C_MEM_SIZE);
 306     sysbus_init_mmio(sbd, &s->iomem);
 307     sysbus_init_irq(sbd, &s->irq);
 308     s->bus = i2c_init_bus(dev, "i2c");
 309 }
 310
 311 static void exynos4210_i2c_class_init(ObjectClass *klass, void *data)
 312 {
 313     DeviceClass *dc = DEVICE_CLASS(klass);
 314
 315     dc->vmsd = &exynos4210_i2c_vmstate;
 316     dc->reset = exynos4210_i2c_reset;
 317 }
 318
 319 static const TypeInfo exynos4210_i2c_type_info = {
 320     .name = TYPE_EXYNOS4_I2C,
 321     .parent = TYPE_SYS_BUS_DEVICE,
 322     .instance_size = sizeof(Exynos4210I2CState),
 323     .instance_init = exynos4210_i2c_init,
 324     .class_init = exynos4210_i2c_class_init,
 325 };
 326
 327 static void exynos4210_i2c_register_types(void)
 328 {
 329     type_register_static(&exynos4210_i2c_type_info);
 330 }
 331
 332 type_init(exynos4210_i2c_register_types)