hw/pci-host/q35.c

   1 /*
   2  * QEMU MCH/ICH9 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2009, 2010, 2011
   6  *               Isaku Yamahata <yamahata at valinux co jp>
   7  *               VA Linux Systems Japan K.K.
   8  * Copyright (C) 2012 Jason Baron <[email protected]>
   9  *
  10  * This is based on piix.c, but heavily modified.
  11  *
  12  * Permission is hereby granted, free of charge, to any person obtaining a copy
  13  * of this software and associated documentation files (the "Software"), to deal
  14  * in the Software without restriction, including without limitation the rights
  15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  16  * copies of the Software, and to permit persons to whom the Software is
  17  * furnished to do so, subject to the following conditions:
  18  *
  19  * The above copyright notice and this permission notice shall be included in
  20  * all copies or substantial portions of the Software.
  21  *
  22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  28  * THE SOFTWARE.
  29  */
  30 #include "hw/hw.h"
  31 #include "hw/pci-host/q35.h"
  32 #include "qapi/visitor.h"
  33
  34 /****************************************************************************
  35  * Q35 host
  36  */
  37
  38 static void q35_host_realize(DeviceState *dev, Error **errp)
  39 {
  40     PCIHostState *pci = PCI_HOST_BRIDGE(dev);
  41     Q35PCIHost *s = Q35_HOST_DEVICE(dev);
  42     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
  43
  44     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
  45     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4);
  46
  47     sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
  48     sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4);
  49
  50     pci->bus = pci_bus_new(DEVICE(s), "pcie.0",
  51                            s->mch.pci_address_space, s->mch.address_space_io,
  52                            0, TYPE_PCIE_BUS);
  53     qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus));
  54     qdev_init_nofail(DEVICE(&s->mch));
  55 }
  56
  57 static const char *q35_host_root_bus_path(PCIHostState *host_bridge,
  58                                           PCIBus *rootbus)
  59 {
  60     Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge);
  61
  62      /* For backwards compat with old device paths */
  63     if (s->mch.short_root_bus) {
  64         return "0000";
  65     }
  66     return "0000:00";
  67 }
  68
  69 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
  70                                         void *opaque, const char *name,
  71                                         Error **errp)
  72 {
  73     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  74     uint32_t value = s->mch.pci_info.w32.begin;
  75
  76     visit_type_uint32(v, &value, name, errp);
  77 }
  78
  79 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
  80                                       void *opaque, const char *name,
  81                                       Error **errp)
  82 {
  83     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
  84     uint32_t value = s->mch.pci_info.w32.end;
  85
  86     visit_type_uint32(v, &value, name, errp);
  87 }
  88
  89 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
  90                                           void *opaque, const char *name,
  91                                           Error **errp)
  92 {
  93     PCIHostState *h = PCI_HOST_BRIDGE(obj);
  94     Range w64;
  95
  96     pci_bus_get_w64_range(h->bus, &w64);
  97
  98     visit_type_uint64(v, &w64.begin, name, errp);
  99 }
 100
 101 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
 102                                         void *opaque, const char *name,
 103                                         Error **errp)
 104 {
 105     PCIHostState *h = PCI_HOST_BRIDGE(obj);
 106     Range w64;
 107
 108     pci_bus_get_w64_range(h->bus, &w64);
 109
 110     visit_type_uint64(v, &w64.end, name, errp);
 111 }
 112
 113 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
 114                                     void *opaque, const char *name,
 115                                     Error **errp)
 116 {
 117     PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
 118     uint32_t value = e->size;
 119
 120     visit_type_uint32(v, &value, name, errp);
 121 }
 122
 123 static Property mch_props[] = {
 124     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
 125                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
 126     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
 127                      mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
 128     DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0),
 129     DEFINE_PROP_END_OF_LIST(),
 130 };
 131
 132 static void q35_host_class_init(ObjectClass *klass, void *data)
 133 {
 134     DeviceClass *dc = DEVICE_CLASS(klass);
 135     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
 136
 137     hc->root_bus_path = q35_host_root_bus_path;
 138     dc->realize = q35_host_realize;
 139     dc->props = mch_props;
 140     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 141     dc->fw_name = "pci";
 142 }
 143
 144 static void q35_host_initfn(Object *obj)
 145 {
 146     Q35PCIHost *s = Q35_HOST_DEVICE(obj);
 147     PCIHostState *phb = PCI_HOST_BRIDGE(obj);
 148
 149     memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb,
 150                           "pci-conf-idx", 4);
 151     memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb,
 152                           "pci-conf-data", 4);
 153
 154     object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE);
 155     object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
 156     qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
 157     qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
 158
 159     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
 160                         q35_host_get_pci_hole_start,
 161                         NULL, NULL, NULL, NULL);
 162
 163     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
 164                         q35_host_get_pci_hole_end,
 165                         NULL, NULL, NULL, NULL);
 166
 167     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
 168                         q35_host_get_pci_hole64_start,
 169                         NULL, NULL, NULL, NULL);
 170
 171     object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
 172                         q35_host_get_pci_hole64_end,
 173                         NULL, NULL, NULL, NULL);
 174
 175     object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
 176                         q35_host_get_mmcfg_size,
 177                         NULL, NULL, NULL, NULL);
 178
 179     /* Leave enough space for the biggest MCFG BAR */
 180     /* TODO: this matches current bios behaviour, but
 181      * it's not a power of two, which means an MTRR
 182      * can't cover it exactly.
 183      */
 184     s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
 185         MCH_HOST_BRIDGE_PCIEXBAR_MAX;
 186     s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
 187 }
 188
 189 static const TypeInfo q35_host_info = {
 190     .name       = TYPE_Q35_HOST_DEVICE,
 191     .parent     = TYPE_PCIE_HOST_BRIDGE,
 192     .instance_size = sizeof(Q35PCIHost),
 193     .instance_init = q35_host_initfn,
 194     .class_init = q35_host_class_init,
 195 };
 196
 197 /****************************************************************************
 198  * MCH D0:F0
 199  */
 200
 201 /* PCIe MMCFG */
 202 static void mch_update_pciexbar(MCHPCIState *mch)
 203 {
 204     PCIDevice *pci_dev = PCI_DEVICE(mch);
 205     BusState *bus = qdev_get_parent_bus(DEVICE(mch));
 206     PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent);
 207
 208     uint64_t pciexbar;
 209     int enable;
 210     uint64_t addr;
 211     uint64_t addr_mask;
 212     uint32_t length;
 213
 214     pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR);
 215     enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN;
 216     addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
 217     switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
 218     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
 219         length = 256 * 1024 * 1024;
 220         break;
 221     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
 222         length = 128 * 1024 * 1024;
 223         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
 224             MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 225         break;
 226     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
 227         length = 64 * 1024 * 1024;
 228         addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
 229         break;
 230     case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
 231     default:
 232         enable = 0;
 233         length = 0;
 234         abort();
 235         break;
 236     }
 237     addr = pciexbar & addr_mask;
 238     pcie_host_mmcfg_update(pehb, enable, addr, length);
 239     /* Leave enough space for the MCFG BAR */
 240     /*
 241      * TODO: this matches current bios behaviour, but it's not a power of two,
 242      * which means an MTRR can't cover it exactly.
 243      */
 244     if (enable) {
 245         mch->pci_info.w32.begin = addr + length;
 246     } else {
 247         mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
 248     }
 249 }
 250
 251 /* PAM */
 252 static void mch_update_pam(MCHPCIState *mch)
 253 {
 254     PCIDevice *pd = PCI_DEVICE(mch);
 255     int i;
 256
 257     memory_region_transaction_begin();
 258     for (i = 0; i < 13; i++) {
 259         pam_update(&mch->pam_regions[i], i,
 260                    pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]);
 261     }
 262     memory_region_transaction_commit();
 263 }
 264
 265 /* SMRAM */
 266 static void mch_update_smram(MCHPCIState *mch)
 267 {
 268     PCIDevice *pd = PCI_DEVICE(mch);
 269     bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME);
 270
 271     memory_region_transaction_begin();
 272
 273     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) {
 274         /* Hide (!) low SMRAM if H_SMRAME = 1 */
 275         memory_region_set_enabled(&mch->smram_region, h_smrame);
 276         /* Show high SMRAM if H_SMRAME = 1 */
 277         memory_region_set_enabled(&mch->open_high_smram, h_smrame);
 278     } else {
 279         /* Hide high SMRAM and low SMRAM */
 280         memory_region_set_enabled(&mch->smram_region, true);
 281         memory_region_set_enabled(&mch->open_high_smram, false);
 282     }
 283
 284     if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) {
 285         memory_region_set_enabled(&mch->low_smram, !h_smrame);
 286         memory_region_set_enabled(&mch->high_smram, h_smrame);
 287     } else {
 288         memory_region_set_enabled(&mch->low_smram, false);
 289         memory_region_set_enabled(&mch->high_smram, false);
 290     }
 291
 292     memory_region_transaction_commit();
 293 }
 294
 295 static void mch_write_config(PCIDevice *d,
 296                               uint32_t address, uint32_t val, int len)
 297 {
 298     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 299
 300     /* XXX: implement SMRAM.D_LOCK */
 301     pci_default_write_config(d, address, val, len);
 302
 303     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0,
 304                        MCH_HOST_BRIDGE_PAM_SIZE)) {
 305         mch_update_pam(mch);
 306     }
 307
 308     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR,
 309                        MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
 310         mch_update_pciexbar(mch);
 311     }
 312
 313     if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
 314                        MCH_HOST_BRIDGE_SMRAM_SIZE)) {
 315         mch_update_smram(mch);
 316     }
 317 }
 318
 319 static void mch_update(MCHPCIState *mch)
 320 {
 321     mch_update_pciexbar(mch);
 322     mch_update_pam(mch);
 323     mch_update_smram(mch);
 324 }
 325
 326 static int mch_post_load(void *opaque, int version_id)
 327 {
 328     MCHPCIState *mch = opaque;
 329     mch_update(mch);
 330     return 0;
 331 }
 332
 333 static const VMStateDescription vmstate_mch = {
 334     .name = "mch",
 335     .version_id = 1,
 336     .minimum_version_id = 1,
 337     .post_load = mch_post_load,
 338     .fields = (VMStateField[]) {
 339         VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState),
 340         /* Used to be smm_enabled, which was basically always zero because
 341          * SeaBIOS hardly uses SMM.  SMRAM is now handled by CPU code.
 342          */
 343         VMSTATE_UNUSED(1),
 344         VMSTATE_END_OF_LIST()
 345     }
 346 };
 347
 348 static void mch_reset(DeviceState *qdev)
 349 {
 350     PCIDevice *d = PCI_DEVICE(qdev);
 351     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 352
 353     pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
 354                  MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
 355
 356     d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
 357
 358     mch_update(mch);
 359 }
 360
 361 static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 362 {
 363     IntelIOMMUState *s = opaque;
 364     VTDAddressSpace **pvtd_as;
 365     int bus_num = pci_bus_num(bus);
 366
 367     assert(0 <= bus_num && bus_num <= VTD_PCI_BUS_MAX);
 368     assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX);
 369
 370     pvtd_as = s->address_spaces[bus_num];
 371     if (!pvtd_as) {
 372         /* No corresponding free() */
 373         pvtd_as = g_malloc0(sizeof(VTDAddressSpace *) * VTD_PCI_DEVFN_MAX);
 374         s->address_spaces[bus_num] = pvtd_as;
 375     }
 376     if (!pvtd_as[devfn]) {
 377         pvtd_as[devfn] = g_malloc0(sizeof(VTDAddressSpace));
 378
 379         pvtd_as[devfn]->bus_num = (uint8_t)bus_num;
 380         pvtd_as[devfn]->devfn = (uint8_t)devfn;
 381         pvtd_as[devfn]->iommu_state = s;
 382         pvtd_as[devfn]->context_cache_entry.context_cache_gen = 0;
 383         memory_region_init_iommu(&pvtd_as[devfn]->iommu, OBJECT(s),
 384                                  &s->iommu_ops, "intel_iommu", UINT64_MAX);
 385         address_space_init(&pvtd_as[devfn]->as,
 386                            &pvtd_as[devfn]->iommu, "intel_iommu");
 387     }
 388     return &pvtd_as[devfn]->as;
 389 }
 390
 391 static void mch_init_dmar(MCHPCIState *mch)
 392 {
 393     PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch)));
 394
 395     mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE));
 396     object_property_add_child(OBJECT(mch), "intel-iommu",
 397                               OBJECT(mch->iommu), NULL);
 398     qdev_init_nofail(DEVICE(mch->iommu));
 399     sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
 400
 401     pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu);
 402 }
 403
 404 static void mch_realize(PCIDevice *d, Error **errp)
 405 {
 406     int i;
 407     MCHPCIState *mch = MCH_PCI_DEVICE(d);
 408
 409     /* setup pci memory mapping */
 410     pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
 411                            mch->pci_address_space);
 412
 413     /* if *disabled* show SMRAM to all CPUs */
 414     memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
 415                              mch->pci_address_space, 0xa0000, 0x20000);
 416     memory_region_add_subregion_overlap(mch->system_memory, 0xa0000,
 417                                         &mch->smram_region, 1);
 418     memory_region_set_enabled(&mch->smram_region, true);
 419
 420     memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high",
 421                              mch->ram_memory, 0xa0000, 0x20000);
 422     memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000,
 423                                         &mch->open_high_smram, 1);
 424     memory_region_set_enabled(&mch->open_high_smram, false);
 425
 426     /* smram, as seen by SMM CPUs */
 427     memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32);
 428     memory_region_set_enabled(&mch->smram, true);
 429     memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low",
 430                              mch->ram_memory, 0xa0000, 0x20000);
 431     memory_region_set_enabled(&mch->low_smram, true);
 432     memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram);
 433     memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high",
 434                              mch->ram_memory, 0xa0000, 0x20000);
 435     memory_region_set_enabled(&mch->high_smram, true);
 436     memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram);
 437     object_property_add_const_link(qdev_get_machine(), "smram",
 438                                    OBJECT(&mch->smram), &error_abort);
 439
 440     init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
 441              mch->pci_address_space, &mch->pam_regions[0],
 442              PAM_BIOS_BASE, PAM_BIOS_SIZE);
 443     for (i = 0; i < 12; ++i) {
 444         init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory,
 445                  mch->pci_address_space, &mch->pam_regions[i+1],
 446                  PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE);
 447     }
 448     /* Intel IOMMU (VT-d) */
 449     if (machine_iommu(current_machine)) {
 450         mch_init_dmar(mch);
 451     }
 452 }
 453
 454 uint64_t mch_mcfg_base(void)
 455 {
 456     bool ambiguous;
 457     Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
 458     if (!o) {
 459         return 0;
 460     }
 461     return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
 462 }
 463
 464 static void mch_class_init(ObjectClass *klass, void *data)
 465 {
 466     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 467     DeviceClass *dc = DEVICE_CLASS(klass);
 468
 469     k->realize = mch_realize;
 470     k->config_write = mch_write_config;
 471     dc->reset = mch_reset;
 472     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 473     dc->desc = "Host bridge";
 474     dc->vmsd = &vmstate_mch;
 475     k->vendor_id = PCI_VENDOR_ID_INTEL;
 476     k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
 477     k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
 478     k->class_id = PCI_CLASS_BRIDGE_HOST;
 479     /*
 480      * PCI-facing part of the host bridge, not usable without the
 481      * host-facing part, which can't be device_add'ed, yet.
 482      */
 483     dc->cannot_instantiate_with_device_add_yet = true;
 484 }
 485
 486 static const TypeInfo mch_info = {
 487     .name = TYPE_MCH_PCI_DEVICE,
 488     .parent = TYPE_PCI_DEVICE,
 489     .instance_size = sizeof(MCHPCIState),
 490     .class_init = mch_class_init,
 491 };
 492
 493 static void q35_register(void)
 494 {
 495     type_register_static(&mch_info);
 496     type_register_static(&q35_host_info);
 497 }
 498
 499 type_init(q35_register);