hw/sd/milkymist-memcard.c

   1 /*
   2  *  QEMU model of the Milkymist SD Card Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <[email protected]>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/memcard.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "qemu/log.h"
  26 #include "hw/hw.h"
  27 #include "hw/sysbus.h"
  28 #include "sysemu/sysemu.h"
  29 #include "trace.h"
  30 #include "include/qapi/error.h"
  31 #include "sysemu/block-backend.h"
  32 #include "sysemu/blockdev.h"
  33 #include "hw/sd/sd.h"
  34
  35 enum {
  36     ENABLE_CMD_TX   = (1<<0),
  37     ENABLE_CMD_RX   = (1<<1),
  38     ENABLE_DAT_TX   = (1<<2),
  39     ENABLE_DAT_RX   = (1<<3),
  40 };
  41
  42 enum {
  43     PENDING_CMD_TX   = (1<<0),
  44     PENDING_CMD_RX   = (1<<1),
  45     PENDING_DAT_TX   = (1<<2),
  46     PENDING_DAT_RX   = (1<<3),
  47 };
  48
  49 enum {
  50     START_CMD_TX    = (1<<0),
  51     START_DAT_RX    = (1<<1),
  52 };
  53
  54 enum {
  55     R_CLK2XDIV = 0,
  56     R_ENABLE,
  57     R_PENDING,
  58     R_START,
  59     R_CMD,
  60     R_DAT,
  61     R_MAX
  62 };
  63
  64 #define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
  65 #define MILKYMIST_MEMCARD(obj) \
  66     OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
  67
  68 struct MilkymistMemcardState {
  69     SysBusDevice parent_obj;
  70
  71     MemoryRegion regs_region;
  72     SDBus sdbus;
  73
  74     int command_write_ptr;
  75     int response_read_ptr;
  76     int response_len;
  77     int ignore_next_cmd;
  78     int enabled;
  79     uint8_t command[6];
  80     uint8_t response[17];
  81     uint32_t regs[R_MAX];
  82 };
  83 typedef struct MilkymistMemcardState MilkymistMemcardState;
  84
  85 static void update_pending_bits(MilkymistMemcardState *s)
  86 {
  87     /* transmits are instantaneous, thus tx pending bits are never set */
  88     s->regs[R_PENDING] = 0;
  89     /* if rx is enabled the corresponding pending bits are always set */
  90     if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
  91         s->regs[R_PENDING] |= PENDING_CMD_RX;
  92     }
  93     if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
  94         s->regs[R_PENDING] |= PENDING_DAT_RX;
  95     }
  96 }
  97
  98 static void memcard_sd_command(MilkymistMemcardState *s)
  99 {
 100     SDRequest req;
 101
 102     req.cmd = s->command[0] & 0x3f;
 103     req.arg = (s->command[1] << 24) | (s->command[2] << 16)
 104               | (s->command[3] << 8) | s->command[4];
 105     req.crc = s->command[5];
 106
 107     s->response[0] = req.cmd;
 108     s->response_len = sdbus_do_command(&s->sdbus, &req, s->response + 1);
 109     s->response_read_ptr = 0;
 110
 111     if (s->response_len == 16) {
 112         /* R2 response */
 113         s->response[0] = 0x3f;
 114         s->response_len += 1;
 115     } else if (s->response_len == 4) {
 116         /* no crc calculation, insert dummy byte */
 117         s->response[5] = 0;
 118         s->response_len += 2;
 119     }
 120
 121     if (req.cmd == 0) {
 122         /* next write is a dummy byte to clock the initialization of the sd
 123          * card */
 124         s->ignore_next_cmd = 1;
 125     }
 126 }
 127
 128 static uint64_t memcard_read(void *opaque, hwaddr addr,
 129                              unsigned size)
 130 {
 131     MilkymistMemcardState *s = opaque;
 132     uint32_t r = 0;
 133
 134     addr >>= 2;
 135     switch (addr) {
 136     case R_CMD:
 137         if (!s->enabled) {
 138             r = 0xff;
 139         } else {
 140             r = s->response[s->response_read_ptr++];
 141             if (s->response_read_ptr > s->response_len) {
 142                 qemu_log_mask(LOG_GUEST_ERROR, "milkymist_memcard: "
 143                               "read more cmd bytes than available. Clipping.");
 144                 s->response_read_ptr = 0;
 145             }
 146         }
 147         break;
 148     case R_DAT:
 149         if (!s->enabled) {
 150             r = 0xffffffff;
 151         } else {
 152             r = 0;
 153             r |= sdbus_read_data(&s->sdbus) << 24;
 154             r |= sdbus_read_data(&s->sdbus) << 16;
 155             r |= sdbus_read_data(&s->sdbus) << 8;
 156             r |= sdbus_read_data(&s->sdbus);
 157         }
 158         break;
 159     case R_CLK2XDIV:
 160     case R_ENABLE:
 161     case R_PENDING:
 162     case R_START:
 163         r = s->regs[addr];
 164         break;
 165
 166     default:
 167         qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
 168                       "read access to unknown register 0x%" HWADDR_PRIx "\n",
 169                       addr << 2);
 170         break;
 171     }
 172
 173     trace_milkymist_memcard_memory_read(addr << 2, r);
 174
 175     return r;
 176 }
 177
 178 static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
 179                           unsigned size)
 180 {
 181     MilkymistMemcardState *s = opaque;
 182
 183     trace_milkymist_memcard_memory_write(addr, value);
 184
 185     addr >>= 2;
 186     switch (addr) {
 187     case R_PENDING:
 188         /* clear rx pending bits */
 189         s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
 190         update_pending_bits(s);
 191         break;
 192     case R_CMD:
 193         if (!s->enabled) {
 194             break;
 195         }
 196         if (s->ignore_next_cmd) {
 197             s->ignore_next_cmd = 0;
 198             break;
 199         }
 200         s->command[s->command_write_ptr] = value & 0xff;
 201         s->command_write_ptr = (s->command_write_ptr + 1) % 6;
 202         if (s->command_write_ptr == 0) {
 203             memcard_sd_command(s);
 204         }
 205         break;
 206     case R_DAT:
 207         if (!s->enabled) {
 208             break;
 209         }
 210         sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
 211         sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
 212         sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
 213         sdbus_write_data(&s->sdbus, value & 0xff);
 214         break;
 215     case R_ENABLE:
 216         s->regs[addr] = value;
 217         update_pending_bits(s);
 218         break;
 219     case R_CLK2XDIV:
 220     case R_START:
 221         s->regs[addr] = value;
 222         break;
 223
 224     default:
 225         qemu_log_mask(LOG_UNIMP, "milkymist_memcard: "
 226                       "write access to unknown register 0x%" HWADDR_PRIx " "
 227                       "(value 0x%" PRIx64 ")\n", addr << 2, value);
 228         break;
 229     }
 230 }
 231
 232 static const MemoryRegionOps memcard_mmio_ops = {
 233     .read = memcard_read,
 234     .write = memcard_write,
 235     .valid = {
 236         .min_access_size = 4,
 237         .max_access_size = 4,
 238     },
 239     .endianness = DEVICE_NATIVE_ENDIAN,
 240 };
 241
 242 static void milkymist_memcard_reset(DeviceState *d)
 243 {
 244     MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
 245     int i;
 246
 247     s->command_write_ptr = 0;
 248     s->response_read_ptr = 0;
 249     s->response_len = 0;
 250
 251     for (i = 0; i < R_MAX; i++) {
 252         s->regs[i] = 0;
 253     }
 254 }
 255
 256 static void milkymist_memcard_init(Object *obj)
 257 {
 258     MilkymistMemcardState *s = MILKYMIST_MEMCARD(obj);
 259     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 260
 261     memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
 262             "milkymist-memcard", R_MAX * 4);
 263     sysbus_init_mmio(dev, &s->regs_region);
 264 }
 265
 266 static void milkymist_memcard_realize(DeviceState *dev, Error **errp)
 267 {
 268     MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
 269     DeviceState *carddev;
 270     BlockBackend *blk;
 271     DriveInfo *dinfo;
 272     Error *err = NULL;
 273
 274     qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), TYPE_SD_BUS,
 275                         dev, "sd-bus");
 276
 277     /* Create and plug in the sd card */
 278     /* FIXME use a qdev drive property instead of drive_get_next() */
 279     dinfo = drive_get_next(IF_SD);
 280     blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL;
 281     carddev = qdev_create(&s->sdbus.qbus, TYPE_SD_CARD);
 282     qdev_prop_set_drive(carddev, "drive", blk, &err);
 283     object_property_set_bool(OBJECT(carddev), true, "realized", &err);
 284     if (err) {
 285         error_setg(errp, "failed to init SD card: %s", error_get_pretty(err));
 286         return;
 287     }
 288     s->enabled = blk && blk_is_inserted(blk);
 289 }
 290
 291 static const VMStateDescription vmstate_milkymist_memcard = {
 292     .name = "milkymist-memcard",
 293     .version_id = 1,
 294     .minimum_version_id = 1,
 295     .fields = (VMStateField[]) {
 296         VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
 297         VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
 298         VMSTATE_INT32(response_len, MilkymistMemcardState),
 299         VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
 300         VMSTATE_INT32(enabled, MilkymistMemcardState),
 301         VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
 302         VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
 303         VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
 304         VMSTATE_END_OF_LIST()
 305     }
 306 };
 307
 308 static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
 309 {
 310     DeviceClass *dc = DEVICE_CLASS(klass);
 311
 312     dc->realize = milkymist_memcard_realize;
 313     dc->reset = milkymist_memcard_reset;
 314     dc->vmsd = &vmstate_milkymist_memcard;
 315     /* Reason: init() method uses drive_get_next() */
 316     dc->user_creatable = false;
 317 }
 318
 319 static const TypeInfo milkymist_memcard_info = {
 320     .name          = TYPE_MILKYMIST_MEMCARD,
 321     .parent        = TYPE_SYS_BUS_DEVICE,
 322     .instance_size = sizeof(MilkymistMemcardState),
 323     .instance_init = milkymist_memcard_init,
 324     .class_init    = milkymist_memcard_class_init,
 325 };
 326
 327 static void milkymist_memcard_register_types(void)
 328 {
 329     type_register_static(&milkymist_memcard_info);
 330 }
 331
 332 type_init(milkymist_memcard_register_types)