hw/intc/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "hw/i386/apic.h"
  23 #include "hw/i386/apic_internal.h"
  24 #include "trace.h"
  25 #include "sysemu/kvm.h"
  26 #include "hw/qdev.h"
  27 #include "hw/sysbus.h"
  28
  29 static int apic_irq_delivered;
  30 bool apic_report_tpr_access;
  31
  32 void cpu_set_apic_base(DeviceState *dev, uint64_t val)
  33 {
  34     trace_cpu_set_apic_base(val);
  35
  36     if (dev) {
  37         APICCommonState *s = APIC_COMMON(dev);
  38         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  39         info->set_base(s, val);
  40     }
  41 }
  42
  43 uint64_t cpu_get_apic_base(DeviceState *dev)
  44 {
  45     if (dev) {
  46         APICCommonState *s = APIC_COMMON(dev);
  47         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  48         return s->apicbase;
  49     } else {
  50         trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP);
  51         return MSR_IA32_APICBASE_BSP;
  52     }
  53 }
  54
  55 void cpu_set_apic_tpr(DeviceState *dev, uint8_t val)
  56 {
  57     APICCommonState *s;
  58     APICCommonClass *info;
  59
  60     if (!dev) {
  61         return;
  62     }
  63
  64     s = APIC_COMMON(dev);
  65     info = APIC_COMMON_GET_CLASS(s);
  66
  67     info->set_tpr(s, val);
  68 }
  69
  70 uint8_t cpu_get_apic_tpr(DeviceState *dev)
  71 {
  72     APICCommonState *s;
  73     APICCommonClass *info;
  74
  75     if (!dev) {
  76         return 0;
  77     }
  78
  79     s = APIC_COMMON(dev);
  80     info = APIC_COMMON_GET_CLASS(s);
  81
  82     return info->get_tpr(s);
  83 }
  84
  85 void apic_enable_tpr_access_reporting(DeviceState *dev, bool enable)
  86 {
  87     APICCommonState *s = APIC_COMMON(dev);
  88     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  89
  90     apic_report_tpr_access = enable;
  91     if (info->enable_tpr_reporting) {
  92         info->enable_tpr_reporting(s, enable);
  93     }
  94 }
  95
  96 void apic_enable_vapic(DeviceState *dev, hwaddr paddr)
  97 {
  98     APICCommonState *s = APIC_COMMON(dev);
  99     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 100
 101     s->vapic_paddr = paddr;
 102     info->vapic_base_update(s);
 103 }
 104
 105 void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
 106                                    TPRAccess access)
 107 {
 108     APICCommonState *s = APIC_COMMON(dev);
 109
 110     vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
 111 }
 112
 113 void apic_report_irq_delivered(int delivered)
 114 {
 115     apic_irq_delivered += delivered;
 116
 117     trace_apic_report_irq_delivered(apic_irq_delivered);
 118 }
 119
 120 void apic_reset_irq_delivered(void)
 121 {
 122     /* Copy this into a local variable to encourage gcc to emit a plain
 123      * register for a sys/sdt.h marker.  For details on this workaround, see:
 124      * https://sourceware.org/bugzilla/show_bug.cgi?id=13296
 125      */
 126     volatile int a_i_d = apic_irq_delivered;
 127     trace_apic_reset_irq_delivered(a_i_d);
 128
 129     apic_irq_delivered = 0;
 130 }
 131
 132 int apic_get_irq_delivered(void)
 133 {
 134     trace_apic_get_irq_delivered(apic_irq_delivered);
 135
 136     return apic_irq_delivered;
 137 }
 138
 139 void apic_deliver_nmi(DeviceState *dev)
 140 {
 141     APICCommonState *s = APIC_COMMON(dev);
 142     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 143
 144     info->external_nmi(s);
 145 }
 146
 147 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 148 {
 149     int64_t d;
 150
 151     /* We need to store the timer state separately to support APIC
 152      * implementations that maintain a non-QEMU timer, e.g. inside the
 153      * host kernel. This open-coded state allows us to migrate between
 154      * both models. */
 155     s->timer_expiry = -1;
 156
 157     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 158         return false;
 159     }
 160
 161     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 162
 163     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 164         if (!s->initial_count) {
 165             return false;
 166         }
 167         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 168             ((uint64_t)s->initial_count + 1);
 169     } else {
 170         if (d >= s->initial_count) {
 171             return false;
 172         }
 173         d = (uint64_t)s->initial_count + 1;
 174     }
 175     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 176     s->timer_expiry = s->next_time;
 177     return true;
 178 }
 179
 180 void apic_init_reset(DeviceState *dev)
 181 {
 182     APICCommonState *s;
 183     APICCommonClass *info;
 184     int i;
 185
 186     if (!dev) {
 187         return;
 188     }
 189     s = APIC_COMMON(dev);
 190     s->tpr = 0;
 191     s->spurious_vec = 0xff;
 192     s->log_dest = 0;
 193     s->dest_mode = 0xf;
 194     memset(s->isr, 0, sizeof(s->isr));
 195     memset(s->tmr, 0, sizeof(s->tmr));
 196     memset(s->irr, 0, sizeof(s->irr));
 197     for (i = 0; i < APIC_LVT_NB; i++) {
 198         s->lvt[i] = APIC_LVT_MASKED;
 199     }
 200     s->esr = 0;
 201     memset(s->icr, 0, sizeof(s->icr));
 202     s->divide_conf = 0;
 203     s->count_shift = 0;
 204     s->initial_count = 0;
 205     s->initial_count_load_time = 0;
 206     s->next_time = 0;
 207     s->wait_for_sipi = !cpu_is_bsp(s->cpu);
 208
 209     if (s->timer) {
 210         timer_del(s->timer);
 211     }
 212     s->timer_expiry = -1;
 213
 214     info = APIC_COMMON_GET_CLASS(s);
 215     if (info->reset) {
 216         info->reset(s);
 217     }
 218 }
 219
 220 void apic_designate_bsp(DeviceState *dev, bool bsp)
 221 {
 222     if (dev == NULL) {
 223         return;
 224     }
 225
 226     APICCommonState *s = APIC_COMMON(dev);
 227     if (bsp) {
 228         s->apicbase |= MSR_IA32_APICBASE_BSP;
 229     } else {
 230         s->apicbase &= ~MSR_IA32_APICBASE_BSP;
 231     }
 232 }
 233
 234 static void apic_reset_common(DeviceState *dev)
 235 {
 236     APICCommonState *s = APIC_COMMON(dev);
 237     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 238     uint32_t bsp;
 239
 240     bsp = s->apicbase & MSR_IA32_APICBASE_BSP;
 241     s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE;
 242
 243     s->vapic_paddr = 0;
 244     info->vapic_base_update(s);
 245
 246     apic_init_reset(dev);
 247 }
 248
 249 /* This function is only used for old state version 1 and 2 */
 250 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 251 {
 252     APICCommonState *s = opaque;
 253     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 254     int i;
 255
 256     if (version_id > 2) {
 257         return -EINVAL;
 258     }
 259
 260     /* XXX: what if the base changes? (registered memory regions) */
 261     qemu_get_be32s(f, &s->apicbase);
 262     qemu_get_8s(f, &s->id);
 263     qemu_get_8s(f, &s->arb_id);
 264     qemu_get_8s(f, &s->tpr);
 265     qemu_get_be32s(f, &s->spurious_vec);
 266     qemu_get_8s(f, &s->log_dest);
 267     qemu_get_8s(f, &s->dest_mode);
 268     for (i = 0; i < 8; i++) {
 269         qemu_get_be32s(f, &s->isr[i]);
 270         qemu_get_be32s(f, &s->tmr[i]);
 271         qemu_get_be32s(f, &s->irr[i]);
 272     }
 273     for (i = 0; i < APIC_LVT_NB; i++) {
 274         qemu_get_be32s(f, &s->lvt[i]);
 275     }
 276     qemu_get_be32s(f, &s->esr);
 277     qemu_get_be32s(f, &s->icr[0]);
 278     qemu_get_be32s(f, &s->icr[1]);
 279     qemu_get_be32s(f, &s->divide_conf);
 280     s->count_shift = qemu_get_be32(f);
 281     qemu_get_be32s(f, &s->initial_count);
 282     s->initial_count_load_time = qemu_get_be64(f);
 283     s->next_time = qemu_get_be64(f);
 284
 285     if (version_id >= 2) {
 286         s->timer_expiry = qemu_get_be64(f);
 287     }
 288
 289     if (info->post_load) {
 290         info->post_load(s);
 291     }
 292     return 0;
 293 }
 294
 295 static void apic_common_realize(DeviceState *dev, Error **errp)
 296 {
 297     APICCommonState *s = APIC_COMMON(dev);
 298     APICCommonClass *info;
 299     static DeviceState *vapic;
 300     static int apic_no;
 301
 302     if (apic_no >= MAX_APICS) {
 303         error_setg(errp, "%s initialization failed.",
 304                    object_get_typename(OBJECT(dev)));
 305         return;
 306     }
 307     s->idx = apic_no++;
 308
 309     info = APIC_COMMON_GET_CLASS(s);
 310     info->realize(dev, errp);
 311
 312     /* Note: We need at least 1M to map the VAPIC option ROM */
 313     if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK &&
 314         ram_size >= 1024 * 1024) {
 315         vapic = sysbus_create_simple("kvmvapic", -1, NULL);
 316     }
 317     s->vapic = vapic;
 318     if (apic_report_tpr_access && info->enable_tpr_reporting) {
 319         info->enable_tpr_reporting(s, true);
 320     }
 321
 322 }
 323
 324 static int apic_pre_load(void *opaque)
 325 {
 326     APICCommonState *s = APIC_COMMON(opaque);
 327
 328     /* The default is !cpu_is_bsp(s->cpu), but the common value is 0
 329      * so that's what apic_common_sipi_needed checks for.  Reset to
 330      * the value that is assumed when the apic_sipi subsection is
 331      * absent.
 332      */
 333     s->wait_for_sipi = 0;
 334     return 0;
 335 }
 336
 337 static void apic_dispatch_pre_save(void *opaque)
 338 {
 339     APICCommonState *s = APIC_COMMON(opaque);
 340     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 341
 342     if (info->pre_save) {
 343         info->pre_save(s);
 344     }
 345 }
 346
 347 static int apic_dispatch_post_load(void *opaque, int version_id)
 348 {
 349     APICCommonState *s = APIC_COMMON(opaque);
 350     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 351
 352     if (info->post_load) {
 353         info->post_load(s);
 354     }
 355     return 0;
 356 }
 357
 358 static bool apic_common_sipi_needed(void *opaque)
 359 {
 360     APICCommonState *s = APIC_COMMON(opaque);
 361     return s->wait_for_sipi != 0;
 362 }
 363
 364 static const VMStateDescription vmstate_apic_common_sipi = {
 365     .name = "apic_sipi",
 366     .version_id = 1,
 367     .minimum_version_id = 1,
 368     .needed = apic_common_sipi_needed,
 369     .fields = (VMStateField[]) {
 370         VMSTATE_INT32(sipi_vector, APICCommonState),
 371         VMSTATE_INT32(wait_for_sipi, APICCommonState),
 372         VMSTATE_END_OF_LIST()
 373     }
 374 };
 375
 376 static const VMStateDescription vmstate_apic_common = {
 377     .name = "apic",
 378     .version_id = 3,
 379     .minimum_version_id = 3,
 380     .minimum_version_id_old = 1,
 381     .load_state_old = apic_load_old,
 382     .pre_load = apic_pre_load,
 383     .pre_save = apic_dispatch_pre_save,
 384     .post_load = apic_dispatch_post_load,
 385     .fields = (VMStateField[]) {
 386         VMSTATE_UINT32(apicbase, APICCommonState),
 387         VMSTATE_UINT8(id, APICCommonState),
 388         VMSTATE_UINT8(arb_id, APICCommonState),
 389         VMSTATE_UINT8(tpr, APICCommonState),
 390         VMSTATE_UINT32(spurious_vec, APICCommonState),
 391         VMSTATE_UINT8(log_dest, APICCommonState),
 392         VMSTATE_UINT8(dest_mode, APICCommonState),
 393         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 394         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 395         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 396         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 397         VMSTATE_UINT32(esr, APICCommonState),
 398         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 399         VMSTATE_UINT32(divide_conf, APICCommonState),
 400         VMSTATE_INT32(count_shift, APICCommonState),
 401         VMSTATE_UINT32(initial_count, APICCommonState),
 402         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 403         VMSTATE_INT64(next_time, APICCommonState),
 404         VMSTATE_INT64(timer_expiry,
 405                       APICCommonState), /* open-coded timer state */
 406         VMSTATE_END_OF_LIST()
 407     },
 408     .subsections = (const VMStateDescription*[]) {
 409         &vmstate_apic_common_sipi,
 410         NULL
 411     }
 412 };
 413
 414 static Property apic_properties_common[] = {
 415     DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
 416     DEFINE_PROP_UINT8("version", APICCommonState, version, 0x14),
 417     DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT,
 418                     true),
 419     DEFINE_PROP_END_OF_LIST(),
 420 };
 421
 422 static void apic_common_class_init(ObjectClass *klass, void *data)
 423 {
 424     DeviceClass *dc = DEVICE_CLASS(klass);
 425
 426     dc->vmsd = &vmstate_apic_common;
 427     dc->reset = apic_reset_common;
 428     dc->props = apic_properties_common;
 429     dc->realize = apic_common_realize;
 430     /*
 431      * Reason: APIC and CPU need to be wired up by
 432      * x86_cpu_apic_create()
 433      */
 434     dc->cannot_instantiate_with_device_add_yet = true;
 435 }
 436
 437 static const TypeInfo apic_common_type = {
 438     .name = TYPE_APIC_COMMON,
 439     .parent = TYPE_DEVICE,
 440     .instance_size = sizeof(APICCommonState),
 441     .class_size = sizeof(APICCommonClass),
 442     .class_init = apic_common_class_init,
 443     .abstract = true,
 444 };
 445
 446 static void apic_common_register_types(void)
 447 {
 448     type_register_static(&apic_common_type);
 449 }
 450
 451 type_init(apic_common_register_types)