2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/units.h"
22 #include "qemu/cutils.h"
23 #include "qemu/bitops.h"
24 #include "qemu/qemu-print.h"
27 #include "exec/exec-all.h"
28 #include "sysemu/kvm.h"
29 #include "sysemu/hvf.h"
30 #include "sysemu/cpus.h"
34 #include "qemu/error-report.h"
35 #include "qemu/option.h"
36 #include "qemu/config-file.h"
37 #include "qapi/error.h"
38 #include "qapi/qapi-visit-misc.h"
39 #include "qapi/qapi-visit-run-state.h"
40 #include "qapi/qmp/qdict.h"
41 #include "qapi/qmp/qerror.h"
42 #include "qapi/visitor.h"
43 #include "qom/qom-qobject.h"
44 #include "sysemu/arch_init.h"
45 #include "qapi/qapi-commands-target.h"
47 #include "standard-headers/asm-x86/kvm_para.h"
49 #include "sysemu/sysemu.h"
50 #include "hw/qdev-properties.h"
51 #include "hw/i386/topology.h"
52 #ifndef CONFIG_USER_ONLY
53 #include "exec/address-spaces.h"
55 #include "hw/xen/xen.h"
56 #include "hw/i386/apic_internal.h"
59 #include "disas/capstone.h"
61 /* Helpers for building CPUID[2] descriptors: */
63 struct CPUID2CacheDescriptorInfo {
72 * Known CPUID 2 cache descriptors.
73 * From Intel SDM Volume 2A, CPUID instruction
75 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
76 [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 8 * KiB,
77 .associativity = 4, .line_size = 32, },
78 [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 16 * KiB,
79 .associativity = 4, .line_size = 32, },
80 [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
81 .associativity = 4, .line_size = 64, },
82 [0x0A] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
83 .associativity = 2, .line_size = 32, },
84 [0x0C] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
85 .associativity = 4, .line_size = 32, },
86 [0x0D] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
87 .associativity = 4, .line_size = 64, },
88 [0x0E] = { .level = 1, .type = DATA_CACHE, .size = 24 * KiB,
89 .associativity = 6, .line_size = 64, },
90 [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
91 .associativity = 2, .line_size = 64, },
92 [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
93 .associativity = 8, .line_size = 64, },
94 /* lines per sector is not supported cpuid2_cache_descriptor(),
95 * so descriptors 0x22, 0x23 are not included
97 [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
98 .associativity = 16, .line_size = 64, },
99 /* lines per sector is not supported cpuid2_cache_descriptor(),
100 * so descriptors 0x25, 0x20 are not included
102 [0x2C] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
103 .associativity = 8, .line_size = 64, },
104 [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size = 32 * KiB,
105 .associativity = 8, .line_size = 64, },
106 [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
107 .associativity = 4, .line_size = 32, },
108 [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
109 .associativity = 4, .line_size = 32, },
110 [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
111 .associativity = 4, .line_size = 32, },
112 [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
113 .associativity = 4, .line_size = 32, },
114 [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
115 .associativity = 4, .line_size = 32, },
116 [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
117 .associativity = 4, .line_size = 64, },
118 [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
119 .associativity = 8, .line_size = 64, },
120 [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size = 3 * MiB,
121 .associativity = 12, .line_size = 64, },
122 /* Descriptor 0x49 depends on CPU family/model, so it is not included */
123 [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
124 .associativity = 12, .line_size = 64, },
125 [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
126 .associativity = 16, .line_size = 64, },
127 [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
128 .associativity = 12, .line_size = 64, },
129 [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size = 16 * MiB,
130 .associativity = 16, .line_size = 64, },
131 [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size = 6 * MiB,
132 .associativity = 24, .line_size = 64, },
133 [0x60] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
134 .associativity = 8, .line_size = 64, },
135 [0x66] = { .level = 1, .type = DATA_CACHE, .size = 8 * KiB,
136 .associativity = 4, .line_size = 64, },
137 [0x67] = { .level = 1, .type = DATA_CACHE, .size = 16 * KiB,
138 .associativity = 4, .line_size = 64, },
139 [0x68] = { .level = 1, .type = DATA_CACHE, .size = 32 * KiB,
140 .associativity = 4, .line_size = 64, },
141 [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
142 .associativity = 4, .line_size = 64, },
143 /* lines per sector is not supported cpuid2_cache_descriptor(),
144 * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
146 [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
147 .associativity = 8, .line_size = 64, },
148 [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
149 .associativity = 2, .line_size = 64, },
150 [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
151 .associativity = 8, .line_size = 64, },
152 [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
153 .associativity = 8, .line_size = 32, },
154 [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
155 .associativity = 8, .line_size = 32, },
156 [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
157 .associativity = 8, .line_size = 32, },
158 [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size = 2 * MiB,
159 .associativity = 8, .line_size = 32, },
160 [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
161 .associativity = 4, .line_size = 64, },
162 [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size = 1 * MiB,
163 .associativity = 8, .line_size = 64, },
164 [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
165 .associativity = 4, .line_size = 64, },
166 [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
167 .associativity = 4, .line_size = 64, },
168 [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
169 .associativity = 4, .line_size = 64, },
170 [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size = 1 * MiB,
171 .associativity = 8, .line_size = 64, },
172 [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
173 .associativity = 8, .line_size = 64, },
174 [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
175 .associativity = 8, .line_size = 64, },
176 [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
177 .associativity = 12, .line_size = 64, },
178 [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size = 3 * MiB,
179 .associativity = 12, .line_size = 64, },
180 [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size = 6 * MiB,
181 .associativity = 12, .line_size = 64, },
182 [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size = 2 * MiB,
183 .associativity = 16, .line_size = 64, },
184 [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size = 4 * MiB,
185 .associativity = 16, .line_size = 64, },
186 [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size = 8 * MiB,
187 .associativity = 16, .line_size = 64, },
188 [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size = 12 * MiB,
189 .associativity = 24, .line_size = 64, },
190 [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size = 18 * MiB,
191 .associativity = 24, .line_size = 64, },
192 [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size = 24 * MiB,
193 .associativity = 24, .line_size = 64, },
197 * "CPUID leaf 2 does not report cache descriptor information,
198 * use CPUID leaf 4 to query cache parameters"
200 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
203 * Return a CPUID 2 cache descriptor for a given cache.
204 * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
206 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
210 assert(cache->size > 0);
211 assert(cache->level > 0);
212 assert(cache->line_size > 0);
213 assert(cache->associativity > 0);
214 for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
215 struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
216 if (d->level == cache->level && d->type == cache->type &&
217 d->size == cache->size && d->line_size == cache->line_size &&
218 d->associativity == cache->associativity) {
223 return CACHE_DESCRIPTOR_UNAVAILABLE;
226 /* CPUID Leaf 4 constants: */
229 #define CACHE_TYPE_D 1
230 #define CACHE_TYPE_I 2
231 #define CACHE_TYPE_UNIFIED 3
233 #define CACHE_LEVEL(l) (l << 5)
235 #define CACHE_SELF_INIT_LEVEL (1 << 8)
238 #define CACHE_NO_INVD_SHARING (1 << 0)
239 #define CACHE_INCLUSIVE (1 << 1)
240 #define CACHE_COMPLEX_IDX (1 << 2)
242 /* Encode CacheType for CPUID[4].EAX */
243 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
244 ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
245 ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
246 0 /* Invalid value */)
249 /* Encode cache info for CPUID[4] */
250 static void encode_cache_cpuid4(CPUCacheInfo *cache,
251 int num_apic_ids, int num_cores,
252 uint32_t *eax, uint32_t *ebx,
253 uint32_t *ecx, uint32_t *edx)
255 assert(cache->size == cache->line_size * cache->associativity *
256 cache->partitions * cache->sets);
258 assert(num_apic_ids > 0);
259 *eax = CACHE_TYPE(cache->type) |
260 CACHE_LEVEL(cache->level) |
261 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
262 ((num_cores - 1) << 26) |
263 ((num_apic_ids - 1) << 14);
265 assert(cache->line_size > 0);
266 assert(cache->partitions > 0);
267 assert(cache->associativity > 0);
268 /* We don't implement fully-associative caches */
269 assert(cache->associativity < cache->sets);
270 *ebx = (cache->line_size - 1) |
271 ((cache->partitions - 1) << 12) |
272 ((cache->associativity - 1) << 22);
274 assert(cache->sets > 0);
275 *ecx = cache->sets - 1;
277 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
278 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
279 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
282 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
283 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
285 assert(cache->size % 1024 == 0);
286 assert(cache->lines_per_tag > 0);
287 assert(cache->associativity > 0);
288 assert(cache->line_size > 0);
289 return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
290 (cache->lines_per_tag << 8) | (cache->line_size);
293 #define ASSOC_FULL 0xFF
295 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
296 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
306 a == ASSOC_FULL ? 0xF : \
307 0 /* invalid value */)
310 * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
313 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
315 uint32_t *ecx, uint32_t *edx)
317 assert(l2->size % 1024 == 0);
318 assert(l2->associativity > 0);
319 assert(l2->lines_per_tag > 0);
320 assert(l2->line_size > 0);
321 *ecx = ((l2->size / 1024) << 16) |
322 (AMD_ENC_ASSOC(l2->associativity) << 12) |
323 (l2->lines_per_tag << 8) | (l2->line_size);
326 assert(l3->size % (512 * 1024) == 0);
327 assert(l3->associativity > 0);
328 assert(l3->lines_per_tag > 0);
329 assert(l3->line_size > 0);
330 *edx = ((l3->size / (512 * 1024)) << 18) |
331 (AMD_ENC_ASSOC(l3->associativity) << 12) |
332 (l3->lines_per_tag << 8) | (l3->line_size);
339 * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E
340 * Please refer to the AMD64 Architecture Programmer’s Manual Volume 3.
341 * Define the constants to build the cpu topology. Right now, TOPOEXT
342 * feature is enabled only on EPYC. So, these constants are based on
343 * EPYC supported configurations. We may need to handle the cases if
344 * these values change in future.
346 /* Maximum core complexes in a node */
348 /* Maximum cores in a core complex */
349 #define MAX_CORES_IN_CCX 4
350 /* Maximum cores in a node */
351 #define MAX_CORES_IN_NODE 8
352 /* Maximum nodes in a socket */
353 #define MAX_NODES_PER_SOCKET 4
356 * Figure out the number of nodes required to build this config.
357 * Max cores in a node is 8
359 static int nodes_in_socket(int nr_cores)
363 nodes = DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE);
365 /* Hardware does not support config with 3 nodes, return 4 in that case */
366 return (nodes == 3) ? 4 : nodes;
370 * Decide the number of cores in a core complex with the given nr_cores using
371 * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and
372 * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible
373 * L3 cache is shared across all cores in a core complex. So, this will also
374 * tell us how many cores are sharing the L3 cache.
376 static int cores_in_core_complex(int nr_cores)
380 /* Check if we can fit all the cores in one core complex */
381 if (nr_cores <= MAX_CORES_IN_CCX) {
384 /* Get the number of nodes required to build this config */
385 nodes = nodes_in_socket(nr_cores);
388 * Divide the cores accros all the core complexes
389 * Return rounded up value
391 return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX);
394 /* Encode cache info for CPUID[8000001D] */
395 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs,
396 uint32_t *eax, uint32_t *ebx,
397 uint32_t *ecx, uint32_t *edx)
400 assert(cache->size == cache->line_size * cache->associativity *
401 cache->partitions * cache->sets);
403 *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
404 (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
406 /* L3 is shared among multiple cores */
407 if (cache->level == 3) {
408 l3_cores = cores_in_core_complex(cs->nr_cores);
409 *eax |= ((l3_cores * cs->nr_threads) - 1) << 14;
411 *eax |= ((cs->nr_threads - 1) << 14);
414 assert(cache->line_size > 0);
415 assert(cache->partitions > 0);
416 assert(cache->associativity > 0);
417 /* We don't implement fully-associative caches */
418 assert(cache->associativity < cache->sets);
419 *ebx = (cache->line_size - 1) |
420 ((cache->partitions - 1) << 12) |
421 ((cache->associativity - 1) << 22);
423 assert(cache->sets > 0);
424 *ecx = cache->sets - 1;
426 *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
427 (cache->inclusive ? CACHE_INCLUSIVE : 0) |
428 (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
431 /* Data structure to hold the configuration info for a given core index */
432 struct core_topology {
433 /* core complex id of the current core index */
436 * Adjusted core index for this core in the topology
437 * This can be 0,1,2,3 with max 4 cores in a core complex
440 /* Node id for this core index */
442 /* Number of nodes in this config */
447 * Build the configuration closely match the EPYC hardware. Using the EPYC
448 * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE)
449 * right now. This could change in future.
450 * nr_cores : Total number of cores in the config
451 * core_id : Core index of the current CPU
452 * topo : Data structure to hold all the config info for this core index
454 static void build_core_topology(int nr_cores, int core_id,
455 struct core_topology *topo)
457 int nodes, cores_in_ccx;
459 /* First get the number of nodes required */
460 nodes = nodes_in_socket(nr_cores);
462 cores_in_ccx = cores_in_core_complex(nr_cores);
464 topo->node_id = core_id / (cores_in_ccx * MAX_CCX);
465 topo->ccx_id = (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx;
466 topo->core_id = core_id % cores_in_ccx;
467 topo->num_nodes = nodes;
470 /* Encode cache info for CPUID[8000001E] */
471 static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
472 uint32_t *eax, uint32_t *ebx,
473 uint32_t *ecx, uint32_t *edx)
475 struct core_topology topo = {0};
479 build_core_topology(cs->nr_cores, cpu->core_id, &topo);
482 * CPUID_Fn8000001E_EBX
484 * 15:8 Threads per core (The number of threads per core is
485 * Threads per core + 1)
486 * 7:0 Core id (see bit decoding below)
496 if (cs->nr_threads - 1) {
497 *ebx = ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) |
498 (topo.ccx_id << 2) | topo.core_id;
500 *ebx = (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id;
503 * CPUID_Fn8000001E_ECX
505 * 10:8 Nodes per processor (Nodes per processor is number of nodes + 1)
506 * 7:0 Node id (see bit decoding below)
510 if (topo.num_nodes <= 4) {
511 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) |
515 * Node id fix up. Actual hardware supports up to 4 nodes. But with
516 * more than 32 cores, we may end up with more than 4 nodes.
517 * Node id is a combination of socket id and node id. Only requirement
518 * here is that this number should be unique accross the system.
519 * Shift the socket id to accommodate more nodes. We dont expect both
520 * socket id and node id to be big number at the same time. This is not
521 * an ideal config but we need to to support it. Max nodes we can have
522 * is 32 (255/8) with 8 cores per node and 255 max cores. We only need
523 * 5 bits for nodes. Find the left most set bit to represent the total
524 * number of nodes. find_last_bit returns last set bit(0 based). Left
525 * shift(+1) the socket id to represent all the nodes.
527 nodes = topo.num_nodes - 1;
528 shift = find_last_bit(&nodes, 8);
529 *ecx = ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift + 1)) |
536 * Definitions of the hardcoded cache entries we expose:
537 * These are legacy cache values. If there is a need to change any
538 * of these values please use builtin_x86_defs
542 static CPUCacheInfo legacy_l1d_cache = {
551 .no_invd_sharing = true,
554 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
555 static CPUCacheInfo legacy_l1d_cache_amd = {
565 .no_invd_sharing = true,
568 /* L1 instruction cache: */
569 static CPUCacheInfo legacy_l1i_cache = {
570 .type = INSTRUCTION_CACHE,
578 .no_invd_sharing = true,
581 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
582 static CPUCacheInfo legacy_l1i_cache_amd = {
583 .type = INSTRUCTION_CACHE,
592 .no_invd_sharing = true,
595 /* Level 2 unified cache: */
596 static CPUCacheInfo legacy_l2_cache = {
597 .type = UNIFIED_CACHE,
605 .no_invd_sharing = true,
608 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
609 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
610 .type = UNIFIED_CACHE,
618 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
619 static CPUCacheInfo legacy_l2_cache_amd = {
620 .type = UNIFIED_CACHE,
630 /* Level 3 unified cache: */
631 static CPUCacheInfo legacy_l3_cache = {
632 .type = UNIFIED_CACHE,
642 .complex_indexing = true,
645 /* TLB definitions: */
647 #define L1_DTLB_2M_ASSOC 1
648 #define L1_DTLB_2M_ENTRIES 255
649 #define L1_DTLB_4K_ASSOC 1
650 #define L1_DTLB_4K_ENTRIES 255
652 #define L1_ITLB_2M_ASSOC 1
653 #define L1_ITLB_2M_ENTRIES 255
654 #define L1_ITLB_4K_ASSOC 1
655 #define L1_ITLB_4K_ENTRIES 255
657 #define L2_DTLB_2M_ASSOC 0 /* disabled */
658 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
659 #define L2_DTLB_4K_ASSOC 4
660 #define L2_DTLB_4K_ENTRIES 512
662 #define L2_ITLB_2M_ASSOC 0 /* disabled */
663 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
664 #define L2_ITLB_4K_ASSOC 4
665 #define L2_ITLB_4K_ENTRIES 512
667 /* CPUID Leaf 0x14 constants: */
668 #define INTEL_PT_MAX_SUBLEAF 0x1
670 * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
671 * MSR can be accessed;
672 * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
673 * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
674 * of Intel PT MSRs across warm reset;
675 * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
677 #define INTEL_PT_MINIMAL_EBX 0xf
679 * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
680 * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
682 * bit[01]: ToPA tables can hold any number of output entries, up to the
683 * maximum allowed by the MaskOrTableOffset field of
684 * IA32_RTIT_OUTPUT_MASK_PTRS;
685 * bit[02]: Support Single-Range Output scheme;
687 #define INTEL_PT_MINIMAL_ECX 0x7
688 /* generated packets which contain IP payloads have LIP values */
689 #define INTEL_PT_IP_LIP (1 << 31)
690 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
691 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
692 #define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */
693 #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */
694 #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
696 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
697 uint32_t vendor2, uint32_t vendor3)
700 for (i = 0; i < 4; i++) {
701 dst[i] = vendor1 >> (8 * i);
702 dst[i + 4] = vendor2 >> (8 * i);
703 dst[i + 8] = vendor3 >> (8 * i);
705 dst[CPUID_VENDOR_SZ] = '\0';
708 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
709 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
710 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
711 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
712 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
713 CPUID_PSE36 | CPUID_FXSR)
714 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
715 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
716 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
717 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
718 CPUID_PAE | CPUID_SEP | CPUID_APIC)
720 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
721 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
722 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
723 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
724 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
725 /* partly implemented:
726 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
728 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
729 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
730 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
731 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
732 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
733 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
736 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
737 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
738 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
739 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
743 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
745 #define TCG_EXT2_X86_64_FEATURES 0
748 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
749 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
750 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
751 TCG_EXT2_X86_64_FEATURES)
752 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
753 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
754 #define TCG_EXT4_FEATURES 0
755 #define TCG_SVM_FEATURES CPUID_SVM_NPT
756 #define TCG_KVM_FEATURES 0
757 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
758 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
759 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
760 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
763 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
764 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
765 CPUID_7_0_EBX_RDSEED */
766 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
767 /* CPUID_7_0_ECX_OSPKE is dynamic */ \
769 #define TCG_7_0_EDX_FEATURES 0
770 #define TCG_APM_FEATURES 0
771 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
772 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
774 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
776 typedef enum FeatureWordType {
781 typedef struct FeatureWordInfo {
782 FeatureWordType type;
783 /* feature flags names are taken from "Intel Processor Identification and
784 * the CPUID Instruction" and AMD's "CPUID Specification".
785 * In cases of disagreement between feature naming conventions,
786 * aliases may be added.
788 const char *feat_names[32];
790 /* If type==CPUID_FEATURE_WORD */
792 uint32_t eax; /* Input EAX for CPUID */
793 bool needs_ecx; /* CPUID instruction uses ECX as input */
794 uint32_t ecx; /* Input ECX value for CPUID */
795 int reg; /* output register (R_* constant) */
797 /* If type==MSR_FEATURE_WORD */
800 struct { /*CPUID that enumerate this MSR*/
801 FeatureWord cpuid_class;
806 uint32_t tcg_features; /* Feature flags supported by TCG */
807 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
808 uint32_t migratable_flags; /* Feature flags known to be migratable */
809 /* Features that shouldn't be auto-enabled by "-cpu host" */
810 uint32_t no_autoenable_flags;
813 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
815 .type = CPUID_FEATURE_WORD,
817 "fpu", "vme", "de", "pse",
818 "tsc", "msr", "pae", "mce",
819 "cx8", "apic", NULL, "sep",
820 "mtrr", "pge", "mca", "cmov",
821 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
822 NULL, "ds" /* Intel dts */, "acpi", "mmx",
823 "fxsr", "sse", "sse2", "ss",
824 "ht" /* Intel htt */, "tm", "ia64", "pbe",
826 .cpuid = {.eax = 1, .reg = R_EDX, },
827 .tcg_features = TCG_FEATURES,
830 .type = CPUID_FEATURE_WORD,
832 "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
833 "ds-cpl", "vmx", "smx", "est",
834 "tm2", "ssse3", "cid", NULL,
835 "fma", "cx16", "xtpr", "pdcm",
836 NULL, "pcid", "dca", "sse4.1",
837 "sse4.2", "x2apic", "movbe", "popcnt",
838 "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
839 "avx", "f16c", "rdrand", "hypervisor",
841 .cpuid = { .eax = 1, .reg = R_ECX, },
842 .tcg_features = TCG_EXT_FEATURES,
844 /* Feature names that are already defined on feature_name[] but
845 * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
846 * names on feat_names below. They are copied automatically
847 * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
849 [FEAT_8000_0001_EDX] = {
850 .type = CPUID_FEATURE_WORD,
852 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
853 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
854 NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
855 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
856 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
857 "nx", NULL, "mmxext", NULL /* mmx */,
858 NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
859 NULL, "lm", "3dnowext", "3dnow",
861 .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
862 .tcg_features = TCG_EXT2_FEATURES,
864 [FEAT_8000_0001_ECX] = {
865 .type = CPUID_FEATURE_WORD,
867 "lahf-lm", "cmp-legacy", "svm", "extapic",
868 "cr8legacy", "abm", "sse4a", "misalignsse",
869 "3dnowprefetch", "osvw", "ibs", "xop",
870 "skinit", "wdt", NULL, "lwp",
871 "fma4", "tce", NULL, "nodeid-msr",
872 NULL, "tbm", "topoext", "perfctr-core",
873 "perfctr-nb", NULL, NULL, NULL,
874 NULL, NULL, NULL, NULL,
876 .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
877 .tcg_features = TCG_EXT3_FEATURES,
879 * TOPOEXT is always allowed but can't be enabled blindly by
880 * "-cpu host", as it requires consistent cache topology info
881 * to be provided so it doesn't confuse guests.
883 .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
885 [FEAT_C000_0001_EDX] = {
886 .type = CPUID_FEATURE_WORD,
888 NULL, NULL, "xstore", "xstore-en",
889 NULL, NULL, "xcrypt", "xcrypt-en",
890 "ace2", "ace2-en", "phe", "phe-en",
891 "pmm", "pmm-en", NULL, NULL,
892 NULL, NULL, NULL, NULL,
893 NULL, NULL, NULL, NULL,
894 NULL, NULL, NULL, NULL,
895 NULL, NULL, NULL, NULL,
897 .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
898 .tcg_features = TCG_EXT4_FEATURES,
901 .type = CPUID_FEATURE_WORD,
903 "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
904 "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
905 NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
906 NULL, NULL, NULL, NULL,
907 NULL, NULL, NULL, NULL,
908 NULL, NULL, NULL, NULL,
909 "kvmclock-stable-bit", NULL, NULL, NULL,
910 NULL, NULL, NULL, NULL,
912 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
913 .tcg_features = TCG_KVM_FEATURES,
916 .type = CPUID_FEATURE_WORD,
918 "kvm-hint-dedicated", NULL, NULL, NULL,
919 NULL, NULL, NULL, NULL,
920 NULL, NULL, NULL, NULL,
921 NULL, NULL, NULL, NULL,
922 NULL, NULL, NULL, NULL,
923 NULL, NULL, NULL, NULL,
924 NULL, NULL, NULL, NULL,
925 NULL, NULL, NULL, NULL,
927 .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
928 .tcg_features = TCG_KVM_FEATURES,
930 * KVM hints aren't auto-enabled by -cpu host, they need to be
931 * explicitly enabled in the command-line.
933 .no_autoenable_flags = ~0U,
936 * .feat_names are commented out for Hyper-V enlightenments because we
937 * don't want to have two different ways for enabling them on QEMU command
938 * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
939 * enabling several feature bits simultaneously, exposing these bits
940 * individually may just confuse guests.
942 [FEAT_HYPERV_EAX] = {
943 .type = CPUID_FEATURE_WORD,
945 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
946 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
947 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
948 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
949 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
950 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
951 NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
953 NULL, NULL, NULL, NULL,
954 NULL, NULL, NULL, NULL,
955 NULL, NULL, NULL, NULL,
956 NULL, NULL, NULL, NULL,
958 .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
960 [FEAT_HYPERV_EBX] = {
961 .type = CPUID_FEATURE_WORD,
963 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
964 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
965 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
966 NULL /* hv_create_port */, NULL /* hv_connect_port */,
967 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
968 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
970 NULL, NULL, NULL, NULL,
971 NULL, NULL, NULL, NULL,
972 NULL, NULL, NULL, NULL,
973 NULL, NULL, NULL, NULL,
975 .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
977 [FEAT_HYPERV_EDX] = {
978 .type = CPUID_FEATURE_WORD,
980 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
981 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
982 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
984 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
985 NULL, NULL, NULL, NULL,
986 NULL, NULL, NULL, NULL,
987 NULL, NULL, NULL, NULL,
988 NULL, NULL, NULL, NULL,
989 NULL, NULL, NULL, NULL,
991 .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
993 [FEAT_HV_RECOMM_EAX] = {
994 .type = CPUID_FEATURE_WORD,
996 NULL /* hv_recommend_pv_as_switch */,
997 NULL /* hv_recommend_pv_tlbflush_local */,
998 NULL /* hv_recommend_pv_tlbflush_remote */,
999 NULL /* hv_recommend_msr_apic_access */,
1000 NULL /* hv_recommend_msr_reset */,
1001 NULL /* hv_recommend_relaxed_timing */,
1002 NULL /* hv_recommend_dma_remapping */,
1003 NULL /* hv_recommend_int_remapping */,
1004 NULL /* hv_recommend_x2apic_msrs */,
1005 NULL /* hv_recommend_autoeoi_deprecation */,
1006 NULL /* hv_recommend_pv_ipi */,
1007 NULL /* hv_recommend_ex_hypercalls */,
1008 NULL /* hv_hypervisor_is_nested */,
1009 NULL /* hv_recommend_int_mbec */,
1010 NULL /* hv_recommend_evmcs */,
1012 NULL, NULL, NULL, NULL,
1013 NULL, NULL, NULL, NULL,
1014 NULL, NULL, NULL, NULL,
1015 NULL, NULL, NULL, NULL,
1017 .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
1019 [FEAT_HV_NESTED_EAX] = {
1020 .type = CPUID_FEATURE_WORD,
1021 .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
1024 .type = CPUID_FEATURE_WORD,
1026 "npt", "lbrv", "svm-lock", "nrip-save",
1027 "tsc-scale", "vmcb-clean", "flushbyasid", "decodeassists",
1028 NULL, NULL, "pause-filter", NULL,
1029 "pfthreshold", NULL, NULL, NULL,
1030 NULL, NULL, NULL, NULL,
1031 NULL, NULL, NULL, NULL,
1032 NULL, NULL, NULL, NULL,
1033 NULL, NULL, NULL, NULL,
1035 .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
1036 .tcg_features = TCG_SVM_FEATURES,
1039 .type = CPUID_FEATURE_WORD,
1041 "fsgsbase", "tsc-adjust", NULL, "bmi1",
1042 "hle", "avx2", NULL, "smep",
1043 "bmi2", "erms", "invpcid", "rtm",
1044 NULL, NULL, "mpx", NULL,
1045 "avx512f", "avx512dq", "rdseed", "adx",
1046 "smap", "avx512ifma", "pcommit", "clflushopt",
1047 "clwb", "intel-pt", "avx512pf", "avx512er",
1048 "avx512cd", "sha-ni", "avx512bw", "avx512vl",
1052 .needs_ecx = true, .ecx = 0,
1055 .tcg_features = TCG_7_0_EBX_FEATURES,
1058 .type = CPUID_FEATURE_WORD,
1060 NULL, "avx512vbmi", "umip", "pku",
1061 NULL /* ospke */, NULL, "avx512vbmi2", NULL,
1062 "gfni", "vaes", "vpclmulqdq", "avx512vnni",
1063 "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
1064 "la57", NULL, NULL, NULL,
1065 NULL, NULL, "rdpid", NULL,
1066 NULL, "cldemote", NULL, "movdiri",
1067 "movdir64b", NULL, NULL, NULL,
1071 .needs_ecx = true, .ecx = 0,
1074 .tcg_features = TCG_7_0_ECX_FEATURES,
1077 .type = CPUID_FEATURE_WORD,
1079 NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
1080 NULL, NULL, NULL, NULL,
1081 NULL, NULL, "md-clear", NULL,
1082 NULL, NULL, NULL, NULL,
1083 NULL, NULL, NULL, NULL,
1084 NULL, NULL, NULL, NULL,
1085 NULL, NULL, "spec-ctrl", "stibp",
1086 NULL, "arch-capabilities", NULL, "ssbd",
1090 .needs_ecx = true, .ecx = 0,
1093 .tcg_features = TCG_7_0_EDX_FEATURES,
1095 [FEAT_8000_0007_EDX] = {
1096 .type = CPUID_FEATURE_WORD,
1098 NULL, NULL, NULL, NULL,
1099 NULL, NULL, NULL, NULL,
1100 "invtsc", NULL, NULL, NULL,
1101 NULL, NULL, NULL, NULL,
1102 NULL, NULL, NULL, NULL,
1103 NULL, NULL, NULL, NULL,
1104 NULL, NULL, NULL, NULL,
1105 NULL, NULL, NULL, NULL,
1107 .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1108 .tcg_features = TCG_APM_FEATURES,
1109 .unmigratable_flags = CPUID_APM_INVTSC,
1111 [FEAT_8000_0008_EBX] = {
1112 .type = CPUID_FEATURE_WORD,
1114 NULL, NULL, NULL, NULL,
1115 NULL, NULL, NULL, NULL,
1116 NULL, "wbnoinvd", NULL, NULL,
1117 "ibpb", NULL, NULL, NULL,
1118 NULL, NULL, NULL, NULL,
1119 NULL, NULL, NULL, NULL,
1120 "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1121 NULL, NULL, NULL, NULL,
1123 .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1125 .unmigratable_flags = 0,
1128 .type = CPUID_FEATURE_WORD,
1130 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1131 NULL, NULL, NULL, NULL,
1132 NULL, NULL, NULL, NULL,
1133 NULL, NULL, NULL, NULL,
1134 NULL, NULL, NULL, NULL,
1135 NULL, NULL, NULL, NULL,
1136 NULL, NULL, NULL, NULL,
1137 NULL, NULL, NULL, NULL,
1141 .needs_ecx = true, .ecx = 1,
1144 .tcg_features = TCG_XSAVE_FEATURES,
1147 .type = CPUID_FEATURE_WORD,
1149 NULL, NULL, "arat", NULL,
1150 NULL, NULL, NULL, NULL,
1151 NULL, NULL, NULL, NULL,
1152 NULL, NULL, NULL, NULL,
1153 NULL, NULL, NULL, NULL,
1154 NULL, NULL, NULL, NULL,
1155 NULL, NULL, NULL, NULL,
1156 NULL, NULL, NULL, NULL,
1158 .cpuid = { .eax = 6, .reg = R_EAX, },
1159 .tcg_features = TCG_6_EAX_FEATURES,
1161 [FEAT_XSAVE_COMP_LO] = {
1162 .type = CPUID_FEATURE_WORD,
1165 .needs_ecx = true, .ecx = 0,
1168 .tcg_features = ~0U,
1169 .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1170 XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1171 XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1174 [FEAT_XSAVE_COMP_HI] = {
1175 .type = CPUID_FEATURE_WORD,
1178 .needs_ecx = true, .ecx = 0,
1181 .tcg_features = ~0U,
1183 /*Below are MSR exposed features*/
1184 [FEAT_ARCH_CAPABILITIES] = {
1185 .type = MSR_FEATURE_WORD,
1187 "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1188 "ssb-no", "mds-no", NULL, NULL,
1189 NULL, NULL, NULL, NULL,
1190 NULL, NULL, NULL, NULL,
1191 NULL, NULL, NULL, NULL,
1192 NULL, NULL, NULL, NULL,
1193 NULL, NULL, NULL, NULL,
1194 NULL, NULL, NULL, NULL,
1197 .index = MSR_IA32_ARCH_CAPABILITIES,
1200 CPUID_7_0_EDX_ARCH_CAPABILITIES
1206 typedef struct X86RegisterInfo32 {
1207 /* Name of register */
1209 /* QAPI enum value register */
1210 X86CPURegister32 qapi_enum;
1211 } X86RegisterInfo32;
1213 #define REGISTER(reg) \
1214 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1215 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1227 typedef struct ExtSaveArea {
1228 uint32_t feature, bits;
1229 uint32_t offset, size;
1232 static const ExtSaveArea x86_ext_save_areas[] = {
1234 /* x87 FP state component is always enabled if XSAVE is supported */
1235 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1236 /* x87 state is in the legacy region of the XSAVE area */
1238 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1240 [XSTATE_SSE_BIT] = {
1241 /* SSE state component is always enabled if XSAVE is supported */
1242 .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1243 /* SSE state is in the legacy region of the XSAVE area */
1245 .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1248 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1249 .offset = offsetof(X86XSaveArea, avx_state),
1250 .size = sizeof(XSaveAVX) },
1251 [XSTATE_BNDREGS_BIT] =
1252 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1253 .offset = offsetof(X86XSaveArea, bndreg_state),
1254 .size = sizeof(XSaveBNDREG) },
1255 [XSTATE_BNDCSR_BIT] =
1256 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1257 .offset = offsetof(X86XSaveArea, bndcsr_state),
1258 .size = sizeof(XSaveBNDCSR) },
1259 [XSTATE_OPMASK_BIT] =
1260 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1261 .offset = offsetof(X86XSaveArea, opmask_state),
1262 .size = sizeof(XSaveOpmask) },
1263 [XSTATE_ZMM_Hi256_BIT] =
1264 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1265 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1266 .size = sizeof(XSaveZMM_Hi256) },
1267 [XSTATE_Hi16_ZMM_BIT] =
1268 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1269 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1270 .size = sizeof(XSaveHi16_ZMM) },
1272 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1273 .offset = offsetof(X86XSaveArea, pkru_state),
1274 .size = sizeof(XSavePKRU) },
1277 static uint32_t xsave_area_size(uint64_t mask)
1282 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1283 const ExtSaveArea *esa = &x86_ext_save_areas[i];
1284 if ((mask >> i) & 1) {
1285 ret = MAX(ret, esa->offset + esa->size);
1291 static inline bool accel_uses_host_cpuid(void)
1293 return kvm_enabled() || hvf_enabled();
1296 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1298 return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1299 cpu->env.features[FEAT_XSAVE_COMP_LO];
1302 const char *get_register_name_32(unsigned int reg)
1304 if (reg >= CPU_NB_REGS32) {
1307 return x86_reg_info_32[reg].name;
1311 * Returns the set of feature flags that are supported and migratable by
1312 * QEMU, for a given FeatureWord.
1314 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
1316 FeatureWordInfo *wi = &feature_word_info[w];
1320 for (i = 0; i < 32; i++) {
1321 uint32_t f = 1U << i;
1323 /* If the feature name is known, it is implicitly considered migratable,
1324 * unless it is explicitly set in unmigratable_flags */
1325 if ((wi->migratable_flags & f) ||
1326 (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1333 void host_cpuid(uint32_t function, uint32_t count,
1334 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1339 asm volatile("cpuid"
1340 : "=a"(vec[0]), "=b"(vec[1]),
1341 "=c"(vec[2]), "=d"(vec[3])
1342 : "0"(function), "c"(count) : "cc");
1343 #elif defined(__i386__)
1344 asm volatile("pusha \n\t"
1346 "mov %%eax, 0(%2) \n\t"
1347 "mov %%ebx, 4(%2) \n\t"
1348 "mov %%ecx, 8(%2) \n\t"
1349 "mov %%edx, 12(%2) \n\t"
1351 : : "a"(function), "c"(count), "S"(vec)
1367 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1369 uint32_t eax, ebx, ecx, edx;
1371 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1372 x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1374 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1376 *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1379 *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1382 *stepping = eax & 0x0F;
1386 /* CPU class name definitions: */
1388 /* Return type name for a given CPU model name
1389 * Caller is responsible for freeing the returned string.
1391 static char *x86_cpu_type_name(const char *model_name)
1393 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1396 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1399 char *typename = x86_cpu_type_name(cpu_model);
1400 oc = object_class_by_name(typename);
1405 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1407 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1408 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1409 return g_strndup(class_name,
1410 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1413 struct X86CPUDefinition {
1417 /* vendor is zero-terminated, 12 character ASCII string */
1418 char vendor[CPUID_VENDOR_SZ + 1];
1422 FeatureWordArray features;
1423 const char *model_id;
1424 CPUCaches *cache_info;
1427 static CPUCaches epyc_cache_info = {
1428 .l1d_cache = &(CPUCacheInfo) {
1438 .no_invd_sharing = true,
1440 .l1i_cache = &(CPUCacheInfo) {
1441 .type = INSTRUCTION_CACHE,
1450 .no_invd_sharing = true,
1452 .l2_cache = &(CPUCacheInfo) {
1453 .type = UNIFIED_CACHE,
1462 .l3_cache = &(CPUCacheInfo) {
1463 .type = UNIFIED_CACHE,
1467 .associativity = 16,
1473 .complex_indexing = true,
1477 static X86CPUDefinition builtin_x86_defs[] = {
1481 .vendor = CPUID_VENDOR_AMD,
1485 .features[FEAT_1_EDX] =
1487 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1489 .features[FEAT_1_ECX] =
1490 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1491 .features[FEAT_8000_0001_EDX] =
1492 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1493 .features[FEAT_8000_0001_ECX] =
1494 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1495 .xlevel = 0x8000000A,
1496 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1501 .vendor = CPUID_VENDOR_AMD,
1505 /* Missing: CPUID_HT */
1506 .features[FEAT_1_EDX] =
1508 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1509 CPUID_PSE36 | CPUID_VME,
1510 .features[FEAT_1_ECX] =
1511 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1513 .features[FEAT_8000_0001_EDX] =
1514 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1515 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1516 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1517 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1519 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1520 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1521 .features[FEAT_8000_0001_ECX] =
1522 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1523 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1524 /* Missing: CPUID_SVM_LBRV */
1525 .features[FEAT_SVM] =
1527 .xlevel = 0x8000001A,
1528 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1533 .vendor = CPUID_VENDOR_INTEL,
1537 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1538 .features[FEAT_1_EDX] =
1540 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1541 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1542 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1543 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1544 .features[FEAT_1_ECX] =
1545 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1547 .features[FEAT_8000_0001_EDX] =
1548 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1549 .features[FEAT_8000_0001_ECX] =
1551 .xlevel = 0x80000008,
1552 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
1557 .vendor = CPUID_VENDOR_INTEL,
1561 /* Missing: CPUID_HT */
1562 .features[FEAT_1_EDX] =
1563 PPRO_FEATURES | CPUID_VME |
1564 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1566 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1567 .features[FEAT_1_ECX] =
1568 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1569 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1570 .features[FEAT_8000_0001_EDX] =
1571 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1572 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1573 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1574 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1575 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1576 .features[FEAT_8000_0001_ECX] =
1578 .xlevel = 0x80000008,
1579 .model_id = "Common KVM processor"
1584 .vendor = CPUID_VENDOR_INTEL,
1588 .features[FEAT_1_EDX] =
1590 .features[FEAT_1_ECX] =
1592 .xlevel = 0x80000004,
1593 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1598 .vendor = CPUID_VENDOR_INTEL,
1602 .features[FEAT_1_EDX] =
1603 PPRO_FEATURES | CPUID_VME |
1604 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1605 .features[FEAT_1_ECX] =
1607 .features[FEAT_8000_0001_ECX] =
1609 .xlevel = 0x80000008,
1610 .model_id = "Common 32-bit KVM processor"
1615 .vendor = CPUID_VENDOR_INTEL,
1619 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1620 .features[FEAT_1_EDX] =
1621 PPRO_FEATURES | CPUID_VME |
1622 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
1624 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
1625 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
1626 .features[FEAT_1_ECX] =
1627 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
1628 .features[FEAT_8000_0001_EDX] =
1630 .xlevel = 0x80000008,
1631 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
1636 .vendor = CPUID_VENDOR_INTEL,
1640 .features[FEAT_1_EDX] =
1648 .vendor = CPUID_VENDOR_INTEL,
1652 .features[FEAT_1_EDX] =
1660 .vendor = CPUID_VENDOR_INTEL,
1664 .features[FEAT_1_EDX] =
1672 .vendor = CPUID_VENDOR_INTEL,
1676 .features[FEAT_1_EDX] =
1684 .vendor = CPUID_VENDOR_AMD,
1688 .features[FEAT_1_EDX] =
1689 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
1691 .features[FEAT_8000_0001_EDX] =
1692 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
1693 .xlevel = 0x80000008,
1694 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1699 .vendor = CPUID_VENDOR_INTEL,
1703 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1704 .features[FEAT_1_EDX] =
1706 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1707 CPUID_ACPI | CPUID_SS,
1708 /* Some CPUs got no CPUID_SEP */
1709 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1711 .features[FEAT_1_ECX] =
1712 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1714 .features[FEAT_8000_0001_EDX] =
1716 .features[FEAT_8000_0001_ECX] =
1718 .xlevel = 0x80000008,
1719 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1724 .vendor = CPUID_VENDOR_INTEL,
1728 .features[FEAT_1_EDX] =
1729 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1730 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1731 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1732 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1733 CPUID_DE | CPUID_FP87,
1734 .features[FEAT_1_ECX] =
1735 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1736 .features[FEAT_8000_0001_EDX] =
1737 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1738 .features[FEAT_8000_0001_ECX] =
1740 .xlevel = 0x80000008,
1741 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1746 .vendor = CPUID_VENDOR_INTEL,
1750 .features[FEAT_1_EDX] =
1751 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1752 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1753 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1754 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1755 CPUID_DE | CPUID_FP87,
1756 .features[FEAT_1_ECX] =
1757 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1759 .features[FEAT_8000_0001_EDX] =
1760 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1761 .features[FEAT_8000_0001_ECX] =
1763 .xlevel = 0x80000008,
1764 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1769 .vendor = CPUID_VENDOR_INTEL,
1773 .features[FEAT_1_EDX] =
1774 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1775 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1776 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1777 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1778 CPUID_DE | CPUID_FP87,
1779 .features[FEAT_1_ECX] =
1780 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1781 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1782 .features[FEAT_8000_0001_EDX] =
1783 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1784 .features[FEAT_8000_0001_ECX] =
1786 .xlevel = 0x80000008,
1787 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1790 .name = "Nehalem-IBRS",
1792 .vendor = CPUID_VENDOR_INTEL,
1796 .features[FEAT_1_EDX] =
1797 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1798 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1799 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1800 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1801 CPUID_DE | CPUID_FP87,
1802 .features[FEAT_1_ECX] =
1803 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1804 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1805 .features[FEAT_7_0_EDX] =
1806 CPUID_7_0_EDX_SPEC_CTRL,
1807 .features[FEAT_8000_0001_EDX] =
1808 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1809 .features[FEAT_8000_0001_ECX] =
1811 .xlevel = 0x80000008,
1812 .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
1817 .vendor = CPUID_VENDOR_INTEL,
1821 .features[FEAT_1_EDX] =
1822 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1823 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1824 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1825 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1826 CPUID_DE | CPUID_FP87,
1827 .features[FEAT_1_ECX] =
1828 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1829 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1830 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1831 .features[FEAT_8000_0001_EDX] =
1832 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1833 .features[FEAT_8000_0001_ECX] =
1835 .features[FEAT_6_EAX] =
1837 .xlevel = 0x80000008,
1838 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1841 .name = "Westmere-IBRS",
1843 .vendor = CPUID_VENDOR_INTEL,
1847 .features[FEAT_1_EDX] =
1848 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1849 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1850 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1851 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1852 CPUID_DE | CPUID_FP87,
1853 .features[FEAT_1_ECX] =
1854 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1855 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1856 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1857 .features[FEAT_8000_0001_EDX] =
1858 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1859 .features[FEAT_8000_0001_ECX] =
1861 .features[FEAT_7_0_EDX] =
1862 CPUID_7_0_EDX_SPEC_CTRL,
1863 .features[FEAT_6_EAX] =
1865 .xlevel = 0x80000008,
1866 .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
1869 .name = "SandyBridge",
1871 .vendor = CPUID_VENDOR_INTEL,
1875 .features[FEAT_1_EDX] =
1876 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1877 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1878 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1879 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1880 CPUID_DE | CPUID_FP87,
1881 .features[FEAT_1_ECX] =
1882 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1883 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1884 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1885 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1887 .features[FEAT_8000_0001_EDX] =
1888 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1890 .features[FEAT_8000_0001_ECX] =
1892 .features[FEAT_XSAVE] =
1893 CPUID_XSAVE_XSAVEOPT,
1894 .features[FEAT_6_EAX] =
1896 .xlevel = 0x80000008,
1897 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1900 .name = "SandyBridge-IBRS",
1902 .vendor = CPUID_VENDOR_INTEL,
1906 .features[FEAT_1_EDX] =
1907 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1908 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1909 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1910 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1911 CPUID_DE | CPUID_FP87,
1912 .features[FEAT_1_ECX] =
1913 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1914 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1915 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1916 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1918 .features[FEAT_8000_0001_EDX] =
1919 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1921 .features[FEAT_8000_0001_ECX] =
1923 .features[FEAT_7_0_EDX] =
1924 CPUID_7_0_EDX_SPEC_CTRL,
1925 .features[FEAT_XSAVE] =
1926 CPUID_XSAVE_XSAVEOPT,
1927 .features[FEAT_6_EAX] =
1929 .xlevel = 0x80000008,
1930 .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
1933 .name = "IvyBridge",
1935 .vendor = CPUID_VENDOR_INTEL,
1939 .features[FEAT_1_EDX] =
1940 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1941 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1942 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1943 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1944 CPUID_DE | CPUID_FP87,
1945 .features[FEAT_1_ECX] =
1946 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1947 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1948 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1949 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1950 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1951 .features[FEAT_7_0_EBX] =
1952 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1954 .features[FEAT_8000_0001_EDX] =
1955 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1957 .features[FEAT_8000_0001_ECX] =
1959 .features[FEAT_XSAVE] =
1960 CPUID_XSAVE_XSAVEOPT,
1961 .features[FEAT_6_EAX] =
1963 .xlevel = 0x80000008,
1964 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1967 .name = "IvyBridge-IBRS",
1969 .vendor = CPUID_VENDOR_INTEL,
1973 .features[FEAT_1_EDX] =
1974 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1975 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1976 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1977 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1978 CPUID_DE | CPUID_FP87,
1979 .features[FEAT_1_ECX] =
1980 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1981 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1982 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1983 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1984 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1985 .features[FEAT_7_0_EBX] =
1986 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1988 .features[FEAT_8000_0001_EDX] =
1989 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1991 .features[FEAT_8000_0001_ECX] =
1993 .features[FEAT_7_0_EDX] =
1994 CPUID_7_0_EDX_SPEC_CTRL,
1995 .features[FEAT_XSAVE] =
1996 CPUID_XSAVE_XSAVEOPT,
1997 .features[FEAT_6_EAX] =
1999 .xlevel = 0x80000008,
2000 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
2003 .name = "Haswell-noTSX",
2005 .vendor = CPUID_VENDOR_INTEL,
2009 .features[FEAT_1_EDX] =
2010 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2011 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2012 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2013 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2014 CPUID_DE | CPUID_FP87,
2015 .features[FEAT_1_ECX] =
2016 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2017 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2018 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2019 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2020 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2021 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2022 .features[FEAT_8000_0001_EDX] =
2023 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2025 .features[FEAT_8000_0001_ECX] =
2026 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2027 .features[FEAT_7_0_EBX] =
2028 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2029 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2030 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2031 .features[FEAT_XSAVE] =
2032 CPUID_XSAVE_XSAVEOPT,
2033 .features[FEAT_6_EAX] =
2035 .xlevel = 0x80000008,
2036 .model_id = "Intel Core Processor (Haswell, no TSX)",
2039 .name = "Haswell-noTSX-IBRS",
2041 .vendor = CPUID_VENDOR_INTEL,
2045 .features[FEAT_1_EDX] =
2046 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2047 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2048 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2049 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2050 CPUID_DE | CPUID_FP87,
2051 .features[FEAT_1_ECX] =
2052 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2053 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2054 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2055 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2056 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2057 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2058 .features[FEAT_8000_0001_EDX] =
2059 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2061 .features[FEAT_8000_0001_ECX] =
2062 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2063 .features[FEAT_7_0_EDX] =
2064 CPUID_7_0_EDX_SPEC_CTRL,
2065 .features[FEAT_7_0_EBX] =
2066 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2067 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2068 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
2069 .features[FEAT_XSAVE] =
2070 CPUID_XSAVE_XSAVEOPT,
2071 .features[FEAT_6_EAX] =
2073 .xlevel = 0x80000008,
2074 .model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
2079 .vendor = CPUID_VENDOR_INTEL,
2083 .features[FEAT_1_EDX] =
2084 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2085 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2086 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2087 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2088 CPUID_DE | CPUID_FP87,
2089 .features[FEAT_1_ECX] =
2090 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2091 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2092 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2093 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2094 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2095 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2096 .features[FEAT_8000_0001_EDX] =
2097 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2099 .features[FEAT_8000_0001_ECX] =
2100 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2101 .features[FEAT_7_0_EBX] =
2102 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2103 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2104 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2106 .features[FEAT_XSAVE] =
2107 CPUID_XSAVE_XSAVEOPT,
2108 .features[FEAT_6_EAX] =
2110 .xlevel = 0x80000008,
2111 .model_id = "Intel Core Processor (Haswell)",
2114 .name = "Haswell-IBRS",
2116 .vendor = CPUID_VENDOR_INTEL,
2120 .features[FEAT_1_EDX] =
2121 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2122 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2123 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2124 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2125 CPUID_DE | CPUID_FP87,
2126 .features[FEAT_1_ECX] =
2127 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2128 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2129 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2130 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2131 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2132 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2133 .features[FEAT_8000_0001_EDX] =
2134 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2136 .features[FEAT_8000_0001_ECX] =
2137 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2138 .features[FEAT_7_0_EDX] =
2139 CPUID_7_0_EDX_SPEC_CTRL,
2140 .features[FEAT_7_0_EBX] =
2141 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2142 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2143 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2145 .features[FEAT_XSAVE] =
2146 CPUID_XSAVE_XSAVEOPT,
2147 .features[FEAT_6_EAX] =
2149 .xlevel = 0x80000008,
2150 .model_id = "Intel Core Processor (Haswell, IBRS)",
2153 .name = "Broadwell-noTSX",
2155 .vendor = CPUID_VENDOR_INTEL,
2159 .features[FEAT_1_EDX] =
2160 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2161 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2162 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2163 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2164 CPUID_DE | CPUID_FP87,
2165 .features[FEAT_1_ECX] =
2166 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2167 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2168 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2169 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2170 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2171 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2172 .features[FEAT_8000_0001_EDX] =
2173 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2175 .features[FEAT_8000_0001_ECX] =
2176 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2177 .features[FEAT_7_0_EBX] =
2178 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2179 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2180 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2181 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2183 .features[FEAT_XSAVE] =
2184 CPUID_XSAVE_XSAVEOPT,
2185 .features[FEAT_6_EAX] =
2187 .xlevel = 0x80000008,
2188 .model_id = "Intel Core Processor (Broadwell, no TSX)",
2191 .name = "Broadwell-noTSX-IBRS",
2193 .vendor = CPUID_VENDOR_INTEL,
2197 .features[FEAT_1_EDX] =
2198 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2199 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2200 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2201 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2202 CPUID_DE | CPUID_FP87,
2203 .features[FEAT_1_ECX] =
2204 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2205 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2206 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2207 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2208 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2209 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2210 .features[FEAT_8000_0001_EDX] =
2211 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2213 .features[FEAT_8000_0001_ECX] =
2214 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2215 .features[FEAT_7_0_EDX] =
2216 CPUID_7_0_EDX_SPEC_CTRL,
2217 .features[FEAT_7_0_EBX] =
2218 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2219 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2220 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2221 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2223 .features[FEAT_XSAVE] =
2224 CPUID_XSAVE_XSAVEOPT,
2225 .features[FEAT_6_EAX] =
2227 .xlevel = 0x80000008,
2228 .model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
2231 .name = "Broadwell",
2233 .vendor = CPUID_VENDOR_INTEL,
2237 .features[FEAT_1_EDX] =
2238 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2239 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2240 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2241 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2242 CPUID_DE | CPUID_FP87,
2243 .features[FEAT_1_ECX] =
2244 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2245 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2246 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2247 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2248 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2249 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2250 .features[FEAT_8000_0001_EDX] =
2251 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2253 .features[FEAT_8000_0001_ECX] =
2254 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2255 .features[FEAT_7_0_EBX] =
2256 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2257 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2258 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2259 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2261 .features[FEAT_XSAVE] =
2262 CPUID_XSAVE_XSAVEOPT,
2263 .features[FEAT_6_EAX] =
2265 .xlevel = 0x80000008,
2266 .model_id = "Intel Core Processor (Broadwell)",
2269 .name = "Broadwell-IBRS",
2271 .vendor = CPUID_VENDOR_INTEL,
2275 .features[FEAT_1_EDX] =
2276 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2277 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2278 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2279 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2280 CPUID_DE | CPUID_FP87,
2281 .features[FEAT_1_ECX] =
2282 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2283 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2284 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2285 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2286 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2287 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2288 .features[FEAT_8000_0001_EDX] =
2289 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2291 .features[FEAT_8000_0001_ECX] =
2292 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2293 .features[FEAT_7_0_EDX] =
2294 CPUID_7_0_EDX_SPEC_CTRL,
2295 .features[FEAT_7_0_EBX] =
2296 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2297 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2298 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2299 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2301 .features[FEAT_XSAVE] =
2302 CPUID_XSAVE_XSAVEOPT,
2303 .features[FEAT_6_EAX] =
2305 .xlevel = 0x80000008,
2306 .model_id = "Intel Core Processor (Broadwell, IBRS)",
2309 .name = "Skylake-Client",
2311 .vendor = CPUID_VENDOR_INTEL,
2315 .features[FEAT_1_EDX] =
2316 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2317 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2318 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2319 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2320 CPUID_DE | CPUID_FP87,
2321 .features[FEAT_1_ECX] =
2322 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2323 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2324 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2325 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2326 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2327 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2328 .features[FEAT_8000_0001_EDX] =
2329 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2331 .features[FEAT_8000_0001_ECX] =
2332 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2333 .features[FEAT_7_0_EBX] =
2334 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2335 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2336 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2337 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2339 /* Missing: XSAVES (not supported by some Linux versions,
2340 * including v4.1 to v4.12).
2341 * KVM doesn't yet expose any XSAVES state save component,
2342 * and the only one defined in Skylake (processor tracing)
2343 * probably will block migration anyway.
2345 .features[FEAT_XSAVE] =
2346 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2347 CPUID_XSAVE_XGETBV1,
2348 .features[FEAT_6_EAX] =
2350 .xlevel = 0x80000008,
2351 .model_id = "Intel Core Processor (Skylake)",
2354 .name = "Skylake-Client-IBRS",
2356 .vendor = CPUID_VENDOR_INTEL,
2360 .features[FEAT_1_EDX] =
2361 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2362 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2363 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2364 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2365 CPUID_DE | CPUID_FP87,
2366 .features[FEAT_1_ECX] =
2367 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2368 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2369 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2370 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2371 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2372 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2373 .features[FEAT_8000_0001_EDX] =
2374 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2376 .features[FEAT_8000_0001_ECX] =
2377 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2378 .features[FEAT_7_0_EDX] =
2379 CPUID_7_0_EDX_SPEC_CTRL,
2380 .features[FEAT_7_0_EBX] =
2381 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2382 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2383 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2384 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2386 /* Missing: XSAVES (not supported by some Linux versions,
2387 * including v4.1 to v4.12).
2388 * KVM doesn't yet expose any XSAVES state save component,
2389 * and the only one defined in Skylake (processor tracing)
2390 * probably will block migration anyway.
2392 .features[FEAT_XSAVE] =
2393 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2394 CPUID_XSAVE_XGETBV1,
2395 .features[FEAT_6_EAX] =
2397 .xlevel = 0x80000008,
2398 .model_id = "Intel Core Processor (Skylake, IBRS)",
2401 .name = "Skylake-Server",
2403 .vendor = CPUID_VENDOR_INTEL,
2407 .features[FEAT_1_EDX] =
2408 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2409 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2410 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2411 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2412 CPUID_DE | CPUID_FP87,
2413 .features[FEAT_1_ECX] =
2414 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2415 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2416 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2417 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2418 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2419 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2420 .features[FEAT_8000_0001_EDX] =
2421 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2422 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2423 .features[FEAT_8000_0001_ECX] =
2424 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2425 .features[FEAT_7_0_EBX] =
2426 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2427 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2428 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2429 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2430 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2431 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2432 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2433 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2434 .features[FEAT_7_0_ECX] =
2436 /* Missing: XSAVES (not supported by some Linux versions,
2437 * including v4.1 to v4.12).
2438 * KVM doesn't yet expose any XSAVES state save component,
2439 * and the only one defined in Skylake (processor tracing)
2440 * probably will block migration anyway.
2442 .features[FEAT_XSAVE] =
2443 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2444 CPUID_XSAVE_XGETBV1,
2445 .features[FEAT_6_EAX] =
2447 .xlevel = 0x80000008,
2448 .model_id = "Intel Xeon Processor (Skylake)",
2451 .name = "Skylake-Server-IBRS",
2453 .vendor = CPUID_VENDOR_INTEL,
2457 .features[FEAT_1_EDX] =
2458 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2459 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2460 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2461 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2462 CPUID_DE | CPUID_FP87,
2463 .features[FEAT_1_ECX] =
2464 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2465 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2466 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2467 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2468 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2469 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2470 .features[FEAT_8000_0001_EDX] =
2471 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2472 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2473 .features[FEAT_8000_0001_ECX] =
2474 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2475 .features[FEAT_7_0_EDX] =
2476 CPUID_7_0_EDX_SPEC_CTRL,
2477 .features[FEAT_7_0_EBX] =
2478 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2479 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2480 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2481 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2482 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2483 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2484 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2485 CPUID_7_0_EBX_AVX512VL,
2486 .features[FEAT_7_0_ECX] =
2488 /* Missing: XSAVES (not supported by some Linux versions,
2489 * including v4.1 to v4.12).
2490 * KVM doesn't yet expose any XSAVES state save component,
2491 * and the only one defined in Skylake (processor tracing)
2492 * probably will block migration anyway.
2494 .features[FEAT_XSAVE] =
2495 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2496 CPUID_XSAVE_XGETBV1,
2497 .features[FEAT_6_EAX] =
2499 .xlevel = 0x80000008,
2500 .model_id = "Intel Xeon Processor (Skylake, IBRS)",
2503 .name = "Cascadelake-Server",
2505 .vendor = CPUID_VENDOR_INTEL,
2509 .features[FEAT_1_EDX] =
2510 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2511 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2512 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2513 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2514 CPUID_DE | CPUID_FP87,
2515 .features[FEAT_1_ECX] =
2516 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2517 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2518 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2519 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2520 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2521 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2522 .features[FEAT_8000_0001_EDX] =
2523 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2524 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2525 .features[FEAT_8000_0001_ECX] =
2526 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2527 .features[FEAT_7_0_EBX] =
2528 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2529 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2530 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2531 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2532 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2533 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2534 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2535 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2536 .features[FEAT_7_0_ECX] =
2538 CPUID_7_0_ECX_AVX512VNNI,
2539 .features[FEAT_7_0_EDX] =
2540 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2541 /* Missing: XSAVES (not supported by some Linux versions,
2542 * including v4.1 to v4.12).
2543 * KVM doesn't yet expose any XSAVES state save component,
2544 * and the only one defined in Skylake (processor tracing)
2545 * probably will block migration anyway.
2547 .features[FEAT_XSAVE] =
2548 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2549 CPUID_XSAVE_XGETBV1,
2550 .features[FEAT_6_EAX] =
2552 .xlevel = 0x80000008,
2553 .model_id = "Intel Xeon Processor (Cascadelake)",
2556 .name = "Icelake-Client",
2558 .vendor = CPUID_VENDOR_INTEL,
2562 .features[FEAT_1_EDX] =
2563 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2564 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2565 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2566 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2567 CPUID_DE | CPUID_FP87,
2568 .features[FEAT_1_ECX] =
2569 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2570 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2571 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2572 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2573 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2574 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2575 .features[FEAT_8000_0001_EDX] =
2576 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2578 .features[FEAT_8000_0001_ECX] =
2579 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2580 .features[FEAT_8000_0008_EBX] =
2581 CPUID_8000_0008_EBX_WBNOINVD,
2582 .features[FEAT_7_0_EBX] =
2583 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2584 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2585 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2586 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2588 .features[FEAT_7_0_ECX] =
2589 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2590 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2591 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2592 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2593 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2594 .features[FEAT_7_0_EDX] =
2595 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2596 /* Missing: XSAVES (not supported by some Linux versions,
2597 * including v4.1 to v4.12).
2598 * KVM doesn't yet expose any XSAVES state save component,
2599 * and the only one defined in Skylake (processor tracing)
2600 * probably will block migration anyway.
2602 .features[FEAT_XSAVE] =
2603 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2604 CPUID_XSAVE_XGETBV1,
2605 .features[FEAT_6_EAX] =
2607 .xlevel = 0x80000008,
2608 .model_id = "Intel Core Processor (Icelake)",
2611 .name = "Icelake-Server",
2613 .vendor = CPUID_VENDOR_INTEL,
2617 .features[FEAT_1_EDX] =
2618 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2619 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2620 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2621 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2622 CPUID_DE | CPUID_FP87,
2623 .features[FEAT_1_ECX] =
2624 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2625 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2626 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2627 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2628 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2629 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2630 .features[FEAT_8000_0001_EDX] =
2631 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2632 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2633 .features[FEAT_8000_0001_ECX] =
2634 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2635 .features[FEAT_8000_0008_EBX] =
2636 CPUID_8000_0008_EBX_WBNOINVD,
2637 .features[FEAT_7_0_EBX] =
2638 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2639 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2640 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2641 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2642 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2643 CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2644 CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2645 CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2646 .features[FEAT_7_0_ECX] =
2647 CPUID_7_0_ECX_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
2648 CPUID_7_0_ECX_VBMI2 | CPUID_7_0_ECX_GFNI |
2649 CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
2650 CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
2651 CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
2652 .features[FEAT_7_0_EDX] =
2653 CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
2654 /* Missing: XSAVES (not supported by some Linux versions,
2655 * including v4.1 to v4.12).
2656 * KVM doesn't yet expose any XSAVES state save component,
2657 * and the only one defined in Skylake (processor tracing)
2658 * probably will block migration anyway.
2660 .features[FEAT_XSAVE] =
2661 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2662 CPUID_XSAVE_XGETBV1,
2663 .features[FEAT_6_EAX] =
2665 .xlevel = 0x80000008,
2666 .model_id = "Intel Xeon Processor (Icelake)",
2669 .name = "KnightsMill",
2671 .vendor = CPUID_VENDOR_INTEL,
2675 .features[FEAT_1_EDX] =
2676 CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
2677 CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
2678 CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
2679 CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
2680 CPUID_PSE | CPUID_DE | CPUID_FP87,
2681 .features[FEAT_1_ECX] =
2682 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2683 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2684 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2685 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2686 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2687 CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2688 .features[FEAT_8000_0001_EDX] =
2689 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2690 CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2691 .features[FEAT_8000_0001_ECX] =
2692 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2693 .features[FEAT_7_0_EBX] =
2694 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2695 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
2696 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
2697 CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
2698 CPUID_7_0_EBX_AVX512ER,
2699 .features[FEAT_7_0_ECX] =
2700 CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
2701 .features[FEAT_7_0_EDX] =
2702 CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
2703 .features[FEAT_XSAVE] =
2704 CPUID_XSAVE_XSAVEOPT,
2705 .features[FEAT_6_EAX] =
2707 .xlevel = 0x80000008,
2708 .model_id = "Intel Xeon Phi Processor (Knights Mill)",
2711 .name = "Opteron_G1",
2713 .vendor = CPUID_VENDOR_AMD,
2717 .features[FEAT_1_EDX] =
2718 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2719 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2720 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2721 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2722 CPUID_DE | CPUID_FP87,
2723 .features[FEAT_1_ECX] =
2725 .features[FEAT_8000_0001_EDX] =
2726 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2727 .xlevel = 0x80000008,
2728 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
2731 .name = "Opteron_G2",
2733 .vendor = CPUID_VENDOR_AMD,
2737 .features[FEAT_1_EDX] =
2738 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2739 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2740 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2741 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2742 CPUID_DE | CPUID_FP87,
2743 .features[FEAT_1_ECX] =
2744 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
2745 .features[FEAT_8000_0001_EDX] =
2746 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2747 .features[FEAT_8000_0001_ECX] =
2748 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2749 .xlevel = 0x80000008,
2750 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
2753 .name = "Opteron_G3",
2755 .vendor = CPUID_VENDOR_AMD,
2759 .features[FEAT_1_EDX] =
2760 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2761 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2762 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2763 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2764 CPUID_DE | CPUID_FP87,
2765 .features[FEAT_1_ECX] =
2766 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
2768 .features[FEAT_8000_0001_EDX] =
2769 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
2771 .features[FEAT_8000_0001_ECX] =
2772 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
2773 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
2774 .xlevel = 0x80000008,
2775 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
2778 .name = "Opteron_G4",
2780 .vendor = CPUID_VENDOR_AMD,
2784 .features[FEAT_1_EDX] =
2785 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2786 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2787 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2788 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2789 CPUID_DE | CPUID_FP87,
2790 .features[FEAT_1_ECX] =
2791 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2792 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2793 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2795 .features[FEAT_8000_0001_EDX] =
2796 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2797 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2798 .features[FEAT_8000_0001_ECX] =
2799 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2800 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2801 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2803 .features[FEAT_SVM] =
2804 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2806 .xlevel = 0x8000001A,
2807 .model_id = "AMD Opteron 62xx class CPU",
2810 .name = "Opteron_G5",
2812 .vendor = CPUID_VENDOR_AMD,
2816 .features[FEAT_1_EDX] =
2817 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2818 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2819 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2820 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2821 CPUID_DE | CPUID_FP87,
2822 .features[FEAT_1_ECX] =
2823 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
2824 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2825 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
2826 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2827 .features[FEAT_8000_0001_EDX] =
2828 CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
2829 CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
2830 .features[FEAT_8000_0001_ECX] =
2831 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
2832 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
2833 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
2835 .features[FEAT_SVM] =
2836 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2838 .xlevel = 0x8000001A,
2839 .model_id = "AMD Opteron 63xx class CPU",
2844 .vendor = CPUID_VENDOR_AMD,
2848 .features[FEAT_1_EDX] =
2849 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2850 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2851 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2852 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2853 CPUID_VME | CPUID_FP87,
2854 .features[FEAT_1_ECX] =
2855 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2856 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2857 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2858 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2859 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2860 .features[FEAT_8000_0001_EDX] =
2861 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2862 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2864 .features[FEAT_8000_0001_ECX] =
2865 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2866 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2867 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2869 .features[FEAT_7_0_EBX] =
2870 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2871 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2872 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2873 CPUID_7_0_EBX_SHA_NI,
2874 /* Missing: XSAVES (not supported by some Linux versions,
2875 * including v4.1 to v4.12).
2876 * KVM doesn't yet expose any XSAVES state save component.
2878 .features[FEAT_XSAVE] =
2879 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2880 CPUID_XSAVE_XGETBV1,
2881 .features[FEAT_6_EAX] =
2883 .features[FEAT_SVM] =
2884 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2885 .xlevel = 0x8000001E,
2886 .model_id = "AMD EPYC Processor",
2887 .cache_info = &epyc_cache_info,
2890 .name = "EPYC-IBPB",
2892 .vendor = CPUID_VENDOR_AMD,
2896 .features[FEAT_1_EDX] =
2897 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2898 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2899 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2900 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2901 CPUID_VME | CPUID_FP87,
2902 .features[FEAT_1_ECX] =
2903 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2904 CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
2905 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2906 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2907 CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2908 .features[FEAT_8000_0001_EDX] =
2909 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2910 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2912 .features[FEAT_8000_0001_ECX] =
2913 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2914 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2915 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2917 .features[FEAT_8000_0008_EBX] =
2918 CPUID_8000_0008_EBX_IBPB,
2919 .features[FEAT_7_0_EBX] =
2920 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2921 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2922 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
2923 CPUID_7_0_EBX_SHA_NI,
2924 /* Missing: XSAVES (not supported by some Linux versions,
2925 * including v4.1 to v4.12).
2926 * KVM doesn't yet expose any XSAVES state save component.
2928 .features[FEAT_XSAVE] =
2929 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2930 CPUID_XSAVE_XGETBV1,
2931 .features[FEAT_6_EAX] =
2933 .features[FEAT_SVM] =
2934 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2935 .xlevel = 0x8000001E,
2936 .model_id = "AMD EPYC Processor (with IBPB)",
2937 .cache_info = &epyc_cache_info,
2942 .vendor = CPUID_VENDOR_HYGON,
2946 .features[FEAT_1_EDX] =
2947 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
2948 CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
2949 CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
2950 CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
2951 CPUID_VME | CPUID_FP87,
2952 .features[FEAT_1_ECX] =
2953 CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
2954 CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
2955 CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2956 CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
2957 CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
2958 .features[FEAT_8000_0001_EDX] =
2959 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
2960 CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
2962 .features[FEAT_8000_0001_ECX] =
2963 CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
2964 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
2965 CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
2967 .features[FEAT_8000_0008_EBX] =
2968 CPUID_8000_0008_EBX_IBPB,
2969 .features[FEAT_7_0_EBX] =
2970 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
2971 CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
2972 CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
2974 * Missing: XSAVES (not supported by some Linux versions,
2975 * including v4.1 to v4.12).
2976 * KVM doesn't yet expose any XSAVES state save component.
2978 .features[FEAT_XSAVE] =
2979 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2980 CPUID_XSAVE_XGETBV1,
2981 .features[FEAT_6_EAX] =
2983 .features[FEAT_SVM] =
2984 CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
2985 .xlevel = 0x8000001E,
2986 .model_id = "Hygon Dhyana Processor",
2987 .cache_info = &epyc_cache_info,
2991 typedef struct PropValue {
2992 const char *prop, *value;
2995 /* KVM-specific features that are automatically added/removed
2996 * from all CPU models when KVM is enabled.
2998 static PropValue kvm_default_props[] = {
2999 { "kvmclock", "on" },
3000 { "kvm-nopiodelay", "on" },
3001 { "kvm-asyncpf", "on" },
3002 { "kvm-steal-time", "on" },
3003 { "kvm-pv-eoi", "on" },
3004 { "kvmclock-stable-bit", "on" },
3007 { "monitor", "off" },
3012 /* TCG-specific defaults that override all CPU models when using TCG
3014 static PropValue tcg_default_props[] = {
3020 void x86_cpu_change_kvm_default(const char *prop, const char *value)
3023 for (pv = kvm_default_props; pv->prop; pv++) {
3024 if (!strcmp(pv->prop, prop)) {
3030 /* It is valid to call this function only for properties that
3031 * are already present in the kvm_default_props table.
3036 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3037 bool migratable_only);
3039 static bool lmce_supported(void)
3041 uint64_t mce_cap = 0;
3044 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
3049 return !!(mce_cap & MCG_LMCE_P);
3052 #define CPUID_MODEL_ID_SZ 48
3055 * cpu_x86_fill_model_id:
3056 * Get CPUID model ID string from host CPU.
3058 * @str should have at least CPUID_MODEL_ID_SZ bytes
3060 * The function does NOT add a null terminator to the string
3063 static int cpu_x86_fill_model_id(char *str)
3065 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3068 for (i = 0; i < 3; i++) {
3069 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
3070 memcpy(str + i * 16 + 0, &eax, 4);
3071 memcpy(str + i * 16 + 4, &ebx, 4);
3072 memcpy(str + i * 16 + 8, &ecx, 4);
3073 memcpy(str + i * 16 + 12, &edx, 4);
3078 static Property max_x86_cpu_properties[] = {
3079 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
3080 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
3081 DEFINE_PROP_END_OF_LIST()
3084 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
3086 DeviceClass *dc = DEVICE_CLASS(oc);
3087 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3091 xcc->model_description =
3092 "Enables all features supported by the accelerator in the current host";
3094 dc->props = max_x86_cpu_properties;
3097 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp);
3099 static void max_x86_cpu_initfn(Object *obj)
3101 X86CPU *cpu = X86_CPU(obj);
3102 CPUX86State *env = &cpu->env;
3103 KVMState *s = kvm_state;
3105 /* We can't fill the features array here because we don't know yet if
3106 * "migratable" is true or false.
3108 cpu->max_features = true;
3110 if (accel_uses_host_cpuid()) {
3111 char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
3112 char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
3113 int family, model, stepping;
3114 X86CPUDefinition host_cpudef = { };
3115 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
3117 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
3118 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
3120 host_vendor_fms(vendor, &family, &model, &stepping);
3122 cpu_x86_fill_model_id(model_id);
3124 object_property_set_str(OBJECT(cpu), vendor, "vendor", &error_abort);
3125 object_property_set_int(OBJECT(cpu), family, "family", &error_abort);
3126 object_property_set_int(OBJECT(cpu), model, "model", &error_abort);
3127 object_property_set_int(OBJECT(cpu), stepping, "stepping",
3129 object_property_set_str(OBJECT(cpu), model_id, "model-id",
3132 if (kvm_enabled()) {
3133 env->cpuid_min_level =
3134 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
3135 env->cpuid_min_xlevel =
3136 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
3137 env->cpuid_min_xlevel2 =
3138 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
3140 env->cpuid_min_level =
3141 hvf_get_supported_cpuid(0x0, 0, R_EAX);
3142 env->cpuid_min_xlevel =
3143 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
3144 env->cpuid_min_xlevel2 =
3145 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
3148 if (lmce_supported()) {
3149 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
3152 object_property_set_str(OBJECT(cpu), CPUID_VENDOR_AMD,
3153 "vendor", &error_abort);
3154 object_property_set_int(OBJECT(cpu), 6, "family", &error_abort);
3155 object_property_set_int(OBJECT(cpu), 6, "model", &error_abort);
3156 object_property_set_int(OBJECT(cpu), 3, "stepping", &error_abort);
3157 object_property_set_str(OBJECT(cpu),
3158 "QEMU TCG CPU version " QEMU_HW_VERSION,
3159 "model-id", &error_abort);
3162 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
3165 static const TypeInfo max_x86_cpu_type_info = {
3166 .name = X86_CPU_TYPE_NAME("max"),
3167 .parent = TYPE_X86_CPU,
3168 .instance_init = max_x86_cpu_initfn,
3169 .class_init = max_x86_cpu_class_init,
3172 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3173 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
3175 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3177 xcc->host_cpuid_required = true;
3180 #if defined(CONFIG_KVM)
3181 xcc->model_description =
3182 "KVM processor with all supported host features ";
3183 #elif defined(CONFIG_HVF)
3184 xcc->model_description =
3185 "HVF processor with all supported host features ";
3189 static const TypeInfo host_x86_cpu_type_info = {
3190 .name = X86_CPU_TYPE_NAME("host"),
3191 .parent = X86_CPU_TYPE_NAME("max"),
3192 .class_init = host_x86_cpu_class_init,
3197 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
3199 assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
3202 case CPUID_FEATURE_WORD:
3204 const char *reg = get_register_name_32(f->cpuid.reg);
3206 return g_strdup_printf("CPUID.%02XH:%s",
3209 case MSR_FEATURE_WORD:
3210 return g_strdup_printf("MSR(%02XH)",
3217 static void report_unavailable_features(FeatureWord w, uint32_t mask)
3219 FeatureWordInfo *f = &feature_word_info[w];
3221 char *feat_word_str;
3223 for (i = 0; i < 32; ++i) {
3224 if ((1UL << i) & mask) {
3225 feat_word_str = feature_word_description(f, i);
3226 warn_report("%s doesn't support requested feature: %s%s%s [bit %d]",
3227 accel_uses_host_cpuid() ? "host" : "TCG",
3229 f->feat_names[i] ? "." : "",
3230 f->feat_names[i] ? f->feat_names[i] : "", i);
3231 g_free(feat_word_str);
3236 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
3237 const char *name, void *opaque,
3240 X86CPU *cpu = X86_CPU(obj);
3241 CPUX86State *env = &cpu->env;
3244 value = (env->cpuid_version >> 8) & 0xf;
3246 value += (env->cpuid_version >> 20) & 0xff;
3248 visit_type_int(v, name, &value, errp);
3251 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
3252 const char *name, void *opaque,
3255 X86CPU *cpu = X86_CPU(obj);
3256 CPUX86State *env = &cpu->env;
3257 const int64_t min = 0;
3258 const int64_t max = 0xff + 0xf;
3259 Error *local_err = NULL;
3262 visit_type_int(v, name, &value, &local_err);
3264 error_propagate(errp, local_err);
3267 if (value < min || value > max) {
3268 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3269 name ? name : "null", value, min, max);
3273 env->cpuid_version &= ~0xff00f00;
3275 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
3277 env->cpuid_version |= value << 8;
3281 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
3282 const char *name, void *opaque,
3285 X86CPU *cpu = X86_CPU(obj);
3286 CPUX86State *env = &cpu->env;
3289 value = (env->cpuid_version >> 4) & 0xf;
3290 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
3291 visit_type_int(v, name, &value, errp);
3294 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
3295 const char *name, void *opaque,
3298 X86CPU *cpu = X86_CPU(obj);
3299 CPUX86State *env = &cpu->env;
3300 const int64_t min = 0;
3301 const int64_t max = 0xff;
3302 Error *local_err = NULL;
3305 visit_type_int(v, name, &value, &local_err);
3307 error_propagate(errp, local_err);
3310 if (value < min || value > max) {
3311 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3312 name ? name : "null", value, min, max);
3316 env->cpuid_version &= ~0xf00f0;
3317 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
3320 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
3321 const char *name, void *opaque,
3324 X86CPU *cpu = X86_CPU(obj);
3325 CPUX86State *env = &cpu->env;
3328 value = env->cpuid_version & 0xf;
3329 visit_type_int(v, name, &value, errp);
3332 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
3333 const char *name, void *opaque,
3336 X86CPU *cpu = X86_CPU(obj);
3337 CPUX86State *env = &cpu->env;
3338 const int64_t min = 0;
3339 const int64_t max = 0xf;
3340 Error *local_err = NULL;
3343 visit_type_int(v, name, &value, &local_err);
3345 error_propagate(errp, local_err);
3348 if (value < min || value > max) {
3349 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3350 name ? name : "null", value, min, max);
3354 env->cpuid_version &= ~0xf;
3355 env->cpuid_version |= value & 0xf;
3358 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
3360 X86CPU *cpu = X86_CPU(obj);
3361 CPUX86State *env = &cpu->env;
3364 value = g_malloc(CPUID_VENDOR_SZ + 1);
3365 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
3366 env->cpuid_vendor3);
3370 static void x86_cpuid_set_vendor(Object *obj, const char *value,
3373 X86CPU *cpu = X86_CPU(obj);
3374 CPUX86State *env = &cpu->env;
3377 if (strlen(value) != CPUID_VENDOR_SZ) {
3378 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
3382 env->cpuid_vendor1 = 0;
3383 env->cpuid_vendor2 = 0;
3384 env->cpuid_vendor3 = 0;
3385 for (i = 0; i < 4; i++) {
3386 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
3387 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
3388 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
3392 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
3394 X86CPU *cpu = X86_CPU(obj);
3395 CPUX86State *env = &cpu->env;
3399 value = g_malloc(48 + 1);
3400 for (i = 0; i < 48; i++) {
3401 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
3407 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
3410 X86CPU *cpu = X86_CPU(obj);
3411 CPUX86State *env = &cpu->env;
3414 if (model_id == NULL) {
3417 len = strlen(model_id);
3418 memset(env->cpuid_model, 0, 48);
3419 for (i = 0; i < 48; i++) {
3423 c = (uint8_t)model_id[i];
3425 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
3429 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
3430 void *opaque, Error **errp)
3432 X86CPU *cpu = X86_CPU(obj);
3435 value = cpu->env.tsc_khz * 1000;
3436 visit_type_int(v, name, &value, errp);
3439 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
3440 void *opaque, Error **errp)
3442 X86CPU *cpu = X86_CPU(obj);
3443 const int64_t min = 0;
3444 const int64_t max = INT64_MAX;
3445 Error *local_err = NULL;
3448 visit_type_int(v, name, &value, &local_err);
3450 error_propagate(errp, local_err);
3453 if (value < min || value > max) {
3454 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
3455 name ? name : "null", value, min, max);
3459 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
3462 /* Generic getter for "feature-words" and "filtered-features" properties */
3463 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
3464 const char *name, void *opaque,
3467 uint32_t *array = (uint32_t *)opaque;
3469 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
3470 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
3471 X86CPUFeatureWordInfoList *list = NULL;
3473 for (w = 0; w < FEATURE_WORDS; w++) {
3474 FeatureWordInfo *wi = &feature_word_info[w];
3476 * We didn't have MSR features when "feature-words" was
3477 * introduced. Therefore skipped other type entries.
3479 if (wi->type != CPUID_FEATURE_WORD) {
3482 X86CPUFeatureWordInfo *qwi = &word_infos[w];
3483 qwi->cpuid_input_eax = wi->cpuid.eax;
3484 qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
3485 qwi->cpuid_input_ecx = wi->cpuid.ecx;
3486 qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
3487 qwi->features = array[w];
3489 /* List will be in reverse order, but order shouldn't matter */
3490 list_entries[w].next = list;
3491 list_entries[w].value = &word_infos[w];
3492 list = &list_entries[w];
3495 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
3498 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3499 void *opaque, Error **errp)
3501 X86CPU *cpu = X86_CPU(obj);
3502 int64_t value = cpu->hyperv_spinlock_attempts;
3504 visit_type_int(v, name, &value, errp);
3507 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
3508 void *opaque, Error **errp)
3510 const int64_t min = 0xFFF;
3511 const int64_t max = UINT_MAX;
3512 X86CPU *cpu = X86_CPU(obj);
3516 visit_type_int(v, name, &value, &err);
3518 error_propagate(errp, err);
3522 if (value < min || value > max) {
3523 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
3524 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
3525 object_get_typename(obj), name ? name : "null",
3529 cpu->hyperv_spinlock_attempts = value;
3532 static const PropertyInfo qdev_prop_spinlocks = {
3534 .get = x86_get_hv_spinlocks,
3535 .set = x86_set_hv_spinlocks,
3538 /* Convert all '_' in a feature string option name to '-', to make feature
3539 * name conform to QOM property naming rule, which uses '-' instead of '_'.
3541 static inline void feat2prop(char *s)
3543 while ((s = strchr(s, '_'))) {
3548 /* Return the feature property name for a feature flag bit */
3549 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
3551 /* XSAVE components are automatically enabled by other features,
3552 * so return the original feature name instead
3554 if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
3555 int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
3557 if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
3558 x86_ext_save_areas[comp].bits) {
3559 w = x86_ext_save_areas[comp].feature;
3560 bitnr = ctz32(x86_ext_save_areas[comp].bits);
3565 assert(w < FEATURE_WORDS);
3566 return feature_word_info[w].feat_names[bitnr];
3569 /* Compatibily hack to maintain legacy +-feat semantic,
3570 * where +-feat overwrites any feature set by
3571 * feat=on|feat even if the later is parsed after +-feat
3572 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
3574 static GList *plus_features, *minus_features;
3576 static gint compare_string(gconstpointer a, gconstpointer b)
3578 return g_strcmp0(a, b);
3581 /* Parse "+feature,-feature,feature=foo" CPU feature string
3583 static void x86_cpu_parse_featurestr(const char *typename, char *features,
3586 char *featurestr; /* Single 'key=value" string being parsed */
3587 static bool cpu_globals_initialized;
3588 bool ambiguous = false;
3590 if (cpu_globals_initialized) {
3593 cpu_globals_initialized = true;
3599 for (featurestr = strtok(features, ",");
3601 featurestr = strtok(NULL, ",")) {
3603 const char *val = NULL;
3606 GlobalProperty *prop;
3608 /* Compatibility syntax: */
3609 if (featurestr[0] == '+') {
3610 plus_features = g_list_append(plus_features,
3611 g_strdup(featurestr + 1));
3613 } else if (featurestr[0] == '-') {
3614 minus_features = g_list_append(minus_features,
3615 g_strdup(featurestr + 1));
3619 eq = strchr(featurestr, '=');
3627 feat2prop(featurestr);
3630 if (g_list_find_custom(plus_features, name, compare_string)) {
3631 warn_report("Ambiguous CPU model string. "
3632 "Don't mix both \"+%s\" and \"%s=%s\"",
3636 if (g_list_find_custom(minus_features, name, compare_string)) {
3637 warn_report("Ambiguous CPU model string. "
3638 "Don't mix both \"-%s\" and \"%s=%s\"",
3644 if (!strcmp(name, "tsc-freq")) {
3648 ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
3649 if (ret < 0 || tsc_freq > INT64_MAX) {
3650 error_setg(errp, "bad numerical value %s", val);
3653 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
3655 name = "tsc-frequency";
3658 prop = g_new0(typeof(*prop), 1);
3659 prop->driver = typename;
3660 prop->property = g_strdup(name);
3661 prop->value = g_strdup(val);
3662 qdev_prop_register_global(prop);
3666 warn_report("Compatibility of ambiguous CPU model "
3667 "strings won't be kept on future QEMU versions");
3671 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
3672 static int x86_cpu_filter_features(X86CPU *cpu);
3674 /* Check for missing features that may prevent the CPU class from
3675 * running using the current machine and accelerator.
3677 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
3678 strList **missing_feats)
3683 strList **next = missing_feats;
3685 if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
3686 strList *new = g_new0(strList, 1);
3687 new->value = g_strdup("kvm");
3688 *missing_feats = new;
3692 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
3694 x86_cpu_expand_features(xc, &err);
3696 /* Errors at x86_cpu_expand_features should never happen,
3697 * but in case it does, just report the model as not
3698 * runnable at all using the "type" property.
3700 strList *new = g_new0(strList, 1);
3701 new->value = g_strdup("type");
3706 x86_cpu_filter_features(xc);
3708 for (w = 0; w < FEATURE_WORDS; w++) {
3709 uint32_t filtered = xc->filtered_features[w];
3711 for (i = 0; i < 32; i++) {
3712 if (filtered & (1UL << i)) {
3713 strList *new = g_new0(strList, 1);
3714 new->value = g_strdup(x86_cpu_feature_name(w, i));
3721 object_unref(OBJECT(xc));
3724 /* Print all cpuid feature names in featureset
3726 static void listflags(GList *features)
3731 for (tmp = features; tmp; tmp = tmp->next) {
3732 const char *name = tmp->data;
3733 if ((len + strlen(name) + 1) >= 75) {
3737 qemu_printf("%s%s", len == 0 ? " " : " ", name);
3738 len += strlen(name) + 1;
3743 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
3744 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
3746 ObjectClass *class_a = (ObjectClass *)a;
3747 ObjectClass *class_b = (ObjectClass *)b;
3748 X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
3749 X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
3750 char *name_a, *name_b;
3753 if (cc_a->ordering != cc_b->ordering) {
3754 ret = cc_a->ordering - cc_b->ordering;
3756 name_a = x86_cpu_class_get_model_name(cc_a);
3757 name_b = x86_cpu_class_get_model_name(cc_b);
3758 ret = strcmp(name_a, name_b);
3765 static GSList *get_sorted_cpu_model_list(void)
3767 GSList *list = object_class_get_list(TYPE_X86_CPU, false);
3768 list = g_slist_sort(list, x86_cpu_list_compare);
3772 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
3774 ObjectClass *oc = data;
3775 X86CPUClass *cc = X86_CPU_CLASS(oc);
3776 char *name = x86_cpu_class_get_model_name(cc);
3777 const char *desc = cc->model_description;
3778 if (!desc && cc->cpu_def) {
3779 desc = cc->cpu_def->model_id;
3782 qemu_printf("x86 %-20s %-48s\n", name, desc);
3786 /* list available CPU models and flags */
3787 void x86_cpu_list(void)
3791 GList *names = NULL;
3793 qemu_printf("Available CPUs:\n");
3794 list = get_sorted_cpu_model_list();
3795 g_slist_foreach(list, x86_cpu_list_entry, NULL);
3799 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
3800 FeatureWordInfo *fw = &feature_word_info[i];
3801 for (j = 0; j < 32; j++) {
3802 if (fw->feat_names[j]) {
3803 names = g_list_append(names, (gpointer)fw->feat_names[j]);
3808 names = g_list_sort(names, (GCompareFunc)strcmp);
3810 qemu_printf("\nRecognized CPUID flags:\n");
3816 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
3818 ObjectClass *oc = data;
3819 X86CPUClass *cc = X86_CPU_CLASS(oc);
3820 CpuDefinitionInfoList **cpu_list = user_data;
3821 CpuDefinitionInfoList *entry;
3822 CpuDefinitionInfo *info;
3824 info = g_malloc0(sizeof(*info));
3825 info->name = x86_cpu_class_get_model_name(cc);
3826 x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
3827 info->has_unavailable_features = true;
3828 info->q_typename = g_strdup(object_class_get_name(oc));
3829 info->migration_safe = cc->migration_safe;
3830 info->has_migration_safe = true;
3831 info->q_static = cc->static_model;
3833 entry = g_malloc0(sizeof(*entry));
3834 entry->value = info;
3835 entry->next = *cpu_list;
3839 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
3841 CpuDefinitionInfoList *cpu_list = NULL;
3842 GSList *list = get_sorted_cpu_model_list();
3843 g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
3848 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
3849 bool migratable_only)
3851 FeatureWordInfo *wi = &feature_word_info[w];
3854 if (kvm_enabled()) {
3856 case CPUID_FEATURE_WORD:
3857 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
3861 case MSR_FEATURE_WORD:
3862 r = kvm_arch_get_supported_msr_feature(kvm_state,
3866 } else if (hvf_enabled()) {
3867 if (wi->type != CPUID_FEATURE_WORD) {
3870 r = hvf_get_supported_cpuid(wi->cpuid.eax,
3873 } else if (tcg_enabled()) {
3874 r = wi->tcg_features;
3878 if (migratable_only) {
3879 r &= x86_cpu_get_migratable_flags(w);
3884 static void x86_cpu_report_filtered_features(X86CPU *cpu)
3888 for (w = 0; w < FEATURE_WORDS; w++) {
3889 report_unavailable_features(w, cpu->filtered_features[w]);
3893 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
3896 for (pv = props; pv->prop; pv++) {
3900 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
3905 /* Load data from X86CPUDefinition into a X86CPU object
3907 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
3909 CPUX86State *env = &cpu->env;
3911 char host_vendor[CPUID_VENDOR_SZ + 1];
3914 /*NOTE: any property set by this function should be returned by
3915 * x86_cpu_static_props(), so static expansion of
3916 * query-cpu-model-expansion is always complete.
3919 /* CPU models only set _minimum_ values for level/xlevel: */
3920 object_property_set_uint(OBJECT(cpu), def->level, "min-level", errp);
3921 object_property_set_uint(OBJECT(cpu), def->xlevel, "min-xlevel", errp);
3923 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
3924 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
3925 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
3926 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
3927 for (w = 0; w < FEATURE_WORDS; w++) {
3928 env->features[w] = def->features[w];
3931 /* legacy-cache defaults to 'off' if CPU model provides cache info */
3932 cpu->legacy_cache = !def->cache_info;
3934 /* Special cases not set in the X86CPUDefinition structs: */
3935 /* TODO: in-kernel irqchip for hvf */
3936 if (kvm_enabled()) {
3937 if (!kvm_irqchip_in_kernel()) {
3938 x86_cpu_change_kvm_default("x2apic", "off");
3941 x86_cpu_apply_props(cpu, kvm_default_props);
3942 } else if (tcg_enabled()) {
3943 x86_cpu_apply_props(cpu, tcg_default_props);
3946 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
3948 /* sysenter isn't supported in compatibility mode on AMD,
3949 * syscall isn't supported in compatibility mode on Intel.
3950 * Normally we advertise the actual CPU vendor, but you can
3951 * override this using the 'vendor' property if you want to use
3952 * KVM's sysenter/syscall emulation in compatibility mode and
3953 * when doing cross vendor migration
3955 vendor = def->vendor;
3956 if (accel_uses_host_cpuid()) {
3957 uint32_t ebx = 0, ecx = 0, edx = 0;
3958 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
3959 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
3960 vendor = host_vendor;
3963 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
3967 #ifndef CONFIG_USER_ONLY
3968 /* Return a QDict containing keys for all properties that can be included
3969 * in static expansion of CPU models. All properties set by x86_cpu_load_def()
3970 * must be included in the dictionary.
3972 static QDict *x86_cpu_static_props(void)
3976 static const char *props[] = {
3994 for (i = 0; props[i]; i++) {
3995 qdict_put_null(d, props[i]);
3998 for (w = 0; w < FEATURE_WORDS; w++) {
3999 FeatureWordInfo *fi = &feature_word_info[w];
4001 for (bit = 0; bit < 32; bit++) {
4002 if (!fi->feat_names[bit]) {
4005 qdict_put_null(d, fi->feat_names[bit]);
4012 /* Add an entry to @props dict, with the value for property. */
4013 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
4015 QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
4018 qdict_put_obj(props, prop, value);
4021 /* Convert CPU model data from X86CPU object to a property dictionary
4022 * that can recreate exactly the same CPU model.
4024 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
4026 QDict *sprops = x86_cpu_static_props();
4027 const QDictEntry *e;
4029 for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
4030 const char *prop = qdict_entry_key(e);
4031 x86_cpu_expand_prop(cpu, props, prop);
4035 /* Convert CPU model data from X86CPU object to a property dictionary
4036 * that can recreate exactly the same CPU model, including every
4037 * writeable QOM property.
4039 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
4041 ObjectPropertyIterator iter;
4042 ObjectProperty *prop;
4044 object_property_iter_init(&iter, OBJECT(cpu));
4045 while ((prop = object_property_iter_next(&iter))) {
4046 /* skip read-only or write-only properties */
4047 if (!prop->get || !prop->set) {
4051 /* "hotplugged" is the only property that is configurable
4052 * on the command-line but will be set differently on CPUs
4053 * created using "-cpu ... -smp ..." and by CPUs created
4054 * on the fly by x86_cpu_from_model() for querying. Skip it.
4056 if (!strcmp(prop->name, "hotplugged")) {
4059 x86_cpu_expand_prop(cpu, props, prop->name);
4063 static void object_apply_props(Object *obj, QDict *props, Error **errp)
4065 const QDictEntry *prop;
4068 for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
4069 object_property_set_qobject(obj, qdict_entry_value(prop),
4070 qdict_entry_key(prop), &err);
4076 error_propagate(errp, err);
4079 /* Create X86CPU object according to model+props specification */
4080 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
4086 xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
4088 error_setg(&err, "CPU model '%s' not found", model);
4092 xc = X86_CPU(object_new(object_class_get_name(OBJECT_CLASS(xcc))));
4094 object_apply_props(OBJECT(xc), props, &err);
4100 x86_cpu_expand_features(xc, &err);
4107 error_propagate(errp, err);
4108 object_unref(OBJECT(xc));
4114 CpuModelExpansionInfo *
4115 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
4116 CpuModelInfo *model,
4121 CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
4122 QDict *props = NULL;
4123 const char *base_name;
4125 xc = x86_cpu_from_model(model->name,
4127 qobject_to(QDict, model->props) :
4133 props = qdict_new();
4134 ret->model = g_new0(CpuModelInfo, 1);
4135 ret->model->props = QOBJECT(props);
4136 ret->model->has_props = true;
4139 case CPU_MODEL_EXPANSION_TYPE_STATIC:
4140 /* Static expansion will be based on "base" only */
4142 x86_cpu_to_dict(xc, props);
4144 case CPU_MODEL_EXPANSION_TYPE_FULL:
4145 /* As we don't return every single property, full expansion needs
4146 * to keep the original model name+props, and add extra
4147 * properties on top of that.
4149 base_name = model->name;
4150 x86_cpu_to_dict_full(xc, props);
4153 error_setg(&err, "Unsupported expansion type");
4157 x86_cpu_to_dict(xc, props);
4159 ret->model->name = g_strdup(base_name);
4162 object_unref(OBJECT(xc));
4164 error_propagate(errp, err);
4165 qapi_free_CpuModelExpansionInfo(ret);
4170 #endif /* !CONFIG_USER_ONLY */
4172 static gchar *x86_gdb_arch_name(CPUState *cs)
4174 #ifdef TARGET_X86_64
4175 return g_strdup("i386:x86-64");
4177 return g_strdup("i386");
4181 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
4183 X86CPUDefinition *cpudef = data;
4184 X86CPUClass *xcc = X86_CPU_CLASS(oc);
4186 xcc->cpu_def = cpudef;
4187 xcc->migration_safe = true;
4190 static void x86_register_cpudef_type(X86CPUDefinition *def)
4192 char *typename = x86_cpu_type_name(def->name);
4195 .parent = TYPE_X86_CPU,
4196 .class_init = x86_cpu_cpudef_class_init,
4200 /* AMD aliases are handled at runtime based on CPUID vendor, so
4201 * they shouldn't be set on the CPU model table.
4203 assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
4204 /* catch mistakes instead of silently truncating model_id when too long */
4205 assert(def->model_id && strlen(def->model_id) <= 48);
4212 #if !defined(CONFIG_USER_ONLY)
4214 void cpu_clear_apic_feature(CPUX86State *env)
4216 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
4219 #endif /* !CONFIG_USER_ONLY */
4221 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
4222 uint32_t *eax, uint32_t *ebx,
4223 uint32_t *ecx, uint32_t *edx)
4225 X86CPU *cpu = env_archcpu(env);
4226 CPUState *cs = env_cpu(env);
4227 uint32_t pkg_offset;
4229 uint32_t signature[3];
4231 /* Calculate & apply limits for different index ranges */
4232 if (index >= 0xC0000000) {
4233 limit = env->cpuid_xlevel2;
4234 } else if (index >= 0x80000000) {
4235 limit = env->cpuid_xlevel;
4236 } else if (index >= 0x40000000) {
4239 limit = env->cpuid_level;
4242 if (index > limit) {
4243 /* Intel documentation states that invalid EAX input will
4244 * return the same information as EAX=cpuid_level
4245 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
4247 index = env->cpuid_level;
4252 *eax = env->cpuid_level;
4253 *ebx = env->cpuid_vendor1;
4254 *edx = env->cpuid_vendor2;
4255 *ecx = env->cpuid_vendor3;
4258 *eax = env->cpuid_version;
4259 *ebx = (cpu->apic_id << 24) |
4260 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
4261 *ecx = env->features[FEAT_1_ECX];
4262 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
4263 *ecx |= CPUID_EXT_OSXSAVE;
4265 *edx = env->features[FEAT_1_EDX];
4266 if (cs->nr_cores * cs->nr_threads > 1) {
4267 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
4272 /* cache info: needed for Pentium Pro compatibility */
4273 if (cpu->cache_info_passthrough) {
4274 host_cpuid(index, 0, eax, ebx, ecx, edx);
4277 *eax = 1; /* Number of CPUID[EAX=2] calls required */
4279 if (!cpu->enable_l3_cache) {
4282 *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
4284 *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
4285 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) << 8) |
4286 (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
4289 /* cache info: needed for Core compatibility */
4290 if (cpu->cache_info_passthrough) {
4291 host_cpuid(index, count, eax, ebx, ecx, edx);
4292 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
4293 *eax &= ~0xFC000000;
4294 if ((*eax & 31) && cs->nr_cores > 1) {
4295 *eax |= (cs->nr_cores - 1) << 26;
4300 case 0: /* L1 dcache info */
4301 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
4303 eax, ebx, ecx, edx);
4305 case 1: /* L1 icache info */
4306 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
4308 eax, ebx, ecx, edx);
4310 case 2: /* L2 cache info */
4311 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
4312 cs->nr_threads, cs->nr_cores,
4313 eax, ebx, ecx, edx);
4315 case 3: /* L3 cache info */
4316 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4317 if (cpu->enable_l3_cache) {
4318 encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
4319 (1 << pkg_offset), cs->nr_cores,
4320 eax, ebx, ecx, edx);
4324 default: /* end of info */
4325 *eax = *ebx = *ecx = *edx = 0;
4331 /* MONITOR/MWAIT Leaf */
4332 *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
4333 *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
4334 *ecx = cpu->mwait.ecx; /* flags */
4335 *edx = cpu->mwait.edx; /* mwait substates */
4338 /* Thermal and Power Leaf */
4339 *eax = env->features[FEAT_6_EAX];
4345 /* Structured Extended Feature Flags Enumeration Leaf */
4347 *eax = 0; /* Maximum ECX value for sub-leaves */
4348 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
4349 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
4350 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
4351 *ecx |= CPUID_7_0_ECX_OSPKE;
4353 *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
4362 /* Direct Cache Access Information Leaf */
4363 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
4369 /* Architectural Performance Monitoring Leaf */
4370 if (kvm_enabled() && cpu->enable_pmu) {
4371 KVMState *s = cs->kvm_state;
4373 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
4374 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
4375 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
4376 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
4377 } else if (hvf_enabled() && cpu->enable_pmu) {
4378 *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
4379 *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
4380 *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
4381 *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
4390 /* Extended Topology Enumeration Leaf */
4391 if (!cpu->enable_cpuid_0xb) {
4392 *eax = *ebx = *ecx = *edx = 0;
4396 *ecx = count & 0xff;
4397 *edx = cpu->apic_id;
4401 *eax = apicid_core_offset(cs->nr_cores, cs->nr_threads);
4402 *ebx = cs->nr_threads;
4403 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
4406 *eax = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
4407 *ebx = cs->nr_cores * cs->nr_threads;
4408 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
4413 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
4416 assert(!(*eax & ~0x1f));
4417 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
4420 /* Processor Extended State */
4425 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4430 *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
4431 *eax = env->features[FEAT_XSAVE_COMP_LO];
4432 *edx = env->features[FEAT_XSAVE_COMP_HI];
4433 *ebx = xsave_area_size(env->xcr0);
4434 } else if (count == 1) {
4435 *eax = env->features[FEAT_XSAVE];
4436 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
4437 if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
4438 const ExtSaveArea *esa = &x86_ext_save_areas[count];
4446 /* Intel Processor Trace Enumeration */
4451 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
4457 *eax = INTEL_PT_MAX_SUBLEAF;
4458 *ebx = INTEL_PT_MINIMAL_EBX;
4459 *ecx = INTEL_PT_MINIMAL_ECX;
4460 } else if (count == 1) {
4461 *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
4462 *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
4468 * CPUID code in kvm_arch_init_vcpu() ignores stuff
4469 * set here, but we restrict to TCG none the less.
4471 if (tcg_enabled() && cpu->expose_tcg) {
4472 memcpy(signature, "TCGTCGTCGTCG", 12);
4474 *ebx = signature[0];
4475 *ecx = signature[1];
4476 *edx = signature[2];
4491 *eax = env->cpuid_xlevel;
4492 *ebx = env->cpuid_vendor1;
4493 *edx = env->cpuid_vendor2;
4494 *ecx = env->cpuid_vendor3;
4497 *eax = env->cpuid_version;
4499 *ecx = env->features[FEAT_8000_0001_ECX];
4500 *edx = env->features[FEAT_8000_0001_EDX];
4502 /* The Linux kernel checks for the CMPLegacy bit and
4503 * discards multiple thread information if it is set.
4504 * So don't set it here for Intel to make Linux guests happy.
4506 if (cs->nr_cores * cs->nr_threads > 1) {
4507 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
4508 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
4509 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
4510 *ecx |= 1 << 1; /* CmpLegacy bit */
4517 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
4518 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
4519 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
4520 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
4523 /* cache info (L1 cache) */
4524 if (cpu->cache_info_passthrough) {
4525 host_cpuid(index, 0, eax, ebx, ecx, edx);
4528 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
4529 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
4530 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
4531 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
4532 *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
4533 *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
4536 /* cache info (L2 cache) */
4537 if (cpu->cache_info_passthrough) {
4538 host_cpuid(index, 0, eax, ebx, ecx, edx);
4541 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
4542 (L2_DTLB_2M_ENTRIES << 16) | \
4543 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
4544 (L2_ITLB_2M_ENTRIES);
4545 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
4546 (L2_DTLB_4K_ENTRIES << 16) | \
4547 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
4548 (L2_ITLB_4K_ENTRIES);
4549 encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
4550 cpu->enable_l3_cache ?
4551 env->cache_info_amd.l3_cache : NULL,
4558 *edx = env->features[FEAT_8000_0007_EDX];
4561 /* virtual & phys address size in low 2 bytes. */
4562 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
4563 /* 64 bit processor */
4564 *eax = cpu->phys_bits; /* configurable physical bits */
4565 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
4566 *eax |= 0x00003900; /* 57 bits virtual */
4568 *eax |= 0x00003000; /* 48 bits virtual */
4571 *eax = cpu->phys_bits;
4573 *ebx = env->features[FEAT_8000_0008_EBX];
4576 if (cs->nr_cores * cs->nr_threads > 1) {
4577 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
4581 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
4582 *eax = 0x00000001; /* SVM Revision */
4583 *ebx = 0x00000010; /* nr of ASIDs */
4585 *edx = env->features[FEAT_SVM]; /* optional features */
4595 if (cpu->cache_info_passthrough) {
4596 host_cpuid(index, count, eax, ebx, ecx, edx);
4600 case 0: /* L1 dcache info */
4601 encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs,
4602 eax, ebx, ecx, edx);
4604 case 1: /* L1 icache info */
4605 encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs,
4606 eax, ebx, ecx, edx);
4608 case 2: /* L2 cache info */
4609 encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs,
4610 eax, ebx, ecx, edx);
4612 case 3: /* L3 cache info */
4613 encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs,
4614 eax, ebx, ecx, edx);
4616 default: /* end of info */
4617 *eax = *ebx = *ecx = *edx = 0;
4622 assert(cpu->core_id <= 255);
4623 encode_topo_cpuid8000001e(cs, cpu,
4624 eax, ebx, ecx, edx);
4627 *eax = env->cpuid_xlevel2;
4633 /* Support for VIA CPU's CPUID instruction */
4634 *eax = env->cpuid_version;
4637 *edx = env->features[FEAT_C000_0001_EDX];
4642 /* Reserved for the future, and now filled with zero */
4649 *eax = sev_enabled() ? 0x2 : 0;
4650 *ebx = sev_get_cbit_position();
4651 *ebx |= sev_get_reduced_phys_bits() << 6;
4656 /* reserved values: zero */
4665 /* CPUClass::reset() */
4666 static void x86_cpu_reset(CPUState *s)
4668 X86CPU *cpu = X86_CPU(s);
4669 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
4670 CPUX86State *env = &cpu->env;
4675 xcc->parent_reset(s);
4677 memset(env, 0, offsetof(CPUX86State, end_reset_fields));
4679 env->old_exception = -1;
4681 /* init to reset state */
4683 env->hflags2 |= HF2_GIF_MASK;
4685 cpu_x86_update_cr0(env, 0x60000010);
4686 env->a20_mask = ~0x0;
4687 env->smbase = 0x30000;
4688 env->msr_smi_count = 0;
4690 env->idt.limit = 0xffff;
4691 env->gdt.limit = 0xffff;
4692 env->ldt.limit = 0xffff;
4693 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
4694 env->tr.limit = 0xffff;
4695 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
4697 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
4698 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
4699 DESC_R_MASK | DESC_A_MASK);
4700 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
4701 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4703 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
4704 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4706 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
4707 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4709 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
4710 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4712 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
4713 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
4717 env->regs[R_EDX] = env->cpuid_version;
4722 for (i = 0; i < 8; i++) {
4725 cpu_set_fpuc(env, 0x37f);
4727 env->mxcsr = 0x1f80;
4728 /* All units are in INIT state. */
4731 env->pat = 0x0007040600070406ULL;
4732 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
4733 if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
4734 env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
4737 memset(env->dr, 0, sizeof(env->dr));
4738 env->dr[6] = DR6_FIXED_1;
4739 env->dr[7] = DR7_FIXED_1;
4740 cpu_breakpoint_remove_all(s, BP_CPU);
4741 cpu_watchpoint_remove_all(s, BP_CPU);
4744 xcr0 = XSTATE_FP_MASK;
4746 #ifdef CONFIG_USER_ONLY
4747 /* Enable all the features for user-mode. */
4748 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
4749 xcr0 |= XSTATE_SSE_MASK;
4751 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4752 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4753 if (env->features[esa->feature] & esa->bits) {
4758 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
4759 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
4761 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
4762 cr4 |= CR4_FSGSBASE_MASK;
4767 cpu_x86_update_cr4(env, cr4);
4770 * SDM 11.11.5 requires:
4771 * - IA32_MTRR_DEF_TYPE MSR.E = 0
4772 * - IA32_MTRR_PHYSMASKn.V = 0
4773 * All other bits are undefined. For simplification, zero it all.
4775 env->mtrr_deftype = 0;
4776 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
4777 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
4779 env->interrupt_injected = -1;
4780 env->exception_injected = -1;
4781 env->nmi_injected = false;
4782 #if !defined(CONFIG_USER_ONLY)
4783 /* We hard-wire the BSP to the first CPU. */
4784 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
4786 s->halted = !cpu_is_bsp(cpu);
4788 if (kvm_enabled()) {
4789 kvm_arch_reset_vcpu(cpu);
4791 else if (hvf_enabled()) {
4797 #ifndef CONFIG_USER_ONLY
4798 bool cpu_is_bsp(X86CPU *cpu)
4800 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
4803 /* TODO: remove me, when reset over QOM tree is implemented */
4804 static void x86_cpu_machine_reset_cb(void *opaque)
4806 X86CPU *cpu = opaque;
4807 cpu_reset(CPU(cpu));
4811 static void mce_init(X86CPU *cpu)
4813 CPUX86State *cenv = &cpu->env;
4816 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
4817 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
4818 (CPUID_MCE | CPUID_MCA)) {
4819 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
4820 (cpu->enable_lmce ? MCG_LMCE_P : 0);
4821 cenv->mcg_ctl = ~(uint64_t)0;
4822 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
4823 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
4828 #ifndef CONFIG_USER_ONLY
4829 APICCommonClass *apic_get_class(void)
4831 const char *apic_type = "apic";
4833 /* TODO: in-kernel irqchip for hvf */
4834 if (kvm_apic_in_kernel()) {
4835 apic_type = "kvm-apic";
4836 } else if (xen_enabled()) {
4837 apic_type = "xen-apic";
4840 return APIC_COMMON_CLASS(object_class_by_name(apic_type));
4843 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
4845 APICCommonState *apic;
4846 ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
4848 cpu->apic_state = DEVICE(object_new(object_class_get_name(apic_class)));
4850 object_property_add_child(OBJECT(cpu), "lapic",
4851 OBJECT(cpu->apic_state), &error_abort);
4852 object_unref(OBJECT(cpu->apic_state));
4854 qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
4855 /* TODO: convert to link<> */
4856 apic = APIC_COMMON(cpu->apic_state);
4858 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
4861 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4863 APICCommonState *apic;
4864 static bool apic_mmio_map_once;
4866 if (cpu->apic_state == NULL) {
4869 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
4872 /* Map APIC MMIO area */
4873 apic = APIC_COMMON(cpu->apic_state);
4874 if (!apic_mmio_map_once) {
4875 memory_region_add_subregion_overlap(get_system_memory(),
4877 MSR_IA32_APICBASE_BASE,
4880 apic_mmio_map_once = true;
4884 static void x86_cpu_machine_done(Notifier *n, void *unused)
4886 X86CPU *cpu = container_of(n, X86CPU, machine_done);
4887 MemoryRegion *smram =
4888 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
4891 cpu->smram = g_new(MemoryRegion, 1);
4892 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
4893 smram, 0, 1ull << 32);
4894 memory_region_set_enabled(cpu->smram, true);
4895 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
4899 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
4904 /* Note: Only safe for use on x86(-64) hosts */
4905 static uint32_t x86_host_phys_bits(void)
4908 uint32_t host_phys_bits;
4910 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
4911 if (eax >= 0x80000008) {
4912 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
4913 /* Note: According to AMD doc 25481 rev 2.34 they have a field
4914 * at 23:16 that can specify a maximum physical address bits for
4915 * the guest that can override this value; but I've not seen
4916 * anything with that set.
4918 host_phys_bits = eax & 0xff;
4920 /* It's an odd 64 bit machine that doesn't have the leaf for
4921 * physical address bits; fall back to 36 that's most older
4924 host_phys_bits = 36;
4927 return host_phys_bits;
4930 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
4937 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
4938 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
4940 CPUX86State *env = &cpu->env;
4941 FeatureWordInfo *fi = &feature_word_info[w];
4942 uint32_t eax = fi->cpuid.eax;
4943 uint32_t region = eax & 0xF0000000;
4945 assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
4946 if (!env->features[w]) {
4952 x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
4955 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
4958 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
4963 /* Calculate XSAVE components based on the configured CPU feature flags */
4964 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
4966 CPUX86State *env = &cpu->env;
4970 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
4975 for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
4976 const ExtSaveArea *esa = &x86_ext_save_areas[i];
4977 if (env->features[esa->feature] & esa->bits) {
4978 mask |= (1ULL << i);
4982 env->features[FEAT_XSAVE_COMP_LO] = mask;
4983 env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
4986 /***** Steps involved on loading and filtering CPUID data
4988 * When initializing and realizing a CPU object, the steps
4989 * involved in setting up CPUID data are:
4991 * 1) Loading CPU model definition (X86CPUDefinition). This is
4992 * implemented by x86_cpu_load_def() and should be completely
4993 * transparent, as it is done automatically by instance_init.
4994 * No code should need to look at X86CPUDefinition structs
4995 * outside instance_init.
4997 * 2) CPU expansion. This is done by realize before CPUID
4998 * filtering, and will make sure host/accelerator data is
4999 * loaded for CPU models that depend on host capabilities
5000 * (e.g. "host"). Done by x86_cpu_expand_features().
5002 * 3) CPUID filtering. This initializes extra data related to
5003 * CPUID, and checks if the host supports all capabilities
5004 * required by the CPU. Runnability of a CPU model is
5005 * determined at this step. Done by x86_cpu_filter_features().
5007 * Some operations don't require all steps to be performed.
5010 * - CPU instance creation (instance_init) will run only CPU
5011 * model loading. CPU expansion can't run at instance_init-time
5012 * because host/accelerator data may be not available yet.
5013 * - CPU realization will perform both CPU model expansion and CPUID
5014 * filtering, and return an error in case one of them fails.
5015 * - query-cpu-definitions needs to run all 3 steps. It needs
5016 * to run CPUID filtering, as the 'unavailable-features'
5017 * field is set based on the filtering results.
5018 * - The query-cpu-model-expansion QMP command only needs to run
5019 * CPU model loading and CPU expansion. It should not filter
5020 * any CPUID data based on host capabilities.
5023 /* Expand CPU configuration data, based on configured features
5024 * and host/accelerator capabilities when appropriate.
5026 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
5028 CPUX86State *env = &cpu->env;
5031 Error *local_err = NULL;
5033 /*TODO: Now cpu->max_features doesn't overwrite features
5034 * set using QOM properties, and we can convert
5035 * plus_features & minus_features to global properties
5036 * inside x86_cpu_parse_featurestr() too.
5038 if (cpu->max_features) {
5039 for (w = 0; w < FEATURE_WORDS; w++) {
5040 /* Override only features that weren't set explicitly
5044 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
5045 ~env->user_features[w] & \
5046 ~feature_word_info[w].no_autoenable_flags;
5050 for (l = plus_features; l; l = l->next) {
5051 const char *prop = l->data;
5052 object_property_set_bool(OBJECT(cpu), true, prop, &local_err);
5058 for (l = minus_features; l; l = l->next) {
5059 const char *prop = l->data;
5060 object_property_set_bool(OBJECT(cpu), false, prop, &local_err);
5066 if (!kvm_enabled() || !cpu->expose_kvm) {
5067 env->features[FEAT_KVM] = 0;
5070 x86_cpu_enable_xsave_components(cpu);
5072 /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
5073 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
5074 if (cpu->full_cpuid_auto_level) {
5075 x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
5076 x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
5077 x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
5078 x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
5079 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
5080 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
5081 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
5082 x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
5083 x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
5084 x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
5085 x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
5087 /* Intel Processor Trace requires CPUID[0x14] */
5088 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5089 kvm_enabled() && cpu->intel_pt_auto_level) {
5090 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
5093 /* SVM requires CPUID[0x8000000A] */
5094 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5095 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
5098 /* SEV requires CPUID[0x8000001F] */
5099 if (sev_enabled()) {
5100 x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
5104 /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
5105 if (env->cpuid_level == UINT32_MAX) {
5106 env->cpuid_level = env->cpuid_min_level;
5108 if (env->cpuid_xlevel == UINT32_MAX) {
5109 env->cpuid_xlevel = env->cpuid_min_xlevel;
5111 if (env->cpuid_xlevel2 == UINT32_MAX) {
5112 env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
5116 if (local_err != NULL) {
5117 error_propagate(errp, local_err);
5122 * Finishes initialization of CPUID data, filters CPU feature
5123 * words based on host availability of each feature.
5125 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
5127 static int x86_cpu_filter_features(X86CPU *cpu)
5129 CPUX86State *env = &cpu->env;
5133 for (w = 0; w < FEATURE_WORDS; w++) {
5134 uint32_t host_feat =
5135 x86_cpu_get_supported_feature_word(w, false);
5136 uint32_t requested_features = env->features[w];
5137 env->features[w] &= host_feat;
5138 cpu->filtered_features[w] = requested_features & ~env->features[w];
5139 if (cpu->filtered_features[w]) {
5144 if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
5146 KVMState *s = CPU(cpu)->kvm_state;
5147 uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
5148 uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
5149 uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
5150 uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
5151 uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
5154 ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
5155 ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
5156 ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
5157 ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
5158 INTEL_PT_ADDR_RANGES_NUM) ||
5159 ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
5160 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
5161 (ecx_0 & INTEL_PT_IP_LIP)) {
5163 * Processor Trace capabilities aren't configurable, so if the
5164 * host can't emulate the capabilities we report on
5165 * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
5167 env->features[FEAT_7_0_EBX] &= ~CPUID_7_0_EBX_INTEL_PT;
5168 cpu->filtered_features[FEAT_7_0_EBX] |= CPUID_7_0_EBX_INTEL_PT;
5176 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
5177 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
5178 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
5179 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
5180 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
5181 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
5182 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
5184 CPUState *cs = CPU(dev);
5185 X86CPU *cpu = X86_CPU(dev);
5186 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5187 CPUX86State *env = &cpu->env;
5188 Error *local_err = NULL;
5189 static bool ht_warned;
5191 if (xcc->host_cpuid_required) {
5192 if (!accel_uses_host_cpuid()) {
5193 char *name = x86_cpu_class_get_model_name(xcc);
5194 error_setg(&local_err, "CPU model '%s' requires KVM", name);
5199 if (enable_cpu_pm) {
5200 host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
5201 &cpu->mwait.ecx, &cpu->mwait.edx);
5202 env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
5206 /* mwait extended info: needed for Core compatibility */
5207 /* We always wake on interrupt even if host does not have the capability */
5208 cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
5210 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
5211 error_setg(errp, "apic-id property was not initialized properly");
5215 x86_cpu_expand_features(cpu, &local_err);
5220 if (x86_cpu_filter_features(cpu) &&
5221 (cpu->check_cpuid || cpu->enforce_cpuid)) {
5222 x86_cpu_report_filtered_features(cpu);
5223 if (cpu->enforce_cpuid) {
5224 error_setg(&local_err,
5225 accel_uses_host_cpuid() ?
5226 "Host doesn't support requested features" :
5227 "TCG doesn't support requested features");
5232 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
5235 if (IS_AMD_CPU(env)) {
5236 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
5237 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
5238 & CPUID_EXT2_AMD_ALIASES);
5241 /* For 64bit systems think about the number of physical bits to present.
5242 * ideally this should be the same as the host; anything other than matching
5243 * the host can cause incorrect guest behaviour.
5244 * QEMU used to pick the magic value of 40 bits that corresponds to
5245 * consumer AMD devices but nothing else.
5247 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5248 if (accel_uses_host_cpuid()) {
5249 uint32_t host_phys_bits = x86_host_phys_bits();
5252 if (cpu->host_phys_bits) {
5253 /* The user asked for us to use the host physical bits */
5254 cpu->phys_bits = host_phys_bits;
5255 if (cpu->host_phys_bits_limit &&
5256 cpu->phys_bits > cpu->host_phys_bits_limit) {
5257 cpu->phys_bits = cpu->host_phys_bits_limit;
5261 /* Print a warning if the user set it to a value that's not the
5264 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
5266 warn_report("Host physical bits (%u)"
5267 " does not match phys-bits property (%u)",
5268 host_phys_bits, cpu->phys_bits);
5272 if (cpu->phys_bits &&
5273 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
5274 cpu->phys_bits < 32)) {
5275 error_setg(errp, "phys-bits should be between 32 and %u "
5277 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
5281 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
5282 error_setg(errp, "TCG only supports phys-bits=%u",
5283 TCG_PHYS_ADDR_BITS);
5287 /* 0 means it was not explicitly set by the user (or by machine
5288 * compat_props or by the host code above). In this case, the default
5289 * is the value used by TCG (40).
5291 if (cpu->phys_bits == 0) {
5292 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
5295 /* For 32 bit systems don't use the user set value, but keep
5296 * phys_bits consistent with what we tell the guest.
5298 if (cpu->phys_bits != 0) {
5299 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
5303 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
5304 cpu->phys_bits = 36;
5306 cpu->phys_bits = 32;
5310 /* Cache information initialization */
5311 if (!cpu->legacy_cache) {
5312 if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
5313 char *name = x86_cpu_class_get_model_name(xcc);
5315 "CPU model '%s' doesn't support legacy-cache=off", name);
5319 env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
5320 *xcc->cpu_def->cache_info;
5322 /* Build legacy cache information */
5323 env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
5324 env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
5325 env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
5326 env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
5328 env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
5329 env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
5330 env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
5331 env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
5333 env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
5334 env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
5335 env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
5336 env->cache_info_amd.l3_cache = &legacy_l3_cache;
5340 cpu_exec_realizefn(cs, &local_err);
5341 if (local_err != NULL) {
5342 error_propagate(errp, local_err);
5346 #ifndef CONFIG_USER_ONLY
5347 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
5349 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
5350 x86_cpu_apic_create(cpu, &local_err);
5351 if (local_err != NULL) {
5359 #ifndef CONFIG_USER_ONLY
5360 if (tcg_enabled()) {
5361 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
5362 cpu->cpu_as_root = g_new(MemoryRegion, 1);
5364 /* Outer container... */
5365 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
5366 memory_region_set_enabled(cpu->cpu_as_root, true);
5368 /* ... with two regions inside: normal system memory with low
5371 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
5372 get_system_memory(), 0, ~0ull);
5373 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
5374 memory_region_set_enabled(cpu->cpu_as_mem, true);
5377 cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
5378 cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
5380 /* ... SMRAM with higher priority, linked from /machine/smram. */
5381 cpu->machine_done.notify = x86_cpu_machine_done;
5382 qemu_add_machine_init_done_notifier(&cpu->machine_done);
5389 * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
5390 * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
5391 * based on inputs (sockets,cores,threads), it is still better to give
5394 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
5395 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
5397 if (IS_AMD_CPU(env) &&
5398 !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
5399 cs->nr_threads > 1 && !ht_warned) {
5400 warn_report("This family of AMD CPU doesn't support "
5401 "hyperthreading(%d)",
5403 error_printf("Please configure -smp options properly"
5404 " or try enabling topoext feature.\n");
5408 x86_cpu_apic_realize(cpu, &local_err);
5409 if (local_err != NULL) {
5414 xcc->parent_realize(dev, &local_err);
5417 if (local_err != NULL) {
5418 error_propagate(errp, local_err);
5423 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
5425 X86CPU *cpu = X86_CPU(dev);
5426 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
5427 Error *local_err = NULL;
5429 #ifndef CONFIG_USER_ONLY
5430 cpu_remove_sync(CPU(dev));
5431 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
5434 if (cpu->apic_state) {
5435 object_unparent(OBJECT(cpu->apic_state));
5436 cpu->apic_state = NULL;
5439 xcc->parent_unrealize(dev, &local_err);
5440 if (local_err != NULL) {
5441 error_propagate(errp, local_err);
5446 typedef struct BitProperty {
5451 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
5452 void *opaque, Error **errp)
5454 X86CPU *cpu = X86_CPU(obj);
5455 BitProperty *fp = opaque;
5456 uint32_t f = cpu->env.features[fp->w];
5457 bool value = (f & fp->mask) == fp->mask;
5458 visit_type_bool(v, name, &value, errp);
5461 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
5462 void *opaque, Error **errp)
5464 DeviceState *dev = DEVICE(obj);
5465 X86CPU *cpu = X86_CPU(obj);
5466 BitProperty *fp = opaque;
5467 Error *local_err = NULL;
5470 if (dev->realized) {
5471 qdev_prop_set_after_realize(dev, name, errp);
5475 visit_type_bool(v, name, &value, &local_err);
5477 error_propagate(errp, local_err);
5482 cpu->env.features[fp->w] |= fp->mask;
5484 cpu->env.features[fp->w] &= ~fp->mask;
5486 cpu->env.user_features[fp->w] |= fp->mask;
5489 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
5492 BitProperty *prop = opaque;
5496 /* Register a boolean property to get/set a single bit in a uint32_t field.
5498 * The same property name can be registered multiple times to make it affect
5499 * multiple bits in the same FeatureWord. In that case, the getter will return
5500 * true only if all bits are set.
5502 static void x86_cpu_register_bit_prop(X86CPU *cpu,
5503 const char *prop_name,
5509 uint32_t mask = (1UL << bitnr);
5511 op = object_property_find(OBJECT(cpu), prop_name, NULL);
5517 fp = g_new0(BitProperty, 1);
5520 object_property_add(OBJECT(cpu), prop_name, "bool",
5521 x86_cpu_get_bit_prop,
5522 x86_cpu_set_bit_prop,
5523 x86_cpu_release_bit_prop, fp, &error_abort);
5527 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
5531 FeatureWordInfo *fi = &feature_word_info[w];
5532 const char *name = fi->feat_names[bitnr];
5538 /* Property names should use "-" instead of "_".
5539 * Old names containing underscores are registered as aliases
5540 * using object_property_add_alias()
5542 assert(!strchr(name, '_'));
5543 /* aliases don't use "|" delimiters anymore, they are registered
5544 * manually using object_property_add_alias() */
5545 assert(!strchr(name, '|'));
5546 x86_cpu_register_bit_prop(cpu, name, w, bitnr);
5549 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
5551 X86CPU *cpu = X86_CPU(cs);
5552 CPUX86State *env = &cpu->env;
5553 GuestPanicInformation *panic_info = NULL;
5555 if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
5556 panic_info = g_malloc0(sizeof(GuestPanicInformation));
5558 panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
5560 assert(HV_CRASH_PARAMS >= 5);
5561 panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
5562 panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
5563 panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
5564 panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
5565 panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
5570 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
5571 const char *name, void *opaque,
5574 CPUState *cs = CPU(obj);
5575 GuestPanicInformation *panic_info;
5577 if (!cs->crash_occurred) {
5578 error_setg(errp, "No crash occured");
5582 panic_info = x86_cpu_get_crash_info(cs);
5583 if (panic_info == NULL) {
5584 error_setg(errp, "No crash information");
5588 visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
5590 qapi_free_GuestPanicInformation(panic_info);
5593 static void x86_cpu_initfn(Object *obj)
5595 X86CPU *cpu = X86_CPU(obj);
5596 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
5597 CPUX86State *env = &cpu->env;
5600 cpu_set_cpustate_pointers(cpu);
5602 object_property_add(obj, "family", "int",
5603 x86_cpuid_version_get_family,
5604 x86_cpuid_version_set_family, NULL, NULL, NULL);
5605 object_property_add(obj, "model", "int",
5606 x86_cpuid_version_get_model,
5607 x86_cpuid_version_set_model, NULL, NULL, NULL);
5608 object_property_add(obj, "stepping", "int",
5609 x86_cpuid_version_get_stepping,
5610 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
5611 object_property_add_str(obj, "vendor",
5612 x86_cpuid_get_vendor,
5613 x86_cpuid_set_vendor, NULL);
5614 object_property_add_str(obj, "model-id",
5615 x86_cpuid_get_model_id,
5616 x86_cpuid_set_model_id, NULL);
5617 object_property_add(obj, "tsc-frequency", "int",
5618 x86_cpuid_get_tsc_freq,
5619 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
5620 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
5621 x86_cpu_get_feature_words,
5622 NULL, NULL, (void *)env->features, NULL);
5623 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
5624 x86_cpu_get_feature_words,
5625 NULL, NULL, (void *)cpu->filtered_features, NULL);
5627 object_property_add(obj, "crash-information", "GuestPanicInformation",
5628 x86_cpu_get_crash_info_qom, NULL, NULL, NULL, NULL);
5630 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
5632 for (w = 0; w < FEATURE_WORDS; w++) {
5635 for (bitnr = 0; bitnr < 32; bitnr++) {
5636 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
5640 object_property_add_alias(obj, "sse3", obj, "pni", &error_abort);
5641 object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq", &error_abort);
5642 object_property_add_alias(obj, "sse4-1", obj, "sse4.1", &error_abort);
5643 object_property_add_alias(obj, "sse4-2", obj, "sse4.2", &error_abort);
5644 object_property_add_alias(obj, "xd", obj, "nx", &error_abort);
5645 object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt", &error_abort);
5646 object_property_add_alias(obj, "i64", obj, "lm", &error_abort);
5648 object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl", &error_abort);
5649 object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust", &error_abort);
5650 object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt", &error_abort);
5651 object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm", &error_abort);
5652 object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy", &error_abort);
5653 object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr", &error_abort);
5654 object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core", &error_abort);
5655 object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb", &error_abort);
5656 object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay", &error_abort);
5657 object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu", &error_abort);
5658 object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf", &error_abort);
5659 object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time", &error_abort);
5660 object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi", &error_abort);
5661 object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt", &error_abort);
5662 object_property_add_alias(obj, "svm_lock", obj, "svm-lock", &error_abort);
5663 object_property_add_alias(obj, "nrip_save", obj, "nrip-save", &error_abort);
5664 object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale", &error_abort);
5665 object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean", &error_abort);
5666 object_property_add_alias(obj, "pause_filter", obj, "pause-filter", &error_abort);
5667 object_property_add_alias(obj, "sse4_1", obj, "sse4.1", &error_abort);
5668 object_property_add_alias(obj, "sse4_2", obj, "sse4.2", &error_abort);
5671 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
5675 static int64_t x86_cpu_get_arch_id(CPUState *cs)
5677 X86CPU *cpu = X86_CPU(cs);
5679 return cpu->apic_id;
5682 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
5684 X86CPU *cpu = X86_CPU(cs);
5686 return cpu->env.cr[0] & CR0_PG_MASK;
5689 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
5691 X86CPU *cpu = X86_CPU(cs);
5693 cpu->env.eip = value;
5696 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
5698 X86CPU *cpu = X86_CPU(cs);
5700 cpu->env.eip = tb->pc - tb->cs_base;
5703 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
5705 X86CPU *cpu = X86_CPU(cs);
5706 CPUX86State *env = &cpu->env;
5708 #if !defined(CONFIG_USER_ONLY)
5709 if (interrupt_request & CPU_INTERRUPT_POLL) {
5710 return CPU_INTERRUPT_POLL;
5713 if (interrupt_request & CPU_INTERRUPT_SIPI) {
5714 return CPU_INTERRUPT_SIPI;
5717 if (env->hflags2 & HF2_GIF_MASK) {
5718 if ((interrupt_request & CPU_INTERRUPT_SMI) &&
5719 !(env->hflags & HF_SMM_MASK)) {
5720 return CPU_INTERRUPT_SMI;
5721 } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
5722 !(env->hflags2 & HF2_NMI_MASK)) {
5723 return CPU_INTERRUPT_NMI;
5724 } else if (interrupt_request & CPU_INTERRUPT_MCE) {
5725 return CPU_INTERRUPT_MCE;
5726 } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
5727 (((env->hflags2 & HF2_VINTR_MASK) &&
5728 (env->hflags2 & HF2_HIF_MASK)) ||
5729 (!(env->hflags2 & HF2_VINTR_MASK) &&
5730 (env->eflags & IF_MASK &&
5731 !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
5732 return CPU_INTERRUPT_HARD;
5733 #if !defined(CONFIG_USER_ONLY)
5734 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
5735 (env->eflags & IF_MASK) &&
5736 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
5737 return CPU_INTERRUPT_VIRQ;
5745 static bool x86_cpu_has_work(CPUState *cs)
5747 return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
5750 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
5752 X86CPU *cpu = X86_CPU(cs);
5753 CPUX86State *env = &cpu->env;
5755 info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
5756 : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
5757 : bfd_mach_i386_i8086);
5758 info->print_insn = print_insn_i386;
5760 info->cap_arch = CS_ARCH_X86;
5761 info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
5762 : env->hflags & HF_CS32_MASK ? CS_MODE_32
5764 info->cap_insn_unit = 1;
5765 info->cap_insn_split = 8;
5768 void x86_update_hflags(CPUX86State *env)
5771 #define HFLAG_COPY_MASK \
5772 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
5773 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
5774 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
5775 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
5777 hflags = env->hflags & HFLAG_COPY_MASK;
5778 hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
5779 hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
5780 hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
5781 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
5782 hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
5784 if (env->cr[4] & CR4_OSFXSR_MASK) {
5785 hflags |= HF_OSFXSR_MASK;
5788 if (env->efer & MSR_EFER_LMA) {
5789 hflags |= HF_LMA_MASK;
5792 if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
5793 hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
5795 hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
5796 (DESC_B_SHIFT - HF_CS32_SHIFT);
5797 hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
5798 (DESC_B_SHIFT - HF_SS32_SHIFT);
5799 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
5800 !(hflags & HF_CS32_MASK)) {
5801 hflags |= HF_ADDSEG_MASK;
5803 hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
5804 env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
5807 env->hflags = hflags;
5810 static Property x86_cpu_properties[] = {
5811 #ifdef CONFIG_USER_ONLY
5812 /* apic_id = 0 by default for *-user, see commit 9886e834 */
5813 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
5814 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
5815 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
5816 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
5818 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
5819 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
5820 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
5821 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
5823 DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
5824 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
5825 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
5826 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
5827 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
5828 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
5829 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
5830 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
5831 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
5832 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
5833 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
5834 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
5835 DEFINE_PROP_BOOL("hv-frequencies", X86CPU, hyperv_frequencies, false),
5836 DEFINE_PROP_BOOL("hv-reenlightenment", X86CPU, hyperv_reenlightenment, false),
5837 DEFINE_PROP_BOOL("hv-tlbflush", X86CPU, hyperv_tlbflush, false),
5838 DEFINE_PROP_BOOL("hv-evmcs", X86CPU, hyperv_evmcs, false),
5839 DEFINE_PROP_BOOL("hv-ipi", X86CPU, hyperv_ipi, false),
5840 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
5841 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
5842 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
5843 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
5844 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
5845 DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
5846 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
5847 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
5848 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
5849 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
5850 DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
5851 DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
5852 DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
5853 DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
5854 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
5855 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
5856 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
5857 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
5858 DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
5860 DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
5861 DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
5862 DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
5865 * lecacy_cache defaults to true unless the CPU model provides its
5866 * own cache information (see x86_cpu_load_def()).
5868 DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
5871 * From "Requirements for Implementing the Microsoft
5872 * Hypervisor Interface":
5873 * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
5875 * "Starting with Windows Server 2012 and Windows 8, if
5876 * CPUID.40000005.EAX contains a value of -1, Windows assumes that
5877 * the hypervisor imposes no specific limit to the number of VPs.
5878 * In this case, Windows Server 2012 guest VMs may use more than
5879 * 64 VPs, up to the maximum supported number of processors applicable
5880 * to the specific Windows version being used."
5882 DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
5883 DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
5885 DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
5887 DEFINE_PROP_END_OF_LIST()
5890 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
5892 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5893 CPUClass *cc = CPU_CLASS(oc);
5894 DeviceClass *dc = DEVICE_CLASS(oc);
5896 device_class_set_parent_realize(dc, x86_cpu_realizefn,
5897 &xcc->parent_realize);
5898 device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
5899 &xcc->parent_unrealize);
5900 dc->props = x86_cpu_properties;
5902 xcc->parent_reset = cc->reset;
5903 cc->reset = x86_cpu_reset;
5904 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
5906 cc->class_by_name = x86_cpu_class_by_name;
5907 cc->parse_features = x86_cpu_parse_featurestr;
5908 cc->has_work = x86_cpu_has_work;
5910 cc->do_interrupt = x86_cpu_do_interrupt;
5911 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
5913 cc->dump_state = x86_cpu_dump_state;
5914 cc->get_crash_info = x86_cpu_get_crash_info;
5915 cc->set_pc = x86_cpu_set_pc;
5916 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
5917 cc->gdb_read_register = x86_cpu_gdb_read_register;
5918 cc->gdb_write_register = x86_cpu_gdb_write_register;
5919 cc->get_arch_id = x86_cpu_get_arch_id;
5920 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
5921 #ifndef CONFIG_USER_ONLY
5922 cc->asidx_from_attrs = x86_asidx_from_attrs;
5923 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
5924 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
5925 cc->write_elf64_note = x86_cpu_write_elf64_note;
5926 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
5927 cc->write_elf32_note = x86_cpu_write_elf32_note;
5928 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
5929 cc->vmsd = &vmstate_x86_cpu;
5931 cc->gdb_arch_name = x86_gdb_arch_name;
5932 #ifdef TARGET_X86_64
5933 cc->gdb_core_xml_file = "i386-64bit.xml";
5934 cc->gdb_num_core_regs = 66;
5936 cc->gdb_core_xml_file = "i386-32bit.xml";
5937 cc->gdb_num_core_regs = 50;
5939 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
5940 cc->debug_excp_handler = breakpoint_handler;
5942 cc->cpu_exec_enter = x86_cpu_exec_enter;
5943 cc->cpu_exec_exit = x86_cpu_exec_exit;
5945 cc->tcg_initialize = tcg_x86_init;
5946 cc->tlb_fill = x86_cpu_tlb_fill;
5948 cc->disas_set_info = x86_disas_set_info;
5950 dc->user_creatable = true;
5953 static const TypeInfo x86_cpu_type_info = {
5954 .name = TYPE_X86_CPU,
5956 .instance_size = sizeof(X86CPU),
5957 .instance_init = x86_cpu_initfn,
5959 .class_size = sizeof(X86CPUClass),
5960 .class_init = x86_cpu_common_class_init,
5964 /* "base" CPU model, used by query-cpu-model-expansion */
5965 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
5967 X86CPUClass *xcc = X86_CPU_CLASS(oc);
5969 xcc->static_model = true;
5970 xcc->migration_safe = true;
5971 xcc->model_description = "base CPU model type with no features enabled";
5975 static const TypeInfo x86_base_cpu_type_info = {
5976 .name = X86_CPU_TYPE_NAME("base"),
5977 .parent = TYPE_X86_CPU,
5978 .class_init = x86_cpu_base_class_init,
5981 static void x86_cpu_register_types(void)
5985 type_register_static(&x86_cpu_type_info);
5986 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
5987 x86_register_cpudef_type(&builtin_x86_defs[i]);
5989 type_register_static(&max_x86_cpu_type_info);
5990 type_register_static(&x86_base_cpu_type_info);
5991 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
5992 type_register_static(&host_x86_cpu_type_info);
5996 type_init(x86_cpu_register_types)