hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/hw.h"
  26 #include "hw/pc.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/pci/pci_host.h"
  29 #include "hw/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "qemu/range.h"
  32 #include "hw/xen.h"
  33 #include "hw/pam.h"
  34 #include "sysemu/sysemu.h"
  35
  36 /*
  37  * I440FX chipset data sheet.
  38  * http://download.intel.com/design/chipsets/datashts/29054901.pdf
  39  */
  40
  41 typedef struct I440FXState {
  42     PCIHostState parent_obj;
  43 } I440FXState;
  44
  45 #define PIIX_NUM_PIC_IRQS       16      /* i8259 * 2 */
  46 #define PIIX_NUM_PIRQS          4ULL    /* PIRQ[A-D] */
  47 #define XEN_PIIX_NUM_PIRQS      128ULL
  48 #define PIIX_PIRQC              0x60
  49
  50 /*
  51  * Reset Control Register: PCI-accessible ISA-Compatible Register at address
  52  * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
  53  */
  54 #define RCR_IOPORT 0xcf9
  55
  56 typedef struct PIIX3State {
  57     PCIDevice dev;
  58
  59     /*
  60      * bitmap to track pic levels.
  61      * The pic level is the logical OR of all the PCI irqs mapped to it
  62      * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
  63      *
  64      * PIRQ is mapped to PIC pins, we track it by
  65      * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
  66      * pic_irq * PIIX_NUM_PIRQS + pirq
  67      */
  68 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
  69 #error "unable to encode pic state in 64bit in pic_levels."
  70 #endif
  71     uint64_t pic_levels;
  72
  73     qemu_irq *pic;
  74
  75     /* This member isn't used. Just for save/load compatibility */
  76     int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
  77
  78     /* Reset Control Register contents */
  79     uint8_t rcr;
  80
  81     /* IO memory region for Reset Control Register (RCR_IOPORT) */
  82     MemoryRegion rcr_mem;
  83 } PIIX3State;
  84
  85 #define TYPE_I440FX_PCI_DEVICE "i440FX"
  86 #define I440FX_PCI_DEVICE(obj) \
  87     OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
  88
  89 struct PCII440FXState {
  90     PCIDevice dev;
  91     MemoryRegion *system_memory;
  92     MemoryRegion *pci_address_space;
  93     MemoryRegion *ram_memory;
  94     MemoryRegion pci_hole;
  95     MemoryRegion pci_hole_64bit;
  96     PAMMemoryRegion pam_regions[13];
  97     MemoryRegion smram_region;
  98     uint8_t smm_enabled;
  99 };
 100
 101
 102 #define I440FX_PAM      0x59
 103 #define I440FX_PAM_SIZE 7
 104 #define I440FX_SMRAM    0x72
 105
 106 static void piix3_set_irq(void *opaque, int pirq, int level);
 107 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
 108 static void piix3_write_config_xen(PCIDevice *dev,
 109                                uint32_t address, uint32_t val, int len);
 110
 111 /* return the global irq number corresponding to a given device irq
 112    pin. We could also use the bus number to have a more precise
 113    mapping. */
 114 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
 115 {
 116     int slot_addend;
 117     slot_addend = (pci_dev->devfn >> 3) - 1;
 118     return (pci_intx + slot_addend) & 3;
 119 }
 120
 121 static void i440fx_update_memory_mappings(PCII440FXState *d)
 122 {
 123     int i;
 124
 125     memory_region_transaction_begin();
 126     for (i = 0; i < 13; i++) {
 127         pam_update(&d->pam_regions[i], i,
 128                    d->dev.config[I440FX_PAM + ((i + 1) / 2)]);
 129     }
 130     smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
 131     memory_region_transaction_commit();
 132 }
 133
 134 static void i440fx_set_smm(int val, void *arg)
 135 {
 136     PCII440FXState *d = arg;
 137
 138     memory_region_transaction_begin();
 139     smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
 140                   &d->smram_region);
 141     memory_region_transaction_commit();
 142 }
 143
 144
 145 static void i440fx_write_config(PCIDevice *dev,
 146                                 uint32_t address, uint32_t val, int len)
 147 {
 148     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 149
 150     /* XXX: implement SMRAM.D_LOCK */
 151     pci_default_write_config(dev, address, val, len);
 152     if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
 153         range_covers_byte(address, len, I440FX_SMRAM)) {
 154         i440fx_update_memory_mappings(d);
 155     }
 156 }
 157
 158 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 159 {
 160     PCII440FXState *d = opaque;
 161     int ret, i;
 162
 163     ret = pci_device_load(&d->dev, f);
 164     if (ret < 0)
 165         return ret;
 166     i440fx_update_memory_mappings(d);
 167     qemu_get_8s(f, &d->smm_enabled);
 168
 169     if (version_id == 2) {
 170         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
 171             qemu_get_be32(f); /* dummy load for compatibility */
 172         }
 173     }
 174
 175     return 0;
 176 }
 177
 178 static int i440fx_post_load(void *opaque, int version_id)
 179 {
 180     PCII440FXState *d = opaque;
 181
 182     i440fx_update_memory_mappings(d);
 183     return 0;
 184 }
 185
 186 static const VMStateDescription vmstate_i440fx = {
 187     .name = "I440FX",
 188     .version_id = 3,
 189     .minimum_version_id = 3,
 190     .minimum_version_id_old = 1,
 191     .load_state_old = i440fx_load_old,
 192     .post_load = i440fx_post_load,
 193     .fields      = (VMStateField []) {
 194         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 195         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 196         VMSTATE_END_OF_LIST()
 197     }
 198 };
 199
 200 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 201 {
 202     PCIHostState *s = PCI_HOST_BRIDGE(dev);
 203
 204     memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
 205                           "pci-conf-idx", 4);
 206     sysbus_add_io(dev, 0xcf8, &s->conf_mem);
 207     sysbus_init_ioports(&s->busdev, 0xcf8, 4);
 208
 209     memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
 210                           "pci-conf-data", 4);
 211     sysbus_add_io(dev, 0xcfc, &s->data_mem);
 212     sysbus_init_ioports(&s->busdev, 0xcfc, 4);
 213
 214     return 0;
 215 }
 216
 217 static int i440fx_initfn(PCIDevice *dev)
 218 {
 219     PCII440FXState *d = I440FX_PCI_DEVICE(dev);
 220
 221     d->dev.config[I440FX_SMRAM] = 0x02;
 222
 223     cpu_smm_register(&i440fx_set_smm, d);
 224     return 0;
 225 }
 226
 227 static PCIBus *i440fx_common_init(const char *device_name,
 228                                   PCII440FXState **pi440fx_state,
 229                                   int *piix3_devfn,
 230                                   ISABus **isa_bus, qemu_irq *pic,
 231                                   MemoryRegion *address_space_mem,
 232                                   MemoryRegion *address_space_io,
 233                                   ram_addr_t ram_size,
 234                                   hwaddr pci_hole_start,
 235                                   hwaddr pci_hole_size,
 236                                   hwaddr pci_hole64_start,
 237                                   hwaddr pci_hole64_size,
 238                                   MemoryRegion *pci_address_space,
 239                                   MemoryRegion *ram_memory)
 240 {
 241     DeviceState *dev;
 242     PCIBus *b;
 243     PCIDevice *d;
 244     PCIHostState *s;
 245     PIIX3State *piix3;
 246     PCII440FXState *f;
 247     unsigned i;
 248
 249     dev = qdev_create(NULL, "i440FX-pcihost");
 250     s = PCI_HOST_BRIDGE(dev);
 251     b = pci_bus_new(dev, NULL, pci_address_space,
 252                     address_space_io, 0, TYPE_PCI_BUS);
 253     s->bus = b;
 254     object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
 255     qdev_init_nofail(dev);
 256
 257     d = pci_create_simple(b, 0, device_name);
 258     *pi440fx_state = I440FX_PCI_DEVICE(d);
 259     f = *pi440fx_state;
 260     f->system_memory = address_space_mem;
 261     f->pci_address_space = pci_address_space;
 262     f->ram_memory = ram_memory;
 263     memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
 264                              pci_hole_start, pci_hole_size);
 265     memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
 266     memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
 267                              f->pci_address_space,
 268                              pci_hole64_start, pci_hole64_size);
 269     if (pci_hole64_size) {
 270         memory_region_add_subregion(f->system_memory, pci_hole64_start,
 271                                     &f->pci_hole_64bit);
 272     }
 273     memory_region_init_alias(&f->smram_region, "smram-region",
 274                              f->pci_address_space, 0xa0000, 0x20000);
 275     memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
 276                                         &f->smram_region, 1);
 277     memory_region_set_enabled(&f->smram_region, false);
 278     init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
 279              &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
 280     for (i = 0; i < 12; ++i) {
 281         init_pam(f->ram_memory, f->system_memory, f->pci_address_space,
 282                  &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
 283                  PAM_EXPAN_SIZE);
 284     }
 285
 286     /* Xen supports additional interrupt routes from the PCI devices to
 287      * the IOAPIC: the four pins of each PCI device on the bus are also
 288      * connected to the IOAPIC directly.
 289      * These additional routes can be discovered through ACPI. */
 290     if (xen_enabled()) {
 291         piix3 = DO_UPCAST(PIIX3State, dev,
 292                 pci_create_simple_multifunction(b, -1, true, "PIIX3-xen"));
 293         pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
 294                 piix3, XEN_PIIX_NUM_PIRQS);
 295     } else {
 296         piix3 = DO_UPCAST(PIIX3State, dev,
 297                 pci_create_simple_multifunction(b, -1, true, "PIIX3"));
 298         pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
 299                 PIIX_NUM_PIRQS);
 300         pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
 301     }
 302     piix3->pic = pic;
 303     *isa_bus = DO_UPCAST(ISABus, qbus,
 304                          qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
 305
 306     *piix3_devfn = piix3->dev.devfn;
 307
 308     ram_size = ram_size / 8 / 1024 / 1024;
 309     if (ram_size > 255)
 310         ram_size = 255;
 311     (*pi440fx_state)->dev.config[0x57]=ram_size;
 312
 313     i440fx_update_memory_mappings(f);
 314
 315     return b;
 316 }
 317
 318 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
 319                     ISABus **isa_bus, qemu_irq *pic,
 320                     MemoryRegion *address_space_mem,
 321                     MemoryRegion *address_space_io,
 322                     ram_addr_t ram_size,
 323                     hwaddr pci_hole_start,
 324                     hwaddr pci_hole_size,
 325                     hwaddr pci_hole64_start,
 326                     hwaddr pci_hole64_size,
 327                     MemoryRegion *pci_memory, MemoryRegion *ram_memory)
 328
 329 {
 330     PCIBus *b;
 331
 332     b = i440fx_common_init(TYPE_I440FX_PCI_DEVICE, pi440fx_state,
 333                            piix3_devfn, isa_bus, pic,
 334                            address_space_mem, address_space_io, ram_size,
 335                            pci_hole_start, pci_hole_size,
 336                            pci_hole64_start, pci_hole64_size,
 337                            pci_memory, ram_memory);
 338     return b;
 339 }
 340
 341 /* PIIX3 PCI to ISA bridge */
 342 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 343 {
 344     qemu_set_irq(piix3->pic[pic_irq],
 345                  !!(piix3->pic_levels &
 346                     (((1ULL << PIIX_NUM_PIRQS) - 1) <<
 347                      (pic_irq * PIIX_NUM_PIRQS))));
 348 }
 349
 350 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
 351 {
 352     int pic_irq;
 353     uint64_t mask;
 354
 355     pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
 356     if (pic_irq >= PIIX_NUM_PIC_IRQS) {
 357         return;
 358     }
 359
 360     mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
 361     piix3->pic_levels &= ~mask;
 362     piix3->pic_levels |= mask * !!level;
 363
 364     piix3_set_irq_pic(piix3, pic_irq);
 365 }
 366
 367 static void piix3_set_irq(void *opaque, int pirq, int level)
 368 {
 369     PIIX3State *piix3 = opaque;
 370     piix3_set_irq_level(piix3, pirq, level);
 371 }
 372
 373 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
 374 {
 375     PIIX3State *piix3 = opaque;
 376     int irq = piix3->dev.config[PIIX_PIRQC + pin];
 377     PCIINTxRoute route;
 378
 379     if (irq < PIIX_NUM_PIC_IRQS) {
 380         route.mode = PCI_INTX_ENABLED;
 381         route.irq = irq;
 382     } else {
 383         route.mode = PCI_INTX_DISABLED;
 384         route.irq = -1;
 385     }
 386     return route;
 387 }
 388
 389 /* irq routing is changed. so rebuild bitmap */
 390 static void piix3_update_irq_levels(PIIX3State *piix3)
 391 {
 392     int pirq;
 393
 394     piix3->pic_levels = 0;
 395     for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
 396         piix3_set_irq_level(piix3, pirq,
 397                             pci_bus_get_irq_level(piix3->dev.bus, pirq));
 398     }
 399 }
 400
 401 static void piix3_write_config(PCIDevice *dev,
 402                                uint32_t address, uint32_t val, int len)
 403 {
 404     pci_default_write_config(dev, address, val, len);
 405     if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
 406         PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev);
 407         int pic_irq;
 408
 409         pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
 410         piix3_update_irq_levels(piix3);
 411         for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
 412             piix3_set_irq_pic(piix3, pic_irq);
 413         }
 414     }
 415 }
 416
 417 static void piix3_write_config_xen(PCIDevice *dev,
 418                                uint32_t address, uint32_t val, int len)
 419 {
 420     xen_piix_pci_write_config_client(address, val, len);
 421     piix3_write_config(dev, address, val, len);
 422 }
 423
 424 static void piix3_reset(void *opaque)
 425 {
 426     PIIX3State *d = opaque;
 427     uint8_t *pci_conf = d->dev.config;
 428
 429     pci_conf[0x04] = 0x07; // master, memory and I/O
 430     pci_conf[0x05] = 0x00;
 431     pci_conf[0x06] = 0x00;
 432     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 433     pci_conf[0x4c] = 0x4d;
 434     pci_conf[0x4e] = 0x03;
 435     pci_conf[0x4f] = 0x00;
 436     pci_conf[0x60] = 0x80;
 437     pci_conf[0x61] = 0x80;
 438     pci_conf[0x62] = 0x80;
 439     pci_conf[0x63] = 0x80;
 440     pci_conf[0x69] = 0x02;
 441     pci_conf[0x70] = 0x80;
 442     pci_conf[0x76] = 0x0c;
 443     pci_conf[0x77] = 0x0c;
 444     pci_conf[0x78] = 0x02;
 445     pci_conf[0x79] = 0x00;
 446     pci_conf[0x80] = 0x00;
 447     pci_conf[0x82] = 0x00;
 448     pci_conf[0xa0] = 0x08;
 449     pci_conf[0xa2] = 0x00;
 450     pci_conf[0xa3] = 0x00;
 451     pci_conf[0xa4] = 0x00;
 452     pci_conf[0xa5] = 0x00;
 453     pci_conf[0xa6] = 0x00;
 454     pci_conf[0xa7] = 0x00;
 455     pci_conf[0xa8] = 0x0f;
 456     pci_conf[0xaa] = 0x00;
 457     pci_conf[0xab] = 0x00;
 458     pci_conf[0xac] = 0x00;
 459     pci_conf[0xae] = 0x00;
 460
 461     d->pic_levels = 0;
 462     d->rcr = 0;
 463 }
 464
 465 static int piix3_post_load(void *opaque, int version_id)
 466 {
 467     PIIX3State *piix3 = opaque;
 468     piix3_update_irq_levels(piix3);
 469     return 0;
 470 }
 471
 472 static void piix3_pre_save(void *opaque)
 473 {
 474     int i;
 475     PIIX3State *piix3 = opaque;
 476
 477     for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
 478         piix3->pci_irq_levels_vmstate[i] =
 479             pci_bus_get_irq_level(piix3->dev.bus, i);
 480     }
 481 }
 482
 483 static bool piix3_rcr_needed(void *opaque)
 484 {
 485     PIIX3State *piix3 = opaque;
 486
 487     return (piix3->rcr != 0);
 488 }
 489
 490 static const VMStateDescription vmstate_piix3_rcr = {
 491     .name = "PIIX3/rcr",
 492     .version_id = 1,
 493     .minimum_version_id = 1,
 494     .fields = (VMStateField []) {
 495         VMSTATE_UINT8(rcr, PIIX3State),
 496         VMSTATE_END_OF_LIST()
 497     }
 498 };
 499
 500 static const VMStateDescription vmstate_piix3 = {
 501     .name = "PIIX3",
 502     .version_id = 3,
 503     .minimum_version_id = 2,
 504     .minimum_version_id_old = 2,
 505     .post_load = piix3_post_load,
 506     .pre_save = piix3_pre_save,
 507     .fields      = (VMStateField[]) {
 508         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 509         VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
 510                               PIIX_NUM_PIRQS, 3),
 511         VMSTATE_END_OF_LIST()
 512     },
 513     .subsections = (VMStateSubsection[]) {
 514         {
 515             .vmsd = &vmstate_piix3_rcr,
 516             .needed = piix3_rcr_needed,
 517         },
 518         { 0 }
 519     }
 520 };
 521
 522
 523 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
 524 {
 525     PIIX3State *d = opaque;
 526
 527     if (val & 4) {
 528         qemu_system_reset_request();
 529         return;
 530     }
 531     d->rcr = val & 2; /* keep System Reset type only */
 532 }
 533
 534 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
 535 {
 536     PIIX3State *d = opaque;
 537
 538     return d->rcr;
 539 }
 540
 541 static const MemoryRegionOps rcr_ops = {
 542     .read = rcr_read,
 543     .write = rcr_write,
 544     .endianness = DEVICE_LITTLE_ENDIAN
 545 };
 546
 547 static int piix3_initfn(PCIDevice *dev)
 548 {
 549     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 550
 551     isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
 552
 553     memory_region_init_io(&d->rcr_mem, &rcr_ops, d, "piix3-reset-control", 1);
 554     memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
 555                                         &d->rcr_mem, 1);
 556
 557     qemu_register_reset(piix3_reset, d);
 558     return 0;
 559 }
 560
 561 static void piix3_class_init(ObjectClass *klass, void *data)
 562 {
 563     DeviceClass *dc = DEVICE_CLASS(klass);
 564     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 565
 566     dc->desc        = "ISA bridge";
 567     dc->vmsd        = &vmstate_piix3;
 568     dc->no_user     = 1,
 569     k->no_hotplug   = 1;
 570     k->init         = piix3_initfn;
 571     k->config_write = piix3_write_config;
 572     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 573     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 574     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 575 }
 576
 577 static const TypeInfo piix3_info = {
 578     .name          = "PIIX3",
 579     .parent        = TYPE_PCI_DEVICE,
 580     .instance_size = sizeof(PIIX3State),
 581     .class_init    = piix3_class_init,
 582 };
 583
 584 static void piix3_xen_class_init(ObjectClass *klass, void *data)
 585 {
 586     DeviceClass *dc = DEVICE_CLASS(klass);
 587     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 588
 589     dc->desc        = "ISA bridge";
 590     dc->vmsd        = &vmstate_piix3;
 591     dc->no_user     = 1;
 592     k->no_hotplug   = 1;
 593     k->init         = piix3_initfn;
 594     k->config_write = piix3_write_config_xen;
 595     k->vendor_id    = PCI_VENDOR_ID_INTEL;
 596     k->device_id    = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 597     k->class_id     = PCI_CLASS_BRIDGE_ISA;
 598 };
 599
 600 static const TypeInfo piix3_xen_info = {
 601     .name          = "PIIX3-xen",
 602     .parent        = TYPE_PCI_DEVICE,
 603     .instance_size = sizeof(PIIX3State),
 604     .class_init    = piix3_xen_class_init,
 605 };
 606
 607 static void i440fx_class_init(ObjectClass *klass, void *data)
 608 {
 609     DeviceClass *dc = DEVICE_CLASS(klass);
 610     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 611
 612     k->no_hotplug = 1;
 613     k->init = i440fx_initfn;
 614     k->config_write = i440fx_write_config;
 615     k->vendor_id = PCI_VENDOR_ID_INTEL;
 616     k->device_id = PCI_DEVICE_ID_INTEL_82441;
 617     k->revision = 0x02;
 618     k->class_id = PCI_CLASS_BRIDGE_HOST;
 619     dc->desc = "Host bridge";
 620     dc->no_user = 1;
 621     dc->vmsd = &vmstate_i440fx;
 622 }
 623
 624 static const TypeInfo i440fx_info = {
 625     .name          = TYPE_I440FX_PCI_DEVICE,
 626     .parent        = TYPE_PCI_DEVICE,
 627     .instance_size = sizeof(PCII440FXState),
 628     .class_init    = i440fx_class_init,
 629 };
 630
 631 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
 632 {
 633     DeviceClass *dc = DEVICE_CLASS(klass);
 634     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 635
 636     k->init = i440fx_pcihost_initfn;
 637     dc->fw_name = "pci";
 638     dc->no_user = 1;
 639 }
 640
 641 static const TypeInfo i440fx_pcihost_info = {
 642     .name          = "i440FX-pcihost",
 643     .parent        = TYPE_PCI_HOST_BRIDGE,
 644     .instance_size = sizeof(I440FXState),
 645     .class_init    = i440fx_pcihost_class_init,
 646 };
 647
 648 static void i440fx_register_types(void)
 649 {
 650     type_register_static(&i440fx_info);
 651     type_register_static(&piix3_info);
 652     type_register_static(&piix3_xen_info);
 653     type_register_static(&i440fx_pcihost_info);
 654 }
 655
 656 type_init(i440fx_register_types)