hw/display/ati_2d.c

   1 /*
   2  * QEMU ATI SVGA emulation
   3  * 2D engine functions
   4  *
   5  * Copyright (c) 2019 BALATON Zoltan
   6  *
   7  * This work is licensed under the GNU GPL license version 2 or later.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "ati_int.h"
  12 #include "ati_regs.h"
  13 #include "qemu/log.h"
  14 #include "ui/pixel_ops.h"
  15
  16 /*
  17  * NOTE:
  18  * This is 2D _acceleration_ and supposed to be fast. Therefore, don't try to
  19  * reinvent the wheel (unlikely to get better with a naive implementation than
  20  * existing libraries) and avoid (poorly) reimplementing gfx primitives.
  21  * That is unnecessary and would become a performance problem. Instead, try to
  22  * map to and reuse existing optimised facilities (e.g. pixman) wherever
  23  * possible.
  24  */
  25
  26 static int ati_bpp_from_datatype(ATIVGAState *s)
  27 {
  28     switch (s->regs.dp_datatype & 0xf) {
  29     case 2:
  30         return 8;
  31     case 3:
  32     case 4:
  33         return 16;
  34     case 5:
  35         return 24;
  36     case 6:
  37         return 32;
  38     default:
  39         qemu_log_mask(LOG_UNIMP, "Unknown dst datatype %d\n",
  40                       s->regs.dp_datatype & 0xf);
  41         return 0;
  42     }
  43 }
  44
  45 #define DEFAULT_CNTL (s->regs.dp_gui_master_cntl & GMC_DST_PITCH_OFFSET_CNTL)
  46
  47 void ati_2d_blt(ATIVGAState *s)
  48 {
  49     /* FIXME it is probably more complex than this and may need to be */
  50     /* rewritten but for now as a start just to get some output: */
  51     DisplaySurface *ds = qemu_console_surface(s->vga.con);
  52     DPRINTF("%p %u ds: %p %d %d rop: %x\n", s->vga.vram_ptr,
  53             s->vga.vbe_start_addr, surface_data(ds), surface_stride(ds),
  54             surface_bits_per_pixel(ds),
  55             (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
  56     int dst_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
  57                  s->regs.dst_x : s->regs.dst_x + 1 - s->regs.dst_width);
  58     int dst_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
  59                  s->regs.dst_y : s->regs.dst_y + 1 - s->regs.dst_height);
  60     int bpp = ati_bpp_from_datatype(s);
  61     int dst_stride = DEFAULT_CNTL ? s->regs.dst_pitch : s->regs.default_pitch;
  62     uint8_t *dst_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
  63                         s->regs.dst_offset : s->regs.default_offset);
  64
  65     if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
  66         dst_bits += s->regs.crtc_offset & 0x07ffffff;
  67         dst_stride *= bpp;
  68     }
  69     uint8_t *end = s->vga.vram_ptr + s->vga.vram_size;
  70     if (dst_bits >= end || dst_bits + dst_x + (dst_y + s->regs.dst_height) *
  71         dst_stride >= end) {
  72         qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
  73         return;
  74     }
  75     DPRINTF("%d %d %d, %d %d %d, (%d,%d) -> (%d,%d) %dx%d %c %c\n",
  76             s->regs.src_offset, s->regs.dst_offset, s->regs.default_offset,
  77             s->regs.src_pitch, s->regs.dst_pitch, s->regs.default_pitch,
  78             s->regs.src_x, s->regs.src_y, s->regs.dst_x, s->regs.dst_y,
  79             s->regs.dst_width, s->regs.dst_height,
  80             (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ? '>' : '<'),
  81             (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ? 'v' : '^'));
  82     switch (s->regs.dp_mix & GMC_ROP3_MASK) {
  83     case ROP3_SRCCOPY:
  84     {
  85         int src_x = (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT ?
  86                      s->regs.src_x : s->regs.src_x + 1 - s->regs.dst_width);
  87         int src_y = (s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM ?
  88                      s->regs.src_y : s->regs.src_y + 1 - s->regs.dst_height);
  89         int src_stride = DEFAULT_CNTL ?
  90                          s->regs.src_pitch : s->regs.default_pitch;
  91         uint8_t *src_bits = s->vga.vram_ptr + (DEFAULT_CNTL ?
  92                             s->regs.src_offset : s->regs.default_offset);
  93
  94         if (s->dev_id == PCI_DEVICE_ID_ATI_RAGE128_PF) {
  95             src_bits += s->regs.crtc_offset & 0x07ffffff;
  96             src_stride *= bpp;
  97         }
  98         if (src_bits >= end || src_bits + src_x +
  99             (src_y + s->regs.dst_height) * src_stride >= end) {
 100             qemu_log_mask(LOG_UNIMP, "blt outside vram not implemented\n");
 101             return;
 102         }
 103
 104         src_stride /= sizeof(uint32_t);
 105         dst_stride /= sizeof(uint32_t);
 106         DPRINTF("pixman_blt(%p, %p, %d, %d, %d, %d, %d, %d, %d, %d, %d, %d)\n",
 107                 src_bits, dst_bits, src_stride, dst_stride, bpp, bpp,
 108                 src_x, src_y, dst_x, dst_y,
 109                 s->regs.dst_width, s->regs.dst_height);
 110         if (s->regs.dp_cntl & DST_X_LEFT_TO_RIGHT &&
 111             s->regs.dp_cntl & DST_Y_TOP_TO_BOTTOM) {
 112             pixman_blt((uint32_t *)src_bits, (uint32_t *)dst_bits,
 113                        src_stride, dst_stride, bpp, bpp,
 114                        src_x, src_y, dst_x, dst_y,
 115                        s->regs.dst_width, s->regs.dst_height);
 116         } else {
 117             /* FIXME: We only really need a temporary if src and dst overlap */
 118             int llb = s->regs.dst_width * (bpp / 8);
 119             int tmp_stride = DIV_ROUND_UP(llb, sizeof(uint32_t));
 120             uint32_t *tmp = g_malloc(tmp_stride * sizeof(uint32_t) *
 121                                      s->regs.dst_height);
 122             pixman_blt((uint32_t *)src_bits, tmp,
 123                        src_stride, tmp_stride, bpp, bpp,
 124                        src_x, src_y, 0, 0,
 125                        s->regs.dst_width, s->regs.dst_height);
 126             pixman_blt(tmp, (uint32_t *)dst_bits,
 127                        tmp_stride, dst_stride, bpp, bpp,
 128                        0, 0, dst_x, dst_y,
 129                        s->regs.dst_width, s->regs.dst_height);
 130             g_free(tmp);
 131         }
 132         if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
 133             dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
 134             s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
 135             memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
 136                                     s->regs.dst_offset +
 137                                     dst_y * surface_stride(ds),
 138                                     s->regs.dst_height * surface_stride(ds));
 139         }
 140         s->regs.dst_x += s->regs.dst_width;
 141         s->regs.dst_y += s->regs.dst_height;
 142         break;
 143     }
 144     case ROP3_PATCOPY:
 145     case ROP3_BLACKNESS:
 146     case ROP3_WHITENESS:
 147     {
 148         uint32_t filler = 0;
 149
 150         switch (s->regs.dp_mix & GMC_ROP3_MASK) {
 151         case ROP3_PATCOPY:
 152             filler = s->regs.dp_brush_frgd_clr;
 153             break;
 154         case ROP3_BLACKNESS:
 155             filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[0],
 156                      s->vga.palette[1], s->vga.palette[2]);
 157             break;
 158         case ROP3_WHITENESS:
 159             filler = 0xffUL << 24 | rgb_to_pixel32(s->vga.palette[3],
 160                      s->vga.palette[4], s->vga.palette[5]);
 161             break;
 162         }
 163
 164         dst_stride /= sizeof(uint32_t);
 165         DPRINTF("pixman_fill(%p, %d, %d, %d, %d, %d, %d, %x)\n",
 166                 dst_bits, dst_stride, bpp,
 167                 s->regs.dst_x, s->regs.dst_y,
 168                 s->regs.dst_width, s->regs.dst_height,
 169                 filler);
 170         pixman_fill((uint32_t *)dst_bits, dst_stride, bpp,
 171                     s->regs.dst_x, s->regs.dst_y,
 172                     s->regs.dst_width, s->regs.dst_height,
 173                     filler);
 174         if (dst_bits >= s->vga.vram_ptr + s->vga.vbe_start_addr &&
 175             dst_bits < s->vga.vram_ptr + s->vga.vbe_start_addr +
 176             s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] * s->vga.vbe_line_offset) {
 177             memory_region_set_dirty(&s->vga.vram, s->vga.vbe_start_addr +
 178                                     s->regs.dst_offset +
 179                                     dst_y * surface_stride(ds),
 180                                     s->regs.dst_height * surface_stride(ds));
 181         }
 182         s->regs.dst_y += s->regs.dst_height;
 183         break;
 184     }
 185     default:
 186         qemu_log_mask(LOG_UNIMP, "Unimplemented ati_2d blt op %x\n",
 187                       (s->regs.dp_mix & GMC_ROP3_MASK) >> 16);
 188     }
 189 }