target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "sysemu/kvm.h"
  26 #include "sysemu/cpus.h"
  27 #include "topology.h"
  28
  29 #include "qemu/option.h"
  30 #include "qemu/config-file.h"
  31 #include "qapi/qmp/qerror.h"
  32
  33 #include "qapi/visitor.h"
  34 #include "sysemu/arch_init.h"
  35
  36 #include "hyperv.h"
  37
  38 #include "hw/hw.h"
  39 #if defined(CONFIG_KVM)
  40 #include <linux/kvm_para.h>
  41 #endif
  42
  43 #include "sysemu/sysemu.h"
  44 #include "hw/qdev-properties.h"
  45 #include "hw/cpu/icc_bus.h"
  46 #ifndef CONFIG_USER_ONLY
  47 #include "hw/xen/xen.h"
  48 #include "hw/i386/apic_internal.h"
  49 #endif
  50
  51 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
  52                                      uint32_t vendor2, uint32_t vendor3)
  53 {
  54     int i;
  55     for (i = 0; i < 4; i++) {
  56         dst[i] = vendor1 >> (8 * i);
  57         dst[i + 4] = vendor2 >> (8 * i);
  58         dst[i + 8] = vendor3 >> (8 * i);
  59     }
  60     dst[CPUID_VENDOR_SZ] = '\0';
  61 }
  62
  63 /* feature flags taken from "Intel Processor Identification and the CPUID
  64  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
  65  * between feature naming conventions, aliases may be added.
  66  */
  67 static const char *feature_name[] = {
  68     "fpu", "vme", "de", "pse",
  69     "tsc", "msr", "pae", "mce",
  70     "cx8", "apic", NULL, "sep",
  71     "mtrr", "pge", "mca", "cmov",
  72     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
  73     NULL, "ds" /* Intel dts */, "acpi", "mmx",
  74     "fxsr", "sse", "sse2", "ss",
  75     "ht" /* Intel htt */, "tm", "ia64", "pbe",
  76 };
  77 static const char *ext_feature_name[] = {
  78     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
  79     "ds_cpl", "vmx", "smx", "est",
  80     "tm2", "ssse3", "cid", NULL,
  81     "fma", "cx16", "xtpr", "pdcm",
  82     NULL, "pcid", "dca", "sse4.1|sse4_1",
  83     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
  84     "tsc-deadline", "aes", "xsave", "osxsave",
  85     "avx", "f16c", "rdrand", "hypervisor",
  86 };
  87 /* Feature names that are already defined on feature_name[] but are set on
  88  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
  89  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
  90  * if and only if CPU vendor is AMD.
  91  */
  92 static const char *ext2_feature_name[] = {
  93     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
  94     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
  95     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
  96     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
  97     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
  98     "nx|xd", NULL, "mmxext", NULL /* mmx */,
  99     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
 100     NULL, "lm|i64", "3dnowext", "3dnow",
 101 };
 102 static const char *ext3_feature_name[] = {
 103     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
 104     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
 105     "3dnowprefetch", "osvw", "ibs", "xop",
 106     "skinit", "wdt", NULL, "lwp",
 107     "fma4", "tce", NULL, "nodeid_msr",
 108     NULL, "tbm", "topoext", "perfctr_core",
 109     "perfctr_nb", NULL, NULL, NULL,
 110     NULL, NULL, NULL, NULL,
 111 };
 112
 113 static const char *ext4_feature_name[] = {
 114     NULL, NULL, "xstore", "xstore-en",
 115     NULL, NULL, "xcrypt", "xcrypt-en",
 116     "ace2", "ace2-en", "phe", "phe-en",
 117     "pmm", "pmm-en", NULL, NULL,
 118     NULL, NULL, NULL, NULL,
 119     NULL, NULL, NULL, NULL,
 120     NULL, NULL, NULL, NULL,
 121     NULL, NULL, NULL, NULL,
 122 };
 123
 124 static const char *kvm_feature_name[] = {
 125     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 126     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL,
 127     NULL, NULL, NULL, NULL,
 128     NULL, NULL, NULL, NULL,
 129     NULL, NULL, NULL, NULL,
 130     NULL, NULL, NULL, NULL,
 131     NULL, NULL, NULL, NULL,
 132     NULL, NULL, NULL, NULL,
 133 };
 134
 135 static const char *svm_feature_name[] = {
 136     "npt", "lbrv", "svm_lock", "nrip_save",
 137     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 138     NULL, NULL, "pause_filter", NULL,
 139     "pfthreshold", NULL, NULL, NULL,
 140     NULL, NULL, NULL, NULL,
 141     NULL, NULL, NULL, NULL,
 142     NULL, NULL, NULL, NULL,
 143     NULL, NULL, NULL, NULL,
 144 };
 145
 146 static const char *cpuid_7_0_ebx_feature_name[] = {
 147     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
 148     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
 149     NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
 150     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 151 };
 152
 153 typedef struct FeatureWordInfo {
 154     const char **feat_names;
 155     uint32_t cpuid_eax; /* Input EAX for CPUID */
 156     int cpuid_reg;      /* R_* register constant */
 157 } FeatureWordInfo;
 158
 159 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 160     [FEAT_1_EDX] = {
 161         .feat_names = feature_name,
 162         .cpuid_eax = 1, .cpuid_reg = R_EDX,
 163     },
 164     [FEAT_1_ECX] = {
 165         .feat_names = ext_feature_name,
 166         .cpuid_eax = 1, .cpuid_reg = R_ECX,
 167     },
 168     [FEAT_8000_0001_EDX] = {
 169         .feat_names = ext2_feature_name,
 170         .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
 171     },
 172     [FEAT_8000_0001_ECX] = {
 173         .feat_names = ext3_feature_name,
 174         .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
 175     },
 176     [FEAT_C000_0001_EDX] = {
 177         .feat_names = ext4_feature_name,
 178         .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
 179     },
 180     [FEAT_KVM] = {
 181         .feat_names = kvm_feature_name,
 182         .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
 183     },
 184     [FEAT_SVM] = {
 185         .feat_names = svm_feature_name,
 186         .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
 187     },
 188     [FEAT_7_0_EBX] = {
 189         .feat_names = cpuid_7_0_ebx_feature_name,
 190         .cpuid_eax = 7, .cpuid_reg = R_EBX,
 191     },
 192 };
 193
 194 const char *get_register_name_32(unsigned int reg)
 195 {
 196     static const char *reg_names[CPU_NB_REGS32] = {
 197         [R_EAX] = "EAX",
 198         [R_ECX] = "ECX",
 199         [R_EDX] = "EDX",
 200         [R_EBX] = "EBX",
 201         [R_ESP] = "ESP",
 202         [R_EBP] = "EBP",
 203         [R_ESI] = "ESI",
 204         [R_EDI] = "EDI",
 205     };
 206
 207     if (reg > CPU_NB_REGS32) {
 208         return NULL;
 209     }
 210     return reg_names[reg];
 211 }
 212
 213 /* collects per-function cpuid data
 214  */
 215 typedef struct model_features_t {
 216     uint32_t *guest_feat;
 217     uint32_t *host_feat;
 218     FeatureWord feat_word;
 219 } model_features_t;
 220
 221 int check_cpuid = 0;
 222 int enforce_cpuid = 0;
 223
 224 static uint32_t kvm_default_features = (1 << KVM_FEATURE_CLOCKSOURCE) |
 225         (1 << KVM_FEATURE_NOP_IO_DELAY) |
 226         (1 << KVM_FEATURE_CLOCKSOURCE2) |
 227         (1 << KVM_FEATURE_ASYNC_PF) |
 228         (1 << KVM_FEATURE_STEAL_TIME) |
 229         (1 << KVM_FEATURE_PV_EOI) |
 230         (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT);
 231
 232 void disable_kvm_pv_eoi(void)
 233 {
 234     kvm_default_features &= ~(1UL << KVM_FEATURE_PV_EOI);
 235 }
 236
 237 void host_cpuid(uint32_t function, uint32_t count,
 238                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 239 {
 240 #if defined(CONFIG_KVM)
 241     uint32_t vec[4];
 242
 243 #ifdef __x86_64__
 244     asm volatile("cpuid"
 245                  : "=a"(vec[0]), "=b"(vec[1]),
 246                    "=c"(vec[2]), "=d"(vec[3])
 247                  : "0"(function), "c"(count) : "cc");
 248 #else
 249     asm volatile("pusha \n\t"
 250                  "cpuid \n\t"
 251                  "mov %%eax, 0(%2) \n\t"
 252                  "mov %%ebx, 4(%2) \n\t"
 253                  "mov %%ecx, 8(%2) \n\t"
 254                  "mov %%edx, 12(%2) \n\t"
 255                  "popa"
 256                  : : "a"(function), "c"(count), "S"(vec)
 257                  : "memory", "cc");
 258 #endif
 259
 260     if (eax)
 261         *eax = vec[0];
 262     if (ebx)
 263         *ebx = vec[1];
 264     if (ecx)
 265         *ecx = vec[2];
 266     if (edx)
 267         *edx = vec[3];
 268 #endif
 269 }
 270
 271 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 272
 273 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 274  * a substring.  ex if !NULL points to the first char after a substring,
 275  * otherwise the string is assumed to sized by a terminating nul.
 276  * Return lexical ordering of *s1:*s2.
 277  */
 278 static int sstrcmp(const char *s1, const char *e1, const char *s2,
 279     const char *e2)
 280 {
 281     for (;;) {
 282         if (!*s1 || !*s2 || *s1 != *s2)
 283             return (*s1 - *s2);
 284         ++s1, ++s2;
 285         if (s1 == e1 && s2 == e2)
 286             return (0);
 287         else if (s1 == e1)
 288             return (*s2);
 289         else if (s2 == e2)
 290             return (*s1);
 291     }
 292 }
 293
 294 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 295  * '|' delimited (possibly empty) strings in which case search for a match
 296  * within the alternatives proceeds left to right.  Return 0 for success,
 297  * non-zero otherwise.
 298  */
 299 static int altcmp(const char *s, const char *e, const char *altstr)
 300 {
 301     const char *p, *q;
 302
 303     for (q = p = altstr; ; ) {
 304         while (*p && *p != '|')
 305             ++p;
 306         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 307             return (0);
 308         if (!*p)
 309             return (1);
 310         else
 311             q = ++p;
 312     }
 313 }
 314
 315 /* search featureset for flag *[s..e), if found set corresponding bit in
 316  * *pval and return true, otherwise return false
 317  */
 318 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 319                            const char **featureset)
 320 {
 321     uint32_t mask;
 322     const char **ppc;
 323     bool found = false;
 324
 325     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 326         if (*ppc && !altcmp(s, e, *ppc)) {
 327             *pval |= mask;
 328             found = true;
 329         }
 330     }
 331     return found;
 332 }
 333
 334 static void add_flagname_to_bitmaps(const char *flagname,
 335                                     FeatureWordArray words)
 336 {
 337     FeatureWord w;
 338     for (w = 0; w < FEATURE_WORDS; w++) {
 339         FeatureWordInfo *wi = &feature_word_info[w];
 340         if (wi->feat_names &&
 341             lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
 342             break;
 343         }
 344     }
 345     if (w == FEATURE_WORDS) {
 346         fprintf(stderr, "CPU feature %s not found\n", flagname);
 347     }
 348 }
 349
 350 typedef struct x86_def_t {
 351     const char *name;
 352     uint32_t level;
 353     /* vendor is zero-terminated, 12 character ASCII string */
 354     char vendor[CPUID_VENDOR_SZ + 1];
 355     int family;
 356     int model;
 357     int stepping;
 358     uint32_t features, ext_features, ext2_features, ext3_features;
 359     uint32_t kvm_features, svm_features;
 360     uint32_t xlevel;
 361     char model_id[48];
 362     /* Store the results of Centaur's CPUID instructions */
 363     uint32_t ext4_features;
 364     uint32_t xlevel2;
 365     /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
 366     uint32_t cpuid_7_0_ebx_features;
 367 } x86_def_t;
 368
 369 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 370 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 371           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 372 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 373           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 374           CPUID_PSE36 | CPUID_FXSR)
 375 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 376 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 377           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 378           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 379           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 380
 381 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 382           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 383           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 384           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 385           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
 386           /* partly implemented:
 387           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
 388           CPUID_PSE36 (needed for Solaris) */
 389           /* missing:
 390           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 391 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 392           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 393           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 394           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
 395           /* missing:
 396           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 397           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 398           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 399           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
 400           CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
 401           CPUID_EXT_RDRAND */
 402 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 403           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 404           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
 405           /* missing:
 406           CPUID_EXT2_PDPE1GB */
 407 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 408           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 409 #define TCG_SVM_FEATURES 0
 410 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
 411           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
 412           /* missing:
 413           CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 414           CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 415           CPUID_7_0_EBX_RDSEED */
 416
 417 /* built-in CPU model definitions
 418  */
 419 static x86_def_t builtin_x86_defs[] = {
 420     {
 421         .name = "qemu64",
 422         .level = 4,
 423         .vendor = CPUID_VENDOR_AMD,
 424         .family = 6,
 425         .model = 2,
 426         .stepping = 3,
 427         .features = PPRO_FEATURES |
 428             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 429             CPUID_PSE36,
 430         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
 431         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 432             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 433         .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 434             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 435         .xlevel = 0x8000000A,
 436     },
 437     {
 438         .name = "phenom",
 439         .level = 5,
 440         .vendor = CPUID_VENDOR_AMD,
 441         .family = 16,
 442         .model = 2,
 443         .stepping = 3,
 444         .features = PPRO_FEATURES |
 445             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 446             CPUID_PSE36 | CPUID_VME | CPUID_HT,
 447         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 448             CPUID_EXT_POPCNT,
 449         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 450             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 451             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 452             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 453         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 454                     CPUID_EXT3_CR8LEG,
 455                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 456                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 457         .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 458             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 459         .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
 460         .xlevel = 0x8000001A,
 461         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 462     },
 463     {
 464         .name = "core2duo",
 465         .level = 10,
 466         .vendor = CPUID_VENDOR_INTEL,
 467         .family = 6,
 468         .model = 15,
 469         .stepping = 11,
 470         .features = PPRO_FEATURES |
 471             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 472             CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
 473             CPUID_HT | CPUID_TM | CPUID_PBE,
 474         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 475             CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
 476             CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 477         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 478         .ext3_features = CPUID_EXT3_LAHF_LM,
 479         .xlevel = 0x80000008,
 480         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 481     },
 482     {
 483         .name = "kvm64",
 484         .level = 5,
 485         .vendor = CPUID_VENDOR_INTEL,
 486         .family = 15,
 487         .model = 6,
 488         .stepping = 1,
 489         /* Missing: CPUID_VME, CPUID_HT */
 490         .features = PPRO_FEATURES |
 491             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 492             CPUID_PSE36,
 493         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 494         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 495         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 496         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 497             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 498         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 499                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 500                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 501                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 502         .ext3_features = 0,
 503         .xlevel = 0x80000008,
 504         .model_id = "Common KVM processor"
 505     },
 506     {
 507         .name = "qemu32",
 508         .level = 4,
 509         .vendor = CPUID_VENDOR_INTEL,
 510         .family = 6,
 511         .model = 3,
 512         .stepping = 3,
 513         .features = PPRO_FEATURES,
 514         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
 515         .xlevel = 0x80000004,
 516     },
 517     {
 518         .name = "kvm32",
 519         .level = 5,
 520         .vendor = CPUID_VENDOR_INTEL,
 521         .family = 15,
 522         .model = 6,
 523         .stepping = 1,
 524         .features = PPRO_FEATURES |
 525             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 526         .ext_features = CPUID_EXT_SSE3,
 527         .ext2_features = PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
 528         .ext3_features = 0,
 529         .xlevel = 0x80000008,
 530         .model_id = "Common 32-bit KVM processor"
 531     },
 532     {
 533         .name = "coreduo",
 534         .level = 10,
 535         .vendor = CPUID_VENDOR_INTEL,
 536         .family = 6,
 537         .model = 14,
 538         .stepping = 8,
 539         .features = PPRO_FEATURES | CPUID_VME |
 540             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
 541             CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 542         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
 543             CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 544         .ext2_features = CPUID_EXT2_NX,
 545         .xlevel = 0x80000008,
 546         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 547     },
 548     {
 549         .name = "486",
 550         .level = 1,
 551         .vendor = CPUID_VENDOR_INTEL,
 552         .family = 4,
 553         .model = 0,
 554         .stepping = 0,
 555         .features = I486_FEATURES,
 556         .xlevel = 0,
 557     },
 558     {
 559         .name = "pentium",
 560         .level = 1,
 561         .vendor = CPUID_VENDOR_INTEL,
 562         .family = 5,
 563         .model = 4,
 564         .stepping = 3,
 565         .features = PENTIUM_FEATURES,
 566         .xlevel = 0,
 567     },
 568     {
 569         .name = "pentium2",
 570         .level = 2,
 571         .vendor = CPUID_VENDOR_INTEL,
 572         .family = 6,
 573         .model = 5,
 574         .stepping = 2,
 575         .features = PENTIUM2_FEATURES,
 576         .xlevel = 0,
 577     },
 578     {
 579         .name = "pentium3",
 580         .level = 2,
 581         .vendor = CPUID_VENDOR_INTEL,
 582         .family = 6,
 583         .model = 7,
 584         .stepping = 3,
 585         .features = PENTIUM3_FEATURES,
 586         .xlevel = 0,
 587     },
 588     {
 589         .name = "athlon",
 590         .level = 2,
 591         .vendor = CPUID_VENDOR_AMD,
 592         .family = 6,
 593         .model = 2,
 594         .stepping = 3,
 595         .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 596             CPUID_MCA,
 597         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 598             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 599         .xlevel = 0x80000008,
 600     },
 601     {
 602         .name = "n270",
 603         /* original is on level 10 */
 604         .level = 5,
 605         .vendor = CPUID_VENDOR_INTEL,
 606         .family = 6,
 607         .model = 28,
 608         .stepping = 2,
 609         .features = PPRO_FEATURES |
 610             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
 611             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 612             /* Some CPUs got no CPUID_SEP */
 613         .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 614             CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
 615         .ext2_features = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 616             CPUID_EXT2_NX,
 617         .ext3_features = CPUID_EXT3_LAHF_LM,
 618         .xlevel = 0x8000000A,
 619         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 620     },
 621     {
 622         .name = "Conroe",
 623         .level = 2,
 624         .vendor = CPUID_VENDOR_INTEL,
 625         .family = 6,
 626         .model = 2,
 627         .stepping = 3,
 628         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 629              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 630              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 631              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 632              CPUID_DE | CPUID_FP87,
 633         .ext_features = CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 634         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 635         .ext3_features = CPUID_EXT3_LAHF_LM,
 636         .xlevel = 0x8000000A,
 637         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 638     },
 639     {
 640         .name = "Penryn",
 641         .level = 2,
 642         .vendor = CPUID_VENDOR_INTEL,
 643         .family = 6,
 644         .model = 2,
 645         .stepping = 3,
 646         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 647              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 648              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 649              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 650              CPUID_DE | CPUID_FP87,
 651         .ext_features = CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 652              CPUID_EXT_SSE3,
 653         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 654         .ext3_features = CPUID_EXT3_LAHF_LM,
 655         .xlevel = 0x8000000A,
 656         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 657     },
 658     {
 659         .name = "Nehalem",
 660         .level = 2,
 661         .vendor = CPUID_VENDOR_INTEL,
 662         .family = 6,
 663         .model = 2,
 664         .stepping = 3,
 665         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 666              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 667              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 668              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 669              CPUID_DE | CPUID_FP87,
 670         .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 671              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 672         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 673         .ext3_features = CPUID_EXT3_LAHF_LM,
 674         .xlevel = 0x8000000A,
 675         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 676     },
 677     {
 678         .name = "Westmere",
 679         .level = 11,
 680         .vendor = CPUID_VENDOR_INTEL,
 681         .family = 6,
 682         .model = 44,
 683         .stepping = 1,
 684         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 685              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 686              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 687              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 688              CPUID_DE | CPUID_FP87,
 689         .ext_features = CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 690              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 691              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 692         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 693         .ext3_features = CPUID_EXT3_LAHF_LM,
 694         .xlevel = 0x8000000A,
 695         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 696     },
 697     {
 698         .name = "SandyBridge",
 699         .level = 0xd,
 700         .vendor = CPUID_VENDOR_INTEL,
 701         .family = 6,
 702         .model = 42,
 703         .stepping = 1,
 704         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 705              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 706              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 707              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 708              CPUID_DE | CPUID_FP87,
 709         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 710              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
 711              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 712              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 713              CPUID_EXT_SSE3,
 714         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 715              CPUID_EXT2_SYSCALL,
 716         .ext3_features = CPUID_EXT3_LAHF_LM,
 717         .xlevel = 0x8000000A,
 718         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
 719     },
 720     {
 721         .name = "Haswell",
 722         .level = 0xd,
 723         .vendor = CPUID_VENDOR_INTEL,
 724         .family = 6,
 725         .model = 60,
 726         .stepping = 1,
 727         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 728              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 729              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 730              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 731              CPUID_DE | CPUID_FP87,
 732         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 733              CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
 734              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 735              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
 736              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
 737              CPUID_EXT_PCID,
 738         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 739              CPUID_EXT2_SYSCALL,
 740         .ext3_features = CPUID_EXT3_LAHF_LM,
 741         .cpuid_7_0_ebx_features = CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
 742             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
 743             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
 744             CPUID_7_0_EBX_RTM,
 745         .xlevel = 0x8000000A,
 746         .model_id = "Intel Core Processor (Haswell)",
 747     },
 748     {
 749         .name = "Opteron_G1",
 750         .level = 5,
 751         .vendor = CPUID_VENDOR_AMD,
 752         .family = 15,
 753         .model = 6,
 754         .stepping = 1,
 755         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 756              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 757              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 758              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 759              CPUID_DE | CPUID_FP87,
 760         .ext_features = CPUID_EXT_SSE3,
 761         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 762              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 763              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 764              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 765              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 766              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 767         .xlevel = 0x80000008,
 768         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
 769     },
 770     {
 771         .name = "Opteron_G2",
 772         .level = 5,
 773         .vendor = CPUID_VENDOR_AMD,
 774         .family = 15,
 775         .model = 6,
 776         .stepping = 1,
 777         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 778              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 779              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 780              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 781              CPUID_DE | CPUID_FP87,
 782         .ext_features = CPUID_EXT_CX16 | CPUID_EXT_SSE3,
 783         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 784              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 785              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 786              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 787              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 788              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 789              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 790         .ext3_features = CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 791         .xlevel = 0x80000008,
 792         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
 793     },
 794     {
 795         .name = "Opteron_G3",
 796         .level = 5,
 797         .vendor = CPUID_VENDOR_AMD,
 798         .family = 15,
 799         .model = 6,
 800         .stepping = 1,
 801         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 802              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 803              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 804              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 805              CPUID_DE | CPUID_FP87,
 806         .ext_features = CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
 807              CPUID_EXT_SSE3,
 808         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
 809              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
 810              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
 811              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
 812              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
 813              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
 814              CPUID_EXT2_DE | CPUID_EXT2_FPU,
 815         .ext3_features = CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
 816              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
 817         .xlevel = 0x80000008,
 818         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
 819     },
 820     {
 821         .name = "Opteron_G4",
 822         .level = 0xd,
 823         .vendor = CPUID_VENDOR_AMD,
 824         .family = 21,
 825         .model = 1,
 826         .stepping = 2,
 827         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 828              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 829              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 830              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 831              CPUID_DE | CPUID_FP87,
 832         .ext_features = CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 833              CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 834              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 835              CPUID_EXT_SSE3,
 836         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
 837              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 838              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 839              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 840              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 841              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 842              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 843         .ext3_features = CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
 844              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
 845              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
 846              CPUID_EXT3_LAHF_LM,
 847         .xlevel = 0x8000001A,
 848         .model_id = "AMD Opteron 62xx class CPU",
 849     },
 850     {
 851         .name = "Opteron_G5",
 852         .level = 0xd,
 853         .vendor = CPUID_VENDOR_AMD,
 854         .family = 21,
 855         .model = 2,
 856         .stepping = 0,
 857         .features = CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 858              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 859              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 860              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 861              CPUID_DE | CPUID_FP87,
 862         .ext_features = CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
 863              CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 864              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
 865              CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 866         .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
 867              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 868              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 869              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 870              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 871              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 872              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 873         .ext3_features = CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
 874              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
 875              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
 876              CPUID_EXT3_LAHF_LM,
 877         .xlevel = 0x8000001A,
 878         .model_id = "AMD Opteron 63xx class CPU",
 879     },
 880 };
 881
 882 #ifdef CONFIG_KVM
 883 static int cpu_x86_fill_model_id(char *str)
 884 {
 885     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 886     int i;
 887
 888     for (i = 0; i < 3; i++) {
 889         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
 890         memcpy(str + i * 16 +  0, &eax, 4);
 891         memcpy(str + i * 16 +  4, &ebx, 4);
 892         memcpy(str + i * 16 +  8, &ecx, 4);
 893         memcpy(str + i * 16 + 12, &edx, 4);
 894     }
 895     return 0;
 896 }
 897 #endif
 898
 899 /* Fill a x86_def_t struct with information about the host CPU, and
 900  * the CPU features supported by the host hardware + host kernel
 901  *
 902  * This function may be called only if KVM is enabled.
 903  */
 904 static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def)
 905 {
 906 #ifdef CONFIG_KVM
 907     KVMState *s = kvm_state;
 908     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
 909
 910     assert(kvm_enabled());
 911
 912     x86_cpu_def->name = "host";
 913     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
 914     x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
 915
 916     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
 917     x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
 918     x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
 919     x86_cpu_def->stepping = eax & 0x0F;
 920
 921     x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
 922     x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX);
 923     x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX);
 924
 925     if (x86_cpu_def->level >= 7) {
 926         x86_cpu_def->cpuid_7_0_ebx_features =
 927                     kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX);
 928     } else {
 929         x86_cpu_def->cpuid_7_0_ebx_features = 0;
 930     }
 931
 932     x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
 933     x86_cpu_def->ext2_features =
 934                 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
 935     x86_cpu_def->ext3_features =
 936                 kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
 937
 938     cpu_x86_fill_model_id(x86_cpu_def->model_id);
 939
 940     /* Call Centaur's CPUID instruction. */
 941     if (!strcmp(x86_cpu_def->vendor, CPUID_VENDOR_VIA)) {
 942         host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
 943         eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
 944         if (eax >= 0xC0000001) {
 945             /* Support VIA max extended level */
 946             x86_cpu_def->xlevel2 = eax;
 947             host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
 948             x86_cpu_def->ext4_features =
 949                     kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
 950         }
 951     }
 952
 953     /* Other KVM-specific feature fields: */
 954     x86_cpu_def->svm_features =
 955         kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
 956     x86_cpu_def->kvm_features =
 957         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
 958
 959 #endif /* CONFIG_KVM */
 960 }
 961
 962 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
 963 {
 964     int i;
 965
 966     for (i = 0; i < 32; ++i)
 967         if (1 << i & mask) {
 968             const char *reg = get_register_name_32(f->cpuid_reg);
 969             assert(reg);
 970             fprintf(stderr, "warning: host doesn't support requested feature: "
 971                 "CPUID.%02XH:%s%s%s [bit %d]\n",
 972                 f->cpuid_eax, reg,
 973                 f->feat_names[i] ? "." : "",
 974                 f->feat_names[i] ? f->feat_names[i] : "", i);
 975             break;
 976         }
 977     return 0;
 978 }
 979
 980 /* Check if all requested cpu flags are making their way to the guest
 981  *
 982  * Returns 0 if all flags are supported by the host, non-zero otherwise.
 983  *
 984  * This function may be called only if KVM is enabled.
 985  */
 986 static int kvm_check_features_against_host(X86CPU *cpu)
 987 {
 988     CPUX86State *env = &cpu->env;
 989     x86_def_t host_def;
 990     uint32_t mask;
 991     int rv, i;
 992     struct model_features_t ft[] = {
 993         {&env->cpuid_features, &host_def.features,
 994             FEAT_1_EDX },
 995         {&env->cpuid_ext_features, &host_def.ext_features,
 996             FEAT_1_ECX },
 997         {&env->cpuid_ext2_features, &host_def.ext2_features,
 998             FEAT_8000_0001_EDX },
 999         {&env->cpuid_ext3_features, &host_def.ext3_features,
1000             FEAT_8000_0001_ECX },
1001         {&env->cpuid_ext4_features, &host_def.ext4_features,
1002             FEAT_C000_0001_EDX },
1003         {&env->cpuid_7_0_ebx_features, &host_def.cpuid_7_0_ebx_features,
1004             FEAT_7_0_EBX },
1005         {&env->cpuid_svm_features, &host_def.svm_features,
1006             FEAT_SVM },
1007         {&env->cpuid_kvm_features, &host_def.kvm_features,
1008             FEAT_KVM },
1009     };
1010
1011     assert(kvm_enabled());
1012
1013     kvm_cpu_fill_host(&host_def);
1014     for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) {
1015         FeatureWord w = ft[i].feat_word;
1016         FeatureWordInfo *wi = &feature_word_info[w];
1017         for (mask = 1; mask; mask <<= 1) {
1018             if (*ft[i].guest_feat & mask &&
1019                 !(*ft[i].host_feat & mask)) {
1020                 unavailable_host_feature(wi, mask);
1021                 rv = 1;
1022             }
1023         }
1024     }
1025     return rv;
1026 }
1027
1028 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1029                                          const char *name, Error **errp)
1030 {
1031     X86CPU *cpu = X86_CPU(obj);
1032     CPUX86State *env = &cpu->env;
1033     int64_t value;
1034
1035     value = (env->cpuid_version >> 8) & 0xf;
1036     if (value == 0xf) {
1037         value += (env->cpuid_version >> 20) & 0xff;
1038     }
1039     visit_type_int(v, &value, name, errp);
1040 }
1041
1042 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1043                                          const char *name, Error **errp)
1044 {
1045     X86CPU *cpu = X86_CPU(obj);
1046     CPUX86State *env = &cpu->env;
1047     const int64_t min = 0;
1048     const int64_t max = 0xff + 0xf;
1049     int64_t value;
1050
1051     visit_type_int(v, &value, name, errp);
1052     if (error_is_set(errp)) {
1053         return;
1054     }
1055     if (value < min || value > max) {
1056         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1057                   name ? name : "null", value, min, max);
1058         return;
1059     }
1060
1061     env->cpuid_version &= ~0xff00f00;
1062     if (value > 0x0f) {
1063         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1064     } else {
1065         env->cpuid_version |= value << 8;
1066     }
1067 }
1068
1069 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1070                                         const char *name, Error **errp)
1071 {
1072     X86CPU *cpu = X86_CPU(obj);
1073     CPUX86State *env = &cpu->env;
1074     int64_t value;
1075
1076     value = (env->cpuid_version >> 4) & 0xf;
1077     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1078     visit_type_int(v, &value, name, errp);
1079 }
1080
1081 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1082                                         const char *name, Error **errp)
1083 {
1084     X86CPU *cpu = X86_CPU(obj);
1085     CPUX86State *env = &cpu->env;
1086     const int64_t min = 0;
1087     const int64_t max = 0xff;
1088     int64_t value;
1089
1090     visit_type_int(v, &value, name, errp);
1091     if (error_is_set(errp)) {
1092         return;
1093     }
1094     if (value < min || value > max) {
1095         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1096                   name ? name : "null", value, min, max);
1097         return;
1098     }
1099
1100     env->cpuid_version &= ~0xf00f0;
1101     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1102 }
1103
1104 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1105                                            void *opaque, const char *name,
1106                                            Error **errp)
1107 {
1108     X86CPU *cpu = X86_CPU(obj);
1109     CPUX86State *env = &cpu->env;
1110     int64_t value;
1111
1112     value = env->cpuid_version & 0xf;
1113     visit_type_int(v, &value, name, errp);
1114 }
1115
1116 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1117                                            void *opaque, const char *name,
1118                                            Error **errp)
1119 {
1120     X86CPU *cpu = X86_CPU(obj);
1121     CPUX86State *env = &cpu->env;
1122     const int64_t min = 0;
1123     const int64_t max = 0xf;
1124     int64_t value;
1125
1126     visit_type_int(v, &value, name, errp);
1127     if (error_is_set(errp)) {
1128         return;
1129     }
1130     if (value < min || value > max) {
1131         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1132                   name ? name : "null", value, min, max);
1133         return;
1134     }
1135
1136     env->cpuid_version &= ~0xf;
1137     env->cpuid_version |= value & 0xf;
1138 }
1139
1140 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1141                                 const char *name, Error **errp)
1142 {
1143     X86CPU *cpu = X86_CPU(obj);
1144
1145     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1146 }
1147
1148 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1149                                 const char *name, Error **errp)
1150 {
1151     X86CPU *cpu = X86_CPU(obj);
1152
1153     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1154 }
1155
1156 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1157                                  const char *name, Error **errp)
1158 {
1159     X86CPU *cpu = X86_CPU(obj);
1160
1161     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1162 }
1163
1164 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1165                                  const char *name, Error **errp)
1166 {
1167     X86CPU *cpu = X86_CPU(obj);
1168
1169     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1170 }
1171
1172 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1173 {
1174     X86CPU *cpu = X86_CPU(obj);
1175     CPUX86State *env = &cpu->env;
1176     char *value;
1177
1178     value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1179     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1180                              env->cpuid_vendor3);
1181     return value;
1182 }
1183
1184 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1185                                  Error **errp)
1186 {
1187     X86CPU *cpu = X86_CPU(obj);
1188     CPUX86State *env = &cpu->env;
1189     int i;
1190
1191     if (strlen(value) != CPUID_VENDOR_SZ) {
1192         error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1193                   "vendor", value);
1194         return;
1195     }
1196
1197     env->cpuid_vendor1 = 0;
1198     env->cpuid_vendor2 = 0;
1199     env->cpuid_vendor3 = 0;
1200     for (i = 0; i < 4; i++) {
1201         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1202         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1203         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1204     }
1205 }
1206
1207 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1208 {
1209     X86CPU *cpu = X86_CPU(obj);
1210     CPUX86State *env = &cpu->env;
1211     char *value;
1212     int i;
1213
1214     value = g_malloc(48 + 1);
1215     for (i = 0; i < 48; i++) {
1216         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1217     }
1218     value[48] = '\0';
1219     return value;
1220 }
1221
1222 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1223                                    Error **errp)
1224 {
1225     X86CPU *cpu = X86_CPU(obj);
1226     CPUX86State *env = &cpu->env;
1227     int c, len, i;
1228
1229     if (model_id == NULL) {
1230         model_id = "";
1231     }
1232     len = strlen(model_id);
1233     memset(env->cpuid_model, 0, 48);
1234     for (i = 0; i < 48; i++) {
1235         if (i >= len) {
1236             c = '\0';
1237         } else {
1238             c = (uint8_t)model_id[i];
1239         }
1240         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1241     }
1242 }
1243
1244 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1245                                    const char *name, Error **errp)
1246 {
1247     X86CPU *cpu = X86_CPU(obj);
1248     int64_t value;
1249
1250     value = cpu->env.tsc_khz * 1000;
1251     visit_type_int(v, &value, name, errp);
1252 }
1253
1254 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1255                                    const char *name, Error **errp)
1256 {
1257     X86CPU *cpu = X86_CPU(obj);
1258     const int64_t min = 0;
1259     const int64_t max = INT64_MAX;
1260     int64_t value;
1261
1262     visit_type_int(v, &value, name, errp);
1263     if (error_is_set(errp)) {
1264         return;
1265     }
1266     if (value < min || value > max) {
1267         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1268                   name ? name : "null", value, min, max);
1269         return;
1270     }
1271
1272     cpu->env.tsc_khz = value / 1000;
1273 }
1274
1275 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1276                                   const char *name, Error **errp)
1277 {
1278     X86CPU *cpu = X86_CPU(obj);
1279     int64_t value = cpu->env.cpuid_apic_id;
1280
1281     visit_type_int(v, &value, name, errp);
1282 }
1283
1284 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1285                                   const char *name, Error **errp)
1286 {
1287     X86CPU *cpu = X86_CPU(obj);
1288     DeviceState *dev = DEVICE(obj);
1289     const int64_t min = 0;
1290     const int64_t max = UINT32_MAX;
1291     Error *error = NULL;
1292     int64_t value;
1293
1294     if (dev->realized) {
1295         error_setg(errp, "Attempt to set property '%s' on '%s' after "
1296                    "it was realized", name, object_get_typename(obj));
1297         return;
1298     }
1299
1300     visit_type_int(v, &value, name, &error);
1301     if (error) {
1302         error_propagate(errp, error);
1303         return;
1304     }
1305     if (value < min || value > max) {
1306         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1307                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1308                    object_get_typename(obj), name, value, min, max);
1309         return;
1310     }
1311
1312     if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1313         error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1314         return;
1315     }
1316     cpu->env.cpuid_apic_id = value;
1317 }
1318
1319 static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
1320 {
1321     x86_def_t *def;
1322     int i;
1323
1324     if (name == NULL) {
1325         return -1;
1326     }
1327     if (kvm_enabled() && strcmp(name, "host") == 0) {
1328         kvm_cpu_fill_host(x86_cpu_def);
1329         return 0;
1330     }
1331
1332     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1333         def = &builtin_x86_defs[i];
1334         if (strcmp(name, def->name) == 0) {
1335             memcpy(x86_cpu_def, def, sizeof(*def));
1336             /* sysenter isn't supported in compatibility mode on AMD,
1337              * syscall isn't supported in compatibility mode on Intel.
1338              * Normally we advertise the actual CPU vendor, but you can
1339              * override this using the 'vendor' property if you want to use
1340              * KVM's sysenter/syscall emulation in compatibility mode and
1341              * when doing cross vendor migration
1342              */
1343             if (kvm_enabled()) {
1344                 uint32_t  ebx = 0, ecx = 0, edx = 0;
1345                 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1346                 x86_cpu_vendor_words2str(x86_cpu_def->vendor, ebx, edx, ecx);
1347             }
1348             return 0;
1349         }
1350     }
1351
1352     return -1;
1353 }
1354
1355 /* Convert all '_' in a feature string option name to '-', to make feature
1356  * name conform to QOM property naming rule, which uses '-' instead of '_'.
1357  */
1358 static inline void feat2prop(char *s)
1359 {
1360     while ((s = strchr(s, '_'))) {
1361         *s = '-';
1362     }
1363 }
1364
1365 /* Parse "+feature,-feature,feature=foo" CPU feature string
1366  */
1367 static void cpu_x86_parse_featurestr(X86CPU *cpu, char *features, Error **errp)
1368 {
1369     char *featurestr; /* Single 'key=value" string being parsed */
1370     /* Features to be added */
1371     FeatureWordArray plus_features = { 0 };
1372     /* Features to be removed */
1373     FeatureWordArray minus_features = { 0 };
1374     uint32_t numvalue;
1375     CPUX86State *env = &cpu->env;
1376
1377     featurestr = features ? strtok(features, ",") : NULL;
1378
1379     while (featurestr) {
1380         char *val;
1381         if (featurestr[0] == '+') {
1382             add_flagname_to_bitmaps(featurestr + 1, plus_features);
1383         } else if (featurestr[0] == '-') {
1384             add_flagname_to_bitmaps(featurestr + 1, minus_features);
1385         } else if ((val = strchr(featurestr, '='))) {
1386             *val = 0; val++;
1387             feat2prop(featurestr);
1388             if (!strcmp(featurestr, "family")) {
1389                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1390             } else if (!strcmp(featurestr, "model")) {
1391                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1392             } else if (!strcmp(featurestr, "stepping")) {
1393                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1394             } else if (!strcmp(featurestr, "level")) {
1395                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1396             } else if (!strcmp(featurestr, "xlevel")) {
1397                 char *err;
1398                 char num[32];
1399
1400                 numvalue = strtoul(val, &err, 0);
1401                 if (!*val || *err) {
1402                     error_setg(errp, "bad numerical value %s", val);
1403                     goto out;
1404                 }
1405                 if (numvalue < 0x80000000) {
1406                     fprintf(stderr, "xlevel value shall always be >= 0x80000000"
1407                             ", fixup will be removed in future versions\n");
1408                     numvalue += 0x80000000;
1409                 }
1410                 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1411                 object_property_parse(OBJECT(cpu), num, featurestr, errp);
1412             } else if (!strcmp(featurestr, "vendor")) {
1413                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1414             } else if (!strcmp(featurestr, "model-id")) {
1415                 object_property_parse(OBJECT(cpu), val, featurestr, errp);
1416             } else if (!strcmp(featurestr, "tsc-freq")) {
1417                 int64_t tsc_freq;
1418                 char *err;
1419                 char num[32];
1420
1421                 tsc_freq = strtosz_suffix_unit(val, &err,
1422                                                STRTOSZ_DEFSUFFIX_B, 1000);
1423                 if (tsc_freq < 0 || *err) {
1424                     error_setg(errp, "bad numerical value %s", val);
1425                     goto out;
1426                 }
1427                 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1428                 object_property_parse(OBJECT(cpu), num, "tsc-frequency", errp);
1429             } else if (!strcmp(featurestr, "hv-spinlocks")) {
1430                 char *err;
1431                 numvalue = strtoul(val, &err, 0);
1432                 if (!*val || *err) {
1433                     error_setg(errp, "bad numerical value %s", val);
1434                     goto out;
1435                 }
1436                 hyperv_set_spinlock_retries(numvalue);
1437             } else {
1438                 error_setg(errp, "unrecognized feature %s", featurestr);
1439                 goto out;
1440             }
1441         } else if (!strcmp(featurestr, "check")) {
1442             check_cpuid = 1;
1443         } else if (!strcmp(featurestr, "enforce")) {
1444             check_cpuid = enforce_cpuid = 1;
1445         } else if (!strcmp(featurestr, "hv_relaxed")) {
1446             hyperv_enable_relaxed_timing(true);
1447         } else if (!strcmp(featurestr, "hv_vapic")) {
1448             hyperv_enable_vapic_recommended(true);
1449         } else {
1450             error_setg(errp, "feature string `%s' not in format (+feature|"
1451                        "-feature|feature=xyz)", featurestr);
1452             goto out;
1453         }
1454         if (error_is_set(errp)) {
1455             goto out;
1456         }
1457         featurestr = strtok(NULL, ",");
1458     }
1459     env->cpuid_features |= plus_features[FEAT_1_EDX];
1460     env->cpuid_ext_features |= plus_features[FEAT_1_ECX];
1461     env->cpuid_ext2_features |= plus_features[FEAT_8000_0001_EDX];
1462     env->cpuid_ext3_features |= plus_features[FEAT_8000_0001_ECX];
1463     env->cpuid_ext4_features |= plus_features[FEAT_C000_0001_EDX];
1464     env->cpuid_kvm_features |= plus_features[FEAT_KVM];
1465     env->cpuid_svm_features |= plus_features[FEAT_SVM];
1466     env->cpuid_7_0_ebx_features |= plus_features[FEAT_7_0_EBX];
1467     env->cpuid_features &= ~minus_features[FEAT_1_EDX];
1468     env->cpuid_ext_features &= ~minus_features[FEAT_1_ECX];
1469     env->cpuid_ext2_features &= ~minus_features[FEAT_8000_0001_EDX];
1470     env->cpuid_ext3_features &= ~minus_features[FEAT_8000_0001_ECX];
1471     env->cpuid_ext4_features &= ~minus_features[FEAT_C000_0001_EDX];
1472     env->cpuid_kvm_features &= ~minus_features[FEAT_KVM];
1473     env->cpuid_svm_features &= ~minus_features[FEAT_SVM];
1474     env->cpuid_7_0_ebx_features &= ~minus_features[FEAT_7_0_EBX];
1475
1476 out:
1477     return;
1478 }
1479
1480 /* generate a composite string into buf of all cpuid names in featureset
1481  * selected by fbits.  indicate truncation at bufsize in the event of overflow.
1482  * if flags, suppress names undefined in featureset.
1483  */
1484 static void listflags(char *buf, int bufsize, uint32_t fbits,
1485     const char **featureset, uint32_t flags)
1486 {
1487     const char **p = &featureset[31];
1488     char *q, *b, bit;
1489     int nc;
1490
1491     b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1492     *buf = '\0';
1493     for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1494         if (fbits & 1 << bit && (*p || !flags)) {
1495             if (*p)
1496                 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1497             else
1498                 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1499             if (bufsize <= nc) {
1500                 if (b) {
1501                     memcpy(b, "...", sizeof("..."));
1502                 }
1503                 return;
1504             }
1505             q += nc;
1506             bufsize -= nc;
1507         }
1508 }
1509
1510 /* generate CPU information. */
1511 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1512 {
1513     x86_def_t *def;
1514     char buf[256];
1515     int i;
1516
1517     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1518         def = &builtin_x86_defs[i];
1519         snprintf(buf, sizeof(buf), "%s", def->name);
1520         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1521     }
1522 #ifdef CONFIG_KVM
1523     (*cpu_fprintf)(f, "x86 %16s  %-48s\n", "host",
1524                    "KVM processor with all supported host features "
1525                    "(only available in KVM mode)");
1526 #endif
1527
1528     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1529     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1530         FeatureWordInfo *fw = &feature_word_info[i];
1531
1532         listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1533         (*cpu_fprintf)(f, "  %s\n", buf);
1534     }
1535 }
1536
1537 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1538 {
1539     CpuDefinitionInfoList *cpu_list = NULL;
1540     x86_def_t *def;
1541     int i;
1542
1543     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1544         CpuDefinitionInfoList *entry;
1545         CpuDefinitionInfo *info;
1546
1547         def = &builtin_x86_defs[i];
1548         info = g_malloc0(sizeof(*info));
1549         info->name = g_strdup(def->name);
1550
1551         entry = g_malloc0(sizeof(*entry));
1552         entry->value = info;
1553         entry->next = cpu_list;
1554         cpu_list = entry;
1555     }
1556
1557     return cpu_list;
1558 }
1559
1560 #ifdef CONFIG_KVM
1561 static void filter_features_for_kvm(X86CPU *cpu)
1562 {
1563     CPUX86State *env = &cpu->env;
1564     KVMState *s = kvm_state;
1565
1566     env->cpuid_features &=
1567         kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
1568     env->cpuid_ext_features &=
1569         kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX);
1570     env->cpuid_ext2_features &=
1571         kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX);
1572     env->cpuid_ext3_features &=
1573         kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX);
1574     env->cpuid_svm_features  &=
1575         kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX);
1576     env->cpuid_7_0_ebx_features &=
1577         kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX);
1578     env->cpuid_kvm_features &=
1579         kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX);
1580     env->cpuid_ext4_features &=
1581         kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX);
1582
1583 }
1584 #endif
1585
1586 static void cpu_x86_register(X86CPU *cpu, const char *name, Error **errp)
1587 {
1588     CPUX86State *env = &cpu->env;
1589     x86_def_t def1, *def = &def1;
1590
1591     memset(def, 0, sizeof(*def));
1592
1593     if (cpu_x86_find_by_name(def, name) < 0) {
1594         error_setg(errp, "Unable to find CPU definition: %s", name);
1595         return;
1596     }
1597
1598     if (kvm_enabled()) {
1599         def->kvm_features |= kvm_default_features;
1600     }
1601     def->ext_features |= CPUID_EXT_HYPERVISOR;
1602
1603     object_property_set_str(OBJECT(cpu), def->vendor, "vendor", errp);
1604     object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1605     object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1606     object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1607     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1608     env->cpuid_features = def->features;
1609     env->cpuid_ext_features = def->ext_features;
1610     env->cpuid_ext2_features = def->ext2_features;
1611     env->cpuid_ext3_features = def->ext3_features;
1612     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1613     env->cpuid_kvm_features = def->kvm_features;
1614     env->cpuid_svm_features = def->svm_features;
1615     env->cpuid_ext4_features = def->ext4_features;
1616     env->cpuid_7_0_ebx_features = def->cpuid_7_0_ebx_features;
1617     env->cpuid_xlevel2 = def->xlevel2;
1618
1619     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1620 }
1621
1622 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1623                        Error **errp)
1624 {
1625     X86CPU *cpu = NULL;
1626     CPUX86State *env;
1627     gchar **model_pieces;
1628     char *name, *features;
1629     Error *error = NULL;
1630
1631     model_pieces = g_strsplit(cpu_model, ",", 2);
1632     if (!model_pieces[0]) {
1633         error_setg(&error, "Invalid/empty CPU model name");
1634         goto out;
1635     }
1636     name = model_pieces[0];
1637     features = model_pieces[1];
1638
1639     cpu = X86_CPU(object_new(TYPE_X86_CPU));
1640 #ifndef CONFIG_USER_ONLY
1641     if (icc_bridge == NULL) {
1642         error_setg(&error, "Invalid icc-bridge value");
1643         goto out;
1644     }
1645     qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1646     object_unref(OBJECT(cpu));
1647 #endif
1648     env = &cpu->env;
1649     env->cpu_model_str = cpu_model;
1650
1651     cpu_x86_register(cpu, name, &error);
1652     if (error) {
1653         goto out;
1654     }
1655
1656     cpu_x86_parse_featurestr(cpu, features, &error);
1657     if (error) {
1658         goto out;
1659     }
1660
1661 out:
1662     error_propagate(errp, error);
1663     g_strfreev(model_pieces);
1664     return cpu;
1665 }
1666
1667 X86CPU *cpu_x86_init(const char *cpu_model)
1668 {
1669     Error *error = NULL;
1670     X86CPU *cpu;
1671
1672     cpu = cpu_x86_create(cpu_model, NULL, &error);
1673     if (error) {
1674         goto out;
1675     }
1676
1677     object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1678
1679 out:
1680     if (error) {
1681         fprintf(stderr, "%s\n", error_get_pretty(error));
1682         error_free(error);
1683         if (cpu != NULL) {
1684             object_unref(OBJECT(cpu));
1685             cpu = NULL;
1686         }
1687     }
1688     return cpu;
1689 }
1690
1691 #if !defined(CONFIG_USER_ONLY)
1692
1693 void cpu_clear_apic_feature(CPUX86State *env)
1694 {
1695     env->cpuid_features &= ~CPUID_APIC;
1696 }
1697
1698 #endif /* !CONFIG_USER_ONLY */
1699
1700 /* Initialize list of CPU models, filling some non-static fields if necessary
1701  */
1702 void x86_cpudef_setup(void)
1703 {
1704     int i, j;
1705     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
1706
1707     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1708         x86_def_t *def = &builtin_x86_defs[i];
1709
1710         /* Look for specific "cpudef" models that */
1711         /* have the QEMU version in .model_id */
1712         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1713             if (strcmp(model_with_versions[j], def->name) == 0) {
1714                 pstrcpy(def->model_id, sizeof(def->model_id),
1715                         "QEMU Virtual CPU version ");
1716                 pstrcat(def->model_id, sizeof(def->model_id),
1717                         qemu_get_version());
1718                 break;
1719             }
1720         }
1721     }
1722 }
1723
1724 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1725                              uint32_t *ecx, uint32_t *edx)
1726 {
1727     *ebx = env->cpuid_vendor1;
1728     *edx = env->cpuid_vendor2;
1729     *ecx = env->cpuid_vendor3;
1730 }
1731
1732 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1733                    uint32_t *eax, uint32_t *ebx,
1734                    uint32_t *ecx, uint32_t *edx)
1735 {
1736     X86CPU *cpu = x86_env_get_cpu(env);
1737     CPUState *cs = CPU(cpu);
1738
1739     /* test if maximum index reached */
1740     if (index & 0x80000000) {
1741         if (index > env->cpuid_xlevel) {
1742             if (env->cpuid_xlevel2 > 0) {
1743                 /* Handle the Centaur's CPUID instruction. */
1744                 if (index > env->cpuid_xlevel2) {
1745                     index = env->cpuid_xlevel2;
1746                 } else if (index < 0xC0000000) {
1747                     index = env->cpuid_xlevel;
1748                 }
1749             } else {
1750                 /* Intel documentation states that invalid EAX input will
1751                  * return the same information as EAX=cpuid_level
1752                  * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
1753                  */
1754                 index =  env->cpuid_level;
1755             }
1756         }
1757     } else {
1758         if (index > env->cpuid_level)
1759             index = env->cpuid_level;
1760     }
1761
1762     switch(index) {
1763     case 0:
1764         *eax = env->cpuid_level;
1765         get_cpuid_vendor(env, ebx, ecx, edx);
1766         break;
1767     case 1:
1768         *eax = env->cpuid_version;
1769         *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1770         *ecx = env->cpuid_ext_features;
1771         *edx = env->cpuid_features;
1772         if (cs->nr_cores * cs->nr_threads > 1) {
1773             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
1774             *edx |= 1 << 28;    /* HTT bit */
1775         }
1776         break;
1777     case 2:
1778         /* cache info: needed for Pentium Pro compatibility */
1779         *eax = 1;
1780         *ebx = 0;
1781         *ecx = 0;
1782         *edx = 0x2c307d;
1783         break;
1784     case 4:
1785         /* cache info: needed for Core compatibility */
1786         if (cs->nr_cores > 1) {
1787             *eax = (cs->nr_cores - 1) << 26;
1788         } else {
1789             *eax = 0;
1790         }
1791         switch (count) {
1792             case 0: /* L1 dcache info */
1793                 *eax |= 0x0000121;
1794                 *ebx = 0x1c0003f;
1795                 *ecx = 0x000003f;
1796                 *edx = 0x0000001;
1797                 break;
1798             case 1: /* L1 icache info */
1799                 *eax |= 0x0000122;
1800                 *ebx = 0x1c0003f;
1801                 *ecx = 0x000003f;
1802                 *edx = 0x0000001;
1803                 break;
1804             case 2: /* L2 cache info */
1805                 *eax |= 0x0000143;
1806                 if (cs->nr_threads > 1) {
1807                     *eax |= (cs->nr_threads - 1) << 14;
1808                 }
1809                 *ebx = 0x3c0003f;
1810                 *ecx = 0x0000fff;
1811                 *edx = 0x0000001;
1812                 break;
1813             default: /* end of info */
1814                 *eax = 0;
1815                 *ebx = 0;
1816                 *ecx = 0;
1817                 *edx = 0;
1818                 break;
1819         }
1820         break;
1821     case 5:
1822         /* mwait info: needed for Core compatibility */
1823         *eax = 0; /* Smallest monitor-line size in bytes */
1824         *ebx = 0; /* Largest monitor-line size in bytes */
1825         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1826         *edx = 0;
1827         break;
1828     case 6:
1829         /* Thermal and Power Leaf */
1830         *eax = 0;
1831         *ebx = 0;
1832         *ecx = 0;
1833         *edx = 0;
1834         break;
1835     case 7:
1836         /* Structured Extended Feature Flags Enumeration Leaf */
1837         if (count == 0) {
1838             *eax = 0; /* Maximum ECX value for sub-leaves */
1839             *ebx = env->cpuid_7_0_ebx_features; /* Feature flags */
1840             *ecx = 0; /* Reserved */
1841             *edx = 0; /* Reserved */
1842         } else {
1843             *eax = 0;
1844             *ebx = 0;
1845             *ecx = 0;
1846             *edx = 0;
1847         }
1848         break;
1849     case 9:
1850         /* Direct Cache Access Information Leaf */
1851         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1852         *ebx = 0;
1853         *ecx = 0;
1854         *edx = 0;
1855         break;
1856     case 0xA:
1857         /* Architectural Performance Monitoring Leaf */
1858         if (kvm_enabled()) {
1859             KVMState *s = cs->kvm_state;
1860
1861             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1862             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1863             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1864             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1865         } else {
1866             *eax = 0;
1867             *ebx = 0;
1868             *ecx = 0;
1869             *edx = 0;
1870         }
1871         break;
1872     case 0xD:
1873         /* Processor Extended State */
1874         if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1875             *eax = 0;
1876             *ebx = 0;
1877             *ecx = 0;
1878             *edx = 0;
1879             break;
1880         }
1881         if (kvm_enabled()) {
1882             KVMState *s = cs->kvm_state;
1883
1884             *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1885             *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1886             *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1887             *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
1888         } else {
1889             *eax = 0;
1890             *ebx = 0;
1891             *ecx = 0;
1892             *edx = 0;
1893         }
1894         break;
1895     case 0x80000000:
1896         *eax = env->cpuid_xlevel;
1897         *ebx = env->cpuid_vendor1;
1898         *edx = env->cpuid_vendor2;
1899         *ecx = env->cpuid_vendor3;
1900         break;
1901     case 0x80000001:
1902         *eax = env->cpuid_version;
1903         *ebx = 0;
1904         *ecx = env->cpuid_ext3_features;
1905         *edx = env->cpuid_ext2_features;
1906
1907         /* The Linux kernel checks for the CMPLegacy bit and
1908          * discards multiple thread information if it is set.
1909          * So dont set it here for Intel to make Linux guests happy.
1910          */
1911         if (cs->nr_cores * cs->nr_threads > 1) {
1912             uint32_t tebx, tecx, tedx;
1913             get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1914             if (tebx != CPUID_VENDOR_INTEL_1 ||
1915                 tedx != CPUID_VENDOR_INTEL_2 ||
1916                 tecx != CPUID_VENDOR_INTEL_3) {
1917                 *ecx |= 1 << 1;    /* CmpLegacy bit */
1918             }
1919         }
1920         break;
1921     case 0x80000002:
1922     case 0x80000003:
1923     case 0x80000004:
1924         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1925         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1926         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1927         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1928         break;
1929     case 0x80000005:
1930         /* cache info (L1 cache) */
1931         *eax = 0x01ff01ff;
1932         *ebx = 0x01ff01ff;
1933         *ecx = 0x40020140;
1934         *edx = 0x40020140;
1935         break;
1936     case 0x80000006:
1937         /* cache info (L2 cache) */
1938         *eax = 0;
1939         *ebx = 0x42004200;
1940         *ecx = 0x02008140;
1941         *edx = 0;
1942         break;
1943     case 0x80000008:
1944         /* virtual & phys address size in low 2 bytes. */
1945 /* XXX: This value must match the one used in the MMU code. */
1946         if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1947             /* 64 bit processor */
1948 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1949             *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1950         } else {
1951             if (env->cpuid_features & CPUID_PSE36) {
1952                 *eax = 0x00000024; /* 36 bits physical */
1953             } else {
1954                 *eax = 0x00000020; /* 32 bits physical */
1955             }
1956         }
1957         *ebx = 0;
1958         *ecx = 0;
1959         *edx = 0;
1960         if (cs->nr_cores * cs->nr_threads > 1) {
1961             *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
1962         }
1963         break;
1964     case 0x8000000A:
1965         if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1966             *eax = 0x00000001; /* SVM Revision */
1967             *ebx = 0x00000010; /* nr of ASIDs */
1968             *ecx = 0;
1969             *edx = env->cpuid_svm_features; /* optional features */
1970         } else {
1971             *eax = 0;
1972             *ebx = 0;
1973             *ecx = 0;
1974             *edx = 0;
1975         }
1976         break;
1977     case 0xC0000000:
1978         *eax = env->cpuid_xlevel2;
1979         *ebx = 0;
1980         *ecx = 0;
1981         *edx = 0;
1982         break;
1983     case 0xC0000001:
1984         /* Support for VIA CPU's CPUID instruction */
1985         *eax = env->cpuid_version;
1986         *ebx = 0;
1987         *ecx = 0;
1988         *edx = env->cpuid_ext4_features;
1989         break;
1990     case 0xC0000002:
1991     case 0xC0000003:
1992     case 0xC0000004:
1993         /* Reserved for the future, and now filled with zero */
1994         *eax = 0;
1995         *ebx = 0;
1996         *ecx = 0;
1997         *edx = 0;
1998         break;
1999     default:
2000         /* reserved values: zero */
2001         *eax = 0;
2002         *ebx = 0;
2003         *ecx = 0;
2004         *edx = 0;
2005         break;
2006     }
2007 }
2008
2009 /* CPUClass::reset() */
2010 static void x86_cpu_reset(CPUState *s)
2011 {
2012     X86CPU *cpu = X86_CPU(s);
2013     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2014     CPUX86State *env = &cpu->env;
2015     int i;
2016
2017     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
2018         qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
2019         log_cpu_state(env, CPU_DUMP_FPU | CPU_DUMP_CCOP);
2020     }
2021
2022     xcc->parent_reset(s);
2023
2024
2025     memset(env, 0, offsetof(CPUX86State, breakpoints));
2026
2027     tlb_flush(env, 1);
2028
2029     env->old_exception = -1;
2030
2031     /* init to reset state */
2032
2033 #ifdef CONFIG_SOFTMMU
2034     env->hflags |= HF_SOFTMMU_MASK;
2035 #endif
2036     env->hflags2 |= HF2_GIF_MASK;
2037
2038     cpu_x86_update_cr0(env, 0x60000010);
2039     env->a20_mask = ~0x0;
2040     env->smbase = 0x30000;
2041
2042     env->idt.limit = 0xffff;
2043     env->gdt.limit = 0xffff;
2044     env->ldt.limit = 0xffff;
2045     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2046     env->tr.limit = 0xffff;
2047     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2048
2049     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2050                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2051                            DESC_R_MASK | DESC_A_MASK);
2052     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2053                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2054                            DESC_A_MASK);
2055     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2056                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2057                            DESC_A_MASK);
2058     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2059                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2060                            DESC_A_MASK);
2061     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2062                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2063                            DESC_A_MASK);
2064     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2065                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2066                            DESC_A_MASK);
2067
2068     env->eip = 0xfff0;
2069     env->regs[R_EDX] = env->cpuid_version;
2070
2071     env->eflags = 0x2;
2072
2073     /* FPU init */
2074     for (i = 0; i < 8; i++) {
2075         env->fptags[i] = 1;
2076     }
2077     env->fpuc = 0x37f;
2078
2079     env->mxcsr = 0x1f80;
2080
2081     env->pat = 0x0007040600070406ULL;
2082     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2083
2084     memset(env->dr, 0, sizeof(env->dr));
2085     env->dr[6] = DR6_FIXED_1;
2086     env->dr[7] = DR7_FIXED_1;
2087     cpu_breakpoint_remove_all(env, BP_CPU);
2088     cpu_watchpoint_remove_all(env, BP_CPU);
2089
2090 #if !defined(CONFIG_USER_ONLY)
2091     /* We hard-wire the BSP to the first CPU. */
2092     if (s->cpu_index == 0) {
2093         apic_designate_bsp(env->apic_state);
2094     }
2095
2096     s->halted = !cpu_is_bsp(cpu);
2097 #endif
2098 }
2099
2100 #ifndef CONFIG_USER_ONLY
2101 bool cpu_is_bsp(X86CPU *cpu)
2102 {
2103     return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
2104 }
2105
2106 /* TODO: remove me, when reset over QOM tree is implemented */
2107 static void x86_cpu_machine_reset_cb(void *opaque)
2108 {
2109     X86CPU *cpu = opaque;
2110     cpu_reset(CPU(cpu));
2111 }
2112 #endif
2113
2114 static void mce_init(X86CPU *cpu)
2115 {
2116     CPUX86State *cenv = &cpu->env;
2117     unsigned int bank;
2118
2119     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2120         && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
2121             (CPUID_MCE | CPUID_MCA)) {
2122         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2123         cenv->mcg_ctl = ~(uint64_t)0;
2124         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2125             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2126         }
2127     }
2128 }
2129
2130 #ifndef CONFIG_USER_ONLY
2131 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2132 {
2133     CPUX86State *env = &cpu->env;
2134     DeviceState *dev = DEVICE(cpu);
2135     APICCommonState *apic;
2136     const char *apic_type = "apic";
2137
2138     if (kvm_irqchip_in_kernel()) {
2139         apic_type = "kvm-apic";
2140     } else if (xen_enabled()) {
2141         apic_type = "xen-apic";
2142     }
2143
2144     env->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2145     if (env->apic_state == NULL) {
2146         error_setg(errp, "APIC device '%s' could not be created", apic_type);
2147         return;
2148     }
2149
2150     object_property_add_child(OBJECT(cpu), "apic",
2151                               OBJECT(env->apic_state), NULL);
2152     qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
2153     /* TODO: convert to link<> */
2154     apic = APIC_COMMON(env->apic_state);
2155     apic->cpu = cpu;
2156 }
2157
2158 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2159 {
2160     CPUX86State *env = &cpu->env;
2161
2162     if (env->apic_state == NULL) {
2163         return;
2164     }
2165
2166     if (qdev_init(env->apic_state)) {
2167         error_setg(errp, "APIC device '%s' could not be initialized",
2168                    object_get_typename(OBJECT(env->apic_state)));
2169         return;
2170     }
2171 }
2172 #else
2173 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2174 {
2175 }
2176 #endif
2177
2178 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2179 {
2180     X86CPU *cpu = X86_CPU(dev);
2181     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2182     CPUX86State *env = &cpu->env;
2183     Error *local_err = NULL;
2184
2185     if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
2186         env->cpuid_level = 7;
2187     }
2188
2189     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2190      * CPUID[1].EDX.
2191      */
2192     if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2193         env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2194         env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2195         env->cpuid_ext2_features &= ~CPUID_EXT2_AMD_ALIASES;
2196         env->cpuid_ext2_features |= (env->cpuid_features
2197            & CPUID_EXT2_AMD_ALIASES);
2198     }
2199
2200     if (!kvm_enabled()) {
2201         env->cpuid_features &= TCG_FEATURES;
2202         env->cpuid_ext_features &= TCG_EXT_FEATURES;
2203         env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
2204 #ifdef TARGET_X86_64
2205             | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2206 #endif
2207             );
2208         env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
2209         env->cpuid_svm_features &= TCG_SVM_FEATURES;
2210     } else {
2211         if (check_cpuid && kvm_check_features_against_host(cpu)
2212             && enforce_cpuid) {
2213             error_setg(&local_err,
2214                        "Host's CPU doesn't support requested features");
2215             goto out;
2216         }
2217 #ifdef CONFIG_KVM
2218         filter_features_for_kvm(cpu);
2219 #endif
2220     }
2221
2222 #ifndef CONFIG_USER_ONLY
2223     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2224
2225     if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
2226         x86_cpu_apic_create(cpu, &local_err);
2227         if (local_err != NULL) {
2228             goto out;
2229         }
2230     }
2231 #endif
2232
2233     mce_init(cpu);
2234     qemu_init_vcpu(&cpu->env);
2235
2236     x86_cpu_apic_realize(cpu, &local_err);
2237     if (local_err != NULL) {
2238         goto out;
2239     }
2240     cpu_reset(CPU(cpu));
2241
2242     xcc->parent_realize(dev, &local_err);
2243 out:
2244     if (local_err != NULL) {
2245         error_propagate(errp, local_err);
2246         return;
2247     }
2248 }
2249
2250 /* Enables contiguous-apic-ID mode, for compatibility */
2251 static bool compat_apic_id_mode;
2252
2253 void enable_compat_apic_id_mode(void)
2254 {
2255     compat_apic_id_mode = true;
2256 }
2257
2258 /* Calculates initial APIC ID for a specific CPU index
2259  *
2260  * Currently we need to be able to calculate the APIC ID from the CPU index
2261  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2262  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2263  * all CPUs up to max_cpus.
2264  */
2265 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2266 {
2267     uint32_t correct_id;
2268     static bool warned;
2269
2270     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2271     if (compat_apic_id_mode) {
2272         if (cpu_index != correct_id && !warned) {
2273             error_report("APIC IDs set in compatibility mode, "
2274                          "CPU topology won't match the configuration");
2275             warned = true;
2276         }
2277         return cpu_index;
2278     } else {
2279         return correct_id;
2280     }
2281 }
2282
2283 static void x86_cpu_initfn(Object *obj)
2284 {
2285     CPUState *cs = CPU(obj);
2286     X86CPU *cpu = X86_CPU(obj);
2287     CPUX86State *env = &cpu->env;
2288     static int inited;
2289
2290     cs->env_ptr = env;
2291     cpu_exec_init(env);
2292
2293     object_property_add(obj, "family", "int",
2294                         x86_cpuid_version_get_family,
2295                         x86_cpuid_version_set_family, NULL, NULL, NULL);
2296     object_property_add(obj, "model", "int",
2297                         x86_cpuid_version_get_model,
2298                         x86_cpuid_version_set_model, NULL, NULL, NULL);
2299     object_property_add(obj, "stepping", "int",
2300                         x86_cpuid_version_get_stepping,
2301                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2302     object_property_add(obj, "level", "int",
2303                         x86_cpuid_get_level,
2304                         x86_cpuid_set_level, NULL, NULL, NULL);
2305     object_property_add(obj, "xlevel", "int",
2306                         x86_cpuid_get_xlevel,
2307                         x86_cpuid_set_xlevel, NULL, NULL, NULL);
2308     object_property_add_str(obj, "vendor",
2309                             x86_cpuid_get_vendor,
2310                             x86_cpuid_set_vendor, NULL);
2311     object_property_add_str(obj, "model-id",
2312                             x86_cpuid_get_model_id,
2313                             x86_cpuid_set_model_id, NULL);
2314     object_property_add(obj, "tsc-frequency", "int",
2315                         x86_cpuid_get_tsc_freq,
2316                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2317     object_property_add(obj, "apic-id", "int",
2318                         x86_cpuid_get_apic_id,
2319                         x86_cpuid_set_apic_id, NULL, NULL, NULL);
2320
2321     env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2322
2323     /* init various static tables used in TCG mode */
2324     if (tcg_enabled() && !inited) {
2325         inited = 1;
2326         optimize_flags_init();
2327 #ifndef CONFIG_USER_ONLY
2328         cpu_set_debug_excp_handler(breakpoint_handler);
2329 #endif
2330     }
2331 }
2332
2333 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2334 {
2335     X86CPU *cpu = X86_CPU(cs);
2336     CPUX86State *env = &cpu->env;
2337
2338     return env->cpuid_apic_id;
2339 }
2340
2341 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2342 {
2343     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2344     CPUClass *cc = CPU_CLASS(oc);
2345     DeviceClass *dc = DEVICE_CLASS(oc);
2346
2347     xcc->parent_realize = dc->realize;
2348     dc->realize = x86_cpu_realizefn;
2349     dc->bus_type = TYPE_ICC_BUS;
2350
2351     xcc->parent_reset = cc->reset;
2352     cc->reset = x86_cpu_reset;
2353
2354     cc->do_interrupt = x86_cpu_do_interrupt;
2355 #ifndef CONFIG_USER_ONLY
2356     cc->write_elf64_note = x86_cpu_write_elf64_note;
2357     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2358     cc->write_elf32_note = x86_cpu_write_elf32_note;
2359     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2360 #endif
2361     cpu_class_set_vmsd(cc, &vmstate_x86_cpu);
2362
2363     cc->get_arch_id = x86_cpu_get_arch_id;
2364 }
2365
2366 static const TypeInfo x86_cpu_type_info = {
2367     .name = TYPE_X86_CPU,
2368     .parent = TYPE_CPU,
2369     .instance_size = sizeof(X86CPU),
2370     .instance_init = x86_cpu_initfn,
2371     .abstract = false,
2372     .class_size = sizeof(X86CPUClass),
2373     .class_init = x86_cpu_common_class_init,
2374 };
2375
2376 static void x86_cpu_register_types(void)
2377 {
2378     type_register_static(&x86_cpu_type_info);
2379 }
2380
2381 type_init(x86_cpu_register_types)