target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & ARM_CP_SPECIAL) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 112         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 115 #else
 116         env->pstate = PSTATE_MODE_EL1h;
 117         env->pc = cpu->rvbar;
 118 #endif
 119     } else {
 120 #if defined(CONFIG_USER_ONLY)
 121         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 122         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 123 #endif
 124     }
 125
 126 #if defined(CONFIG_USER_ONLY)
 127     env->uncached_cpsr = ARM_CPU_MODE_USR;
 128     /* For user mode we must enable access to coprocessors */
 129     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 130     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 131         env->cp15.c15_cpar = 3;
 132     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 133         env->cp15.c15_cpar = 1;
 134     }
 135 #else
 136     /* SVC mode with interrupts disabled.  */
 137     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 138     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 139     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 140      * clear at reset. Initial SP and PC are loaded from ROM.
 141      */
 142     if (IS_M(env)) {
 143         uint32_t initial_msp; /* Loaded from 0x0 */
 144         uint32_t initial_pc; /* Loaded from 0x4 */
 145         uint8_t *rom;
 146
 147         env->daif &= ~PSTATE_I;
 148         rom = rom_ptr(0);
 149         if (rom) {
 150             /* Address zero is covered by ROM which hasn't yet been
 151              * copied into physical memory.
 152              */
 153             initial_msp = ldl_p(rom);
 154             initial_pc = ldl_p(rom + 4);
 155         } else {
 156             /* Address zero not covered by a ROM blob, or the ROM blob
 157              * is in non-modifiable memory and this is a second reset after
 158              * it got copied into memory. In the latter case, rom_ptr
 159              * will return a NULL pointer and we should use ldl_phys instead.
 160              */
 161             initial_msp = ldl_phys(s->as, 0);
 162             initial_pc = ldl_phys(s->as, 4);
 163         }
 164
 165         env->regs[13] = initial_msp & 0xFFFFFFFC;
 166         env->regs[15] = initial_pc & ~1;
 167         env->thumb = initial_pc & 1;
 168     }
 169
 170     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 171      * executing as AArch32 then check if highvecs are enabled and
 172      * adjust the PC accordingly.
 173      */
 174     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 175         env->regs[15] = 0xFFFF0000;
 176     }
 177
 178     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 179 #endif
 180     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 181     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 182     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 183     set_float_detect_tininess(float_tininess_before_rounding,
 184                               &env->vfp.fp_status);
 185     set_float_detect_tininess(float_tininess_before_rounding,
 186                               &env->vfp.standard_fp_status);
 187     tlb_flush(s, 1);
 188
 189 #ifndef CONFIG_USER_ONLY
 190     if (kvm_enabled()) {
 191         kvm_arm_reset_vcpu(cpu);
 192     }
 193 #endif
 194
 195     hw_breakpoint_update_all(cpu);
 196     hw_watchpoint_update_all(cpu);
 197 }
 198
 199 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 200 {
 201     CPUClass *cc = CPU_GET_CLASS(cs);
 202     bool ret = false;
 203
 204     if (interrupt_request & CPU_INTERRUPT_FIQ
 205         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 206         cs->exception_index = EXCP_FIQ;
 207         cc->do_interrupt(cs);
 208         ret = true;
 209     }
 210     if (interrupt_request & CPU_INTERRUPT_HARD
 211         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 212         cs->exception_index = EXCP_IRQ;
 213         cc->do_interrupt(cs);
 214         ret = true;
 215     }
 216     if (interrupt_request & CPU_INTERRUPT_VIRQ
 217         && arm_excp_unmasked(cs, EXCP_VIRQ)) {
 218         cs->exception_index = EXCP_VIRQ;
 219         cc->do_interrupt(cs);
 220         ret = true;
 221     }
 222     if (interrupt_request & CPU_INTERRUPT_VFIQ
 223         && arm_excp_unmasked(cs, EXCP_VFIQ)) {
 224         cs->exception_index = EXCP_VFIQ;
 225         cc->do_interrupt(cs);
 226         ret = true;
 227     }
 228
 229     return ret;
 230 }
 231
 232 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 233 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 234 {
 235     CPUClass *cc = CPU_GET_CLASS(cs);
 236     ARMCPU *cpu = ARM_CPU(cs);
 237     CPUARMState *env = &cpu->env;
 238     bool ret = false;
 239
 240
 241     if (interrupt_request & CPU_INTERRUPT_FIQ
 242         && !(env->daif & PSTATE_F)) {
 243         cs->exception_index = EXCP_FIQ;
 244         cc->do_interrupt(cs);
 245         ret = true;
 246     }
 247     /* ARMv7-M interrupt return works by loading a magic value
 248      * into the PC.  On real hardware the load causes the
 249      * return to occur.  The qemu implementation performs the
 250      * jump normally, then does the exception return when the
 251      * CPU tries to execute code at the magic address.
 252      * This will cause the magic PC value to be pushed to
 253      * the stack if an interrupt occurred at the wrong time.
 254      * We avoid this by disabling interrupts when
 255      * pc contains a magic address.
 256      */
 257     if (interrupt_request & CPU_INTERRUPT_HARD
 258         && !(env->daif & PSTATE_I)
 259         && (env->regs[15] < 0xfffffff0)) {
 260         cs->exception_index = EXCP_IRQ;
 261         cc->do_interrupt(cs);
 262         ret = true;
 263     }
 264     return ret;
 265 }
 266 #endif
 267
 268 #ifndef CONFIG_USER_ONLY
 269 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 270 {
 271     ARMCPU *cpu = opaque;
 272     CPUARMState *env = &cpu->env;
 273     CPUState *cs = CPU(cpu);
 274     static const int mask[] = {
 275         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 276         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 277         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 278         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 279     };
 280
 281     switch (irq) {
 282     case ARM_CPU_VIRQ:
 283     case ARM_CPU_VFIQ:
 284         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 285             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 286                      __func__, irq);
 287         }
 288         /* fall through */
 289     case ARM_CPU_IRQ:
 290     case ARM_CPU_FIQ:
 291         if (level) {
 292             cpu_interrupt(cs, mask[irq]);
 293         } else {
 294             cpu_reset_interrupt(cs, mask[irq]);
 295         }
 296         break;
 297     default:
 298         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 299     }
 300 }
 301
 302 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 303 {
 304 #ifdef CONFIG_KVM
 305     ARMCPU *cpu = opaque;
 306     CPUState *cs = CPU(cpu);
 307     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 308
 309     switch (irq) {
 310     case ARM_CPU_IRQ:
 311         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 312         break;
 313     case ARM_CPU_FIQ:
 314         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 315         break;
 316     default:
 317         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 318     }
 319     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 320     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 321 #endif
 322 }
 323 #endif
 324
 325 static inline void set_feature(CPUARMState *env, int feature)
 326 {
 327     env->features |= 1ULL << feature;
 328 }
 329
 330 static inline void unset_feature(CPUARMState *env, int feature)
 331 {
 332     env->features &= ~(1ULL << feature);
 333 }
 334
 335 static void arm_cpu_initfn(Object *obj)
 336 {
 337     CPUState *cs = CPU(obj);
 338     ARMCPU *cpu = ARM_CPU(obj);
 339     static bool inited;
 340
 341     cs->env_ptr = &cpu->env;
 342     cpu_exec_init(&cpu->env);
 343     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 344                                          g_free, g_free);
 345
 346 #ifndef CONFIG_USER_ONLY
 347     /* Our inbound IRQ and FIQ lines */
 348     if (kvm_enabled()) {
 349         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 350          * the same interface as non-KVM CPUs.
 351          */
 352         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 353     } else {
 354         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 355     }
 356
 357     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 358                                                 arm_gt_ptimer_cb, cpu);
 359     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 360                                                 arm_gt_vtimer_cb, cpu);
 361     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 362                        ARRAY_SIZE(cpu->gt_timer_outputs));
 363 #endif
 364
 365     /* DTB consumers generally don't in fact care what the 'compatible'
 366      * string is, so always provide some string and trust that a hypothetical
 367      * picky DTB consumer will also provide a helpful error message.
 368      */
 369     cpu->dtb_compatible = "qemu,unknown";
 370     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 371     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 372
 373     if (tcg_enabled()) {
 374         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 375         if (!inited) {
 376             inited = true;
 377             arm_translate_init();
 378         }
 379     }
 380 }
 381
 382 static Property arm_cpu_reset_cbar_property =
 383             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 384
 385 static Property arm_cpu_reset_hivecs_property =
 386             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 387
 388 static Property arm_cpu_rvbar_property =
 389             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 390
 391 static Property arm_cpu_has_el3_property =
 392             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 393
 394 static void arm_cpu_post_init(Object *obj)
 395 {
 396     ARMCPU *cpu = ARM_CPU(obj);
 397
 398     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 399         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 400         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 401                                  &error_abort);
 402     }
 403
 404     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 405         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 406                                  &error_abort);
 407     }
 408
 409     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 410         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 411                                  &error_abort);
 412     }
 413
 414     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 415         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 416          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 417          */
 418         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 419                                  &error_abort);
 420     }
 421 }
 422
 423 static void arm_cpu_finalizefn(Object *obj)
 424 {
 425     ARMCPU *cpu = ARM_CPU(obj);
 426     g_hash_table_destroy(cpu->cp_regs);
 427 }
 428
 429 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 430 {
 431     CPUState *cs = CPU(dev);
 432     ARMCPU *cpu = ARM_CPU(dev);
 433     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 434     CPUARMState *env = &cpu->env;
 435
 436     /* Some features automatically imply others: */
 437     if (arm_feature(env, ARM_FEATURE_V8)) {
 438         set_feature(env, ARM_FEATURE_V7);
 439         set_feature(env, ARM_FEATURE_ARM_DIV);
 440         set_feature(env, ARM_FEATURE_LPAE);
 441     }
 442     if (arm_feature(env, ARM_FEATURE_V7)) {
 443         set_feature(env, ARM_FEATURE_VAPA);
 444         set_feature(env, ARM_FEATURE_THUMB2);
 445         set_feature(env, ARM_FEATURE_MPIDR);
 446         if (!arm_feature(env, ARM_FEATURE_M)) {
 447             set_feature(env, ARM_FEATURE_V6K);
 448         } else {
 449             set_feature(env, ARM_FEATURE_V6);
 450         }
 451     }
 452     if (arm_feature(env, ARM_FEATURE_V6K)) {
 453         set_feature(env, ARM_FEATURE_V6);
 454         set_feature(env, ARM_FEATURE_MVFR);
 455     }
 456     if (arm_feature(env, ARM_FEATURE_V6)) {
 457         set_feature(env, ARM_FEATURE_V5);
 458         if (!arm_feature(env, ARM_FEATURE_M)) {
 459             set_feature(env, ARM_FEATURE_AUXCR);
 460         }
 461     }
 462     if (arm_feature(env, ARM_FEATURE_V5)) {
 463         set_feature(env, ARM_FEATURE_V4T);
 464     }
 465     if (arm_feature(env, ARM_FEATURE_M)) {
 466         set_feature(env, ARM_FEATURE_THUMB_DIV);
 467     }
 468     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 469         set_feature(env, ARM_FEATURE_THUMB_DIV);
 470     }
 471     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 472         set_feature(env, ARM_FEATURE_VFP3);
 473         set_feature(env, ARM_FEATURE_VFP_FP16);
 474     }
 475     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 476         set_feature(env, ARM_FEATURE_VFP);
 477     }
 478     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 479         set_feature(env, ARM_FEATURE_V7MP);
 480         set_feature(env, ARM_FEATURE_PXN);
 481     }
 482     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 483         set_feature(env, ARM_FEATURE_CBAR);
 484     }
 485
 486     if (cpu->reset_hivecs) {
 487             cpu->reset_sctlr |= (1 << 13);
 488     }
 489
 490     if (!cpu->has_el3) {
 491         /* If the has_el3 CPU property is disabled then we need to disable the
 492          * feature.
 493          */
 494         unset_feature(env, ARM_FEATURE_EL3);
 495
 496         /* Disable the security extension feature bits in the processor feature
 497          * register as well.  This is id_pfr1[7:4].
 498          */
 499         cpu->id_pfr1 &= ~0xf0;
 500     }
 501
 502     register_cp_regs_for_features(cpu);
 503     arm_cpu_register_gdb_regs_for_features(cpu);
 504
 505     init_cpreg_list(cpu);
 506
 507     qemu_init_vcpu(cs);
 508     cpu_reset(cs);
 509
 510     acc->parent_realize(dev, errp);
 511 }
 512
 513 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 514 {
 515     ObjectClass *oc;
 516     char *typename;
 517
 518     if (!cpu_model) {
 519         return NULL;
 520     }
 521
 522     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 523     oc = object_class_by_name(typename);
 524     g_free(typename);
 525     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 526         object_class_is_abstract(oc)) {
 527         return NULL;
 528     }
 529     return oc;
 530 }
 531
 532 /* CPU models. These are not needed for the AArch64 linux-user build. */
 533 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 534
 535 static void arm926_initfn(Object *obj)
 536 {
 537     ARMCPU *cpu = ARM_CPU(obj);
 538
 539     cpu->dtb_compatible = "arm,arm926";
 540     set_feature(&cpu->env, ARM_FEATURE_V5);
 541     set_feature(&cpu->env, ARM_FEATURE_VFP);
 542     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 543     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 544     cpu->midr = 0x41069265;
 545     cpu->reset_fpsid = 0x41011090;
 546     cpu->ctr = 0x1dd20d2;
 547     cpu->reset_sctlr = 0x00090078;
 548 }
 549
 550 static void arm946_initfn(Object *obj)
 551 {
 552     ARMCPU *cpu = ARM_CPU(obj);
 553
 554     cpu->dtb_compatible = "arm,arm946";
 555     set_feature(&cpu->env, ARM_FEATURE_V5);
 556     set_feature(&cpu->env, ARM_FEATURE_MPU);
 557     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 558     cpu->midr = 0x41059461;
 559     cpu->ctr = 0x0f004006;
 560     cpu->reset_sctlr = 0x00000078;
 561 }
 562
 563 static void arm1026_initfn(Object *obj)
 564 {
 565     ARMCPU *cpu = ARM_CPU(obj);
 566
 567     cpu->dtb_compatible = "arm,arm1026";
 568     set_feature(&cpu->env, ARM_FEATURE_V5);
 569     set_feature(&cpu->env, ARM_FEATURE_VFP);
 570     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 571     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 572     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 573     cpu->midr = 0x4106a262;
 574     cpu->reset_fpsid = 0x410110a0;
 575     cpu->ctr = 0x1dd20d2;
 576     cpu->reset_sctlr = 0x00090078;
 577     cpu->reset_auxcr = 1;
 578     {
 579         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 580         ARMCPRegInfo ifar = {
 581             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 582             .access = PL1_RW,
 583             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 584             .resetvalue = 0
 585         };
 586         define_one_arm_cp_reg(cpu, &ifar);
 587     }
 588 }
 589
 590 static void arm1136_r2_initfn(Object *obj)
 591 {
 592     ARMCPU *cpu = ARM_CPU(obj);
 593     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 594      * older core than plain "arm1136". In particular this does not
 595      * have the v6K features.
 596      * These ID register values are correct for 1136 but may be wrong
 597      * for 1136_r2 (in particular r0p2 does not actually implement most
 598      * of the ID registers).
 599      */
 600
 601     cpu->dtb_compatible = "arm,arm1136";
 602     set_feature(&cpu->env, ARM_FEATURE_V6);
 603     set_feature(&cpu->env, ARM_FEATURE_VFP);
 604     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 605     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 606     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 607     cpu->midr = 0x4107b362;
 608     cpu->reset_fpsid = 0x410120b4;
 609     cpu->mvfr0 = 0x11111111;
 610     cpu->mvfr1 = 0x00000000;
 611     cpu->ctr = 0x1dd20d2;
 612     cpu->reset_sctlr = 0x00050078;
 613     cpu->id_pfr0 = 0x111;
 614     cpu->id_pfr1 = 0x1;
 615     cpu->id_dfr0 = 0x2;
 616     cpu->id_afr0 = 0x3;
 617     cpu->id_mmfr0 = 0x01130003;
 618     cpu->id_mmfr1 = 0x10030302;
 619     cpu->id_mmfr2 = 0x01222110;
 620     cpu->id_isar0 = 0x00140011;
 621     cpu->id_isar1 = 0x12002111;
 622     cpu->id_isar2 = 0x11231111;
 623     cpu->id_isar3 = 0x01102131;
 624     cpu->id_isar4 = 0x141;
 625     cpu->reset_auxcr = 7;
 626 }
 627
 628 static void arm1136_initfn(Object *obj)
 629 {
 630     ARMCPU *cpu = ARM_CPU(obj);
 631
 632     cpu->dtb_compatible = "arm,arm1136";
 633     set_feature(&cpu->env, ARM_FEATURE_V6K);
 634     set_feature(&cpu->env, ARM_FEATURE_V6);
 635     set_feature(&cpu->env, ARM_FEATURE_VFP);
 636     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 637     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 638     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 639     cpu->midr = 0x4117b363;
 640     cpu->reset_fpsid = 0x410120b4;
 641     cpu->mvfr0 = 0x11111111;
 642     cpu->mvfr1 = 0x00000000;
 643     cpu->ctr = 0x1dd20d2;
 644     cpu->reset_sctlr = 0x00050078;
 645     cpu->id_pfr0 = 0x111;
 646     cpu->id_pfr1 = 0x1;
 647     cpu->id_dfr0 = 0x2;
 648     cpu->id_afr0 = 0x3;
 649     cpu->id_mmfr0 = 0x01130003;
 650     cpu->id_mmfr1 = 0x10030302;
 651     cpu->id_mmfr2 = 0x01222110;
 652     cpu->id_isar0 = 0x00140011;
 653     cpu->id_isar1 = 0x12002111;
 654     cpu->id_isar2 = 0x11231111;
 655     cpu->id_isar3 = 0x01102131;
 656     cpu->id_isar4 = 0x141;
 657     cpu->reset_auxcr = 7;
 658 }
 659
 660 static void arm1176_initfn(Object *obj)
 661 {
 662     ARMCPU *cpu = ARM_CPU(obj);
 663
 664     cpu->dtb_compatible = "arm,arm1176";
 665     set_feature(&cpu->env, ARM_FEATURE_V6K);
 666     set_feature(&cpu->env, ARM_FEATURE_VFP);
 667     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 668     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 669     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 670     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 671     cpu->midr = 0x410fb767;
 672     cpu->reset_fpsid = 0x410120b5;
 673     cpu->mvfr0 = 0x11111111;
 674     cpu->mvfr1 = 0x00000000;
 675     cpu->ctr = 0x1dd20d2;
 676     cpu->reset_sctlr = 0x00050078;
 677     cpu->id_pfr0 = 0x111;
 678     cpu->id_pfr1 = 0x11;
 679     cpu->id_dfr0 = 0x33;
 680     cpu->id_afr0 = 0;
 681     cpu->id_mmfr0 = 0x01130003;
 682     cpu->id_mmfr1 = 0x10030302;
 683     cpu->id_mmfr2 = 0x01222100;
 684     cpu->id_isar0 = 0x0140011;
 685     cpu->id_isar1 = 0x12002111;
 686     cpu->id_isar2 = 0x11231121;
 687     cpu->id_isar3 = 0x01102131;
 688     cpu->id_isar4 = 0x01141;
 689     cpu->reset_auxcr = 7;
 690 }
 691
 692 static void arm11mpcore_initfn(Object *obj)
 693 {
 694     ARMCPU *cpu = ARM_CPU(obj);
 695
 696     cpu->dtb_compatible = "arm,arm11mpcore";
 697     set_feature(&cpu->env, ARM_FEATURE_V6K);
 698     set_feature(&cpu->env, ARM_FEATURE_VFP);
 699     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 700     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 701     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 702     cpu->midr = 0x410fb022;
 703     cpu->reset_fpsid = 0x410120b4;
 704     cpu->mvfr0 = 0x11111111;
 705     cpu->mvfr1 = 0x00000000;
 706     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 707     cpu->id_pfr0 = 0x111;
 708     cpu->id_pfr1 = 0x1;
 709     cpu->id_dfr0 = 0;
 710     cpu->id_afr0 = 0x2;
 711     cpu->id_mmfr0 = 0x01100103;
 712     cpu->id_mmfr1 = 0x10020302;
 713     cpu->id_mmfr2 = 0x01222000;
 714     cpu->id_isar0 = 0x00100011;
 715     cpu->id_isar1 = 0x12002111;
 716     cpu->id_isar2 = 0x11221011;
 717     cpu->id_isar3 = 0x01102131;
 718     cpu->id_isar4 = 0x141;
 719     cpu->reset_auxcr = 1;
 720 }
 721
 722 static void cortex_m3_initfn(Object *obj)
 723 {
 724     ARMCPU *cpu = ARM_CPU(obj);
 725     set_feature(&cpu->env, ARM_FEATURE_V7);
 726     set_feature(&cpu->env, ARM_FEATURE_M);
 727     cpu->midr = 0x410fc231;
 728 }
 729
 730 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 731 {
 732     CPUClass *cc = CPU_CLASS(oc);
 733
 734 #ifndef CONFIG_USER_ONLY
 735     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 736 #endif
 737
 738     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 739 }
 740
 741 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 742     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 743       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 744     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 745       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 746     REGINFO_SENTINEL
 747 };
 748
 749 static void cortex_a8_initfn(Object *obj)
 750 {
 751     ARMCPU *cpu = ARM_CPU(obj);
 752
 753     cpu->dtb_compatible = "arm,cortex-a8";
 754     set_feature(&cpu->env, ARM_FEATURE_V7);
 755     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 756     set_feature(&cpu->env, ARM_FEATURE_NEON);
 757     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 758     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 759     cpu->midr = 0x410fc080;
 760     cpu->reset_fpsid = 0x410330c0;
 761     cpu->mvfr0 = 0x11110222;
 762     cpu->mvfr1 = 0x00011100;
 763     cpu->ctr = 0x82048004;
 764     cpu->reset_sctlr = 0x00c50078;
 765     cpu->id_pfr0 = 0x1031;
 766     cpu->id_pfr1 = 0x11;
 767     cpu->id_dfr0 = 0x400;
 768     cpu->id_afr0 = 0;
 769     cpu->id_mmfr0 = 0x31100003;
 770     cpu->id_mmfr1 = 0x20000000;
 771     cpu->id_mmfr2 = 0x01202000;
 772     cpu->id_mmfr3 = 0x11;
 773     cpu->id_isar0 = 0x00101111;
 774     cpu->id_isar1 = 0x12112111;
 775     cpu->id_isar2 = 0x21232031;
 776     cpu->id_isar3 = 0x11112131;
 777     cpu->id_isar4 = 0x00111142;
 778     cpu->dbgdidr = 0x15141000;
 779     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 780     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 781     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 782     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 783     cpu->reset_auxcr = 2;
 784     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 785 }
 786
 787 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 788     /* power_control should be set to maximum latency. Again,
 789      * default to 0 and set by private hook
 790      */
 791     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 792       .access = PL1_RW, .resetvalue = 0,
 793       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 794     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 795       .access = PL1_RW, .resetvalue = 0,
 796       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 797     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 798       .access = PL1_RW, .resetvalue = 0,
 799       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 800     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 801       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 802     /* TLB lockdown control */
 803     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 804       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 805     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 806       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 807     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 808       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 809     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 810       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 811     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 812       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 813     REGINFO_SENTINEL
 814 };
 815
 816 static void cortex_a9_initfn(Object *obj)
 817 {
 818     ARMCPU *cpu = ARM_CPU(obj);
 819
 820     cpu->dtb_compatible = "arm,cortex-a9";
 821     set_feature(&cpu->env, ARM_FEATURE_V7);
 822     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 823     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 824     set_feature(&cpu->env, ARM_FEATURE_NEON);
 825     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 826     /* Note that A9 supports the MP extensions even for
 827      * A9UP and single-core A9MP (which are both different
 828      * and valid configurations; we don't model A9UP).
 829      */
 830     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 831     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 832     cpu->midr = 0x410fc090;
 833     cpu->reset_fpsid = 0x41033090;
 834     cpu->mvfr0 = 0x11110222;
 835     cpu->mvfr1 = 0x01111111;
 836     cpu->ctr = 0x80038003;
 837     cpu->reset_sctlr = 0x00c50078;
 838     cpu->id_pfr0 = 0x1031;
 839     cpu->id_pfr1 = 0x11;
 840     cpu->id_dfr0 = 0x000;
 841     cpu->id_afr0 = 0;
 842     cpu->id_mmfr0 = 0x00100103;
 843     cpu->id_mmfr1 = 0x20000000;
 844     cpu->id_mmfr2 = 0x01230000;
 845     cpu->id_mmfr3 = 0x00002111;
 846     cpu->id_isar0 = 0x00101111;
 847     cpu->id_isar1 = 0x13112111;
 848     cpu->id_isar2 = 0x21232041;
 849     cpu->id_isar3 = 0x11112131;
 850     cpu->id_isar4 = 0x00111142;
 851     cpu->dbgdidr = 0x35141000;
 852     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 853     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 854     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 855     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 856 }
 857
 858 #ifndef CONFIG_USER_ONLY
 859 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 860 {
 861     /* Linux wants the number of processors from here.
 862      * Might as well set the interrupt-controller bit too.
 863      */
 864     return ((smp_cpus - 1) << 24) | (1 << 23);
 865 }
 866 #endif
 867
 868 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 869 #ifndef CONFIG_USER_ONLY
 870     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 871       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 872       .writefn = arm_cp_write_ignore, },
 873 #endif
 874     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 875       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 876     REGINFO_SENTINEL
 877 };
 878
 879 static void cortex_a15_initfn(Object *obj)
 880 {
 881     ARMCPU *cpu = ARM_CPU(obj);
 882
 883     cpu->dtb_compatible = "arm,cortex-a15";
 884     set_feature(&cpu->env, ARM_FEATURE_V7);
 885     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 886     set_feature(&cpu->env, ARM_FEATURE_NEON);
 887     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 888     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 889     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 890     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 891     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 892     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 893     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 894     cpu->midr = 0x412fc0f1;
 895     cpu->reset_fpsid = 0x410430f0;
 896     cpu->mvfr0 = 0x10110222;
 897     cpu->mvfr1 = 0x11111111;
 898     cpu->ctr = 0x8444c004;
 899     cpu->reset_sctlr = 0x00c50078;
 900     cpu->id_pfr0 = 0x00001131;
 901     cpu->id_pfr1 = 0x00011011;
 902     cpu->id_dfr0 = 0x02010555;
 903     cpu->id_afr0 = 0x00000000;
 904     cpu->id_mmfr0 = 0x10201105;
 905     cpu->id_mmfr1 = 0x20000000;
 906     cpu->id_mmfr2 = 0x01240000;
 907     cpu->id_mmfr3 = 0x02102211;
 908     cpu->id_isar0 = 0x02101110;
 909     cpu->id_isar1 = 0x13112111;
 910     cpu->id_isar2 = 0x21232041;
 911     cpu->id_isar3 = 0x11112131;
 912     cpu->id_isar4 = 0x10011142;
 913     cpu->dbgdidr = 0x3515f021;
 914     cpu->clidr = 0x0a200023;
 915     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 916     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 917     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 918     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 919 }
 920
 921 static void ti925t_initfn(Object *obj)
 922 {
 923     ARMCPU *cpu = ARM_CPU(obj);
 924     set_feature(&cpu->env, ARM_FEATURE_V4T);
 925     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 926     cpu->midr = ARM_CPUID_TI925T;
 927     cpu->ctr = 0x5109149;
 928     cpu->reset_sctlr = 0x00000070;
 929 }
 930
 931 static void sa1100_initfn(Object *obj)
 932 {
 933     ARMCPU *cpu = ARM_CPU(obj);
 934
 935     cpu->dtb_compatible = "intel,sa1100";
 936     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 937     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 938     cpu->midr = 0x4401A11B;
 939     cpu->reset_sctlr = 0x00000070;
 940 }
 941
 942 static void sa1110_initfn(Object *obj)
 943 {
 944     ARMCPU *cpu = ARM_CPU(obj);
 945     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 946     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 947     cpu->midr = 0x6901B119;
 948     cpu->reset_sctlr = 0x00000070;
 949 }
 950
 951 static void pxa250_initfn(Object *obj)
 952 {
 953     ARMCPU *cpu = ARM_CPU(obj);
 954
 955     cpu->dtb_compatible = "marvell,xscale";
 956     set_feature(&cpu->env, ARM_FEATURE_V5);
 957     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 958     cpu->midr = 0x69052100;
 959     cpu->ctr = 0xd172172;
 960     cpu->reset_sctlr = 0x00000078;
 961 }
 962
 963 static void pxa255_initfn(Object *obj)
 964 {
 965     ARMCPU *cpu = ARM_CPU(obj);
 966
 967     cpu->dtb_compatible = "marvell,xscale";
 968     set_feature(&cpu->env, ARM_FEATURE_V5);
 969     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 970     cpu->midr = 0x69052d00;
 971     cpu->ctr = 0xd172172;
 972     cpu->reset_sctlr = 0x00000078;
 973 }
 974
 975 static void pxa260_initfn(Object *obj)
 976 {
 977     ARMCPU *cpu = ARM_CPU(obj);
 978
 979     cpu->dtb_compatible = "marvell,xscale";
 980     set_feature(&cpu->env, ARM_FEATURE_V5);
 981     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 982     cpu->midr = 0x69052903;
 983     cpu->ctr = 0xd172172;
 984     cpu->reset_sctlr = 0x00000078;
 985 }
 986
 987 static void pxa261_initfn(Object *obj)
 988 {
 989     ARMCPU *cpu = ARM_CPU(obj);
 990
 991     cpu->dtb_compatible = "marvell,xscale";
 992     set_feature(&cpu->env, ARM_FEATURE_V5);
 993     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 994     cpu->midr = 0x69052d05;
 995     cpu->ctr = 0xd172172;
 996     cpu->reset_sctlr = 0x00000078;
 997 }
 998
 999 static void pxa262_initfn(Object *obj)
1000 {
1001     ARMCPU *cpu = ARM_CPU(obj);
1002
1003     cpu->dtb_compatible = "marvell,xscale";
1004     set_feature(&cpu->env, ARM_FEATURE_V5);
1005     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1006     cpu->midr = 0x69052d06;
1007     cpu->ctr = 0xd172172;
1008     cpu->reset_sctlr = 0x00000078;
1009 }
1010
1011 static void pxa270a0_initfn(Object *obj)
1012 {
1013     ARMCPU *cpu = ARM_CPU(obj);
1014
1015     cpu->dtb_compatible = "marvell,xscale";
1016     set_feature(&cpu->env, ARM_FEATURE_V5);
1017     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1018     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1019     cpu->midr = 0x69054110;
1020     cpu->ctr = 0xd172172;
1021     cpu->reset_sctlr = 0x00000078;
1022 }
1023
1024 static void pxa270a1_initfn(Object *obj)
1025 {
1026     ARMCPU *cpu = ARM_CPU(obj);
1027
1028     cpu->dtb_compatible = "marvell,xscale";
1029     set_feature(&cpu->env, ARM_FEATURE_V5);
1030     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1031     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1032     cpu->midr = 0x69054111;
1033     cpu->ctr = 0xd172172;
1034     cpu->reset_sctlr = 0x00000078;
1035 }
1036
1037 static void pxa270b0_initfn(Object *obj)
1038 {
1039     ARMCPU *cpu = ARM_CPU(obj);
1040
1041     cpu->dtb_compatible = "marvell,xscale";
1042     set_feature(&cpu->env, ARM_FEATURE_V5);
1043     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1044     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1045     cpu->midr = 0x69054112;
1046     cpu->ctr = 0xd172172;
1047     cpu->reset_sctlr = 0x00000078;
1048 }
1049
1050 static void pxa270b1_initfn(Object *obj)
1051 {
1052     ARMCPU *cpu = ARM_CPU(obj);
1053
1054     cpu->dtb_compatible = "marvell,xscale";
1055     set_feature(&cpu->env, ARM_FEATURE_V5);
1056     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1057     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1058     cpu->midr = 0x69054113;
1059     cpu->ctr = 0xd172172;
1060     cpu->reset_sctlr = 0x00000078;
1061 }
1062
1063 static void pxa270c0_initfn(Object *obj)
1064 {
1065     ARMCPU *cpu = ARM_CPU(obj);
1066
1067     cpu->dtb_compatible = "marvell,xscale";
1068     set_feature(&cpu->env, ARM_FEATURE_V5);
1069     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1070     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1071     cpu->midr = 0x69054114;
1072     cpu->ctr = 0xd172172;
1073     cpu->reset_sctlr = 0x00000078;
1074 }
1075
1076 static void pxa270c5_initfn(Object *obj)
1077 {
1078     ARMCPU *cpu = ARM_CPU(obj);
1079
1080     cpu->dtb_compatible = "marvell,xscale";
1081     set_feature(&cpu->env, ARM_FEATURE_V5);
1082     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1083     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1084     cpu->midr = 0x69054117;
1085     cpu->ctr = 0xd172172;
1086     cpu->reset_sctlr = 0x00000078;
1087 }
1088
1089 #ifdef CONFIG_USER_ONLY
1090 static void arm_any_initfn(Object *obj)
1091 {
1092     ARMCPU *cpu = ARM_CPU(obj);
1093     set_feature(&cpu->env, ARM_FEATURE_V8);
1094     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1095     set_feature(&cpu->env, ARM_FEATURE_NEON);
1096     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1097     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1098     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1099     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1100     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1101     set_feature(&cpu->env, ARM_FEATURE_CRC);
1102     cpu->midr = 0xffffffff;
1103 }
1104 #endif
1105
1106 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1107
1108 typedef struct ARMCPUInfo {
1109     const char *name;
1110     void (*initfn)(Object *obj);
1111     void (*class_init)(ObjectClass *oc, void *data);
1112 } ARMCPUInfo;
1113
1114 static const ARMCPUInfo arm_cpus[] = {
1115 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1116     { .name = "arm926",      .initfn = arm926_initfn },
1117     { .name = "arm946",      .initfn = arm946_initfn },
1118     { .name = "arm1026",     .initfn = arm1026_initfn },
1119     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1120      * older core than plain "arm1136". In particular this does not
1121      * have the v6K features.
1122      */
1123     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1124     { .name = "arm1136",     .initfn = arm1136_initfn },
1125     { .name = "arm1176",     .initfn = arm1176_initfn },
1126     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1127     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1128                              .class_init = arm_v7m_class_init },
1129     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1130     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1131     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1132     { .name = "ti925t",      .initfn = ti925t_initfn },
1133     { .name = "sa1100",      .initfn = sa1100_initfn },
1134     { .name = "sa1110",      .initfn = sa1110_initfn },
1135     { .name = "pxa250",      .initfn = pxa250_initfn },
1136     { .name = "pxa255",      .initfn = pxa255_initfn },
1137     { .name = "pxa260",      .initfn = pxa260_initfn },
1138     { .name = "pxa261",      .initfn = pxa261_initfn },
1139     { .name = "pxa262",      .initfn = pxa262_initfn },
1140     /* "pxa270" is an alias for "pxa270-a0" */
1141     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1142     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1143     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1144     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1145     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1146     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1147     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1148 #ifdef CONFIG_USER_ONLY
1149     { .name = "any",         .initfn = arm_any_initfn },
1150 #endif
1151 #endif
1152     { .name = NULL }
1153 };
1154
1155 static Property arm_cpu_properties[] = {
1156     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1157     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1158     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1159     DEFINE_PROP_END_OF_LIST()
1160 };
1161
1162 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1163 {
1164     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1165     CPUClass *cc = CPU_CLASS(acc);
1166     DeviceClass *dc = DEVICE_CLASS(oc);
1167
1168     acc->parent_realize = dc->realize;
1169     dc->realize = arm_cpu_realizefn;
1170     dc->props = arm_cpu_properties;
1171
1172     acc->parent_reset = cc->reset;
1173     cc->reset = arm_cpu_reset;
1174
1175     cc->class_by_name = arm_cpu_class_by_name;
1176     cc->has_work = arm_cpu_has_work;
1177     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1178     cc->dump_state = arm_cpu_dump_state;
1179     cc->set_pc = arm_cpu_set_pc;
1180     cc->gdb_read_register = arm_cpu_gdb_read_register;
1181     cc->gdb_write_register = arm_cpu_gdb_write_register;
1182 #ifdef CONFIG_USER_ONLY
1183     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1184 #else
1185     cc->do_interrupt = arm_cpu_do_interrupt;
1186     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1187     cc->vmsd = &vmstate_arm_cpu;
1188 #endif
1189     cc->gdb_num_core_regs = 26;
1190     cc->gdb_core_xml_file = "arm-core.xml";
1191     cc->gdb_stop_before_watchpoint = true;
1192     cc->debug_excp_handler = arm_debug_excp_handler;
1193 }
1194
1195 static void cpu_register(const ARMCPUInfo *info)
1196 {
1197     TypeInfo type_info = {
1198         .parent = TYPE_ARM_CPU,
1199         .instance_size = sizeof(ARMCPU),
1200         .instance_init = info->initfn,
1201         .class_size = sizeof(ARMCPUClass),
1202         .class_init = info->class_init,
1203     };
1204
1205     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1206     type_register(&type_info);
1207     g_free((void *)type_info.name);
1208 }
1209
1210 static const TypeInfo arm_cpu_type_info = {
1211     .name = TYPE_ARM_CPU,
1212     .parent = TYPE_CPU,
1213     .instance_size = sizeof(ARMCPU),
1214     .instance_init = arm_cpu_initfn,
1215     .instance_post_init = arm_cpu_post_init,
1216     .instance_finalize = arm_cpu_finalizefn,
1217     .abstract = true,
1218     .class_size = sizeof(ARMCPUClass),
1219     .class_init = arm_cpu_class_init,
1220 };
1221
1222 static void arm_cpu_register_types(void)
1223 {
1224     const ARMCPUInfo *info = arm_cpus;
1225
1226     type_register_static(&arm_cpu_type_info);
1227
1228     while (info->name) {
1229         cpu_register(info);
1230         info++;
1231     }
1232 }
1233
1234 type_init(arm_cpu_register_types)