target-i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include <stdio.h>
  21 #include <string.h>
  22 #include <inttypes.h>
  23
  24 #include "cpu.h"
  25 #include "sysemu/kvm.h"
  26 #include "sysemu/cpus.h"
  27 #include "kvm_i386.h"
  28 #include "topology.h"
  29
  30 #include "qemu/option.h"
  31 #include "qemu/config-file.h"
  32 #include "qapi/qmp/qerror.h"
  33
  34 #include "qapi-types.h"
  35 #include "qapi-visit.h"
  36 #include "qapi/visitor.h"
  37 #include "sysemu/arch_init.h"
  38
  39 #include "hw/hw.h"
  40 #if defined(CONFIG_KVM)
  41 #include <linux/kvm_para.h>
  42 #endif
  43
  44 #include "sysemu/sysemu.h"
  45 #include "hw/qdev-properties.h"
  46 #include "hw/cpu/icc_bus.h"
  47 #ifndef CONFIG_USER_ONLY
  48 #include "hw/xen/xen.h"
  49 #include "hw/i386/apic_internal.h"
  50 #endif
  51
  52
  53 /* Cache topology CPUID constants: */
  54
  55 /* CPUID Leaf 2 Descriptors */
  56
  57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
  58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
  59 #define CPUID_2_L2_2MB_8WAY_64B   0x7d
  60
  61
  62 /* CPUID Leaf 4 constants: */
  63
  64 /* EAX: */
  65 #define CPUID_4_TYPE_DCACHE  1
  66 #define CPUID_4_TYPE_ICACHE  2
  67 #define CPUID_4_TYPE_UNIFIED 3
  68
  69 #define CPUID_4_LEVEL(l)          ((l) << 5)
  70
  71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
  72 #define CPUID_4_FULLY_ASSOC     (1 << 9)
  73
  74 /* EDX: */
  75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
  76 #define CPUID_4_INCLUSIVE       (1 << 1)
  77 #define CPUID_4_COMPLEX_IDX     (1 << 2)
  78
  79 #define ASSOC_FULL 0xFF
  80
  81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
  82 #define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
  83                           a ==   2 ? 0x2 : \
  84                           a ==   4 ? 0x4 : \
  85                           a ==   8 ? 0x6 : \
  86                           a ==  16 ? 0x8 : \
  87                           a ==  32 ? 0xA : \
  88                           a ==  48 ? 0xB : \
  89                           a ==  64 ? 0xC : \
  90                           a ==  96 ? 0xD : \
  91                           a == 128 ? 0xE : \
  92                           a == ASSOC_FULL ? 0xF : \
  93                           0 /* invalid value */)
  94
  95
  96 /* Definitions of the hardcoded cache entries we expose: */
  97
  98 /* L1 data cache: */
  99 #define L1D_LINE_SIZE         64
 100 #define L1D_ASSOCIATIVITY      8
 101 #define L1D_SETS              64
 102 #define L1D_PARTITIONS         1
 103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
 105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 106 #define L1D_LINES_PER_TAG      1
 107 #define L1D_SIZE_KB_AMD       64
 108 #define L1D_ASSOCIATIVITY_AMD  2
 109
 110 /* L1 instruction cache: */
 111 #define L1I_LINE_SIZE         64
 112 #define L1I_ASSOCIATIVITY      8
 113 #define L1I_SETS              64
 114 #define L1I_PARTITIONS         1
 115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
 116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
 117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 118 #define L1I_LINES_PER_TAG      1
 119 #define L1I_SIZE_KB_AMD       64
 120 #define L1I_ASSOCIATIVITY_AMD  2
 121
 122 /* Level 2 unified cache: */
 123 #define L2_LINE_SIZE          64
 124 #define L2_ASSOCIATIVITY      16
 125 #define L2_SETS             4096
 126 #define L2_PARTITIONS          1
 127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
 128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
 129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
 130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
 131 #define L2_LINES_PER_TAG       1
 132 #define L2_SIZE_KB_AMD       512
 133
 134 /* No L3 cache: */
 135 #define L3_SIZE_KB             0 /* disabled */
 136 #define L3_ASSOCIATIVITY       0 /* disabled */
 137 #define L3_LINES_PER_TAG       0 /* disabled */
 138 #define L3_LINE_SIZE           0 /* disabled */
 139
 140 /* TLB definitions: */
 141
 142 #define L1_DTLB_2M_ASSOC       1
 143 #define L1_DTLB_2M_ENTRIES   255
 144 #define L1_DTLB_4K_ASSOC       1
 145 #define L1_DTLB_4K_ENTRIES   255
 146
 147 #define L1_ITLB_2M_ASSOC       1
 148 #define L1_ITLB_2M_ENTRIES   255
 149 #define L1_ITLB_4K_ASSOC       1
 150 #define L1_ITLB_4K_ENTRIES   255
 151
 152 #define L2_DTLB_2M_ASSOC       0 /* disabled */
 153 #define L2_DTLB_2M_ENTRIES     0 /* disabled */
 154 #define L2_DTLB_4K_ASSOC       4
 155 #define L2_DTLB_4K_ENTRIES   512
 156
 157 #define L2_ITLB_2M_ASSOC       0 /* disabled */
 158 #define L2_ITLB_2M_ENTRIES     0 /* disabled */
 159 #define L2_ITLB_4K_ASSOC       4
 160 #define L2_ITLB_4K_ENTRIES   512
 161
 162
 163
 164 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 165                                      uint32_t vendor2, uint32_t vendor3)
 166 {
 167     int i;
 168     for (i = 0; i < 4; i++) {
 169         dst[i] = vendor1 >> (8 * i);
 170         dst[i + 4] = vendor2 >> (8 * i);
 171         dst[i + 8] = vendor3 >> (8 * i);
 172     }
 173     dst[CPUID_VENDOR_SZ] = '\0';
 174 }
 175
 176 /* feature flags taken from "Intel Processor Identification and the CPUID
 177  * Instruction" and AMD's "CPUID Specification".  In cases of disagreement
 178  * between feature naming conventions, aliases may be added.
 179  */
 180 static const char *feature_name[] = {
 181     "fpu", "vme", "de", "pse",
 182     "tsc", "msr", "pae", "mce",
 183     "cx8", "apic", NULL, "sep",
 184     "mtrr", "pge", "mca", "cmov",
 185     "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
 186     NULL, "ds" /* Intel dts */, "acpi", "mmx",
 187     "fxsr", "sse", "sse2", "ss",
 188     "ht" /* Intel htt */, "tm", "ia64", "pbe",
 189 };
 190 static const char *ext_feature_name[] = {
 191     "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
 192     "ds_cpl", "vmx", "smx", "est",
 193     "tm2", "ssse3", "cid", NULL,
 194     "fma", "cx16", "xtpr", "pdcm",
 195     NULL, "pcid", "dca", "sse4.1|sse4_1",
 196     "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
 197     "tsc-deadline", "aes", "xsave", "osxsave",
 198     "avx", "f16c", "rdrand", "hypervisor",
 199 };
 200 /* Feature names that are already defined on feature_name[] but are set on
 201  * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
 202  * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
 203  * if and only if CPU vendor is AMD.
 204  */
 205 static const char *ext2_feature_name[] = {
 206     NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
 207     NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
 208     NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
 209     NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
 210     NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
 211     "nx|xd", NULL, "mmxext", NULL /* mmx */,
 212     NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
 213     NULL, "lm|i64", "3dnowext", "3dnow",
 214 };
 215 static const char *ext3_feature_name[] = {
 216     "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
 217     "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
 218     "3dnowprefetch", "osvw", "ibs", "xop",
 219     "skinit", "wdt", NULL, "lwp",
 220     "fma4", "tce", NULL, "nodeid_msr",
 221     NULL, "tbm", "topoext", "perfctr_core",
 222     "perfctr_nb", NULL, NULL, NULL,
 223     NULL, NULL, NULL, NULL,
 224 };
 225
 226 static const char *ext4_feature_name[] = {
 227     NULL, NULL, "xstore", "xstore-en",
 228     NULL, NULL, "xcrypt", "xcrypt-en",
 229     "ace2", "ace2-en", "phe", "phe-en",
 230     "pmm", "pmm-en", NULL, NULL,
 231     NULL, NULL, NULL, NULL,
 232     NULL, NULL, NULL, NULL,
 233     NULL, NULL, NULL, NULL,
 234     NULL, NULL, NULL, NULL,
 235 };
 236
 237 static const char *kvm_feature_name[] = {
 238     "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
 239     "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
 240     NULL, NULL, NULL, NULL,
 241     NULL, NULL, NULL, NULL,
 242     NULL, NULL, NULL, NULL,
 243     NULL, NULL, NULL, NULL,
 244     NULL, NULL, NULL, NULL,
 245     NULL, NULL, NULL, NULL,
 246 };
 247
 248 static const char *svm_feature_name[] = {
 249     "npt", "lbrv", "svm_lock", "nrip_save",
 250     "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",
 251     NULL, NULL, "pause_filter", NULL,
 252     "pfthreshold", NULL, NULL, NULL,
 253     NULL, NULL, NULL, NULL,
 254     NULL, NULL, NULL, NULL,
 255     NULL, NULL, NULL, NULL,
 256     NULL, NULL, NULL, NULL,
 257 };
 258
 259 static const char *cpuid_7_0_ebx_feature_name[] = {
 260     "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
 261     "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
 262     NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
 263     NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
 264 };
 265
 266 typedef struct FeatureWordInfo {
 267     const char **feat_names;
 268     uint32_t cpuid_eax;   /* Input EAX for CPUID */
 269     bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
 270     uint32_t cpuid_ecx;   /* Input ECX value for CPUID */
 271     int cpuid_reg;        /* output register (R_* constant) */
 272 } FeatureWordInfo;
 273
 274 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 275     [FEAT_1_EDX] = {
 276         .feat_names = feature_name,
 277         .cpuid_eax = 1, .cpuid_reg = R_EDX,
 278     },
 279     [FEAT_1_ECX] = {
 280         .feat_names = ext_feature_name,
 281         .cpuid_eax = 1, .cpuid_reg = R_ECX,
 282     },
 283     [FEAT_8000_0001_EDX] = {
 284         .feat_names = ext2_feature_name,
 285         .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
 286     },
 287     [FEAT_8000_0001_ECX] = {
 288         .feat_names = ext3_feature_name,
 289         .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
 290     },
 291     [FEAT_C000_0001_EDX] = {
 292         .feat_names = ext4_feature_name,
 293         .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
 294     },
 295     [FEAT_KVM] = {
 296         .feat_names = kvm_feature_name,
 297         .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
 298     },
 299     [FEAT_SVM] = {
 300         .feat_names = svm_feature_name,
 301         .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
 302     },
 303     [FEAT_7_0_EBX] = {
 304         .feat_names = cpuid_7_0_ebx_feature_name,
 305         .cpuid_eax = 7,
 306         .cpuid_needs_ecx = true, .cpuid_ecx = 0,
 307         .cpuid_reg = R_EBX,
 308     },
 309 };
 310
 311 typedef struct X86RegisterInfo32 {
 312     /* Name of register */
 313     const char *name;
 314     /* QAPI enum value register */
 315     X86CPURegister32 qapi_enum;
 316 } X86RegisterInfo32;
 317
 318 #define REGISTER(reg) \
 319     [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
 320 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
 321     REGISTER(EAX),
 322     REGISTER(ECX),
 323     REGISTER(EDX),
 324     REGISTER(EBX),
 325     REGISTER(ESP),
 326     REGISTER(EBP),
 327     REGISTER(ESI),
 328     REGISTER(EDI),
 329 };
 330 #undef REGISTER
 331
 332 typedef struct ExtSaveArea {
 333     uint32_t feature, bits;
 334     uint32_t offset, size;
 335 } ExtSaveArea;
 336
 337 static const ExtSaveArea ext_save_areas[] = {
 338     [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
 339             .offset = 0x240, .size = 0x100 },
 340     [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 341             .offset = 0x3c0, .size = 0x40  },
 342     [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
 343             .offset = 0x400, .size = 0x40  },
 344 };
 345
 346 const char *get_register_name_32(unsigned int reg)
 347 {
 348     if (reg >= CPU_NB_REGS32) {
 349         return NULL;
 350     }
 351     return x86_reg_info_32[reg].name;
 352 }
 353
 354 /* collects per-function cpuid data
 355  */
 356 typedef struct model_features_t {
 357     uint32_t *guest_feat;
 358     uint32_t *host_feat;
 359     FeatureWord feat_word;
 360 } model_features_t;
 361
 362 /* KVM-specific features that are automatically added to all CPU models
 363  * when KVM is enabled.
 364  */
 365 static uint32_t kvm_default_features[FEATURE_WORDS] = {
 366     [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
 367         (1 << KVM_FEATURE_NOP_IO_DELAY) |
 368         (1 << KVM_FEATURE_CLOCKSOURCE2) |
 369         (1 << KVM_FEATURE_ASYNC_PF) |
 370         (1 << KVM_FEATURE_STEAL_TIME) |
 371         (1 << KVM_FEATURE_PV_EOI) |
 372         (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
 373     [FEAT_1_ECX] = CPUID_EXT_X2APIC,
 374 };
 375
 376 void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
 377 {
 378     kvm_default_features[w] &= ~features;
 379 }
 380
 381 void host_cpuid(uint32_t function, uint32_t count,
 382                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
 383 {
 384     uint32_t vec[4];
 385
 386 #ifdef __x86_64__
 387     asm volatile("cpuid"
 388                  : "=a"(vec[0]), "=b"(vec[1]),
 389                    "=c"(vec[2]), "=d"(vec[3])
 390                  : "0"(function), "c"(count) : "cc");
 391 #elif defined(__i386__)
 392     asm volatile("pusha \n\t"
 393                  "cpuid \n\t"
 394                  "mov %%eax, 0(%2) \n\t"
 395                  "mov %%ebx, 4(%2) \n\t"
 396                  "mov %%ecx, 8(%2) \n\t"
 397                  "mov %%edx, 12(%2) \n\t"
 398                  "popa"
 399                  : : "a"(function), "c"(count), "S"(vec)
 400                  : "memory", "cc");
 401 #else
 402     abort();
 403 #endif
 404
 405     if (eax)
 406         *eax = vec[0];
 407     if (ebx)
 408         *ebx = vec[1];
 409     if (ecx)
 410         *ecx = vec[2];
 411     if (edx)
 412         *edx = vec[3];
 413 }
 414
 415 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
 416
 417 /* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of
 418  * a substring.  ex if !NULL points to the first char after a substring,
 419  * otherwise the string is assumed to sized by a terminating nul.
 420  * Return lexical ordering of *s1:*s2.
 421  */
 422 static int sstrcmp(const char *s1, const char *e1, const char *s2,
 423     const char *e2)
 424 {
 425     for (;;) {
 426         if (!*s1 || !*s2 || *s1 != *s2)
 427             return (*s1 - *s2);
 428         ++s1, ++s2;
 429         if (s1 == e1 && s2 == e2)
 430             return (0);
 431         else if (s1 == e1)
 432             return (*s2);
 433         else if (s2 == e2)
 434             return (*s1);
 435     }
 436 }
 437
 438 /* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple
 439  * '|' delimited (possibly empty) strings in which case search for a match
 440  * within the alternatives proceeds left to right.  Return 0 for success,
 441  * non-zero otherwise.
 442  */
 443 static int altcmp(const char *s, const char *e, const char *altstr)
 444 {
 445     const char *p, *q;
 446
 447     for (q = p = altstr; ; ) {
 448         while (*p && *p != '|')
 449             ++p;
 450         if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
 451             return (0);
 452         if (!*p)
 453             return (1);
 454         else
 455             q = ++p;
 456     }
 457 }
 458
 459 /* search featureset for flag *[s..e), if found set corresponding bit in
 460  * *pval and return true, otherwise return false
 461  */
 462 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
 463                            const char **featureset)
 464 {
 465     uint32_t mask;
 466     const char **ppc;
 467     bool found = false;
 468
 469     for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
 470         if (*ppc && !altcmp(s, e, *ppc)) {
 471             *pval |= mask;
 472             found = true;
 473         }
 474     }
 475     return found;
 476 }
 477
 478 static void add_flagname_to_bitmaps(const char *flagname,
 479                                     FeatureWordArray words)
 480 {
 481     FeatureWord w;
 482     for (w = 0; w < FEATURE_WORDS; w++) {
 483         FeatureWordInfo *wi = &feature_word_info[w];
 484         if (wi->feat_names &&
 485             lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
 486             break;
 487         }
 488     }
 489     if (w == FEATURE_WORDS) {
 490         fprintf(stderr, "CPU feature %s not found\n", flagname);
 491     }
 492 }
 493
 494 /* CPU class name definitions: */
 495
 496 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
 497 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
 498
 499 /* Return type name for a given CPU model name
 500  * Caller is responsible for freeing the returned string.
 501  */
 502 static char *x86_cpu_type_name(const char *model_name)
 503 {
 504     return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
 505 }
 506
 507 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
 508 {
 509     ObjectClass *oc;
 510     char *typename;
 511
 512     if (cpu_model == NULL) {
 513         return NULL;
 514     }
 515
 516     typename = x86_cpu_type_name(cpu_model);
 517     oc = object_class_by_name(typename);
 518     g_free(typename);
 519     return oc;
 520 }
 521
 522 struct X86CPUDefinition {
 523     const char *name;
 524     uint32_t level;
 525     uint32_t xlevel;
 526     uint32_t xlevel2;
 527     /* vendor is zero-terminated, 12 character ASCII string */
 528     char vendor[CPUID_VENDOR_SZ + 1];
 529     int family;
 530     int model;
 531     int stepping;
 532     FeatureWordArray features;
 533     char model_id[48];
 534     bool cache_info_passthrough;
 535 };
 536
 537 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 538 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 539           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 540 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 541           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 542           CPUID_PSE36 | CPUID_FXSR)
 543 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 544 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 545           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 546           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 547           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 548
 549 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 550           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 551           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 552           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 553           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
 554           /* partly implemented:
 555           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
 556           /* missing:
 557           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 558 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 559           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 560           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 561           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
 562           /* missing:
 563           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 564           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 565           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 566           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
 567           CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
 568           CPUID_EXT_RDRAND */
 569 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 570           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 571           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB)
 572 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 573           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 574 #define TCG_SVM_FEATURES 0
 575 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
 576           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
 577           /* missing:
 578           CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 579           CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 580           CPUID_7_0_EBX_RDSEED */
 581
 582 static X86CPUDefinition builtin_x86_defs[] = {
 583     {
 584         .name = "qemu64",
 585         .level = 4,
 586         .vendor = CPUID_VENDOR_AMD,
 587         .family = 6,
 588         .model = 6,
 589         .stepping = 3,
 590         .features[FEAT_1_EDX] =
 591             PPRO_FEATURES |
 592             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 593             CPUID_PSE36,
 594         .features[FEAT_1_ECX] =
 595             CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
 596         .features[FEAT_8000_0001_EDX] =
 597             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 598             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 599         .features[FEAT_8000_0001_ECX] =
 600             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 601             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 602         .xlevel = 0x8000000A,
 603     },
 604     {
 605         .name = "phenom",
 606         .level = 5,
 607         .vendor = CPUID_VENDOR_AMD,
 608         .family = 16,
 609         .model = 2,
 610         .stepping = 3,
 611         .features[FEAT_1_EDX] =
 612             PPRO_FEATURES |
 613             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 614             CPUID_PSE36 | CPUID_VME | CPUID_HT,
 615         .features[FEAT_1_ECX] =
 616             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
 617             CPUID_EXT_POPCNT,
 618         .features[FEAT_8000_0001_EDX] =
 619             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 620             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
 621             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
 622             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
 623         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 624                     CPUID_EXT3_CR8LEG,
 625                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 626                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
 627         .features[FEAT_8000_0001_ECX] =
 628             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
 629             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
 630         .features[FEAT_SVM] =
 631             CPUID_SVM_NPT | CPUID_SVM_LBRV,
 632         .xlevel = 0x8000001A,
 633         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
 634     },
 635     {
 636         .name = "core2duo",
 637         .level = 10,
 638         .vendor = CPUID_VENDOR_INTEL,
 639         .family = 6,
 640         .model = 15,
 641         .stepping = 11,
 642         .features[FEAT_1_EDX] =
 643             PPRO_FEATURES |
 644             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 645             CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
 646             CPUID_HT | CPUID_TM | CPUID_PBE,
 647         .features[FEAT_1_ECX] =
 648             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 649             CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
 650             CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 651         .features[FEAT_8000_0001_EDX] =
 652             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 653         .features[FEAT_8000_0001_ECX] =
 654             CPUID_EXT3_LAHF_LM,
 655         .xlevel = 0x80000008,
 656         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
 657     },
 658     {
 659         .name = "kvm64",
 660         .level = 5,
 661         .vendor = CPUID_VENDOR_INTEL,
 662         .family = 15,
 663         .model = 6,
 664         .stepping = 1,
 665         /* Missing: CPUID_VME, CPUID_HT */
 666         .features[FEAT_1_EDX] =
 667             PPRO_FEATURES |
 668             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
 669             CPUID_PSE36,
 670         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
 671         .features[FEAT_1_ECX] =
 672             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
 673         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
 674         .features[FEAT_8000_0001_EDX] =
 675             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 676             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 677         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
 678                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
 679                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
 680                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
 681         .features[FEAT_8000_0001_ECX] =
 682             0,
 683         .xlevel = 0x80000008,
 684         .model_id = "Common KVM processor"
 685     },
 686     {
 687         .name = "qemu32",
 688         .level = 4,
 689         .vendor = CPUID_VENDOR_INTEL,
 690         .family = 6,
 691         .model = 6,
 692         .stepping = 3,
 693         .features[FEAT_1_EDX] =
 694             PPRO_FEATURES,
 695         .features[FEAT_1_ECX] =
 696             CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
 697         .xlevel = 0x80000004,
 698     },
 699     {
 700         .name = "kvm32",
 701         .level = 5,
 702         .vendor = CPUID_VENDOR_INTEL,
 703         .family = 15,
 704         .model = 6,
 705         .stepping = 1,
 706         .features[FEAT_1_EDX] =
 707             PPRO_FEATURES |
 708             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
 709         .features[FEAT_1_ECX] =
 710             CPUID_EXT_SSE3,
 711         .features[FEAT_8000_0001_EDX] =
 712             PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
 713         .features[FEAT_8000_0001_ECX] =
 714             0,
 715         .xlevel = 0x80000008,
 716         .model_id = "Common 32-bit KVM processor"
 717     },
 718     {
 719         .name = "coreduo",
 720         .level = 10,
 721         .vendor = CPUID_VENDOR_INTEL,
 722         .family = 6,
 723         .model = 14,
 724         .stepping = 8,
 725         .features[FEAT_1_EDX] =
 726             PPRO_FEATURES | CPUID_VME |
 727             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
 728             CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 729         .features[FEAT_1_ECX] =
 730             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
 731             CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
 732         .features[FEAT_8000_0001_EDX] =
 733             CPUID_EXT2_NX,
 734         .xlevel = 0x80000008,
 735         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
 736     },
 737     {
 738         .name = "486",
 739         .level = 1,
 740         .vendor = CPUID_VENDOR_INTEL,
 741         .family = 4,
 742         .model = 8,
 743         .stepping = 0,
 744         .features[FEAT_1_EDX] =
 745             I486_FEATURES,
 746         .xlevel = 0,
 747     },
 748     {
 749         .name = "pentium",
 750         .level = 1,
 751         .vendor = CPUID_VENDOR_INTEL,
 752         .family = 5,
 753         .model = 4,
 754         .stepping = 3,
 755         .features[FEAT_1_EDX] =
 756             PENTIUM_FEATURES,
 757         .xlevel = 0,
 758     },
 759     {
 760         .name = "pentium2",
 761         .level = 2,
 762         .vendor = CPUID_VENDOR_INTEL,
 763         .family = 6,
 764         .model = 5,
 765         .stepping = 2,
 766         .features[FEAT_1_EDX] =
 767             PENTIUM2_FEATURES,
 768         .xlevel = 0,
 769     },
 770     {
 771         .name = "pentium3",
 772         .level = 2,
 773         .vendor = CPUID_VENDOR_INTEL,
 774         .family = 6,
 775         .model = 7,
 776         .stepping = 3,
 777         .features[FEAT_1_EDX] =
 778             PENTIUM3_FEATURES,
 779         .xlevel = 0,
 780     },
 781     {
 782         .name = "athlon",
 783         .level = 2,
 784         .vendor = CPUID_VENDOR_AMD,
 785         .family = 6,
 786         .model = 2,
 787         .stepping = 3,
 788         .features[FEAT_1_EDX] =
 789             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
 790             CPUID_MCA,
 791         .features[FEAT_8000_0001_EDX] =
 792             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 793             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
 794         .xlevel = 0x80000008,
 795     },
 796     {
 797         .name = "n270",
 798         /* original is on level 10 */
 799         .level = 5,
 800         .vendor = CPUID_VENDOR_INTEL,
 801         .family = 6,
 802         .model = 28,
 803         .stepping = 2,
 804         .features[FEAT_1_EDX] =
 805             PPRO_FEATURES |
 806             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
 807             CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
 808             /* Some CPUs got no CPUID_SEP */
 809         .features[FEAT_1_ECX] =
 810             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
 811             CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
 812             CPUID_EXT_MOVBE,
 813         .features[FEAT_8000_0001_EDX] =
 814             (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
 815             CPUID_EXT2_NX,
 816         .features[FEAT_8000_0001_ECX] =
 817             CPUID_EXT3_LAHF_LM,
 818         .xlevel = 0x8000000A,
 819         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
 820     },
 821     {
 822         .name = "Conroe",
 823         .level = 4,
 824         .vendor = CPUID_VENDOR_INTEL,
 825         .family = 6,
 826         .model = 15,
 827         .stepping = 3,
 828         .features[FEAT_1_EDX] =
 829             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 830              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 831              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 832              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 833              CPUID_DE | CPUID_FP87,
 834         .features[FEAT_1_ECX] =
 835             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 836         .features[FEAT_8000_0001_EDX] =
 837             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 838         .features[FEAT_8000_0001_ECX] =
 839             CPUID_EXT3_LAHF_LM,
 840         .xlevel = 0x8000000A,
 841         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
 842     },
 843     {
 844         .name = "Penryn",
 845         .level = 4,
 846         .vendor = CPUID_VENDOR_INTEL,
 847         .family = 6,
 848         .model = 23,
 849         .stepping = 3,
 850         .features[FEAT_1_EDX] =
 851             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 852              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 853              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 854              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 855              CPUID_DE | CPUID_FP87,
 856         .features[FEAT_1_ECX] =
 857             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 858              CPUID_EXT_SSE3,
 859         .features[FEAT_8000_0001_EDX] =
 860             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
 861         .features[FEAT_8000_0001_ECX] =
 862             CPUID_EXT3_LAHF_LM,
 863         .xlevel = 0x8000000A,
 864         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
 865     },
 866     {
 867         .name = "Nehalem",
 868         .level = 4,
 869         .vendor = CPUID_VENDOR_INTEL,
 870         .family = 6,
 871         .model = 26,
 872         .stepping = 3,
 873         .features[FEAT_1_EDX] =
 874             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 875              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 876              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 877              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 878              CPUID_DE | CPUID_FP87,
 879         .features[FEAT_1_ECX] =
 880             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 881              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
 882         .features[FEAT_8000_0001_EDX] =
 883             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 884         .features[FEAT_8000_0001_ECX] =
 885             CPUID_EXT3_LAHF_LM,
 886         .xlevel = 0x8000000A,
 887         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
 888     },
 889     {
 890         .name = "Westmere",
 891         .level = 11,
 892         .vendor = CPUID_VENDOR_INTEL,
 893         .family = 6,
 894         .model = 44,
 895         .stepping = 1,
 896         .features[FEAT_1_EDX] =
 897             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 898              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 899              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 900              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 901              CPUID_DE | CPUID_FP87,
 902         .features[FEAT_1_ECX] =
 903             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
 904              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 905              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
 906         .features[FEAT_8000_0001_EDX] =
 907             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
 908         .features[FEAT_8000_0001_ECX] =
 909             CPUID_EXT3_LAHF_LM,
 910         .xlevel = 0x8000000A,
 911         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
 912     },
 913     {
 914         .name = "SandyBridge",
 915         .level = 0xd,
 916         .vendor = CPUID_VENDOR_INTEL,
 917         .family = 6,
 918         .model = 42,
 919         .stepping = 1,
 920         .features[FEAT_1_EDX] =
 921             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 922              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 923              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 924              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 925              CPUID_DE | CPUID_FP87,
 926         .features[FEAT_1_ECX] =
 927             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 928              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
 929              CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
 930              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
 931              CPUID_EXT_SSE3,
 932         .features[FEAT_8000_0001_EDX] =
 933             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 934              CPUID_EXT2_SYSCALL,
 935         .features[FEAT_8000_0001_ECX] =
 936             CPUID_EXT3_LAHF_LM,
 937         .xlevel = 0x8000000A,
 938         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
 939     },
 940     {
 941         .name = "Haswell",
 942         .level = 0xd,
 943         .vendor = CPUID_VENDOR_INTEL,
 944         .family = 6,
 945         .model = 60,
 946         .stepping = 1,
 947         .features[FEAT_1_EDX] =
 948             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 949              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 950              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 951              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 952              CPUID_DE | CPUID_FP87,
 953         .features[FEAT_1_ECX] =
 954             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
 955              CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
 956              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
 957              CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
 958              CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
 959              CPUID_EXT_PCID,
 960         .features[FEAT_8000_0001_EDX] =
 961             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
 962              CPUID_EXT2_SYSCALL,
 963         .features[FEAT_8000_0001_ECX] =
 964             CPUID_EXT3_LAHF_LM,
 965         .features[FEAT_7_0_EBX] =
 966             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
 967             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
 968             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
 969             CPUID_7_0_EBX_RTM,
 970         .xlevel = 0x8000000A,
 971         .model_id = "Intel Core Processor (Haswell)",
 972     },
 973     {
 974         .name = "Opteron_G1",
 975         .level = 5,
 976         .vendor = CPUID_VENDOR_AMD,
 977         .family = 15,
 978         .model = 6,
 979         .stepping = 1,
 980         .features[FEAT_1_EDX] =
 981             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
 982              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
 983              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
 984              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
 985              CPUID_DE | CPUID_FP87,
 986         .features[FEAT_1_ECX] =
 987             CPUID_EXT_SSE3,
 988         .features[FEAT_8000_0001_EDX] =
 989             CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
 990              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
 991              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
 992              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
 993              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
 994              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
 995         .xlevel = 0x80000008,
 996         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
 997     },
 998     {
 999         .name = "Opteron_G2",
1000         .level = 5,
1001         .vendor = CPUID_VENDOR_AMD,
1002         .family = 15,
1003         .model = 6,
1004         .stepping = 1,
1005         .features[FEAT_1_EDX] =
1006             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1007              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1008              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1009              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1010              CPUID_DE | CPUID_FP87,
1011         .features[FEAT_1_ECX] =
1012             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1013         .features[FEAT_8000_0001_EDX] =
1014             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1015              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1016              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1017              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1018              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1019              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1020              CPUID_EXT2_DE | CPUID_EXT2_FPU,
1021         .features[FEAT_8000_0001_ECX] =
1022             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1023         .xlevel = 0x80000008,
1024         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1025     },
1026     {
1027         .name = "Opteron_G3",
1028         .level = 5,
1029         .vendor = CPUID_VENDOR_AMD,
1030         .family = 15,
1031         .model = 6,
1032         .stepping = 1,
1033         .features[FEAT_1_EDX] =
1034             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1035              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1036              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1037              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1038              CPUID_DE | CPUID_FP87,
1039         .features[FEAT_1_ECX] =
1040             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1041              CPUID_EXT_SSE3,
1042         .features[FEAT_8000_0001_EDX] =
1043             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1044              CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1045              CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1046              CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1047              CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1048              CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1049              CPUID_EXT2_DE | CPUID_EXT2_FPU,
1050         .features[FEAT_8000_0001_ECX] =
1051             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1052              CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1053         .xlevel = 0x80000008,
1054         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1055     },
1056     {
1057         .name = "Opteron_G4",
1058         .level = 0xd,
1059         .vendor = CPUID_VENDOR_AMD,
1060         .family = 21,
1061         .model = 1,
1062         .stepping = 2,
1063         .features[FEAT_1_EDX] =
1064             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1065              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1066              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1067              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1068              CPUID_DE | CPUID_FP87,
1069         .features[FEAT_1_ECX] =
1070             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1071              CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1072              CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1073              CPUID_EXT_SSE3,
1074         .features[FEAT_8000_0001_EDX] =
1075             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1076              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1077              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1078              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1079              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1080              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1081              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1082         .features[FEAT_8000_0001_ECX] =
1083             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1084              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1085              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1086              CPUID_EXT3_LAHF_LM,
1087         .xlevel = 0x8000001A,
1088         .model_id = "AMD Opteron 62xx class CPU",
1089     },
1090     {
1091         .name = "Opteron_G5",
1092         .level = 0xd,
1093         .vendor = CPUID_VENDOR_AMD,
1094         .family = 21,
1095         .model = 2,
1096         .stepping = 0,
1097         .features[FEAT_1_EDX] =
1098             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1099              CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1100              CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1101              CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1102              CPUID_DE | CPUID_FP87,
1103         .features[FEAT_1_ECX] =
1104             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1105              CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1106              CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1107              CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1108         .features[FEAT_8000_0001_EDX] =
1109             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1110              CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1111              CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1112              CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1113              CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1114              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1115              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1116         .features[FEAT_8000_0001_ECX] =
1117             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1118              CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1119              CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1120              CPUID_EXT3_LAHF_LM,
1121         .xlevel = 0x8000001A,
1122         .model_id = "AMD Opteron 63xx class CPU",
1123     },
1124 };
1125
1126 /**
1127  * x86_cpu_compat_set_features:
1128  * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1129  * @w: Identifies the feature word to be changed.
1130  * @feat_add: Feature bits to be added to feature word
1131  * @feat_remove: Feature bits to be removed from feature word
1132  *
1133  * Change CPU model feature bits for compatibility.
1134  *
1135  * This function may be used by machine-type compatibility functions
1136  * to enable or disable feature bits on specific CPU models.
1137  */
1138 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1139                                  uint32_t feat_add, uint32_t feat_remove)
1140 {
1141     X86CPUDefinition *def;
1142     int i;
1143     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1144         def = &builtin_x86_defs[i];
1145         if (!cpu_model || !strcmp(cpu_model, def->name)) {
1146             def->features[w] |= feat_add;
1147             def->features[w] &= ~feat_remove;
1148         }
1149     }
1150 }
1151
1152 #ifdef CONFIG_KVM
1153
1154 static int cpu_x86_fill_model_id(char *str)
1155 {
1156     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1157     int i;
1158
1159     for (i = 0; i < 3; i++) {
1160         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1161         memcpy(str + i * 16 +  0, &eax, 4);
1162         memcpy(str + i * 16 +  4, &ebx, 4);
1163         memcpy(str + i * 16 +  8, &ecx, 4);
1164         memcpy(str + i * 16 + 12, &edx, 4);
1165     }
1166     return 0;
1167 }
1168
1169 static X86CPUDefinition host_cpudef;
1170
1171 /* class_init for the "host" CPU model
1172  *
1173  * This function may be called before KVM is initialized.
1174  */
1175 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1176 {
1177     X86CPUClass *xcc = X86_CPU_CLASS(oc);
1178     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1179
1180     xcc->kvm_required = true;
1181
1182     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1183     x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1184
1185     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1186     host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1187     host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1188     host_cpudef.stepping = eax & 0x0F;
1189
1190     cpu_x86_fill_model_id(host_cpudef.model_id);
1191
1192     xcc->cpu_def = &host_cpudef;
1193     host_cpudef.cache_info_passthrough = true;
1194
1195     /* level, xlevel, xlevel2, and the feature words are initialized on
1196      * instance_init, because they require KVM to be initialized.
1197      */
1198 }
1199
1200 static void host_x86_cpu_initfn(Object *obj)
1201 {
1202     X86CPU *cpu = X86_CPU(obj);
1203     CPUX86State *env = &cpu->env;
1204     KVMState *s = kvm_state;
1205     FeatureWord w;
1206
1207     assert(kvm_enabled());
1208
1209     env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1210     env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1211     env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1212
1213     for (w = 0; w < FEATURE_WORDS; w++) {
1214         FeatureWordInfo *wi = &feature_word_info[w];
1215         env->features[w] =
1216             kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1217                                          wi->cpuid_reg);
1218     }
1219     object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1220 }
1221
1222 static const TypeInfo host_x86_cpu_type_info = {
1223     .name = X86_CPU_TYPE_NAME("host"),
1224     .parent = TYPE_X86_CPU,
1225     .instance_init = host_x86_cpu_initfn,
1226     .class_init = host_x86_cpu_class_init,
1227 };
1228
1229 #endif
1230
1231 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1232 {
1233     int i;
1234
1235     for (i = 0; i < 32; ++i)
1236         if (1 << i & mask) {
1237             const char *reg = get_register_name_32(f->cpuid_reg);
1238             assert(reg);
1239             fprintf(stderr, "warning: host doesn't support requested feature: "
1240                 "CPUID.%02XH:%s%s%s [bit %d]\n",
1241                 f->cpuid_eax, reg,
1242                 f->feat_names[i] ? "." : "",
1243                 f->feat_names[i] ? f->feat_names[i] : "", i);
1244             break;
1245         }
1246     return 0;
1247 }
1248
1249 /* Check if all requested cpu flags are making their way to the guest
1250  *
1251  * Returns 0 if all flags are supported by the host, non-zero otherwise.
1252  *
1253  * This function may be called only if KVM is enabled.
1254  */
1255 static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
1256 {
1257     CPUX86State *env = &cpu->env;
1258     int rv = 0;
1259     FeatureWord w;
1260
1261     assert(kvm_enabled());
1262
1263     for (w = 0; w < FEATURE_WORDS; w++) {
1264         FeatureWordInfo *wi = &feature_word_info[w];
1265         uint32_t guest_feat = env->features[w];
1266         uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1267                                                              wi->cpuid_ecx,
1268                                                              wi->cpuid_reg);
1269         uint32_t mask;
1270         for (mask = 1; mask; mask <<= 1) {
1271             if (guest_feat & mask && !(host_feat & mask)) {
1272                 unavailable_host_feature(wi, mask);
1273                 rv = 1;
1274             }
1275         }
1276     }
1277     return rv;
1278 }
1279
1280 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1281                                          const char *name, Error **errp)
1282 {
1283     X86CPU *cpu = X86_CPU(obj);
1284     CPUX86State *env = &cpu->env;
1285     int64_t value;
1286
1287     value = (env->cpuid_version >> 8) & 0xf;
1288     if (value == 0xf) {
1289         value += (env->cpuid_version >> 20) & 0xff;
1290     }
1291     visit_type_int(v, &value, name, errp);
1292 }
1293
1294 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1295                                          const char *name, Error **errp)
1296 {
1297     X86CPU *cpu = X86_CPU(obj);
1298     CPUX86State *env = &cpu->env;
1299     const int64_t min = 0;
1300     const int64_t max = 0xff + 0xf;
1301     Error *local_err = NULL;
1302     int64_t value;
1303
1304     visit_type_int(v, &value, name, &local_err);
1305     if (local_err) {
1306         error_propagate(errp, local_err);
1307         return;
1308     }
1309     if (value < min || value > max) {
1310         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1311                   name ? name : "null", value, min, max);
1312         return;
1313     }
1314
1315     env->cpuid_version &= ~0xff00f00;
1316     if (value > 0x0f) {
1317         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1318     } else {
1319         env->cpuid_version |= value << 8;
1320     }
1321 }
1322
1323 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1324                                         const char *name, Error **errp)
1325 {
1326     X86CPU *cpu = X86_CPU(obj);
1327     CPUX86State *env = &cpu->env;
1328     int64_t value;
1329
1330     value = (env->cpuid_version >> 4) & 0xf;
1331     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1332     visit_type_int(v, &value, name, errp);
1333 }
1334
1335 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1336                                         const char *name, Error **errp)
1337 {
1338     X86CPU *cpu = X86_CPU(obj);
1339     CPUX86State *env = &cpu->env;
1340     const int64_t min = 0;
1341     const int64_t max = 0xff;
1342     Error *local_err = NULL;
1343     int64_t value;
1344
1345     visit_type_int(v, &value, name, &local_err);
1346     if (local_err) {
1347         error_propagate(errp, local_err);
1348         return;
1349     }
1350     if (value < min || value > max) {
1351         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1352                   name ? name : "null", value, min, max);
1353         return;
1354     }
1355
1356     env->cpuid_version &= ~0xf00f0;
1357     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1358 }
1359
1360 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1361                                            void *opaque, const char *name,
1362                                            Error **errp)
1363 {
1364     X86CPU *cpu = X86_CPU(obj);
1365     CPUX86State *env = &cpu->env;
1366     int64_t value;
1367
1368     value = env->cpuid_version & 0xf;
1369     visit_type_int(v, &value, name, errp);
1370 }
1371
1372 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1373                                            void *opaque, const char *name,
1374                                            Error **errp)
1375 {
1376     X86CPU *cpu = X86_CPU(obj);
1377     CPUX86State *env = &cpu->env;
1378     const int64_t min = 0;
1379     const int64_t max = 0xf;
1380     Error *local_err = NULL;
1381     int64_t value;
1382
1383     visit_type_int(v, &value, name, &local_err);
1384     if (local_err) {
1385         error_propagate(errp, local_err);
1386         return;
1387     }
1388     if (value < min || value > max) {
1389         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1390                   name ? name : "null", value, min, max);
1391         return;
1392     }
1393
1394     env->cpuid_version &= ~0xf;
1395     env->cpuid_version |= value & 0xf;
1396 }
1397
1398 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1399                                 const char *name, Error **errp)
1400 {
1401     X86CPU *cpu = X86_CPU(obj);
1402
1403     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1404 }
1405
1406 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1407                                 const char *name, Error **errp)
1408 {
1409     X86CPU *cpu = X86_CPU(obj);
1410
1411     visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1412 }
1413
1414 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1415                                  const char *name, Error **errp)
1416 {
1417     X86CPU *cpu = X86_CPU(obj);
1418
1419     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1420 }
1421
1422 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1423                                  const char *name, Error **errp)
1424 {
1425     X86CPU *cpu = X86_CPU(obj);
1426
1427     visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1428 }
1429
1430 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1431 {
1432     X86CPU *cpu = X86_CPU(obj);
1433     CPUX86State *env = &cpu->env;
1434     char *value;
1435
1436     value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1437     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1438                              env->cpuid_vendor3);
1439     return value;
1440 }
1441
1442 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1443                                  Error **errp)
1444 {
1445     X86CPU *cpu = X86_CPU(obj);
1446     CPUX86State *env = &cpu->env;
1447     int i;
1448
1449     if (strlen(value) != CPUID_VENDOR_SZ) {
1450         error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1451                   "vendor", value);
1452         return;
1453     }
1454
1455     env->cpuid_vendor1 = 0;
1456     env->cpuid_vendor2 = 0;
1457     env->cpuid_vendor3 = 0;
1458     for (i = 0; i < 4; i++) {
1459         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
1460         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1461         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1462     }
1463 }
1464
1465 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1466 {
1467     X86CPU *cpu = X86_CPU(obj);
1468     CPUX86State *env = &cpu->env;
1469     char *value;
1470     int i;
1471
1472     value = g_malloc(48 + 1);
1473     for (i = 0; i < 48; i++) {
1474         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1475     }
1476     value[48] = '\0';
1477     return value;
1478 }
1479
1480 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1481                                    Error **errp)
1482 {
1483     X86CPU *cpu = X86_CPU(obj);
1484     CPUX86State *env = &cpu->env;
1485     int c, len, i;
1486
1487     if (model_id == NULL) {
1488         model_id = "";
1489     }
1490     len = strlen(model_id);
1491     memset(env->cpuid_model, 0, 48);
1492     for (i = 0; i < 48; i++) {
1493         if (i >= len) {
1494             c = '\0';
1495         } else {
1496             c = (uint8_t)model_id[i];
1497         }
1498         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1499     }
1500 }
1501
1502 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1503                                    const char *name, Error **errp)
1504 {
1505     X86CPU *cpu = X86_CPU(obj);
1506     int64_t value;
1507
1508     value = cpu->env.tsc_khz * 1000;
1509     visit_type_int(v, &value, name, errp);
1510 }
1511
1512 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1513                                    const char *name, Error **errp)
1514 {
1515     X86CPU *cpu = X86_CPU(obj);
1516     const int64_t min = 0;
1517     const int64_t max = INT64_MAX;
1518     Error *local_err = NULL;
1519     int64_t value;
1520
1521     visit_type_int(v, &value, name, &local_err);
1522     if (local_err) {
1523         error_propagate(errp, local_err);
1524         return;
1525     }
1526     if (value < min || value > max) {
1527         error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1528                   name ? name : "null", value, min, max);
1529         return;
1530     }
1531
1532     cpu->env.tsc_khz = value / 1000;
1533 }
1534
1535 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1536                                   const char *name, Error **errp)
1537 {
1538     X86CPU *cpu = X86_CPU(obj);
1539     int64_t value = cpu->env.cpuid_apic_id;
1540
1541     visit_type_int(v, &value, name, errp);
1542 }
1543
1544 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1545                                   const char *name, Error **errp)
1546 {
1547     X86CPU *cpu = X86_CPU(obj);
1548     DeviceState *dev = DEVICE(obj);
1549     const int64_t min = 0;
1550     const int64_t max = UINT32_MAX;
1551     Error *error = NULL;
1552     int64_t value;
1553
1554     if (dev->realized) {
1555         error_setg(errp, "Attempt to set property '%s' on '%s' after "
1556                    "it was realized", name, object_get_typename(obj));
1557         return;
1558     }
1559
1560     visit_type_int(v, &value, name, &error);
1561     if (error) {
1562         error_propagate(errp, error);
1563         return;
1564     }
1565     if (value < min || value > max) {
1566         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1567                    " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1568                    object_get_typename(obj), name, value, min, max);
1569         return;
1570     }
1571
1572     if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1573         error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1574         return;
1575     }
1576     cpu->env.cpuid_apic_id = value;
1577 }
1578
1579 /* Generic getter for "feature-words" and "filtered-features" properties */
1580 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1581                                       const char *name, Error **errp)
1582 {
1583     uint32_t *array = (uint32_t *)opaque;
1584     FeatureWord w;
1585     Error *err = NULL;
1586     X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1587     X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1588     X86CPUFeatureWordInfoList *list = NULL;
1589
1590     for (w = 0; w < FEATURE_WORDS; w++) {
1591         FeatureWordInfo *wi = &feature_word_info[w];
1592         X86CPUFeatureWordInfo *qwi = &word_infos[w];
1593         qwi->cpuid_input_eax = wi->cpuid_eax;
1594         qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1595         qwi->cpuid_input_ecx = wi->cpuid_ecx;
1596         qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1597         qwi->features = array[w];
1598
1599         /* List will be in reverse order, but order shouldn't matter */
1600         list_entries[w].next = list;
1601         list_entries[w].value = &word_infos[w];
1602         list = &list_entries[w];
1603     }
1604
1605     visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1606     error_propagate(errp, err);
1607 }
1608
1609 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1610                                  const char *name, Error **errp)
1611 {
1612     X86CPU *cpu = X86_CPU(obj);
1613     int64_t value = cpu->hyperv_spinlock_attempts;
1614
1615     visit_type_int(v, &value, name, errp);
1616 }
1617
1618 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1619                                  const char *name, Error **errp)
1620 {
1621     const int64_t min = 0xFFF;
1622     const int64_t max = UINT_MAX;
1623     X86CPU *cpu = X86_CPU(obj);
1624     Error *err = NULL;
1625     int64_t value;
1626
1627     visit_type_int(v, &value, name, &err);
1628     if (err) {
1629         error_propagate(errp, err);
1630         return;
1631     }
1632
1633     if (value < min || value > max) {
1634         error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1635                   " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1636                   object_get_typename(obj), name ? name : "null",
1637                   value, min, max);
1638         return;
1639     }
1640     cpu->hyperv_spinlock_attempts = value;
1641 }
1642
1643 static PropertyInfo qdev_prop_spinlocks = {
1644     .name  = "int",
1645     .get   = x86_get_hv_spinlocks,
1646     .set   = x86_set_hv_spinlocks,
1647 };
1648
1649 /* Convert all '_' in a feature string option name to '-', to make feature
1650  * name conform to QOM property naming rule, which uses '-' instead of '_'.
1651  */
1652 static inline void feat2prop(char *s)
1653 {
1654     while ((s = strchr(s, '_'))) {
1655         *s = '-';
1656     }
1657 }
1658
1659 /* Parse "+feature,-feature,feature=foo" CPU feature string
1660  */
1661 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1662                                      Error **errp)
1663 {
1664     X86CPU *cpu = X86_CPU(cs);
1665     char *featurestr; /* Single 'key=value" string being parsed */
1666     /* Features to be added */
1667     FeatureWordArray plus_features = { 0 };
1668     /* Features to be removed */
1669     FeatureWordArray minus_features = { 0 };
1670     uint32_t numvalue;
1671     CPUX86State *env = &cpu->env;
1672     Error *local_err = NULL;
1673
1674     featurestr = features ? strtok(features, ",") : NULL;
1675
1676     while (featurestr) {
1677         char *val;
1678         if (featurestr[0] == '+') {
1679             add_flagname_to_bitmaps(featurestr + 1, plus_features);
1680         } else if (featurestr[0] == '-') {
1681             add_flagname_to_bitmaps(featurestr + 1, minus_features);
1682         } else if ((val = strchr(featurestr, '='))) {
1683             *val = 0; val++;
1684             feat2prop(featurestr);
1685             if (!strcmp(featurestr, "xlevel")) {
1686                 char *err;
1687                 char num[32];
1688
1689                 numvalue = strtoul(val, &err, 0);
1690                 if (!*val || *err) {
1691                     error_setg(&local_err, "bad numerical value %s", val);
1692                     goto out;
1693                 }
1694                 if (numvalue < 0x80000000) {
1695                     error_report("xlevel value shall always be >= 0x80000000"
1696                                  ", fixup will be removed in future versions");
1697                     numvalue += 0x80000000;
1698                 }
1699                 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1700                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1701             } else if (!strcmp(featurestr, "tsc-freq")) {
1702                 int64_t tsc_freq;
1703                 char *err;
1704                 char num[32];
1705
1706                 tsc_freq = strtosz_suffix_unit(val, &err,
1707                                                STRTOSZ_DEFSUFFIX_B, 1000);
1708                 if (tsc_freq < 0 || *err) {
1709                     error_setg(&local_err, "bad numerical value %s", val);
1710                     goto out;
1711                 }
1712                 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1713                 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1714                                       &local_err);
1715             } else if (!strcmp(featurestr, "hv-spinlocks")) {
1716                 char *err;
1717                 const int min = 0xFFF;
1718                 char num[32];
1719                 numvalue = strtoul(val, &err, 0);
1720                 if (!*val || *err) {
1721                     error_setg(&local_err, "bad numerical value %s", val);
1722                     goto out;
1723                 }
1724                 if (numvalue < min) {
1725                     error_report("hv-spinlocks value shall always be >= 0x%x"
1726                             ", fixup will be removed in future versions",
1727                             min);
1728                     numvalue = min;
1729                 }
1730                 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1731                 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1732             } else {
1733                 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1734             }
1735         } else {
1736             feat2prop(featurestr);
1737             object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1738         }
1739         if (local_err) {
1740             error_propagate(errp, local_err);
1741             goto out;
1742         }
1743         featurestr = strtok(NULL, ",");
1744     }
1745     env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1746     env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1747     env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1748     env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1749     env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1750     env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1751     env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1752     env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1753     env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1754     env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1755     env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1756     env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1757     env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1758     env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1759     env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1760     env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1761
1762 out:
1763     return;
1764 }
1765
1766 /* generate a composite string into buf of all cpuid names in featureset
1767  * selected by fbits.  indicate truncation at bufsize in the event of overflow.
1768  * if flags, suppress names undefined in featureset.
1769  */
1770 static void listflags(char *buf, int bufsize, uint32_t fbits,
1771     const char **featureset, uint32_t flags)
1772 {
1773     const char **p = &featureset[31];
1774     char *q, *b, bit;
1775     int nc;
1776
1777     b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1778     *buf = '\0';
1779     for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1780         if (fbits & 1 << bit && (*p || !flags)) {
1781             if (*p)
1782                 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1783             else
1784                 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1785             if (bufsize <= nc) {
1786                 if (b) {
1787                     memcpy(b, "...", sizeof("..."));
1788                 }
1789                 return;
1790             }
1791             q += nc;
1792             bufsize -= nc;
1793         }
1794 }
1795
1796 /* generate CPU information. */
1797 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1798 {
1799     X86CPUDefinition *def;
1800     char buf[256];
1801     int i;
1802
1803     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1804         def = &builtin_x86_defs[i];
1805         snprintf(buf, sizeof(buf), "%s", def->name);
1806         (*cpu_fprintf)(f, "x86 %16s  %-48s\n", buf, def->model_id);
1807     }
1808 #ifdef CONFIG_KVM
1809     (*cpu_fprintf)(f, "x86 %16s  %-48s\n", "host",
1810                    "KVM processor with all supported host features "
1811                    "(only available in KVM mode)");
1812 #endif
1813
1814     (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1815     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1816         FeatureWordInfo *fw = &feature_word_info[i];
1817
1818         listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1819         (*cpu_fprintf)(f, "  %s\n", buf);
1820     }
1821 }
1822
1823 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1824 {
1825     CpuDefinitionInfoList *cpu_list = NULL;
1826     X86CPUDefinition *def;
1827     int i;
1828
1829     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1830         CpuDefinitionInfoList *entry;
1831         CpuDefinitionInfo *info;
1832
1833         def = &builtin_x86_defs[i];
1834         info = g_malloc0(sizeof(*info));
1835         info->name = g_strdup(def->name);
1836
1837         entry = g_malloc0(sizeof(*entry));
1838         entry->value = info;
1839         entry->next = cpu_list;
1840         cpu_list = entry;
1841     }
1842
1843     return cpu_list;
1844 }
1845
1846 static void filter_features_for_kvm(X86CPU *cpu)
1847 {
1848     CPUX86State *env = &cpu->env;
1849     KVMState *s = kvm_state;
1850     FeatureWord w;
1851
1852     for (w = 0; w < FEATURE_WORDS; w++) {
1853         FeatureWordInfo *wi = &feature_word_info[w];
1854         uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1855                                                              wi->cpuid_ecx,
1856                                                              wi->cpuid_reg);
1857         uint32_t requested_features = env->features[w];
1858         env->features[w] &= host_feat;
1859         cpu->filtered_features[w] = requested_features & ~env->features[w];
1860     }
1861 }
1862
1863 /* Load data from X86CPUDefinition
1864  */
1865 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1866 {
1867     CPUX86State *env = &cpu->env;
1868     const char *vendor;
1869     char host_vendor[CPUID_VENDOR_SZ + 1];
1870
1871     object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1872     object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1873     object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1874     object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1875     env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1876     env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1877     env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1878     env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1879     object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1880     env->features[FEAT_KVM] = def->features[FEAT_KVM];
1881     env->features[FEAT_SVM] = def->features[FEAT_SVM];
1882     env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1883     env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1884     env->cpuid_xlevel2 = def->xlevel2;
1885     cpu->cache_info_passthrough = def->cache_info_passthrough;
1886
1887     object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1888
1889     /* Special cases not set in the X86CPUDefinition structs: */
1890     if (kvm_enabled()) {
1891         FeatureWord w;
1892         for (w = 0; w < FEATURE_WORDS; w++) {
1893             env->features[w] |= kvm_default_features[w];
1894         }
1895     }
1896
1897     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1898
1899     /* sysenter isn't supported in compatibility mode on AMD,
1900      * syscall isn't supported in compatibility mode on Intel.
1901      * Normally we advertise the actual CPU vendor, but you can
1902      * override this using the 'vendor' property if you want to use
1903      * KVM's sysenter/syscall emulation in compatibility mode and
1904      * when doing cross vendor migration
1905      */
1906     vendor = def->vendor;
1907     if (kvm_enabled()) {
1908         uint32_t  ebx = 0, ecx = 0, edx = 0;
1909         host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1910         x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1911         vendor = host_vendor;
1912     }
1913
1914     object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1915
1916 }
1917
1918 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1919                        Error **errp)
1920 {
1921     X86CPU *cpu = NULL;
1922     X86CPUClass *xcc;
1923     ObjectClass *oc;
1924     gchar **model_pieces;
1925     char *name, *features;
1926     Error *error = NULL;
1927
1928     model_pieces = g_strsplit(cpu_model, ",", 2);
1929     if (!model_pieces[0]) {
1930         error_setg(&error, "Invalid/empty CPU model name");
1931         goto out;
1932     }
1933     name = model_pieces[0];
1934     features = model_pieces[1];
1935
1936     oc = x86_cpu_class_by_name(name);
1937     if (oc == NULL) {
1938         error_setg(&error, "Unable to find CPU definition: %s", name);
1939         goto out;
1940     }
1941     xcc = X86_CPU_CLASS(oc);
1942
1943     if (xcc->kvm_required && !kvm_enabled()) {
1944         error_setg(&error, "CPU model '%s' requires KVM", name);
1945         goto out;
1946     }
1947
1948     cpu = X86_CPU(object_new(object_class_get_name(oc)));
1949
1950 #ifndef CONFIG_USER_ONLY
1951     if (icc_bridge == NULL) {
1952         error_setg(&error, "Invalid icc-bridge value");
1953         goto out;
1954     }
1955     qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1956     object_unref(OBJECT(cpu));
1957 #endif
1958
1959     x86_cpu_parse_featurestr(CPU(cpu), features, &error);
1960     if (error) {
1961         goto out;
1962     }
1963
1964 out:
1965     if (error != NULL) {
1966         error_propagate(errp, error);
1967         if (cpu) {
1968             object_unref(OBJECT(cpu));
1969             cpu = NULL;
1970         }
1971     }
1972     g_strfreev(model_pieces);
1973     return cpu;
1974 }
1975
1976 X86CPU *cpu_x86_init(const char *cpu_model)
1977 {
1978     Error *error = NULL;
1979     X86CPU *cpu;
1980
1981     cpu = cpu_x86_create(cpu_model, NULL, &error);
1982     if (error) {
1983         goto out;
1984     }
1985
1986     object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1987
1988 out:
1989     if (error) {
1990         error_report("%s", error_get_pretty(error));
1991         error_free(error);
1992         if (cpu != NULL) {
1993             object_unref(OBJECT(cpu));
1994             cpu = NULL;
1995         }
1996     }
1997     return cpu;
1998 }
1999
2000 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2001 {
2002     X86CPUDefinition *cpudef = data;
2003     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2004
2005     xcc->cpu_def = cpudef;
2006 }
2007
2008 static void x86_register_cpudef_type(X86CPUDefinition *def)
2009 {
2010     char *typename = x86_cpu_type_name(def->name);
2011     TypeInfo ti = {
2012         .name = typename,
2013         .parent = TYPE_X86_CPU,
2014         .class_init = x86_cpu_cpudef_class_init,
2015         .class_data = def,
2016     };
2017
2018     type_register(&ti);
2019     g_free(typename);
2020 }
2021
2022 #if !defined(CONFIG_USER_ONLY)
2023
2024 void cpu_clear_apic_feature(CPUX86State *env)
2025 {
2026     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2027 }
2028
2029 #endif /* !CONFIG_USER_ONLY */
2030
2031 /* Initialize list of CPU models, filling some non-static fields if necessary
2032  */
2033 void x86_cpudef_setup(void)
2034 {
2035     int i, j;
2036     static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2037
2038     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2039         X86CPUDefinition *def = &builtin_x86_defs[i];
2040
2041         /* Look for specific "cpudef" models that */
2042         /* have the QEMU version in .model_id */
2043         for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2044             if (strcmp(model_with_versions[j], def->name) == 0) {
2045                 pstrcpy(def->model_id, sizeof(def->model_id),
2046                         "QEMU Virtual CPU version ");
2047                 pstrcat(def->model_id, sizeof(def->model_id),
2048                         qemu_get_version());
2049                 break;
2050             }
2051         }
2052     }
2053 }
2054
2055 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2056                              uint32_t *ecx, uint32_t *edx)
2057 {
2058     *ebx = env->cpuid_vendor1;
2059     *edx = env->cpuid_vendor2;
2060     *ecx = env->cpuid_vendor3;
2061 }
2062
2063 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2064                    uint32_t *eax, uint32_t *ebx,
2065                    uint32_t *ecx, uint32_t *edx)
2066 {
2067     X86CPU *cpu = x86_env_get_cpu(env);
2068     CPUState *cs = CPU(cpu);
2069
2070     /* test if maximum index reached */
2071     if (index & 0x80000000) {
2072         if (index > env->cpuid_xlevel) {
2073             if (env->cpuid_xlevel2 > 0) {
2074                 /* Handle the Centaur's CPUID instruction. */
2075                 if (index > env->cpuid_xlevel2) {
2076                     index = env->cpuid_xlevel2;
2077                 } else if (index < 0xC0000000) {
2078                     index = env->cpuid_xlevel;
2079                 }
2080             } else {
2081                 /* Intel documentation states that invalid EAX input will
2082                  * return the same information as EAX=cpuid_level
2083                  * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2084                  */
2085                 index =  env->cpuid_level;
2086             }
2087         }
2088     } else {
2089         if (index > env->cpuid_level)
2090             index = env->cpuid_level;
2091     }
2092
2093     switch(index) {
2094     case 0:
2095         *eax = env->cpuid_level;
2096         get_cpuid_vendor(env, ebx, ecx, edx);
2097         break;
2098     case 1:
2099         *eax = env->cpuid_version;
2100         *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2101         *ecx = env->features[FEAT_1_ECX];
2102         *edx = env->features[FEAT_1_EDX];
2103         if (cs->nr_cores * cs->nr_threads > 1) {
2104             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2105             *edx |= 1 << 28;    /* HTT bit */
2106         }
2107         break;
2108     case 2:
2109         /* cache info: needed for Pentium Pro compatibility */
2110         if (cpu->cache_info_passthrough) {
2111             host_cpuid(index, 0, eax, ebx, ecx, edx);
2112             break;
2113         }
2114         *eax = 1; /* Number of CPUID[EAX=2] calls required */
2115         *ebx = 0;
2116         *ecx = 0;
2117         *edx = (L1D_DESCRIPTOR << 16) | \
2118                (L1I_DESCRIPTOR <<  8) | \
2119                (L2_DESCRIPTOR);
2120         break;
2121     case 4:
2122         /* cache info: needed for Core compatibility */
2123         if (cpu->cache_info_passthrough) {
2124             host_cpuid(index, count, eax, ebx, ecx, edx);
2125             *eax &= ~0xFC000000;
2126         } else {
2127             *eax = 0;
2128             switch (count) {
2129             case 0: /* L1 dcache info */
2130                 *eax |= CPUID_4_TYPE_DCACHE | \
2131                         CPUID_4_LEVEL(1) | \
2132                         CPUID_4_SELF_INIT_LEVEL;
2133                 *ebx = (L1D_LINE_SIZE - 1) | \
2134                        ((L1D_PARTITIONS - 1) << 12) | \
2135                        ((L1D_ASSOCIATIVITY - 1) << 22);
2136                 *ecx = L1D_SETS - 1;
2137                 *edx = CPUID_4_NO_INVD_SHARING;
2138                 break;
2139             case 1: /* L1 icache info */
2140                 *eax |= CPUID_4_TYPE_ICACHE | \
2141                         CPUID_4_LEVEL(1) | \
2142                         CPUID_4_SELF_INIT_LEVEL;
2143                 *ebx = (L1I_LINE_SIZE - 1) | \
2144                        ((L1I_PARTITIONS - 1) << 12) | \
2145                        ((L1I_ASSOCIATIVITY - 1) << 22);
2146                 *ecx = L1I_SETS - 1;
2147                 *edx = CPUID_4_NO_INVD_SHARING;
2148                 break;
2149             case 2: /* L2 cache info */
2150                 *eax |= CPUID_4_TYPE_UNIFIED | \
2151                         CPUID_4_LEVEL(2) | \
2152                         CPUID_4_SELF_INIT_LEVEL;
2153                 if (cs->nr_threads > 1) {
2154                     *eax |= (cs->nr_threads - 1) << 14;
2155                 }
2156                 *ebx = (L2_LINE_SIZE - 1) | \
2157                        ((L2_PARTITIONS - 1) << 12) | \
2158                        ((L2_ASSOCIATIVITY - 1) << 22);
2159                 *ecx = L2_SETS - 1;
2160                 *edx = CPUID_4_NO_INVD_SHARING;
2161                 break;
2162             default: /* end of info */
2163                 *eax = 0;
2164                 *ebx = 0;
2165                 *ecx = 0;
2166                 *edx = 0;
2167                 break;
2168             }
2169         }
2170
2171         /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  */
2172         if ((*eax & 31) && cs->nr_cores > 1) {
2173             *eax |= (cs->nr_cores - 1) << 26;
2174         }
2175         break;
2176     case 5:
2177         /* mwait info: needed for Core compatibility */
2178         *eax = 0; /* Smallest monitor-line size in bytes */
2179         *ebx = 0; /* Largest monitor-line size in bytes */
2180         *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2181         *edx = 0;
2182         break;
2183     case 6:
2184         /* Thermal and Power Leaf */
2185         *eax = 0;
2186         *ebx = 0;
2187         *ecx = 0;
2188         *edx = 0;
2189         break;
2190     case 7:
2191         /* Structured Extended Feature Flags Enumeration Leaf */
2192         if (count == 0) {
2193             *eax = 0; /* Maximum ECX value for sub-leaves */
2194             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2195             *ecx = 0; /* Reserved */
2196             *edx = 0; /* Reserved */
2197         } else {
2198             *eax = 0;
2199             *ebx = 0;
2200             *ecx = 0;
2201             *edx = 0;
2202         }
2203         break;
2204     case 9:
2205         /* Direct Cache Access Information Leaf */
2206         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2207         *ebx = 0;
2208         *ecx = 0;
2209         *edx = 0;
2210         break;
2211     case 0xA:
2212         /* Architectural Performance Monitoring Leaf */
2213         if (kvm_enabled() && cpu->enable_pmu) {
2214             KVMState *s = cs->kvm_state;
2215
2216             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2217             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2218             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2219             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2220         } else {
2221             *eax = 0;
2222             *ebx = 0;
2223             *ecx = 0;
2224             *edx = 0;
2225         }
2226         break;
2227     case 0xD: {
2228         KVMState *s = cs->kvm_state;
2229         uint64_t kvm_mask;
2230         int i;
2231
2232         /* Processor Extended State */
2233         *eax = 0;
2234         *ebx = 0;
2235         *ecx = 0;
2236         *edx = 0;
2237         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2238             break;
2239         }
2240         kvm_mask =
2241             kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2242             ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2243
2244         if (count == 0) {
2245             *ecx = 0x240;
2246             for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2247                 const ExtSaveArea *esa = &ext_save_areas[i];
2248                 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2249                     (kvm_mask & (1 << i)) != 0) {
2250                     if (i < 32) {
2251                         *eax |= 1 << i;
2252                     } else {
2253                         *edx |= 1 << (i - 32);
2254                     }
2255                     *ecx = MAX(*ecx, esa->offset + esa->size);
2256                 }
2257             }
2258             *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2259             *ebx = *ecx;
2260         } else if (count == 1) {
2261             *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2262         } else if (count < ARRAY_SIZE(ext_save_areas)) {
2263             const ExtSaveArea *esa = &ext_save_areas[count];
2264             if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2265                 (kvm_mask & (1 << count)) != 0) {
2266                 *eax = esa->size;
2267                 *ebx = esa->offset;
2268             }
2269         }
2270         break;
2271     }
2272     case 0x80000000:
2273         *eax = env->cpuid_xlevel;
2274         *ebx = env->cpuid_vendor1;
2275         *edx = env->cpuid_vendor2;
2276         *ecx = env->cpuid_vendor3;
2277         break;
2278     case 0x80000001:
2279         *eax = env->cpuid_version;
2280         *ebx = 0;
2281         *ecx = env->features[FEAT_8000_0001_ECX];
2282         *edx = env->features[FEAT_8000_0001_EDX];
2283
2284         /* The Linux kernel checks for the CMPLegacy bit and
2285          * discards multiple thread information if it is set.
2286          * So dont set it here for Intel to make Linux guests happy.
2287          */
2288         if (cs->nr_cores * cs->nr_threads > 1) {
2289             uint32_t tebx, tecx, tedx;
2290             get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2291             if (tebx != CPUID_VENDOR_INTEL_1 ||
2292                 tedx != CPUID_VENDOR_INTEL_2 ||
2293                 tecx != CPUID_VENDOR_INTEL_3) {
2294                 *ecx |= 1 << 1;    /* CmpLegacy bit */
2295             }
2296         }
2297         break;
2298     case 0x80000002:
2299     case 0x80000003:
2300     case 0x80000004:
2301         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2302         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2303         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2304         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2305         break;
2306     case 0x80000005:
2307         /* cache info (L1 cache) */
2308         if (cpu->cache_info_passthrough) {
2309             host_cpuid(index, 0, eax, ebx, ecx, edx);
2310             break;
2311         }
2312         *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2313                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
2314         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2315                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
2316         *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2317                (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2318         *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2319                (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2320         break;
2321     case 0x80000006:
2322         /* cache info (L2 cache) */
2323         if (cpu->cache_info_passthrough) {
2324             host_cpuid(index, 0, eax, ebx, ecx, edx);
2325             break;
2326         }
2327         *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2328                (L2_DTLB_2M_ENTRIES << 16) | \
2329                (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2330                (L2_ITLB_2M_ENTRIES);
2331         *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2332                (L2_DTLB_4K_ENTRIES << 16) | \
2333                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2334                (L2_ITLB_4K_ENTRIES);
2335         *ecx = (L2_SIZE_KB_AMD << 16) | \
2336                (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2337                (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2338         *edx = ((L3_SIZE_KB/512) << 18) | \
2339                (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2340                (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2341         break;
2342     case 0x80000008:
2343         /* virtual & phys address size in low 2 bytes. */
2344 /* XXX: This value must match the one used in the MMU code. */
2345         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2346             /* 64 bit processor */
2347 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2348             *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2349         } else {
2350             if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2351                 *eax = 0x00000024; /* 36 bits physical */
2352             } else {
2353                 *eax = 0x00000020; /* 32 bits physical */
2354             }
2355         }
2356         *ebx = 0;
2357         *ecx = 0;
2358         *edx = 0;
2359         if (cs->nr_cores * cs->nr_threads > 1) {
2360             *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2361         }
2362         break;
2363     case 0x8000000A:
2364         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2365             *eax = 0x00000001; /* SVM Revision */
2366             *ebx = 0x00000010; /* nr of ASIDs */
2367             *ecx = 0;
2368             *edx = env->features[FEAT_SVM]; /* optional features */
2369         } else {
2370             *eax = 0;
2371             *ebx = 0;
2372             *ecx = 0;
2373             *edx = 0;
2374         }
2375         break;
2376     case 0xC0000000:
2377         *eax = env->cpuid_xlevel2;
2378         *ebx = 0;
2379         *ecx = 0;
2380         *edx = 0;
2381         break;
2382     case 0xC0000001:
2383         /* Support for VIA CPU's CPUID instruction */
2384         *eax = env->cpuid_version;
2385         *ebx = 0;
2386         *ecx = 0;
2387         *edx = env->features[FEAT_C000_0001_EDX];
2388         break;
2389     case 0xC0000002:
2390     case 0xC0000003:
2391     case 0xC0000004:
2392         /* Reserved for the future, and now filled with zero */
2393         *eax = 0;
2394         *ebx = 0;
2395         *ecx = 0;
2396         *edx = 0;
2397         break;
2398     default:
2399         /* reserved values: zero */
2400         *eax = 0;
2401         *ebx = 0;
2402         *ecx = 0;
2403         *edx = 0;
2404         break;
2405     }
2406 }
2407
2408 /* CPUClass::reset() */
2409 static void x86_cpu_reset(CPUState *s)
2410 {
2411     X86CPU *cpu = X86_CPU(s);
2412     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2413     CPUX86State *env = &cpu->env;
2414     int i;
2415
2416     xcc->parent_reset(s);
2417
2418     memset(env, 0, offsetof(CPUX86State, cpuid_level));
2419
2420     tlb_flush(s, 1);
2421
2422     env->old_exception = -1;
2423
2424     /* init to reset state */
2425
2426 #ifdef CONFIG_SOFTMMU
2427     env->hflags |= HF_SOFTMMU_MASK;
2428 #endif
2429     env->hflags2 |= HF2_GIF_MASK;
2430
2431     cpu_x86_update_cr0(env, 0x60000010);
2432     env->a20_mask = ~0x0;
2433     env->smbase = 0x30000;
2434
2435     env->idt.limit = 0xffff;
2436     env->gdt.limit = 0xffff;
2437     env->ldt.limit = 0xffff;
2438     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2439     env->tr.limit = 0xffff;
2440     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2441
2442     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2443                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2444                            DESC_R_MASK | DESC_A_MASK);
2445     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2446                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2447                            DESC_A_MASK);
2448     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2449                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2450                            DESC_A_MASK);
2451     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2452                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2453                            DESC_A_MASK);
2454     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2455                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2456                            DESC_A_MASK);
2457     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2458                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2459                            DESC_A_MASK);
2460
2461     env->eip = 0xfff0;
2462     env->regs[R_EDX] = env->cpuid_version;
2463
2464     env->eflags = 0x2;
2465
2466     /* FPU init */
2467     for (i = 0; i < 8; i++) {
2468         env->fptags[i] = 1;
2469     }
2470     env->fpuc = 0x37f;
2471
2472     env->mxcsr = 0x1f80;
2473     env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2474
2475     env->pat = 0x0007040600070406ULL;
2476     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2477
2478     memset(env->dr, 0, sizeof(env->dr));
2479     env->dr[6] = DR6_FIXED_1;
2480     env->dr[7] = DR7_FIXED_1;
2481     cpu_breakpoint_remove_all(s, BP_CPU);
2482     cpu_watchpoint_remove_all(s, BP_CPU);
2483
2484     env->xcr0 = 1;
2485
2486 #if !defined(CONFIG_USER_ONLY)
2487     /* We hard-wire the BSP to the first CPU. */
2488     if (s->cpu_index == 0) {
2489         apic_designate_bsp(cpu->apic_state);
2490     }
2491
2492     s->halted = !cpu_is_bsp(cpu);
2493
2494     if (kvm_enabled()) {
2495         kvm_arch_reset_vcpu(cpu);
2496     }
2497 #endif
2498 }
2499
2500 #ifndef CONFIG_USER_ONLY
2501 bool cpu_is_bsp(X86CPU *cpu)
2502 {
2503     return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2504 }
2505
2506 /* TODO: remove me, when reset over QOM tree is implemented */
2507 static void x86_cpu_machine_reset_cb(void *opaque)
2508 {
2509     X86CPU *cpu = opaque;
2510     cpu_reset(CPU(cpu));
2511 }
2512 #endif
2513
2514 static void mce_init(X86CPU *cpu)
2515 {
2516     CPUX86State *cenv = &cpu->env;
2517     unsigned int bank;
2518
2519     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2520         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2521             (CPUID_MCE | CPUID_MCA)) {
2522         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2523         cenv->mcg_ctl = ~(uint64_t)0;
2524         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2525             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2526         }
2527     }
2528 }
2529
2530 #ifndef CONFIG_USER_ONLY
2531 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2532 {
2533     CPUX86State *env = &cpu->env;
2534     DeviceState *dev = DEVICE(cpu);
2535     APICCommonState *apic;
2536     const char *apic_type = "apic";
2537
2538     if (kvm_irqchip_in_kernel()) {
2539         apic_type = "kvm-apic";
2540     } else if (xen_enabled()) {
2541         apic_type = "xen-apic";
2542     }
2543
2544     cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2545     if (cpu->apic_state == NULL) {
2546         error_setg(errp, "APIC device '%s' could not be created", apic_type);
2547         return;
2548     }
2549
2550     object_property_add_child(OBJECT(cpu), "apic",
2551                               OBJECT(cpu->apic_state), NULL);
2552     qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2553     /* TODO: convert to link<> */
2554     apic = APIC_COMMON(cpu->apic_state);
2555     apic->cpu = cpu;
2556 }
2557
2558 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2559 {
2560     if (cpu->apic_state == NULL) {
2561         return;
2562     }
2563
2564     if (qdev_init(cpu->apic_state)) {
2565         error_setg(errp, "APIC device '%s' could not be initialized",
2566                    object_get_typename(OBJECT(cpu->apic_state)));
2567         return;
2568     }
2569 }
2570 #else
2571 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2572 {
2573 }
2574 #endif
2575
2576 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2577 {
2578     CPUState *cs = CPU(dev);
2579     X86CPU *cpu = X86_CPU(dev);
2580     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2581     CPUX86State *env = &cpu->env;
2582     Error *local_err = NULL;
2583
2584     if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2585         env->cpuid_level = 7;
2586     }
2587
2588     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2589      * CPUID[1].EDX.
2590      */
2591     if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2592         env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2593         env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2594         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2595         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2596            & CPUID_EXT2_AMD_ALIASES);
2597     }
2598
2599     if (!kvm_enabled()) {
2600         env->features[FEAT_1_EDX] &= TCG_FEATURES;
2601         env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2602         env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2603 #ifdef TARGET_X86_64
2604             | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2605 #endif
2606             );
2607         env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2608         env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2609     } else {
2610         KVMState *s = kvm_state;
2611         if ((cpu->check_cpuid || cpu->enforce_cpuid)
2612             && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
2613             error_setg(&local_err,
2614                        "Host's CPU doesn't support requested features");
2615             goto out;
2616         }
2617         filter_features_for_kvm(cpu);
2618     }
2619
2620 #ifndef CONFIG_USER_ONLY
2621     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2622
2623     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2624         x86_cpu_apic_create(cpu, &local_err);
2625         if (local_err != NULL) {
2626             goto out;
2627         }
2628     }
2629 #endif
2630
2631     mce_init(cpu);
2632     qemu_init_vcpu(cs);
2633
2634     x86_cpu_apic_realize(cpu, &local_err);
2635     if (local_err != NULL) {
2636         goto out;
2637     }
2638     cpu_reset(cs);
2639
2640     xcc->parent_realize(dev, &local_err);
2641 out:
2642     if (local_err != NULL) {
2643         error_propagate(errp, local_err);
2644         return;
2645     }
2646 }
2647
2648 /* Enables contiguous-apic-ID mode, for compatibility */
2649 static bool compat_apic_id_mode;
2650
2651 void enable_compat_apic_id_mode(void)
2652 {
2653     compat_apic_id_mode = true;
2654 }
2655
2656 /* Calculates initial APIC ID for a specific CPU index
2657  *
2658  * Currently we need to be able to calculate the APIC ID from the CPU index
2659  * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2660  * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2661  * all CPUs up to max_cpus.
2662  */
2663 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2664 {
2665     uint32_t correct_id;
2666     static bool warned;
2667
2668     correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2669     if (compat_apic_id_mode) {
2670         if (cpu_index != correct_id && !warned) {
2671             error_report("APIC IDs set in compatibility mode, "
2672                          "CPU topology won't match the configuration");
2673             warned = true;
2674         }
2675         return cpu_index;
2676     } else {
2677         return correct_id;
2678     }
2679 }
2680
2681 static void x86_cpu_initfn(Object *obj)
2682 {
2683     CPUState *cs = CPU(obj);
2684     X86CPU *cpu = X86_CPU(obj);
2685     X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2686     CPUX86State *env = &cpu->env;
2687     static int inited;
2688
2689     cs->env_ptr = env;
2690     cpu_exec_init(env);
2691
2692     object_property_add(obj, "family", "int",
2693                         x86_cpuid_version_get_family,
2694                         x86_cpuid_version_set_family, NULL, NULL, NULL);
2695     object_property_add(obj, "model", "int",
2696                         x86_cpuid_version_get_model,
2697                         x86_cpuid_version_set_model, NULL, NULL, NULL);
2698     object_property_add(obj, "stepping", "int",
2699                         x86_cpuid_version_get_stepping,
2700                         x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2701     object_property_add(obj, "level", "int",
2702                         x86_cpuid_get_level,
2703                         x86_cpuid_set_level, NULL, NULL, NULL);
2704     object_property_add(obj, "xlevel", "int",
2705                         x86_cpuid_get_xlevel,
2706                         x86_cpuid_set_xlevel, NULL, NULL, NULL);
2707     object_property_add_str(obj, "vendor",
2708                             x86_cpuid_get_vendor,
2709                             x86_cpuid_set_vendor, NULL);
2710     object_property_add_str(obj, "model-id",
2711                             x86_cpuid_get_model_id,
2712                             x86_cpuid_set_model_id, NULL);
2713     object_property_add(obj, "tsc-frequency", "int",
2714                         x86_cpuid_get_tsc_freq,
2715                         x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2716     object_property_add(obj, "apic-id", "int",
2717                         x86_cpuid_get_apic_id,
2718                         x86_cpuid_set_apic_id, NULL, NULL, NULL);
2719     object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2720                         x86_cpu_get_feature_words,
2721                         NULL, NULL, (void *)env->features, NULL);
2722     object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2723                         x86_cpu_get_feature_words,
2724                         NULL, NULL, (void *)cpu->filtered_features, NULL);
2725
2726     cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2727     env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2728
2729     x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2730
2731     /* init various static tables used in TCG mode */
2732     if (tcg_enabled() && !inited) {
2733         inited = 1;
2734         optimize_flags_init();
2735 #ifndef CONFIG_USER_ONLY
2736         cpu_set_debug_excp_handler(breakpoint_handler);
2737 #endif
2738     }
2739 }
2740
2741 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2742 {
2743     X86CPU *cpu = X86_CPU(cs);
2744     CPUX86State *env = &cpu->env;
2745
2746     return env->cpuid_apic_id;
2747 }
2748
2749 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2750 {
2751     X86CPU *cpu = X86_CPU(cs);
2752
2753     return cpu->env.cr[0] & CR0_PG_MASK;
2754 }
2755
2756 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2757 {
2758     X86CPU *cpu = X86_CPU(cs);
2759
2760     cpu->env.eip = value;
2761 }
2762
2763 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2764 {
2765     X86CPU *cpu = X86_CPU(cs);
2766
2767     cpu->env.eip = tb->pc - tb->cs_base;
2768 }
2769
2770 static bool x86_cpu_has_work(CPUState *cs)
2771 {
2772     X86CPU *cpu = X86_CPU(cs);
2773     CPUX86State *env = &cpu->env;
2774
2775     return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2776                                       CPU_INTERRUPT_POLL)) &&
2777             (env->eflags & IF_MASK)) ||
2778            (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2779                                      CPU_INTERRUPT_INIT |
2780                                      CPU_INTERRUPT_SIPI |
2781                                      CPU_INTERRUPT_MCE));
2782 }
2783
2784 static Property x86_cpu_properties[] = {
2785     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2786     { .name  = "hv-spinlocks", .info  = &qdev_prop_spinlocks },
2787     DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2788     DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2789     DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2790     DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2791     DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2792     DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
2793     DEFINE_PROP_END_OF_LIST()
2794 };
2795
2796 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2797 {
2798     X86CPUClass *xcc = X86_CPU_CLASS(oc);
2799     CPUClass *cc = CPU_CLASS(oc);
2800     DeviceClass *dc = DEVICE_CLASS(oc);
2801
2802     xcc->parent_realize = dc->realize;
2803     dc->realize = x86_cpu_realizefn;
2804     dc->bus_type = TYPE_ICC_BUS;
2805     dc->props = x86_cpu_properties;
2806
2807     xcc->parent_reset = cc->reset;
2808     cc->reset = x86_cpu_reset;
2809     cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2810
2811     cc->class_by_name = x86_cpu_class_by_name;
2812     cc->parse_features = x86_cpu_parse_featurestr;
2813     cc->has_work = x86_cpu_has_work;
2814     cc->do_interrupt = x86_cpu_do_interrupt;
2815     cc->dump_state = x86_cpu_dump_state;
2816     cc->set_pc = x86_cpu_set_pc;
2817     cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2818     cc->gdb_read_register = x86_cpu_gdb_read_register;
2819     cc->gdb_write_register = x86_cpu_gdb_write_register;
2820     cc->get_arch_id = x86_cpu_get_arch_id;
2821     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2822 #ifdef CONFIG_USER_ONLY
2823     cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2824 #else
2825     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2826     cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2827     cc->write_elf64_note = x86_cpu_write_elf64_note;
2828     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2829     cc->write_elf32_note = x86_cpu_write_elf32_note;
2830     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2831     cc->vmsd = &vmstate_x86_cpu;
2832 #endif
2833     cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2834 }
2835
2836 static const TypeInfo x86_cpu_type_info = {
2837     .name = TYPE_X86_CPU,
2838     .parent = TYPE_CPU,
2839     .instance_size = sizeof(X86CPU),
2840     .instance_init = x86_cpu_initfn,
2841     .abstract = true,
2842     .class_size = sizeof(X86CPUClass),
2843     .class_init = x86_cpu_common_class_init,
2844 };
2845
2846 static void x86_cpu_register_types(void)
2847 {
2848     int i;
2849
2850     type_register_static(&x86_cpu_type_info);
2851     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2852         x86_register_cpudef_type(&builtin_x86_defs[i]);
2853     }
2854 #ifdef CONFIG_KVM
2855     type_register_static(&host_x86_cpu_type_info);
2856 #endif
2857 }
2858
2859 type_init(x86_cpu_register_types)