target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     return cs->interrupt_request &
  44         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
  45 }
  46
  47 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  48 {
  49     /* Reset a single ARMCPRegInfo register */
  50     ARMCPRegInfo *ri = value;
  51     ARMCPU *cpu = opaque;
  52
  53     if (ri->type & ARM_CP_SPECIAL) {
  54         return;
  55     }
  56
  57     if (ri->resetfn) {
  58         ri->resetfn(&cpu->env, ri);
  59         return;
  60     }
  61
  62     /* A zero offset is never possible as it would be regs[0]
  63      * so we use it to indicate that reset is being handled elsewhere.
  64      * This is basically only used for fields in non-core coprocessors
  65      * (like the pxa2xx ones).
  66      */
  67     if (!ri->fieldoffset) {
  68         return;
  69     }
  70
  71     if (cpreg_field_is_64bit(ri)) {
  72         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  73     } else {
  74         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  75     }
  76 }
  77
  78 /* CPUClass::reset() */
  79 static void arm_cpu_reset(CPUState *s)
  80 {
  81     ARMCPU *cpu = ARM_CPU(s);
  82     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  83     CPUARMState *env = &cpu->env;
  84
  85     acc->parent_reset(s);
  86
  87     memset(env, 0, offsetof(CPUARMState, features));
  88     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  89     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  90     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  91     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  92     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  93
  94     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  95         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  96     }
  97
  98     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
  99         /* 64 bit CPUs always start in 64 bit mode */
 100         env->aarch64 = 1;
 101 #if defined(CONFIG_USER_ONLY)
 102         env->pstate = PSTATE_MODE_EL0t;
 103         /* Userspace expects access to CTL_EL0 and the cache ops */
 104         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 105         /* and to the FP/Neon instructions */
 106         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 107 #else
 108         env->pstate = PSTATE_MODE_EL1h;
 109         env->pc = cpu->rvbar;
 110 #endif
 111     } else {
 112 #if defined(CONFIG_USER_ONLY)
 113         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 115 #endif
 116     }
 117
 118 #if defined(CONFIG_USER_ONLY)
 119     env->uncached_cpsr = ARM_CPU_MODE_USR;
 120     /* For user mode we must enable access to coprocessors */
 121     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 122     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 123         env->cp15.c15_cpar = 3;
 124     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 125         env->cp15.c15_cpar = 1;
 126     }
 127 #else
 128     /* SVC mode with interrupts disabled.  */
 129     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 130     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 131     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 132        clear at reset.  Initial SP and PC are loaded from ROM.  */
 133     if (IS_M(env)) {
 134         uint32_t pc;
 135         uint8_t *rom;
 136         env->daif &= ~PSTATE_I;
 137         rom = rom_ptr(0);
 138         if (rom) {
 139             /* We should really use ldl_phys here, in case the guest
 140                modified flash and reset itself.  However images
 141                loaded via -kernel have not been copied yet, so load the
 142                values directly from there.  */
 143             env->regs[13] = ldl_p(rom) & 0xFFFFFFFC;
 144             pc = ldl_p(rom + 4);
 145             env->thumb = pc & 1;
 146             env->regs[15] = pc & ~1;
 147         }
 148     }
 149
 150     if (env->cp15.c1_sys & SCTLR_V) {
 151             env->regs[15] = 0xFFFF0000;
 152     }
 153
 154     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 155 #endif
 156     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 157     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 158     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 159     set_float_detect_tininess(float_tininess_before_rounding,
 160                               &env->vfp.fp_status);
 161     set_float_detect_tininess(float_tininess_before_rounding,
 162                               &env->vfp.standard_fp_status);
 163     tlb_flush(s, 1);
 164     /* Reset is a state change for some CPUARMState fields which we
 165      * bake assumptions about into translated code, so we need to
 166      * tb_flush().
 167      */
 168     tb_flush(env);
 169
 170 #ifndef CONFIG_USER_ONLY
 171     if (kvm_enabled()) {
 172         kvm_arm_reset_vcpu(cpu);
 173     }
 174 #endif
 175 }
 176
 177 #ifndef CONFIG_USER_ONLY
 178 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 179 {
 180     ARMCPU *cpu = opaque;
 181     CPUState *cs = CPU(cpu);
 182
 183     switch (irq) {
 184     case ARM_CPU_IRQ:
 185         if (level) {
 186             cpu_interrupt(cs, CPU_INTERRUPT_HARD);
 187         } else {
 188             cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
 189         }
 190         break;
 191     case ARM_CPU_FIQ:
 192         if (level) {
 193             cpu_interrupt(cs, CPU_INTERRUPT_FIQ);
 194         } else {
 195             cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);
 196         }
 197         break;
 198     default:
 199         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 200     }
 201 }
 202
 203 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 204 {
 205 #ifdef CONFIG_KVM
 206     ARMCPU *cpu = opaque;
 207     CPUState *cs = CPU(cpu);
 208     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 209
 210     switch (irq) {
 211     case ARM_CPU_IRQ:
 212         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 213         break;
 214     case ARM_CPU_FIQ:
 215         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 216         break;
 217     default:
 218         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 219     }
 220     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 221     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 222 #endif
 223 }
 224 #endif
 225
 226 static inline void set_feature(CPUARMState *env, int feature)
 227 {
 228     env->features |= 1ULL << feature;
 229 }
 230
 231 static void arm_cpu_initfn(Object *obj)
 232 {
 233     CPUState *cs = CPU(obj);
 234     ARMCPU *cpu = ARM_CPU(obj);
 235     static bool inited;
 236
 237     cs->env_ptr = &cpu->env;
 238     cpu_exec_init(&cpu->env);
 239     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 240                                          g_free, g_free);
 241
 242 #ifndef CONFIG_USER_ONLY
 243     /* Our inbound IRQ and FIQ lines */
 244     if (kvm_enabled()) {
 245         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
 246     } else {
 247         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
 248     }
 249
 250     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 251                                                 arm_gt_ptimer_cb, cpu);
 252     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 253                                                 arm_gt_vtimer_cb, cpu);
 254     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 255                        ARRAY_SIZE(cpu->gt_timer_outputs));
 256 #endif
 257
 258     /* DTB consumers generally don't in fact care what the 'compatible'
 259      * string is, so always provide some string and trust that a hypothetical
 260      * picky DTB consumer will also provide a helpful error message.
 261      */
 262     cpu->dtb_compatible = "qemu,unknown";
 263     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 264
 265     if (tcg_enabled() && !inited) {
 266         inited = true;
 267         arm_translate_init();
 268     }
 269 }
 270
 271 static Property arm_cpu_reset_cbar_property =
 272             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 273
 274 static Property arm_cpu_reset_hivecs_property =
 275             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 276
 277 static Property arm_cpu_rvbar_property =
 278             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 279
 280 static void arm_cpu_post_init(Object *obj)
 281 {
 282     ARMCPU *cpu = ARM_CPU(obj);
 283
 284     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 285         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 286         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 287                                  &error_abort);
 288     }
 289
 290     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 291         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 292                                  &error_abort);
 293     }
 294
 295     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 296         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 297                                  &error_abort);
 298     }
 299 }
 300
 301 static void arm_cpu_finalizefn(Object *obj)
 302 {
 303     ARMCPU *cpu = ARM_CPU(obj);
 304     g_hash_table_destroy(cpu->cp_regs);
 305 }
 306
 307 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 308 {
 309     CPUState *cs = CPU(dev);
 310     ARMCPU *cpu = ARM_CPU(dev);
 311     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 312     CPUARMState *env = &cpu->env;
 313
 314     /* Some features automatically imply others: */
 315     if (arm_feature(env, ARM_FEATURE_V8)) {
 316         set_feature(env, ARM_FEATURE_V7);
 317         set_feature(env, ARM_FEATURE_ARM_DIV);
 318         set_feature(env, ARM_FEATURE_LPAE);
 319         set_feature(env, ARM_FEATURE_V8_AES);
 320     }
 321     if (arm_feature(env, ARM_FEATURE_V7)) {
 322         set_feature(env, ARM_FEATURE_VAPA);
 323         set_feature(env, ARM_FEATURE_THUMB2);
 324         set_feature(env, ARM_FEATURE_MPIDR);
 325         if (!arm_feature(env, ARM_FEATURE_M)) {
 326             set_feature(env, ARM_FEATURE_V6K);
 327         } else {
 328             set_feature(env, ARM_FEATURE_V6);
 329         }
 330     }
 331     if (arm_feature(env, ARM_FEATURE_V6K)) {
 332         set_feature(env, ARM_FEATURE_V6);
 333         set_feature(env, ARM_FEATURE_MVFR);
 334     }
 335     if (arm_feature(env, ARM_FEATURE_V6)) {
 336         set_feature(env, ARM_FEATURE_V5);
 337         if (!arm_feature(env, ARM_FEATURE_M)) {
 338             set_feature(env, ARM_FEATURE_AUXCR);
 339         }
 340     }
 341     if (arm_feature(env, ARM_FEATURE_V5)) {
 342         set_feature(env, ARM_FEATURE_V4T);
 343     }
 344     if (arm_feature(env, ARM_FEATURE_M)) {
 345         set_feature(env, ARM_FEATURE_THUMB_DIV);
 346     }
 347     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 348         set_feature(env, ARM_FEATURE_THUMB_DIV);
 349     }
 350     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 351         set_feature(env, ARM_FEATURE_VFP3);
 352     }
 353     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 354         set_feature(env, ARM_FEATURE_VFP);
 355     }
 356     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 357         set_feature(env, ARM_FEATURE_V7MP);
 358         set_feature(env, ARM_FEATURE_PXN);
 359     }
 360     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 361         set_feature(env, ARM_FEATURE_CBAR);
 362     }
 363
 364     if (cpu->reset_hivecs) {
 365             cpu->reset_sctlr |= (1 << 13);
 366     }
 367
 368     register_cp_regs_for_features(cpu);
 369     arm_cpu_register_gdb_regs_for_features(cpu);
 370
 371     init_cpreg_list(cpu);
 372
 373     qemu_init_vcpu(cs);
 374     cpu_reset(cs);
 375
 376     acc->parent_realize(dev, errp);
 377 }
 378
 379 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 380 {
 381     ObjectClass *oc;
 382     char *typename;
 383
 384     if (!cpu_model) {
 385         return NULL;
 386     }
 387
 388     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 389     oc = object_class_by_name(typename);
 390     g_free(typename);
 391     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 392         object_class_is_abstract(oc)) {
 393         return NULL;
 394     }
 395     return oc;
 396 }
 397
 398 /* CPU models. These are not needed for the AArch64 linux-user build. */
 399 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 400
 401 static void arm926_initfn(Object *obj)
 402 {
 403     ARMCPU *cpu = ARM_CPU(obj);
 404
 405     cpu->dtb_compatible = "arm,arm926";
 406     set_feature(&cpu->env, ARM_FEATURE_V5);
 407     set_feature(&cpu->env, ARM_FEATURE_VFP);
 408     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 409     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 410     cpu->midr = 0x41069265;
 411     cpu->reset_fpsid = 0x41011090;
 412     cpu->ctr = 0x1dd20d2;
 413     cpu->reset_sctlr = 0x00090078;
 414 }
 415
 416 static void arm946_initfn(Object *obj)
 417 {
 418     ARMCPU *cpu = ARM_CPU(obj);
 419
 420     cpu->dtb_compatible = "arm,arm946";
 421     set_feature(&cpu->env, ARM_FEATURE_V5);
 422     set_feature(&cpu->env, ARM_FEATURE_MPU);
 423     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 424     cpu->midr = 0x41059461;
 425     cpu->ctr = 0x0f004006;
 426     cpu->reset_sctlr = 0x00000078;
 427 }
 428
 429 static void arm1026_initfn(Object *obj)
 430 {
 431     ARMCPU *cpu = ARM_CPU(obj);
 432
 433     cpu->dtb_compatible = "arm,arm1026";
 434     set_feature(&cpu->env, ARM_FEATURE_V5);
 435     set_feature(&cpu->env, ARM_FEATURE_VFP);
 436     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 437     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 438     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 439     cpu->midr = 0x4106a262;
 440     cpu->reset_fpsid = 0x410110a0;
 441     cpu->ctr = 0x1dd20d2;
 442     cpu->reset_sctlr = 0x00090078;
 443     cpu->reset_auxcr = 1;
 444     {
 445         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 446         ARMCPRegInfo ifar = {
 447             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 448             .access = PL1_RW,
 449             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),
 450             .resetvalue = 0
 451         };
 452         define_one_arm_cp_reg(cpu, &ifar);
 453     }
 454 }
 455
 456 static void arm1136_r2_initfn(Object *obj)
 457 {
 458     ARMCPU *cpu = ARM_CPU(obj);
 459     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 460      * older core than plain "arm1136". In particular this does not
 461      * have the v6K features.
 462      * These ID register values are correct for 1136 but may be wrong
 463      * for 1136_r2 (in particular r0p2 does not actually implement most
 464      * of the ID registers).
 465      */
 466
 467     cpu->dtb_compatible = "arm,arm1136";
 468     set_feature(&cpu->env, ARM_FEATURE_V6);
 469     set_feature(&cpu->env, ARM_FEATURE_VFP);
 470     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 471     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 472     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 473     cpu->midr = 0x4107b362;
 474     cpu->reset_fpsid = 0x410120b4;
 475     cpu->mvfr0 = 0x11111111;
 476     cpu->mvfr1 = 0x00000000;
 477     cpu->ctr = 0x1dd20d2;
 478     cpu->reset_sctlr = 0x00050078;
 479     cpu->id_pfr0 = 0x111;
 480     cpu->id_pfr1 = 0x1;
 481     cpu->id_dfr0 = 0x2;
 482     cpu->id_afr0 = 0x3;
 483     cpu->id_mmfr0 = 0x01130003;
 484     cpu->id_mmfr1 = 0x10030302;
 485     cpu->id_mmfr2 = 0x01222110;
 486     cpu->id_isar0 = 0x00140011;
 487     cpu->id_isar1 = 0x12002111;
 488     cpu->id_isar2 = 0x11231111;
 489     cpu->id_isar3 = 0x01102131;
 490     cpu->id_isar4 = 0x141;
 491     cpu->reset_auxcr = 7;
 492 }
 493
 494 static void arm1136_initfn(Object *obj)
 495 {
 496     ARMCPU *cpu = ARM_CPU(obj);
 497
 498     cpu->dtb_compatible = "arm,arm1136";
 499     set_feature(&cpu->env, ARM_FEATURE_V6K);
 500     set_feature(&cpu->env, ARM_FEATURE_V6);
 501     set_feature(&cpu->env, ARM_FEATURE_VFP);
 502     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 503     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 504     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 505     cpu->midr = 0x4117b363;
 506     cpu->reset_fpsid = 0x410120b4;
 507     cpu->mvfr0 = 0x11111111;
 508     cpu->mvfr1 = 0x00000000;
 509     cpu->ctr = 0x1dd20d2;
 510     cpu->reset_sctlr = 0x00050078;
 511     cpu->id_pfr0 = 0x111;
 512     cpu->id_pfr1 = 0x1;
 513     cpu->id_dfr0 = 0x2;
 514     cpu->id_afr0 = 0x3;
 515     cpu->id_mmfr0 = 0x01130003;
 516     cpu->id_mmfr1 = 0x10030302;
 517     cpu->id_mmfr2 = 0x01222110;
 518     cpu->id_isar0 = 0x00140011;
 519     cpu->id_isar1 = 0x12002111;
 520     cpu->id_isar2 = 0x11231111;
 521     cpu->id_isar3 = 0x01102131;
 522     cpu->id_isar4 = 0x141;
 523     cpu->reset_auxcr = 7;
 524 }
 525
 526 static void arm1176_initfn(Object *obj)
 527 {
 528     ARMCPU *cpu = ARM_CPU(obj);
 529
 530     cpu->dtb_compatible = "arm,arm1176";
 531     set_feature(&cpu->env, ARM_FEATURE_V6K);
 532     set_feature(&cpu->env, ARM_FEATURE_VFP);
 533     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 534     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 535     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 536     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 537     cpu->midr = 0x410fb767;
 538     cpu->reset_fpsid = 0x410120b5;
 539     cpu->mvfr0 = 0x11111111;
 540     cpu->mvfr1 = 0x00000000;
 541     cpu->ctr = 0x1dd20d2;
 542     cpu->reset_sctlr = 0x00050078;
 543     cpu->id_pfr0 = 0x111;
 544     cpu->id_pfr1 = 0x11;
 545     cpu->id_dfr0 = 0x33;
 546     cpu->id_afr0 = 0;
 547     cpu->id_mmfr0 = 0x01130003;
 548     cpu->id_mmfr1 = 0x10030302;
 549     cpu->id_mmfr2 = 0x01222100;
 550     cpu->id_isar0 = 0x0140011;
 551     cpu->id_isar1 = 0x12002111;
 552     cpu->id_isar2 = 0x11231121;
 553     cpu->id_isar3 = 0x01102131;
 554     cpu->id_isar4 = 0x01141;
 555     cpu->reset_auxcr = 7;
 556 }
 557
 558 static void arm11mpcore_initfn(Object *obj)
 559 {
 560     ARMCPU *cpu = ARM_CPU(obj);
 561
 562     cpu->dtb_compatible = "arm,arm11mpcore";
 563     set_feature(&cpu->env, ARM_FEATURE_V6K);
 564     set_feature(&cpu->env, ARM_FEATURE_VFP);
 565     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 566     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 567     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 568     cpu->midr = 0x410fb022;
 569     cpu->reset_fpsid = 0x410120b4;
 570     cpu->mvfr0 = 0x11111111;
 571     cpu->mvfr1 = 0x00000000;
 572     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 573     cpu->id_pfr0 = 0x111;
 574     cpu->id_pfr1 = 0x1;
 575     cpu->id_dfr0 = 0;
 576     cpu->id_afr0 = 0x2;
 577     cpu->id_mmfr0 = 0x01100103;
 578     cpu->id_mmfr1 = 0x10020302;
 579     cpu->id_mmfr2 = 0x01222000;
 580     cpu->id_isar0 = 0x00100011;
 581     cpu->id_isar1 = 0x12002111;
 582     cpu->id_isar2 = 0x11221011;
 583     cpu->id_isar3 = 0x01102131;
 584     cpu->id_isar4 = 0x141;
 585     cpu->reset_auxcr = 1;
 586 }
 587
 588 static void cortex_m3_initfn(Object *obj)
 589 {
 590     ARMCPU *cpu = ARM_CPU(obj);
 591     set_feature(&cpu->env, ARM_FEATURE_V7);
 592     set_feature(&cpu->env, ARM_FEATURE_M);
 593     cpu->midr = 0x410fc231;
 594 }
 595
 596 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 597 {
 598 #ifndef CONFIG_USER_ONLY
 599     CPUClass *cc = CPU_CLASS(oc);
 600
 601     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 602 #endif
 603 }
 604
 605 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 606     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 607       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 608     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 609       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 610     REGINFO_SENTINEL
 611 };
 612
 613 static void cortex_a8_initfn(Object *obj)
 614 {
 615     ARMCPU *cpu = ARM_CPU(obj);
 616
 617     cpu->dtb_compatible = "arm,cortex-a8";
 618     set_feature(&cpu->env, ARM_FEATURE_V7);
 619     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 620     set_feature(&cpu->env, ARM_FEATURE_NEON);
 621     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 622     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 623     cpu->midr = 0x410fc080;
 624     cpu->reset_fpsid = 0x410330c0;
 625     cpu->mvfr0 = 0x11110222;
 626     cpu->mvfr1 = 0x00011100;
 627     cpu->ctr = 0x82048004;
 628     cpu->reset_sctlr = 0x00c50078;
 629     cpu->id_pfr0 = 0x1031;
 630     cpu->id_pfr1 = 0x11;
 631     cpu->id_dfr0 = 0x400;
 632     cpu->id_afr0 = 0;
 633     cpu->id_mmfr0 = 0x31100003;
 634     cpu->id_mmfr1 = 0x20000000;
 635     cpu->id_mmfr2 = 0x01202000;
 636     cpu->id_mmfr3 = 0x11;
 637     cpu->id_isar0 = 0x00101111;
 638     cpu->id_isar1 = 0x12112111;
 639     cpu->id_isar2 = 0x21232031;
 640     cpu->id_isar3 = 0x11112131;
 641     cpu->id_isar4 = 0x00111142;
 642     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 643     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 644     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 645     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 646     cpu->reset_auxcr = 2;
 647     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 648 }
 649
 650 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 651     /* power_control should be set to maximum latency. Again,
 652      * default to 0 and set by private hook
 653      */
 654     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 655       .access = PL1_RW, .resetvalue = 0,
 656       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 657     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 658       .access = PL1_RW, .resetvalue = 0,
 659       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 660     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 661       .access = PL1_RW, .resetvalue = 0,
 662       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 663     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 664       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 665     /* TLB lockdown control */
 666     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 667       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 668     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 669       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 670     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 671       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 672     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 673       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 674     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 675       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 676     REGINFO_SENTINEL
 677 };
 678
 679 static void cortex_a9_initfn(Object *obj)
 680 {
 681     ARMCPU *cpu = ARM_CPU(obj);
 682
 683     cpu->dtb_compatible = "arm,cortex-a9";
 684     set_feature(&cpu->env, ARM_FEATURE_V7);
 685     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 686     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 687     set_feature(&cpu->env, ARM_FEATURE_NEON);
 688     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 689     /* Note that A9 supports the MP extensions even for
 690      * A9UP and single-core A9MP (which are both different
 691      * and valid configurations; we don't model A9UP).
 692      */
 693     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 694     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 695     cpu->midr = 0x410fc090;
 696     cpu->reset_fpsid = 0x41033090;
 697     cpu->mvfr0 = 0x11110222;
 698     cpu->mvfr1 = 0x01111111;
 699     cpu->ctr = 0x80038003;
 700     cpu->reset_sctlr = 0x00c50078;
 701     cpu->id_pfr0 = 0x1031;
 702     cpu->id_pfr1 = 0x11;
 703     cpu->id_dfr0 = 0x000;
 704     cpu->id_afr0 = 0;
 705     cpu->id_mmfr0 = 0x00100103;
 706     cpu->id_mmfr1 = 0x20000000;
 707     cpu->id_mmfr2 = 0x01230000;
 708     cpu->id_mmfr3 = 0x00002111;
 709     cpu->id_isar0 = 0x00101111;
 710     cpu->id_isar1 = 0x13112111;
 711     cpu->id_isar2 = 0x21232041;
 712     cpu->id_isar3 = 0x11112131;
 713     cpu->id_isar4 = 0x00111142;
 714     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 715     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 716     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 717     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 718 }
 719
 720 #ifndef CONFIG_USER_ONLY
 721 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 722 {
 723     /* Linux wants the number of processors from here.
 724      * Might as well set the interrupt-controller bit too.
 725      */
 726     return ((smp_cpus - 1) << 24) | (1 << 23);
 727 }
 728 #endif
 729
 730 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 731 #ifndef CONFIG_USER_ONLY
 732     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 733       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 734       .writefn = arm_cp_write_ignore, },
 735 #endif
 736     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 737       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 738     REGINFO_SENTINEL
 739 };
 740
 741 static void cortex_a15_initfn(Object *obj)
 742 {
 743     ARMCPU *cpu = ARM_CPU(obj);
 744
 745     cpu->dtb_compatible = "arm,cortex-a15";
 746     set_feature(&cpu->env, ARM_FEATURE_V7);
 747     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 748     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 749     set_feature(&cpu->env, ARM_FEATURE_NEON);
 750     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 751     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 752     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 753     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 754     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 755     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 756     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 757     cpu->midr = 0x412fc0f1;
 758     cpu->reset_fpsid = 0x410430f0;
 759     cpu->mvfr0 = 0x10110222;
 760     cpu->mvfr1 = 0x11111111;
 761     cpu->ctr = 0x8444c004;
 762     cpu->reset_sctlr = 0x00c50078;
 763     cpu->id_pfr0 = 0x00001131;
 764     cpu->id_pfr1 = 0x00011011;
 765     cpu->id_dfr0 = 0x02010555;
 766     cpu->id_afr0 = 0x00000000;
 767     cpu->id_mmfr0 = 0x10201105;
 768     cpu->id_mmfr1 = 0x20000000;
 769     cpu->id_mmfr2 = 0x01240000;
 770     cpu->id_mmfr3 = 0x02102211;
 771     cpu->id_isar0 = 0x02101110;
 772     cpu->id_isar1 = 0x13112111;
 773     cpu->id_isar2 = 0x21232041;
 774     cpu->id_isar3 = 0x11112131;
 775     cpu->id_isar4 = 0x10011142;
 776     cpu->clidr = 0x0a200023;
 777     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 778     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 779     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 780     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 781 }
 782
 783 static void ti925t_initfn(Object *obj)
 784 {
 785     ARMCPU *cpu = ARM_CPU(obj);
 786     set_feature(&cpu->env, ARM_FEATURE_V4T);
 787     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 788     cpu->midr = ARM_CPUID_TI925T;
 789     cpu->ctr = 0x5109149;
 790     cpu->reset_sctlr = 0x00000070;
 791 }
 792
 793 static void sa1100_initfn(Object *obj)
 794 {
 795     ARMCPU *cpu = ARM_CPU(obj);
 796
 797     cpu->dtb_compatible = "intel,sa1100";
 798     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 799     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 800     cpu->midr = 0x4401A11B;
 801     cpu->reset_sctlr = 0x00000070;
 802 }
 803
 804 static void sa1110_initfn(Object *obj)
 805 {
 806     ARMCPU *cpu = ARM_CPU(obj);
 807     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 808     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 809     cpu->midr = 0x6901B119;
 810     cpu->reset_sctlr = 0x00000070;
 811 }
 812
 813 static void pxa250_initfn(Object *obj)
 814 {
 815     ARMCPU *cpu = ARM_CPU(obj);
 816
 817     cpu->dtb_compatible = "marvell,xscale";
 818     set_feature(&cpu->env, ARM_FEATURE_V5);
 819     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 820     cpu->midr = 0x69052100;
 821     cpu->ctr = 0xd172172;
 822     cpu->reset_sctlr = 0x00000078;
 823 }
 824
 825 static void pxa255_initfn(Object *obj)
 826 {
 827     ARMCPU *cpu = ARM_CPU(obj);
 828
 829     cpu->dtb_compatible = "marvell,xscale";
 830     set_feature(&cpu->env, ARM_FEATURE_V5);
 831     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 832     cpu->midr = 0x69052d00;
 833     cpu->ctr = 0xd172172;
 834     cpu->reset_sctlr = 0x00000078;
 835 }
 836
 837 static void pxa260_initfn(Object *obj)
 838 {
 839     ARMCPU *cpu = ARM_CPU(obj);
 840
 841     cpu->dtb_compatible = "marvell,xscale";
 842     set_feature(&cpu->env, ARM_FEATURE_V5);
 843     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 844     cpu->midr = 0x69052903;
 845     cpu->ctr = 0xd172172;
 846     cpu->reset_sctlr = 0x00000078;
 847 }
 848
 849 static void pxa261_initfn(Object *obj)
 850 {
 851     ARMCPU *cpu = ARM_CPU(obj);
 852
 853     cpu->dtb_compatible = "marvell,xscale";
 854     set_feature(&cpu->env, ARM_FEATURE_V5);
 855     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 856     cpu->midr = 0x69052d05;
 857     cpu->ctr = 0xd172172;
 858     cpu->reset_sctlr = 0x00000078;
 859 }
 860
 861 static void pxa262_initfn(Object *obj)
 862 {
 863     ARMCPU *cpu = ARM_CPU(obj);
 864
 865     cpu->dtb_compatible = "marvell,xscale";
 866     set_feature(&cpu->env, ARM_FEATURE_V5);
 867     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 868     cpu->midr = 0x69052d06;
 869     cpu->ctr = 0xd172172;
 870     cpu->reset_sctlr = 0x00000078;
 871 }
 872
 873 static void pxa270a0_initfn(Object *obj)
 874 {
 875     ARMCPU *cpu = ARM_CPU(obj);
 876
 877     cpu->dtb_compatible = "marvell,xscale";
 878     set_feature(&cpu->env, ARM_FEATURE_V5);
 879     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 880     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 881     cpu->midr = 0x69054110;
 882     cpu->ctr = 0xd172172;
 883     cpu->reset_sctlr = 0x00000078;
 884 }
 885
 886 static void pxa270a1_initfn(Object *obj)
 887 {
 888     ARMCPU *cpu = ARM_CPU(obj);
 889
 890     cpu->dtb_compatible = "marvell,xscale";
 891     set_feature(&cpu->env, ARM_FEATURE_V5);
 892     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 893     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 894     cpu->midr = 0x69054111;
 895     cpu->ctr = 0xd172172;
 896     cpu->reset_sctlr = 0x00000078;
 897 }
 898
 899 static void pxa270b0_initfn(Object *obj)
 900 {
 901     ARMCPU *cpu = ARM_CPU(obj);
 902
 903     cpu->dtb_compatible = "marvell,xscale";
 904     set_feature(&cpu->env, ARM_FEATURE_V5);
 905     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 906     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 907     cpu->midr = 0x69054112;
 908     cpu->ctr = 0xd172172;
 909     cpu->reset_sctlr = 0x00000078;
 910 }
 911
 912 static void pxa270b1_initfn(Object *obj)
 913 {
 914     ARMCPU *cpu = ARM_CPU(obj);
 915
 916     cpu->dtb_compatible = "marvell,xscale";
 917     set_feature(&cpu->env, ARM_FEATURE_V5);
 918     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 919     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 920     cpu->midr = 0x69054113;
 921     cpu->ctr = 0xd172172;
 922     cpu->reset_sctlr = 0x00000078;
 923 }
 924
 925 static void pxa270c0_initfn(Object *obj)
 926 {
 927     ARMCPU *cpu = ARM_CPU(obj);
 928
 929     cpu->dtb_compatible = "marvell,xscale";
 930     set_feature(&cpu->env, ARM_FEATURE_V5);
 931     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 932     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 933     cpu->midr = 0x69054114;
 934     cpu->ctr = 0xd172172;
 935     cpu->reset_sctlr = 0x00000078;
 936 }
 937
 938 static void pxa270c5_initfn(Object *obj)
 939 {
 940     ARMCPU *cpu = ARM_CPU(obj);
 941
 942     cpu->dtb_compatible = "marvell,xscale";
 943     set_feature(&cpu->env, ARM_FEATURE_V5);
 944     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 945     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 946     cpu->midr = 0x69054117;
 947     cpu->ctr = 0xd172172;
 948     cpu->reset_sctlr = 0x00000078;
 949 }
 950
 951 #ifdef CONFIG_USER_ONLY
 952 static void arm_any_initfn(Object *obj)
 953 {
 954     ARMCPU *cpu = ARM_CPU(obj);
 955     set_feature(&cpu->env, ARM_FEATURE_V8);
 956     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 957     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 958     set_feature(&cpu->env, ARM_FEATURE_NEON);
 959     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 960     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 961     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 962     set_feature(&cpu->env, ARM_FEATURE_CRC);
 963 #ifdef TARGET_AARCH64
 964     set_feature(&cpu->env, ARM_FEATURE_AARCH64);
 965 #endif
 966     cpu->midr = 0xffffffff;
 967 }
 968 #endif
 969
 970 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
 971
 972 typedef struct ARMCPUInfo {
 973     const char *name;
 974     void (*initfn)(Object *obj);
 975     void (*class_init)(ObjectClass *oc, void *data);
 976 } ARMCPUInfo;
 977
 978 static const ARMCPUInfo arm_cpus[] = {
 979 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 980     { .name = "arm926",      .initfn = arm926_initfn },
 981     { .name = "arm946",      .initfn = arm946_initfn },
 982     { .name = "arm1026",     .initfn = arm1026_initfn },
 983     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 984      * older core than plain "arm1136". In particular this does not
 985      * have the v6K features.
 986      */
 987     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 988     { .name = "arm1136",     .initfn = arm1136_initfn },
 989     { .name = "arm1176",     .initfn = arm1176_initfn },
 990     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 991     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
 992                              .class_init = arm_v7m_class_init },
 993     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 994     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 995     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 996     { .name = "ti925t",      .initfn = ti925t_initfn },
 997     { .name = "sa1100",      .initfn = sa1100_initfn },
 998     { .name = "sa1110",      .initfn = sa1110_initfn },
 999     { .name = "pxa250",      .initfn = pxa250_initfn },
1000     { .name = "pxa255",      .initfn = pxa255_initfn },
1001     { .name = "pxa260",      .initfn = pxa260_initfn },
1002     { .name = "pxa261",      .initfn = pxa261_initfn },
1003     { .name = "pxa262",      .initfn = pxa262_initfn },
1004     /* "pxa270" is an alias for "pxa270-a0" */
1005     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1006     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1007     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1008     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1009     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1010     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1011     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1012 #ifdef CONFIG_USER_ONLY
1013     { .name = "any",         .initfn = arm_any_initfn },
1014 #endif
1015 #endif
1016     { .name = NULL }
1017 };
1018
1019 static Property arm_cpu_properties[] = {
1020     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1021     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1022     DEFINE_PROP_END_OF_LIST()
1023 };
1024
1025 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1026 {
1027     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1028     CPUClass *cc = CPU_CLASS(acc);
1029     DeviceClass *dc = DEVICE_CLASS(oc);
1030
1031     acc->parent_realize = dc->realize;
1032     dc->realize = arm_cpu_realizefn;
1033     dc->props = arm_cpu_properties;
1034
1035     acc->parent_reset = cc->reset;
1036     cc->reset = arm_cpu_reset;
1037
1038     cc->class_by_name = arm_cpu_class_by_name;
1039     cc->has_work = arm_cpu_has_work;
1040     cc->do_interrupt = arm_cpu_do_interrupt;
1041     cc->dump_state = arm_cpu_dump_state;
1042     cc->set_pc = arm_cpu_set_pc;
1043     cc->gdb_read_register = arm_cpu_gdb_read_register;
1044     cc->gdb_write_register = arm_cpu_gdb_write_register;
1045 #ifdef CONFIG_USER_ONLY
1046     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1047 #else
1048     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1049     cc->vmsd = &vmstate_arm_cpu;
1050 #endif
1051     cc->gdb_num_core_regs = 26;
1052     cc->gdb_core_xml_file = "arm-core.xml";
1053 }
1054
1055 static void cpu_register(const ARMCPUInfo *info)
1056 {
1057     TypeInfo type_info = {
1058         .parent = TYPE_ARM_CPU,
1059         .instance_size = sizeof(ARMCPU),
1060         .instance_init = info->initfn,
1061         .class_size = sizeof(ARMCPUClass),
1062         .class_init = info->class_init,
1063     };
1064
1065     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1066     type_register(&type_info);
1067     g_free((void *)type_info.name);
1068 }
1069
1070 static const TypeInfo arm_cpu_type_info = {
1071     .name = TYPE_ARM_CPU,
1072     .parent = TYPE_CPU,
1073     .instance_size = sizeof(ARMCPU),
1074     .instance_init = arm_cpu_initfn,
1075     .instance_post_init = arm_cpu_post_init,
1076     .instance_finalize = arm_cpu_finalizefn,
1077     .abstract = true,
1078     .class_size = sizeof(ARMCPUClass),
1079     .class_init = arm_cpu_class_init,
1080 };
1081
1082 static void arm_cpu_register_types(void)
1083 {
1084     const ARMCPUInfo *info = arm_cpus;
1085
1086     type_register_static(&arm_cpu_type_info);
1087
1088     while (info->name) {
1089         cpu_register(info);
1090         info++;
1091     }
1092 }
1093
1094 type_init(arm_cpu_register_types)