target/i386/machine.c

   1 #include "qemu/osdep.h"
   2 #include "qemu-common.h"
   3 #include "cpu.h"
   4 #include "exec/exec-all.h"
   5 #include "hw/hw.h"
   6 #include "hw/boards.h"
   7 #include "hw/i386/pc.h"
   8 #include "hw/isa/isa.h"
   9 #include "migration/cpu.h"
  10
  11 #include "sysemu/kvm.h"
  12
  13 #include "qemu/error-report.h"
  14
  15 static const VMStateDescription vmstate_segment = {
  16     .name = "segment",
  17     .version_id = 1,
  18     .minimum_version_id = 1,
  19     .fields = (VMStateField[]) {
  20         VMSTATE_UINT32(selector, SegmentCache),
  21         VMSTATE_UINTTL(base, SegmentCache),
  22         VMSTATE_UINT32(limit, SegmentCache),
  23         VMSTATE_UINT32(flags, SegmentCache),
  24         VMSTATE_END_OF_LIST()
  25     }
  26 };
  27
  28 #define VMSTATE_SEGMENT(_field, _state) {                            \
  29     .name       = (stringify(_field)),                               \
  30     .size       = sizeof(SegmentCache),                              \
  31     .vmsd       = &vmstate_segment,                                  \
  32     .flags      = VMS_STRUCT,                                        \
  33     .offset     = offsetof(_state, _field)                           \
  34             + type_check(SegmentCache,typeof_field(_state, _field))  \
  35 }
  36
  37 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  38     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  39
  40 static const VMStateDescription vmstate_xmm_reg = {
  41     .name = "xmm_reg",
  42     .version_id = 1,
  43     .minimum_version_id = 1,
  44     .fields = (VMStateField[]) {
  45         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  46         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  47         VMSTATE_END_OF_LIST()
  48     }
  49 };
  50
  51 #define VMSTATE_XMM_REGS(_field, _state, _start)                         \
  52     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  53                              vmstate_xmm_reg, ZMMReg)
  54
  55 /* YMMH format is the same as XMM, but for bits 128-255 */
  56 static const VMStateDescription vmstate_ymmh_reg = {
  57     .name = "ymmh_reg",
  58     .version_id = 1,
  59     .minimum_version_id = 1,
  60     .fields = (VMStateField[]) {
  61         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  62         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  63         VMSTATE_END_OF_LIST()
  64     }
  65 };
  66
  67 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v)               \
  68     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v,    \
  69                              vmstate_ymmh_reg, ZMMReg)
  70
  71 static const VMStateDescription vmstate_zmmh_reg = {
  72     .name = "zmmh_reg",
  73     .version_id = 1,
  74     .minimum_version_id = 1,
  75     .fields = (VMStateField[]) {
  76         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  77         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
  78         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
  79         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
  80         VMSTATE_END_OF_LIST()
  81     }
  82 };
  83
  84 #define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start)                   \
  85     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
  86                              vmstate_zmmh_reg, ZMMReg)
  87
  88 #ifdef TARGET_X86_64
  89 static const VMStateDescription vmstate_hi16_zmm_reg = {
  90     .name = "hi16_zmm_reg",
  91     .version_id = 1,
  92     .minimum_version_id = 1,
  93     .fields = (VMStateField[]) {
  94         VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
  95         VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
  96         VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
  97         VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
  98         VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
  99         VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
 100         VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
 101         VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
 102         VMSTATE_END_OF_LIST()
 103     }
 104 };
 105
 106 #define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start)               \
 107     VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0,     \
 108                              vmstate_hi16_zmm_reg, ZMMReg)
 109 #endif
 110
 111 static const VMStateDescription vmstate_bnd_regs = {
 112     .name = "bnd_regs",
 113     .version_id = 1,
 114     .minimum_version_id = 1,
 115     .fields = (VMStateField[]) {
 116         VMSTATE_UINT64(lb, BNDReg),
 117         VMSTATE_UINT64(ub, BNDReg),
 118         VMSTATE_END_OF_LIST()
 119     }
 120 };
 121
 122 #define VMSTATE_BND_REGS(_field, _state, _n)          \
 123     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
 124
 125 static const VMStateDescription vmstate_mtrr_var = {
 126     .name = "mtrr_var",
 127     .version_id = 1,
 128     .minimum_version_id = 1,
 129     .fields = (VMStateField[]) {
 130         VMSTATE_UINT64(base, MTRRVar),
 131         VMSTATE_UINT64(mask, MTRRVar),
 132         VMSTATE_END_OF_LIST()
 133     }
 134 };
 135
 136 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
 137     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
 138
 139 static int get_fpreg(QEMUFile *f, void *opaque, size_t size,
 140                      VMStateField *field)
 141 {
 142     FPReg *fp_reg = opaque;
 143     uint64_t mant;
 144     uint16_t exp;
 145
 146     qemu_get_be64s(f, &mant);
 147     qemu_get_be16s(f, &exp);
 148     fp_reg->d = cpu_set_fp80(mant, exp);
 149     return 0;
 150 }
 151
 152 static int put_fpreg(QEMUFile *f, void *opaque, size_t size,
 153                      VMStateField *field, QJSON *vmdesc)
 154 {
 155     FPReg *fp_reg = opaque;
 156     uint64_t mant;
 157     uint16_t exp;
 158     /* we save the real CPU data (in case of MMX usage only 'mant'
 159        contains the MMX register */
 160     cpu_get_fp80(&mant, &exp, fp_reg->d);
 161     qemu_put_be64s(f, &mant);
 162     qemu_put_be16s(f, &exp);
 163
 164     return 0;
 165 }
 166
 167 static const VMStateInfo vmstate_fpreg = {
 168     .name = "fpreg",
 169     .get  = get_fpreg,
 170     .put  = put_fpreg,
 171 };
 172
 173 static bool version_is_5(void *opaque, int version_id)
 174 {
 175     return version_id == 5;
 176 }
 177
 178 #ifdef TARGET_X86_64
 179 static bool less_than_7(void *opaque, int version_id)
 180 {
 181     return version_id < 7;
 182 }
 183
 184 static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size,
 185                                 VMStateField *field)
 186 {
 187     uint64_t *v = pv;
 188     *v = qemu_get_be32(f);
 189     return 0;
 190 }
 191
 192 static int put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size,
 193                                 VMStateField *field, QJSON *vmdesc)
 194 {
 195     uint64_t *v = pv;
 196     qemu_put_be32(f, *v);
 197
 198     return 0;
 199 }
 200
 201 static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
 202     .name = "uint64_as_uint32",
 203     .get  = get_uint64_as_uint32,
 204     .put  = put_uint64_as_uint32,
 205 };
 206
 207 #define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
 208     VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
 209 #endif
 210
 211 static void cpu_pre_save(void *opaque)
 212 {
 213     X86CPU *cpu = opaque;
 214     CPUX86State *env = &cpu->env;
 215     int i;
 216
 217     /* FPU */
 218     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 219     env->fptag_vmstate = 0;
 220     for(i = 0; i < 8; i++) {
 221         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 222     }
 223
 224     env->fpregs_format_vmstate = 0;
 225
 226     /*
 227      * Real mode guest segments register DPL should be zero.
 228      * Older KVM version were setting it wrongly.
 229      * Fixing it will allow live migration to host with unrestricted guest
 230      * support (otherwise the migration will fail with invalid guest state
 231      * error).
 232      */
 233     if (!(env->cr[0] & CR0_PE_MASK) &&
 234         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 235         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 236         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 237         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 238         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 239         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 240         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 241     }
 242
 243 }
 244
 245 static int cpu_post_load(void *opaque, int version_id)
 246 {
 247     X86CPU *cpu = opaque;
 248     CPUState *cs = CPU(cpu);
 249     CPUX86State *env = &cpu->env;
 250     int i;
 251
 252     if (env->tsc_khz && env->user_tsc_khz &&
 253         env->tsc_khz != env->user_tsc_khz) {
 254         error_report("Mismatch between user-specified TSC frequency and "
 255                      "migrated TSC frequency");
 256         return -EINVAL;
 257     }
 258
 259     if (env->fpregs_format_vmstate) {
 260         error_report("Unsupported old non-softfloat CPU state");
 261         return -EINVAL;
 262     }
 263     /*
 264      * Real mode guest segments register DPL should be zero.
 265      * Older KVM version were setting it wrongly.
 266      * Fixing it will allow live migration from such host that don't have
 267      * restricted guest support to a host with unrestricted guest support
 268      * (otherwise the migration will fail with invalid guest state
 269      * error).
 270      */
 271     if (!(env->cr[0] & CR0_PE_MASK) &&
 272         (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
 273         env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
 274         env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
 275         env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
 276         env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
 277         env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
 278         env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
 279     }
 280
 281     /* Older versions of QEMU incorrectly used CS.DPL as the CPL when
 282      * running under KVM.  This is wrong for conforming code segments.
 283      * Luckily, in our implementation the CPL field of hflags is redundant
 284      * and we can get the right value from the SS descriptor privilege level.
 285      */
 286     env->hflags &= ~HF_CPL_MASK;
 287     env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 288
 289     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 290     env->fpus = env->fpus_vmstate & ~0x3800;
 291     env->fptag_vmstate ^= 0xff;
 292     for(i = 0; i < 8; i++) {
 293         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 294     }
 295     update_fp_status(env);
 296
 297     cpu_breakpoint_remove_all(cs, BP_CPU);
 298     cpu_watchpoint_remove_all(cs, BP_CPU);
 299     {
 300         /* Indicate all breakpoints disabled, as they are, then
 301            let the helper re-enable them.  */
 302         target_ulong dr7 = env->dr[7];
 303         env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
 304         cpu_x86_update_dr7(env, dr7);
 305     }
 306     tlb_flush(cs);
 307
 308     if (tcg_enabled()) {
 309         cpu_smm_update(cpu);
 310     }
 311     return 0;
 312 }
 313
 314 static bool async_pf_msr_needed(void *opaque)
 315 {
 316     X86CPU *cpu = opaque;
 317
 318     return cpu->env.async_pf_en_msr != 0;
 319 }
 320
 321 static bool pv_eoi_msr_needed(void *opaque)
 322 {
 323     X86CPU *cpu = opaque;
 324
 325     return cpu->env.pv_eoi_en_msr != 0;
 326 }
 327
 328 static bool steal_time_msr_needed(void *opaque)
 329 {
 330     X86CPU *cpu = opaque;
 331
 332     return cpu->env.steal_time_msr != 0;
 333 }
 334
 335 static const VMStateDescription vmstate_steal_time_msr = {
 336     .name = "cpu/steal_time_msr",
 337     .version_id = 1,
 338     .minimum_version_id = 1,
 339     .needed = steal_time_msr_needed,
 340     .fields = (VMStateField[]) {
 341         VMSTATE_UINT64(env.steal_time_msr, X86CPU),
 342         VMSTATE_END_OF_LIST()
 343     }
 344 };
 345
 346 static const VMStateDescription vmstate_async_pf_msr = {
 347     .name = "cpu/async_pf_msr",
 348     .version_id = 1,
 349     .minimum_version_id = 1,
 350     .needed = async_pf_msr_needed,
 351     .fields = (VMStateField[]) {
 352         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
 353         VMSTATE_END_OF_LIST()
 354     }
 355 };
 356
 357 static const VMStateDescription vmstate_pv_eoi_msr = {
 358     .name = "cpu/async_pv_eoi_msr",
 359     .version_id = 1,
 360     .minimum_version_id = 1,
 361     .needed = pv_eoi_msr_needed,
 362     .fields = (VMStateField[]) {
 363         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
 364         VMSTATE_END_OF_LIST()
 365     }
 366 };
 367
 368 static bool fpop_ip_dp_needed(void *opaque)
 369 {
 370     X86CPU *cpu = opaque;
 371     CPUX86State *env = &cpu->env;
 372
 373     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 374 }
 375
 376 static const VMStateDescription vmstate_fpop_ip_dp = {
 377     .name = "cpu/fpop_ip_dp",
 378     .version_id = 1,
 379     .minimum_version_id = 1,
 380     .needed = fpop_ip_dp_needed,
 381     .fields = (VMStateField[]) {
 382         VMSTATE_UINT16(env.fpop, X86CPU),
 383         VMSTATE_UINT64(env.fpip, X86CPU),
 384         VMSTATE_UINT64(env.fpdp, X86CPU),
 385         VMSTATE_END_OF_LIST()
 386     }
 387 };
 388
 389 static bool tsc_adjust_needed(void *opaque)
 390 {
 391     X86CPU *cpu = opaque;
 392     CPUX86State *env = &cpu->env;
 393
 394     return env->tsc_adjust != 0;
 395 }
 396
 397 static const VMStateDescription vmstate_msr_tsc_adjust = {
 398     .name = "cpu/msr_tsc_adjust",
 399     .version_id = 1,
 400     .minimum_version_id = 1,
 401     .needed = tsc_adjust_needed,
 402     .fields = (VMStateField[]) {
 403         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
 404         VMSTATE_END_OF_LIST()
 405     }
 406 };
 407
 408 static bool tscdeadline_needed(void *opaque)
 409 {
 410     X86CPU *cpu = opaque;
 411     CPUX86State *env = &cpu->env;
 412
 413     return env->tsc_deadline != 0;
 414 }
 415
 416 static const VMStateDescription vmstate_msr_tscdeadline = {
 417     .name = "cpu/msr_tscdeadline",
 418     .version_id = 1,
 419     .minimum_version_id = 1,
 420     .needed = tscdeadline_needed,
 421     .fields = (VMStateField[]) {
 422         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
 423         VMSTATE_END_OF_LIST()
 424     }
 425 };
 426
 427 static bool misc_enable_needed(void *opaque)
 428 {
 429     X86CPU *cpu = opaque;
 430     CPUX86State *env = &cpu->env;
 431
 432     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 433 }
 434
 435 static bool feature_control_needed(void *opaque)
 436 {
 437     X86CPU *cpu = opaque;
 438     CPUX86State *env = &cpu->env;
 439
 440     return env->msr_ia32_feature_control != 0;
 441 }
 442
 443 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 444     .name = "cpu/msr_ia32_misc_enable",
 445     .version_id = 1,
 446     .minimum_version_id = 1,
 447     .needed = misc_enable_needed,
 448     .fields = (VMStateField[]) {
 449         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
 450         VMSTATE_END_OF_LIST()
 451     }
 452 };
 453
 454 static const VMStateDescription vmstate_msr_ia32_feature_control = {
 455     .name = "cpu/msr_ia32_feature_control",
 456     .version_id = 1,
 457     .minimum_version_id = 1,
 458     .needed = feature_control_needed,
 459     .fields = (VMStateField[]) {
 460         VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
 461         VMSTATE_END_OF_LIST()
 462     }
 463 };
 464
 465 static bool pmu_enable_needed(void *opaque)
 466 {
 467     X86CPU *cpu = opaque;
 468     CPUX86State *env = &cpu->env;
 469     int i;
 470
 471     if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
 472         env->msr_global_status || env->msr_global_ovf_ctrl) {
 473         return true;
 474     }
 475     for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
 476         if (env->msr_fixed_counters[i]) {
 477             return true;
 478         }
 479     }
 480     for (i = 0; i < MAX_GP_COUNTERS; i++) {
 481         if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
 482             return true;
 483         }
 484     }
 485
 486     return false;
 487 }
 488
 489 static const VMStateDescription vmstate_msr_architectural_pmu = {
 490     .name = "cpu/msr_architectural_pmu",
 491     .version_id = 1,
 492     .minimum_version_id = 1,
 493     .needed = pmu_enable_needed,
 494     .fields = (VMStateField[]) {
 495         VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
 496         VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
 497         VMSTATE_UINT64(env.msr_global_status, X86CPU),
 498         VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
 499         VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
 500         VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
 501         VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
 502         VMSTATE_END_OF_LIST()
 503     }
 504 };
 505
 506 static bool mpx_needed(void *opaque)
 507 {
 508     X86CPU *cpu = opaque;
 509     CPUX86State *env = &cpu->env;
 510     unsigned int i;
 511
 512     for (i = 0; i < 4; i++) {
 513         if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
 514             return true;
 515         }
 516     }
 517
 518     if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
 519         return true;
 520     }
 521
 522     return !!env->msr_bndcfgs;
 523 }
 524
 525 static const VMStateDescription vmstate_mpx = {
 526     .name = "cpu/mpx",
 527     .version_id = 1,
 528     .minimum_version_id = 1,
 529     .needed = mpx_needed,
 530     .fields = (VMStateField[]) {
 531         VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
 532         VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
 533         VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
 534         VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
 535         VMSTATE_END_OF_LIST()
 536     }
 537 };
 538
 539 static bool hyperv_hypercall_enable_needed(void *opaque)
 540 {
 541     X86CPU *cpu = opaque;
 542     CPUX86State *env = &cpu->env;
 543
 544     return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
 545 }
 546
 547 static const VMStateDescription vmstate_msr_hypercall_hypercall = {
 548     .name = "cpu/msr_hyperv_hypercall",
 549     .version_id = 1,
 550     .minimum_version_id = 1,
 551     .needed = hyperv_hypercall_enable_needed,
 552     .fields = (VMStateField[]) {
 553         VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
 554         VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
 555         VMSTATE_END_OF_LIST()
 556     }
 557 };
 558
 559 static bool hyperv_vapic_enable_needed(void *opaque)
 560 {
 561     X86CPU *cpu = opaque;
 562     CPUX86State *env = &cpu->env;
 563
 564     return env->msr_hv_vapic != 0;
 565 }
 566
 567 static const VMStateDescription vmstate_msr_hyperv_vapic = {
 568     .name = "cpu/msr_hyperv_vapic",
 569     .version_id = 1,
 570     .minimum_version_id = 1,
 571     .needed = hyperv_vapic_enable_needed,
 572     .fields = (VMStateField[]) {
 573         VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
 574         VMSTATE_END_OF_LIST()
 575     }
 576 };
 577
 578 static bool hyperv_time_enable_needed(void *opaque)
 579 {
 580     X86CPU *cpu = opaque;
 581     CPUX86State *env = &cpu->env;
 582
 583     return env->msr_hv_tsc != 0;
 584 }
 585
 586 static const VMStateDescription vmstate_msr_hyperv_time = {
 587     .name = "cpu/msr_hyperv_time",
 588     .version_id = 1,
 589     .minimum_version_id = 1,
 590     .needed = hyperv_time_enable_needed,
 591     .fields = (VMStateField[]) {
 592         VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
 593         VMSTATE_END_OF_LIST()
 594     }
 595 };
 596
 597 static bool hyperv_crash_enable_needed(void *opaque)
 598 {
 599     X86CPU *cpu = opaque;
 600     CPUX86State *env = &cpu->env;
 601     int i;
 602
 603     for (i = 0; i < HV_X64_MSR_CRASH_PARAMS; i++) {
 604         if (env->msr_hv_crash_params[i]) {
 605             return true;
 606         }
 607     }
 608     return false;
 609 }
 610
 611 static const VMStateDescription vmstate_msr_hyperv_crash = {
 612     .name = "cpu/msr_hyperv_crash",
 613     .version_id = 1,
 614     .minimum_version_id = 1,
 615     .needed = hyperv_crash_enable_needed,
 616     .fields = (VMStateField[]) {
 617         VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params,
 618                              X86CPU, HV_X64_MSR_CRASH_PARAMS),
 619         VMSTATE_END_OF_LIST()
 620     }
 621 };
 622
 623 static bool hyperv_runtime_enable_needed(void *opaque)
 624 {
 625     X86CPU *cpu = opaque;
 626     CPUX86State *env = &cpu->env;
 627
 628     if (!cpu->hyperv_runtime) {
 629         return false;
 630     }
 631
 632     return env->msr_hv_runtime != 0;
 633 }
 634
 635 static const VMStateDescription vmstate_msr_hyperv_runtime = {
 636     .name = "cpu/msr_hyperv_runtime",
 637     .version_id = 1,
 638     .minimum_version_id = 1,
 639     .needed = hyperv_runtime_enable_needed,
 640     .fields = (VMStateField[]) {
 641         VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
 642         VMSTATE_END_OF_LIST()
 643     }
 644 };
 645
 646 static bool hyperv_synic_enable_needed(void *opaque)
 647 {
 648     X86CPU *cpu = opaque;
 649     CPUX86State *env = &cpu->env;
 650     int i;
 651
 652     if (env->msr_hv_synic_control != 0 ||
 653         env->msr_hv_synic_evt_page != 0 ||
 654         env->msr_hv_synic_msg_page != 0) {
 655         return true;
 656     }
 657
 658     for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
 659         if (env->msr_hv_synic_sint[i] != 0) {
 660             return true;
 661         }
 662     }
 663
 664     return false;
 665 }
 666
 667 static const VMStateDescription vmstate_msr_hyperv_synic = {
 668     .name = "cpu/msr_hyperv_synic",
 669     .version_id = 1,
 670     .minimum_version_id = 1,
 671     .needed = hyperv_synic_enable_needed,
 672     .fields = (VMStateField[]) {
 673         VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
 674         VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
 675         VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
 676         VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU,
 677                              HV_SYNIC_SINT_COUNT),
 678         VMSTATE_END_OF_LIST()
 679     }
 680 };
 681
 682 static bool hyperv_stimer_enable_needed(void *opaque)
 683 {
 684     X86CPU *cpu = opaque;
 685     CPUX86State *env = &cpu->env;
 686     int i;
 687
 688     for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
 689         if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
 690             return true;
 691         }
 692     }
 693     return false;
 694 }
 695
 696 static const VMStateDescription vmstate_msr_hyperv_stimer = {
 697     .name = "cpu/msr_hyperv_stimer",
 698     .version_id = 1,
 699     .minimum_version_id = 1,
 700     .needed = hyperv_stimer_enable_needed,
 701     .fields = (VMStateField[]) {
 702         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config,
 703                              X86CPU, HV_SYNIC_STIMER_COUNT),
 704         VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count,
 705                              X86CPU, HV_SYNIC_STIMER_COUNT),
 706         VMSTATE_END_OF_LIST()
 707     }
 708 };
 709
 710 static bool avx512_needed(void *opaque)
 711 {
 712     X86CPU *cpu = opaque;
 713     CPUX86State *env = &cpu->env;
 714     unsigned int i;
 715
 716     for (i = 0; i < NB_OPMASK_REGS; i++) {
 717         if (env->opmask_regs[i]) {
 718             return true;
 719         }
 720     }
 721
 722     for (i = 0; i < CPU_NB_REGS; i++) {
 723 #define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
 724         if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
 725             ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
 726             return true;
 727         }
 728 #ifdef TARGET_X86_64
 729         if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
 730             ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
 731             ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
 732             ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
 733             return true;
 734         }
 735 #endif
 736     }
 737
 738     return false;
 739 }
 740
 741 static const VMStateDescription vmstate_avx512 = {
 742     .name = "cpu/avx512",
 743     .version_id = 1,
 744     .minimum_version_id = 1,
 745     .needed = avx512_needed,
 746     .fields = (VMStateField[]) {
 747         VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
 748         VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
 749 #ifdef TARGET_X86_64
 750         VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
 751 #endif
 752         VMSTATE_END_OF_LIST()
 753     }
 754 };
 755
 756 static bool xss_needed(void *opaque)
 757 {
 758     X86CPU *cpu = opaque;
 759     CPUX86State *env = &cpu->env;
 760
 761     return env->xss != 0;
 762 }
 763
 764 static const VMStateDescription vmstate_xss = {
 765     .name = "cpu/xss",
 766     .version_id = 1,
 767     .minimum_version_id = 1,
 768     .needed = xss_needed,
 769     .fields = (VMStateField[]) {
 770         VMSTATE_UINT64(env.xss, X86CPU),
 771         VMSTATE_END_OF_LIST()
 772     }
 773 };
 774
 775 #ifdef TARGET_X86_64
 776 static bool pkru_needed(void *opaque)
 777 {
 778     X86CPU *cpu = opaque;
 779     CPUX86State *env = &cpu->env;
 780
 781     return env->pkru != 0;
 782 }
 783
 784 static const VMStateDescription vmstate_pkru = {
 785     .name = "cpu/pkru",
 786     .version_id = 1,
 787     .minimum_version_id = 1,
 788     .needed = pkru_needed,
 789     .fields = (VMStateField[]){
 790         VMSTATE_UINT32(env.pkru, X86CPU),
 791         VMSTATE_END_OF_LIST()
 792     }
 793 };
 794 #endif
 795
 796 static bool tsc_khz_needed(void *opaque)
 797 {
 798     X86CPU *cpu = opaque;
 799     CPUX86State *env = &cpu->env;
 800     MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
 801     PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
 802     return env->tsc_khz && pcmc->save_tsc_khz;
 803 }
 804
 805 static const VMStateDescription vmstate_tsc_khz = {
 806     .name = "cpu/tsc_khz",
 807     .version_id = 1,
 808     .minimum_version_id = 1,
 809     .needed = tsc_khz_needed,
 810     .fields = (VMStateField[]) {
 811         VMSTATE_INT64(env.tsc_khz, X86CPU),
 812         VMSTATE_END_OF_LIST()
 813     }
 814 };
 815
 816 static bool mcg_ext_ctl_needed(void *opaque)
 817 {
 818     X86CPU *cpu = opaque;
 819     CPUX86State *env = &cpu->env;
 820     return cpu->enable_lmce && env->mcg_ext_ctl;
 821 }
 822
 823 static const VMStateDescription vmstate_mcg_ext_ctl = {
 824     .name = "cpu/mcg_ext_ctl",
 825     .version_id = 1,
 826     .minimum_version_id = 1,
 827     .needed = mcg_ext_ctl_needed,
 828     .fields = (VMStateField[]) {
 829         VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU),
 830         VMSTATE_END_OF_LIST()
 831     }
 832 };
 833
 834 VMStateDescription vmstate_x86_cpu = {
 835     .name = "cpu",
 836     .version_id = 12,
 837     .minimum_version_id = 3,
 838     .pre_save = cpu_pre_save,
 839     .post_load = cpu_post_load,
 840     .fields = (VMStateField[]) {
 841         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
 842         VMSTATE_UINTTL(env.eip, X86CPU),
 843         VMSTATE_UINTTL(env.eflags, X86CPU),
 844         VMSTATE_UINT32(env.hflags, X86CPU),
 845         /* FPU */
 846         VMSTATE_UINT16(env.fpuc, X86CPU),
 847         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
 848         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
 849         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
 850
 851         VMSTATE_STRUCT_ARRAY(env.fpregs, X86CPU, 8, 0, vmstate_fpreg, FPReg),
 852
 853         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
 854         VMSTATE_SEGMENT(env.ldt, X86CPU),
 855         VMSTATE_SEGMENT(env.tr, X86CPU),
 856         VMSTATE_SEGMENT(env.gdt, X86CPU),
 857         VMSTATE_SEGMENT(env.idt, X86CPU),
 858
 859         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
 860 #ifdef TARGET_X86_64
 861         /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
 862         VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
 863         VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
 864         VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
 865         VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
 866 #else
 867         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
 868         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
 869 #endif
 870
 871         VMSTATE_UINTTL(env.cr[0], X86CPU),
 872         VMSTATE_UINTTL(env.cr[2], X86CPU),
 873         VMSTATE_UINTTL(env.cr[3], X86CPU),
 874         VMSTATE_UINTTL(env.cr[4], X86CPU),
 875         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
 876         /* MMU */
 877         VMSTATE_INT32(env.a20_mask, X86CPU),
 878         /* XMM */
 879         VMSTATE_UINT32(env.mxcsr, X86CPU),
 880         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
 881
 882 #ifdef TARGET_X86_64
 883         VMSTATE_UINT64(env.efer, X86CPU),
 884         VMSTATE_UINT64(env.star, X86CPU),
 885         VMSTATE_UINT64(env.lstar, X86CPU),
 886         VMSTATE_UINT64(env.cstar, X86CPU),
 887         VMSTATE_UINT64(env.fmask, X86CPU),
 888         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
 889 #endif
 890         VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
 891
 892         VMSTATE_UINT64_V(env.pat, X86CPU, 5),
 893         VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
 894
 895         VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5),
 896         VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
 897         VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
 898         VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
 899         VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
 900         VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
 901         VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
 902         VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
 903         VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
 904         VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
 905         VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
 906         /* MTRRs */
 907         VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
 908         VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
 909         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
 910         /* KVM-related states */
 911         VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
 912         VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
 913         VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
 914         VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
 915         VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
 916         VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
 917         VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
 918         VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
 919         VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
 920         /* MCE */
 921         VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
 922         VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
 923         VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
 924         VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
 925         /* rdtscp */
 926         VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
 927         /* KVM pvclock msr */
 928         VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
 929         VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
 930         /* XSAVE related fields */
 931         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
 932         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
 933         VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
 934         VMSTATE_END_OF_LIST()
 935         /* The above list is not sorted /wrt version numbers, watch out! */
 936     },
 937     .subsections = (const VMStateDescription*[]) {
 938         &vmstate_async_pf_msr,
 939         &vmstate_pv_eoi_msr,
 940         &vmstate_steal_time_msr,
 941         &vmstate_fpop_ip_dp,
 942         &vmstate_msr_tsc_adjust,
 943         &vmstate_msr_tscdeadline,
 944         &vmstate_msr_ia32_misc_enable,
 945         &vmstate_msr_ia32_feature_control,
 946         &vmstate_msr_architectural_pmu,
 947         &vmstate_mpx,
 948         &vmstate_msr_hypercall_hypercall,
 949         &vmstate_msr_hyperv_vapic,
 950         &vmstate_msr_hyperv_time,
 951         &vmstate_msr_hyperv_crash,
 952         &vmstate_msr_hyperv_runtime,
 953         &vmstate_msr_hyperv_synic,
 954         &vmstate_msr_hyperv_stimer,
 955         &vmstate_avx512,
 956         &vmstate_xss,
 957         &vmstate_tsc_khz,
 958 #ifdef TARGET_X86_64
 959         &vmstate_pkru,
 960 #endif
 961         &vmstate_mcg_ext_ctl,
 962         NULL
 963     }
 964 };