target/riscv/csr.c

   1 /*
   2  * RISC-V Control and Status Registers.
   3  *
   4  * Copyright (c) 2016-2017 Sagar Karandikar, [email protected]
   5  * Copyright (c) 2017-2018 SiFive, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2 or later, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/log.h"
  22 #include "cpu.h"
  23 #include "qemu/main-loop.h"
  24 #include "exec/exec-all.h"
  25
  26 /* CSR function table public API */
  27 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
  28 {
  29     *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
  30 }
  31
  32 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
  33 {
  34     csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
  35 }
  36
  37 /* Predicates */
  38 static RISCVException fs(CPURISCVState *env, int csrno)
  39 {
  40 #if !defined(CONFIG_USER_ONLY)
  41     if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
  42         return RISCV_EXCP_ILLEGAL_INST;
  43     }
  44 #endif
  45     return RISCV_EXCP_NONE;
  46 }
  47
  48 static RISCVException vs(CPURISCVState *env, int csrno)
  49 {
  50     if (env->misa_ext & RVV) {
  51 #if !defined(CONFIG_USER_ONLY)
  52         if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
  53             return RISCV_EXCP_ILLEGAL_INST;
  54         }
  55 #endif
  56         return RISCV_EXCP_NONE;
  57     }
  58     return RISCV_EXCP_ILLEGAL_INST;
  59 }
  60
  61 static RISCVException ctr(CPURISCVState *env, int csrno)
  62 {
  63 #if !defined(CONFIG_USER_ONLY)
  64     CPUState *cs = env_cpu(env);
  65     RISCVCPU *cpu = RISCV_CPU(cs);
  66
  67     if (!cpu->cfg.ext_counters) {
  68         /* The Counters extensions is not enabled */
  69         return RISCV_EXCP_ILLEGAL_INST;
  70     }
  71
  72     if (riscv_cpu_virt_enabled(env)) {
  73         switch (csrno) {
  74         case CSR_CYCLE:
  75             if (!get_field(env->hcounteren, COUNTEREN_CY) &&
  76                 get_field(env->mcounteren, COUNTEREN_CY)) {
  77                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  78             }
  79             break;
  80         case CSR_TIME:
  81             if (!get_field(env->hcounteren, COUNTEREN_TM) &&
  82                 get_field(env->mcounteren, COUNTEREN_TM)) {
  83                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  84             }
  85             break;
  86         case CSR_INSTRET:
  87             if (!get_field(env->hcounteren, COUNTEREN_IR) &&
  88                 get_field(env->mcounteren, COUNTEREN_IR)) {
  89                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  90             }
  91             break;
  92         case CSR_HPMCOUNTER3...CSR_HPMCOUNTER31:
  93             if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3)) &&
  94                 get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3))) {
  95                 return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
  96             }
  97             break;
  98         }
  99         if (riscv_cpu_mxl(env) == MXL_RV32) {
 100             switch (csrno) {
 101             case CSR_CYCLEH:
 102                 if (!get_field(env->hcounteren, COUNTEREN_CY) &&
 103                     get_field(env->mcounteren, COUNTEREN_CY)) {
 104                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 105                 }
 106                 break;
 107             case CSR_TIMEH:
 108                 if (!get_field(env->hcounteren, COUNTEREN_TM) &&
 109                     get_field(env->mcounteren, COUNTEREN_TM)) {
 110                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 111                 }
 112                 break;
 113             case CSR_INSTRETH:
 114                 if (!get_field(env->hcounteren, COUNTEREN_IR) &&
 115                     get_field(env->mcounteren, COUNTEREN_IR)) {
 116                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 117                 }
 118                 break;
 119             case CSR_HPMCOUNTER3H...CSR_HPMCOUNTER31H:
 120                 if (!get_field(env->hcounteren, 1 << (csrno - CSR_HPMCOUNTER3H)) &&
 121                     get_field(env->mcounteren, 1 << (csrno - CSR_HPMCOUNTER3H))) {
 122                     return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 123                 }
 124                 break;
 125             }
 126         }
 127     }
 128 #endif
 129     return RISCV_EXCP_NONE;
 130 }
 131
 132 static RISCVException ctr32(CPURISCVState *env, int csrno)
 133 {
 134     if (riscv_cpu_mxl(env) != MXL_RV32) {
 135         return RISCV_EXCP_ILLEGAL_INST;
 136     }
 137
 138     return ctr(env, csrno);
 139 }
 140
 141 #if !defined(CONFIG_USER_ONLY)
 142 static RISCVException any(CPURISCVState *env, int csrno)
 143 {
 144     return RISCV_EXCP_NONE;
 145 }
 146
 147 static RISCVException any32(CPURISCVState *env, int csrno)
 148 {
 149     if (riscv_cpu_mxl(env) != MXL_RV32) {
 150         return RISCV_EXCP_ILLEGAL_INST;
 151     }
 152
 153     return any(env, csrno);
 154
 155 }
 156
 157 static RISCVException smode(CPURISCVState *env, int csrno)
 158 {
 159     if (riscv_has_ext(env, RVS)) {
 160         return RISCV_EXCP_NONE;
 161     }
 162
 163     return RISCV_EXCP_ILLEGAL_INST;
 164 }
 165
 166 static RISCVException hmode(CPURISCVState *env, int csrno)
 167 {
 168     if (riscv_has_ext(env, RVS) &&
 169         riscv_has_ext(env, RVH)) {
 170         /* Hypervisor extension is supported */
 171         if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
 172             env->priv == PRV_M) {
 173             return RISCV_EXCP_NONE;
 174         } else {
 175             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 176         }
 177     }
 178
 179     return RISCV_EXCP_ILLEGAL_INST;
 180 }
 181
 182 static RISCVException hmode32(CPURISCVState *env, int csrno)
 183 {
 184     if (riscv_cpu_mxl(env) != MXL_RV32) {
 185         if (riscv_cpu_virt_enabled(env)) {
 186             return RISCV_EXCP_ILLEGAL_INST;
 187         } else {
 188             return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
 189         }
 190     }
 191
 192     return hmode(env, csrno);
 193
 194 }
 195
 196 /* Checks if PointerMasking registers could be accessed */
 197 static RISCVException pointer_masking(CPURISCVState *env, int csrno)
 198 {
 199     /* Check if j-ext is present */
 200     if (riscv_has_ext(env, RVJ)) {
 201         return RISCV_EXCP_NONE;
 202     }
 203     return RISCV_EXCP_ILLEGAL_INST;
 204 }
 205
 206 static RISCVException pmp(CPURISCVState *env, int csrno)
 207 {
 208     if (riscv_feature(env, RISCV_FEATURE_PMP)) {
 209         return RISCV_EXCP_NONE;
 210     }
 211
 212     return RISCV_EXCP_ILLEGAL_INST;
 213 }
 214
 215 static RISCVException epmp(CPURISCVState *env, int csrno)
 216 {
 217     if (env->priv == PRV_M && riscv_feature(env, RISCV_FEATURE_EPMP)) {
 218         return RISCV_EXCP_NONE;
 219     }
 220
 221     return RISCV_EXCP_ILLEGAL_INST;
 222 }
 223 #endif
 224
 225 /* User Floating-Point CSRs */
 226 static RISCVException read_fflags(CPURISCVState *env, int csrno,
 227                                   target_ulong *val)
 228 {
 229     *val = riscv_cpu_get_fflags(env);
 230     return RISCV_EXCP_NONE;
 231 }
 232
 233 static RISCVException write_fflags(CPURISCVState *env, int csrno,
 234                                    target_ulong val)
 235 {
 236 #if !defined(CONFIG_USER_ONLY)
 237     env->mstatus |= MSTATUS_FS;
 238 #endif
 239     riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
 240     return RISCV_EXCP_NONE;
 241 }
 242
 243 static RISCVException read_frm(CPURISCVState *env, int csrno,
 244                                target_ulong *val)
 245 {
 246     *val = env->frm;
 247     return RISCV_EXCP_NONE;
 248 }
 249
 250 static RISCVException write_frm(CPURISCVState *env, int csrno,
 251                                 target_ulong val)
 252 {
 253 #if !defined(CONFIG_USER_ONLY)
 254     env->mstatus |= MSTATUS_FS;
 255 #endif
 256     env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
 257     return RISCV_EXCP_NONE;
 258 }
 259
 260 static RISCVException read_fcsr(CPURISCVState *env, int csrno,
 261                                 target_ulong *val)
 262 {
 263     *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
 264         | (env->frm << FSR_RD_SHIFT);
 265     return RISCV_EXCP_NONE;
 266 }
 267
 268 static RISCVException write_fcsr(CPURISCVState *env, int csrno,
 269                                  target_ulong val)
 270 {
 271 #if !defined(CONFIG_USER_ONLY)
 272     env->mstatus |= MSTATUS_FS;
 273 #endif
 274     env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
 275     riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
 276     return RISCV_EXCP_NONE;
 277 }
 278
 279 static RISCVException read_vtype(CPURISCVState *env, int csrno,
 280                                  target_ulong *val)
 281 {
 282     *val = env->vtype;
 283     return RISCV_EXCP_NONE;
 284 }
 285
 286 static RISCVException read_vl(CPURISCVState *env, int csrno,
 287                               target_ulong *val)
 288 {
 289     *val = env->vl;
 290     return RISCV_EXCP_NONE;
 291 }
 292
 293 static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
 294 {
 295     *val = env_archcpu(env)->cfg.vlen >> 3;
 296     return RISCV_EXCP_NONE;
 297 }
 298
 299 static RISCVException read_vxrm(CPURISCVState *env, int csrno,
 300                                 target_ulong *val)
 301 {
 302     *val = env->vxrm;
 303     return RISCV_EXCP_NONE;
 304 }
 305
 306 static RISCVException write_vxrm(CPURISCVState *env, int csrno,
 307                                  target_ulong val)
 308 {
 309 #if !defined(CONFIG_USER_ONLY)
 310     env->mstatus |= MSTATUS_VS;
 311 #endif
 312     env->vxrm = val;
 313     return RISCV_EXCP_NONE;
 314 }
 315
 316 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
 317                                  target_ulong *val)
 318 {
 319     *val = env->vxsat;
 320     return RISCV_EXCP_NONE;
 321 }
 322
 323 static RISCVException write_vxsat(CPURISCVState *env, int csrno,
 324                                   target_ulong val)
 325 {
 326 #if !defined(CONFIG_USER_ONLY)
 327     env->mstatus |= MSTATUS_VS;
 328 #endif
 329     env->vxsat = val;
 330     return RISCV_EXCP_NONE;
 331 }
 332
 333 static RISCVException read_vstart(CPURISCVState *env, int csrno,
 334                                   target_ulong *val)
 335 {
 336     *val = env->vstart;
 337     return RISCV_EXCP_NONE;
 338 }
 339
 340 static RISCVException write_vstart(CPURISCVState *env, int csrno,
 341                                    target_ulong val)
 342 {
 343 #if !defined(CONFIG_USER_ONLY)
 344     env->mstatus |= MSTATUS_VS;
 345 #endif
 346     /*
 347      * The vstart CSR is defined to have only enough writable bits
 348      * to hold the largest element index, i.e. lg2(VLEN) bits.
 349      */
 350     env->vstart = val & ~(~0ULL << ctzl(env_archcpu(env)->cfg.vlen));
 351     return RISCV_EXCP_NONE;
 352 }
 353
 354 static int read_vcsr(CPURISCVState *env, int csrno, target_ulong *val)
 355 {
 356     *val = (env->vxrm << VCSR_VXRM_SHIFT) | (env->vxsat << VCSR_VXSAT_SHIFT);
 357     return RISCV_EXCP_NONE;
 358 }
 359
 360 static int write_vcsr(CPURISCVState *env, int csrno, target_ulong val)
 361 {
 362 #if !defined(CONFIG_USER_ONLY)
 363     env->mstatus |= MSTATUS_VS;
 364 #endif
 365     env->vxrm = (val & VCSR_VXRM) >> VCSR_VXRM_SHIFT;
 366     env->vxsat = (val & VCSR_VXSAT) >> VCSR_VXSAT_SHIFT;
 367     return RISCV_EXCP_NONE;
 368 }
 369
 370 /* User Timers and Counters */
 371 static RISCVException read_instret(CPURISCVState *env, int csrno,
 372                                    target_ulong *val)
 373 {
 374 #if !defined(CONFIG_USER_ONLY)
 375     if (icount_enabled()) {
 376         *val = icount_get();
 377     } else {
 378         *val = cpu_get_host_ticks();
 379     }
 380 #else
 381     *val = cpu_get_host_ticks();
 382 #endif
 383     return RISCV_EXCP_NONE;
 384 }
 385
 386 static RISCVException read_instreth(CPURISCVState *env, int csrno,
 387                                     target_ulong *val)
 388 {
 389 #if !defined(CONFIG_USER_ONLY)
 390     if (icount_enabled()) {
 391         *val = icount_get() >> 32;
 392     } else {
 393         *val = cpu_get_host_ticks() >> 32;
 394     }
 395 #else
 396     *val = cpu_get_host_ticks() >> 32;
 397 #endif
 398     return RISCV_EXCP_NONE;
 399 }
 400
 401 #if defined(CONFIG_USER_ONLY)
 402 static RISCVException read_time(CPURISCVState *env, int csrno,
 403                                 target_ulong *val)
 404 {
 405     *val = cpu_get_host_ticks();
 406     return RISCV_EXCP_NONE;
 407 }
 408
 409 static RISCVException read_timeh(CPURISCVState *env, int csrno,
 410                                  target_ulong *val)
 411 {
 412     *val = cpu_get_host_ticks() >> 32;
 413     return RISCV_EXCP_NONE;
 414 }
 415
 416 #else /* CONFIG_USER_ONLY */
 417
 418 static RISCVException read_time(CPURISCVState *env, int csrno,
 419                                 target_ulong *val)
 420 {
 421     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 422
 423     if (!env->rdtime_fn) {
 424         return RISCV_EXCP_ILLEGAL_INST;
 425     }
 426
 427     *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 428     return RISCV_EXCP_NONE;
 429 }
 430
 431 static RISCVException read_timeh(CPURISCVState *env, int csrno,
 432                                  target_ulong *val)
 433 {
 434     uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
 435
 436     if (!env->rdtime_fn) {
 437         return RISCV_EXCP_ILLEGAL_INST;
 438     }
 439
 440     *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
 441     return RISCV_EXCP_NONE;
 442 }
 443
 444 /* Machine constants */
 445
 446 #define M_MODE_INTERRUPTS  (MIP_MSIP | MIP_MTIP | MIP_MEIP)
 447 #define S_MODE_INTERRUPTS  (MIP_SSIP | MIP_STIP | MIP_SEIP)
 448 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
 449
 450 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
 451                                            VS_MODE_INTERRUPTS;
 452 static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS;
 453 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
 454                                      VS_MODE_INTERRUPTS;
 455 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \
 456                          (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \
 457                          (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \
 458                          (1ULL << (RISCV_EXCP_BREAKPOINT)) | \
 459                          (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) | \
 460                          (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) | \
 461                          (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) | \
 462                          (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) | \
 463                          (1ULL << (RISCV_EXCP_U_ECALL)) | \
 464                          (1ULL << (RISCV_EXCP_S_ECALL)) | \
 465                          (1ULL << (RISCV_EXCP_VS_ECALL)) | \
 466                          (1ULL << (RISCV_EXCP_M_ECALL)) | \
 467                          (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) | \
 468                          (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) | \
 469                          (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) | \
 470                          (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) | \
 471                          (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) | \
 472                          (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) | \
 473                          (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)))
 474 static const target_ulong vs_delegable_excps = DELEGABLE_EXCPS &
 475     ~((1ULL << (RISCV_EXCP_S_ECALL)) |
 476       (1ULL << (RISCV_EXCP_VS_ECALL)) |
 477       (1ULL << (RISCV_EXCP_M_ECALL)) |
 478       (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
 479       (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
 480       (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT)) |
 481       (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT)));
 482 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
 483     SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
 484     SSTATUS_SUM | SSTATUS_MXR | SSTATUS_VS | (target_ulong)SSTATUS64_UXL;
 485 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
 486 static const target_ulong hip_writable_mask = MIP_VSSIP;
 487 static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
 488 static const target_ulong vsip_writable_mask = MIP_VSSIP;
 489
 490 static const char valid_vm_1_10_32[16] = {
 491     [VM_1_10_MBARE] = 1,
 492     [VM_1_10_SV32] = 1
 493 };
 494
 495 static const char valid_vm_1_10_64[16] = {
 496     [VM_1_10_MBARE] = 1,
 497     [VM_1_10_SV39] = 1,
 498     [VM_1_10_SV48] = 1,
 499     [VM_1_10_SV57] = 1
 500 };
 501
 502 /* Machine Information Registers */
 503 static RISCVException read_zero(CPURISCVState *env, int csrno,
 504                                 target_ulong *val)
 505 {
 506     *val = 0;
 507     return RISCV_EXCP_NONE;
 508 }
 509
 510 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
 511                                    target_ulong *val)
 512 {
 513     *val = env->mhartid;
 514     return RISCV_EXCP_NONE;
 515 }
 516
 517 /* Machine Trap Setup */
 518
 519 /* We do not store SD explicitly, only compute it on demand. */
 520 static uint64_t add_status_sd(RISCVMXL xl, uint64_t status)
 521 {
 522     if ((status & MSTATUS_FS) == MSTATUS_FS ||
 523         (status & MSTATUS_VS) == MSTATUS_VS ||
 524         (status & MSTATUS_XS) == MSTATUS_XS) {
 525         switch (xl) {
 526         case MXL_RV32:
 527             return status | MSTATUS32_SD;
 528         case MXL_RV64:
 529             return status | MSTATUS64_SD;
 530         case MXL_RV128:
 531             return MSTATUSH128_SD;
 532         default:
 533             g_assert_not_reached();
 534         }
 535     }
 536     return status;
 537 }
 538
 539 static RISCVException read_mstatus(CPURISCVState *env, int csrno,
 540                                    target_ulong *val)
 541 {
 542     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus);
 543     return RISCV_EXCP_NONE;
 544 }
 545
 546 static int validate_vm(CPURISCVState *env, target_ulong vm)
 547 {
 548     if (riscv_cpu_mxl(env) == MXL_RV32) {
 549         return valid_vm_1_10_32[vm & 0xf];
 550     } else {
 551         return valid_vm_1_10_64[vm & 0xf];
 552     }
 553 }
 554
 555 static RISCVException write_mstatus(CPURISCVState *env, int csrno,
 556                                     target_ulong val)
 557 {
 558     uint64_t mstatus = env->mstatus;
 559     uint64_t mask = 0;
 560
 561     /* flush tlb on mstatus fields that affect VM */
 562     if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
 563             MSTATUS_MPRV | MSTATUS_SUM)) {
 564         tlb_flush(env_cpu(env));
 565     }
 566     mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
 567         MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
 568         MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
 569         MSTATUS_TW | MSTATUS_VS;
 570
 571     if (riscv_cpu_mxl(env) != MXL_RV32) {
 572         /*
 573          * RV32: MPV and GVA are not in mstatus. The current plan is to
 574          * add them to mstatush. For now, we just don't support it.
 575          */
 576         mask |= MSTATUS_MPV | MSTATUS_GVA;
 577     }
 578
 579     mstatus = (mstatus & ~mask) | (val & mask);
 580
 581     RISCVMXL xl = riscv_cpu_mxl(env);
 582     if (xl > MXL_RV32) {
 583         /* SXL and UXL fields are for now read only */
 584         mstatus = set_field(mstatus, MSTATUS64_SXL, xl);
 585         mstatus = set_field(mstatus, MSTATUS64_UXL, xl);
 586     }
 587     env->mstatus = mstatus;
 588
 589     return RISCV_EXCP_NONE;
 590 }
 591
 592 static RISCVException read_mstatush(CPURISCVState *env, int csrno,
 593                                     target_ulong *val)
 594 {
 595     *val = env->mstatus >> 32;
 596     return RISCV_EXCP_NONE;
 597 }
 598
 599 static RISCVException write_mstatush(CPURISCVState *env, int csrno,
 600                                      target_ulong val)
 601 {
 602     uint64_t valh = (uint64_t)val << 32;
 603     uint64_t mask = MSTATUS_MPV | MSTATUS_GVA;
 604
 605     if ((valh ^ env->mstatus) & (MSTATUS_MPV)) {
 606         tlb_flush(env_cpu(env));
 607     }
 608
 609     env->mstatus = (env->mstatus & ~mask) | (valh & mask);
 610
 611     return RISCV_EXCP_NONE;
 612 }
 613
 614 static RISCVException read_mstatus_i128(CPURISCVState *env, int csrno,
 615                                         Int128 *val)
 616 {
 617     *val = int128_make128(env->mstatus, add_status_sd(MXL_RV128, env->mstatus));
 618     return RISCV_EXCP_NONE;
 619 }
 620
 621 static RISCVException read_misa_i128(CPURISCVState *env, int csrno,
 622                                      Int128 *val)
 623 {
 624     *val = int128_make128(env->misa_ext, (uint64_t)MXL_RV128 << 62);
 625     return RISCV_EXCP_NONE;
 626 }
 627
 628 static RISCVException read_misa(CPURISCVState *env, int csrno,
 629                                 target_ulong *val)
 630 {
 631     target_ulong misa;
 632
 633     switch (env->misa_mxl) {
 634     case MXL_RV32:
 635         misa = (target_ulong)MXL_RV32 << 30;
 636         break;
 637 #ifdef TARGET_RISCV64
 638     case MXL_RV64:
 639         misa = (target_ulong)MXL_RV64 << 62;
 640         break;
 641 #endif
 642     default:
 643         g_assert_not_reached();
 644     }
 645
 646     *val = misa | env->misa_ext;
 647     return RISCV_EXCP_NONE;
 648 }
 649
 650 static RISCVException write_misa(CPURISCVState *env, int csrno,
 651                                  target_ulong val)
 652 {
 653     if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
 654         /* drop write to misa */
 655         return RISCV_EXCP_NONE;
 656     }
 657
 658     /* 'I' or 'E' must be present */
 659     if (!(val & (RVI | RVE))) {
 660         /* It is not, drop write to misa */
 661         return RISCV_EXCP_NONE;
 662     }
 663
 664     /* 'E' excludes all other extensions */
 665     if (val & RVE) {
 666         /* when we support 'E' we can do "val = RVE;" however
 667          * for now we just drop writes if 'E' is present.
 668          */
 669         return RISCV_EXCP_NONE;
 670     }
 671
 672     /*
 673      * misa.MXL writes are not supported by QEMU.
 674      * Drop writes to those bits.
 675      */
 676
 677     /* Mask extensions that are not supported by this hart */
 678     val &= env->misa_ext_mask;
 679
 680     /* Mask extensions that are not supported by QEMU */
 681     val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU | RVV);
 682
 683     /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
 684     if ((val & RVD) && !(val & RVF)) {
 685         val &= ~RVD;
 686     }
 687
 688     /* Suppress 'C' if next instruction is not aligned
 689      * TODO: this should check next_pc
 690      */
 691     if ((val & RVC) && (GETPC() & ~3) != 0) {
 692         val &= ~RVC;
 693     }
 694
 695     /* If nothing changed, do nothing. */
 696     if (val == env->misa_ext) {
 697         return RISCV_EXCP_NONE;
 698     }
 699
 700     /* flush translation cache */
 701     tb_flush(env_cpu(env));
 702     env->misa_ext = val;
 703     return RISCV_EXCP_NONE;
 704 }
 705
 706 static RISCVException read_medeleg(CPURISCVState *env, int csrno,
 707                                    target_ulong *val)
 708 {
 709     *val = env->medeleg;
 710     return RISCV_EXCP_NONE;
 711 }
 712
 713 static RISCVException write_medeleg(CPURISCVState *env, int csrno,
 714                                     target_ulong val)
 715 {
 716     env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS);
 717     return RISCV_EXCP_NONE;
 718 }
 719
 720 static RISCVException read_mideleg(CPURISCVState *env, int csrno,
 721                                    target_ulong *val)
 722 {
 723     *val = env->mideleg;
 724     return RISCV_EXCP_NONE;
 725 }
 726
 727 static RISCVException write_mideleg(CPURISCVState *env, int csrno,
 728                                     target_ulong val)
 729 {
 730     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
 731     if (riscv_has_ext(env, RVH)) {
 732         env->mideleg |= VS_MODE_INTERRUPTS;
 733     }
 734     return RISCV_EXCP_NONE;
 735 }
 736
 737 static RISCVException read_mie(CPURISCVState *env, int csrno,
 738                                target_ulong *val)
 739 {
 740     *val = env->mie;
 741     return RISCV_EXCP_NONE;
 742 }
 743
 744 static RISCVException write_mie(CPURISCVState *env, int csrno,
 745                                 target_ulong val)
 746 {
 747     env->mie = (env->mie & ~all_ints) | (val & all_ints);
 748     return RISCV_EXCP_NONE;
 749 }
 750
 751 static RISCVException read_mtvec(CPURISCVState *env, int csrno,
 752                                  target_ulong *val)
 753 {
 754     *val = env->mtvec;
 755     return RISCV_EXCP_NONE;
 756 }
 757
 758 static RISCVException write_mtvec(CPURISCVState *env, int csrno,
 759                                   target_ulong val)
 760 {
 761     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 762     if ((val & 3) < 2) {
 763         env->mtvec = val;
 764     } else {
 765         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
 766     }
 767     return RISCV_EXCP_NONE;
 768 }
 769
 770 static RISCVException read_mcounteren(CPURISCVState *env, int csrno,
 771                                       target_ulong *val)
 772 {
 773     *val = env->mcounteren;
 774     return RISCV_EXCP_NONE;
 775 }
 776
 777 static RISCVException write_mcounteren(CPURISCVState *env, int csrno,
 778                                        target_ulong val)
 779 {
 780     env->mcounteren = val;
 781     return RISCV_EXCP_NONE;
 782 }
 783
 784 /* Machine Trap Handling */
 785 static RISCVException read_mscratch_i128(CPURISCVState *env, int csrno,
 786                                          Int128 *val)
 787 {
 788     *val = int128_make128(env->mscratch, env->mscratchh);
 789     return RISCV_EXCP_NONE;
 790 }
 791
 792 static RISCVException write_mscratch_i128(CPURISCVState *env, int csrno,
 793                                           Int128 val)
 794 {
 795     env->mscratch = int128_getlo(val);
 796     env->mscratchh = int128_gethi(val);
 797     return RISCV_EXCP_NONE;
 798 }
 799
 800 static RISCVException read_mscratch(CPURISCVState *env, int csrno,
 801                                     target_ulong *val)
 802 {
 803     *val = env->mscratch;
 804     return RISCV_EXCP_NONE;
 805 }
 806
 807 static RISCVException write_mscratch(CPURISCVState *env, int csrno,
 808                                      target_ulong val)
 809 {
 810     env->mscratch = val;
 811     return RISCV_EXCP_NONE;
 812 }
 813
 814 static RISCVException read_mepc(CPURISCVState *env, int csrno,
 815                                      target_ulong *val)
 816 {
 817     *val = env->mepc;
 818     return RISCV_EXCP_NONE;
 819 }
 820
 821 static RISCVException write_mepc(CPURISCVState *env, int csrno,
 822                                      target_ulong val)
 823 {
 824     env->mepc = val;
 825     return RISCV_EXCP_NONE;
 826 }
 827
 828 static RISCVException read_mcause(CPURISCVState *env, int csrno,
 829                                      target_ulong *val)
 830 {
 831     *val = env->mcause;
 832     return RISCV_EXCP_NONE;
 833 }
 834
 835 static RISCVException write_mcause(CPURISCVState *env, int csrno,
 836                                      target_ulong val)
 837 {
 838     env->mcause = val;
 839     return RISCV_EXCP_NONE;
 840 }
 841
 842 static RISCVException read_mtval(CPURISCVState *env, int csrno,
 843                                  target_ulong *val)
 844 {
 845     *val = env->mtval;
 846     return RISCV_EXCP_NONE;
 847 }
 848
 849 static RISCVException write_mtval(CPURISCVState *env, int csrno,
 850                                   target_ulong val)
 851 {
 852     env->mtval = val;
 853     return RISCV_EXCP_NONE;
 854 }
 855
 856 static RISCVException rmw_mip(CPURISCVState *env, int csrno,
 857                               target_ulong *ret_value,
 858                               target_ulong new_value, target_ulong write_mask)
 859 {
 860     RISCVCPU *cpu = env_archcpu(env);
 861     /* Allow software control of delegable interrupts not claimed by hardware */
 862     target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
 863     uint32_t old_mip;
 864
 865     if (mask) {
 866         old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
 867     } else {
 868         old_mip = env->mip;
 869     }
 870
 871     if (ret_value) {
 872         *ret_value = old_mip;
 873     }
 874
 875     return RISCV_EXCP_NONE;
 876 }
 877
 878 /* Supervisor Trap Setup */
 879 static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
 880                                         Int128 *val)
 881 {
 882     uint64_t mask = sstatus_v1_10_mask;
 883     uint64_t sstatus = env->mstatus & mask;
 884
 885     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
 886     return RISCV_EXCP_NONE;
 887 }
 888
 889 static RISCVException read_sstatus(CPURISCVState *env, int csrno,
 890                                    target_ulong *val)
 891 {
 892     target_ulong mask = (sstatus_v1_10_mask);
 893
 894     /* TODO: Use SXL not MXL. */
 895     *val = add_status_sd(riscv_cpu_mxl(env), env->mstatus & mask);
 896     return RISCV_EXCP_NONE;
 897 }
 898
 899 static RISCVException write_sstatus(CPURISCVState *env, int csrno,
 900                                     target_ulong val)
 901 {
 902     target_ulong mask = (sstatus_v1_10_mask);
 903     target_ulong newval = (env->mstatus & ~mask) | (val & mask);
 904     return write_mstatus(env, CSR_MSTATUS, newval);
 905 }
 906
 907 static RISCVException read_vsie(CPURISCVState *env, int csrno,
 908                                 target_ulong *val)
 909 {
 910     /* Shift the VS bits to their S bit location in vsie */
 911     *val = (env->mie & env->hideleg & VS_MODE_INTERRUPTS) >> 1;
 912     return RISCV_EXCP_NONE;
 913 }
 914
 915 static RISCVException read_sie(CPURISCVState *env, int csrno,
 916                                target_ulong *val)
 917 {
 918     if (riscv_cpu_virt_enabled(env)) {
 919         read_vsie(env, CSR_VSIE, val);
 920     } else {
 921         *val = env->mie & env->mideleg;
 922     }
 923     return RISCV_EXCP_NONE;
 924 }
 925
 926 static RISCVException write_vsie(CPURISCVState *env, int csrno,
 927                                  target_ulong val)
 928 {
 929     /* Shift the S bits to their VS bit location in mie */
 930     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) |
 931                           ((val << 1) & env->hideleg & VS_MODE_INTERRUPTS);
 932     return write_mie(env, CSR_MIE, newval);
 933 }
 934
 935 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
 936 {
 937     if (riscv_cpu_virt_enabled(env)) {
 938         write_vsie(env, CSR_VSIE, val);
 939     } else {
 940         target_ulong newval = (env->mie & ~S_MODE_INTERRUPTS) |
 941                               (val & S_MODE_INTERRUPTS);
 942         write_mie(env, CSR_MIE, newval);
 943     }
 944
 945     return RISCV_EXCP_NONE;
 946 }
 947
 948 static RISCVException read_stvec(CPURISCVState *env, int csrno,
 949                                  target_ulong *val)
 950 {
 951     *val = env->stvec;
 952     return RISCV_EXCP_NONE;
 953 }
 954
 955 static RISCVException write_stvec(CPURISCVState *env, int csrno,
 956                                   target_ulong val)
 957 {
 958     /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
 959     if ((val & 3) < 2) {
 960         env->stvec = val;
 961     } else {
 962         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
 963     }
 964     return RISCV_EXCP_NONE;
 965 }
 966
 967 static RISCVException read_scounteren(CPURISCVState *env, int csrno,
 968                                       target_ulong *val)
 969 {
 970     *val = env->scounteren;
 971     return RISCV_EXCP_NONE;
 972 }
 973
 974 static RISCVException write_scounteren(CPURISCVState *env, int csrno,
 975                                        target_ulong val)
 976 {
 977     env->scounteren = val;
 978     return RISCV_EXCP_NONE;
 979 }
 980
 981 /* Supervisor Trap Handling */
 982 static RISCVException read_sscratch_i128(CPURISCVState *env, int csrno,
 983                                          Int128 *val)
 984 {
 985     *val = int128_make128(env->sscratch, env->sscratchh);
 986     return RISCV_EXCP_NONE;
 987 }
 988
 989 static RISCVException write_sscratch_i128(CPURISCVState *env, int csrno,
 990                                           Int128 val)
 991 {
 992     env->sscratch = int128_getlo(val);
 993     env->sscratchh = int128_gethi(val);
 994     return RISCV_EXCP_NONE;
 995 }
 996
 997 static RISCVException read_sscratch(CPURISCVState *env, int csrno,
 998                                     target_ulong *val)
 999 {
1000     *val = env->sscratch;
1001     return RISCV_EXCP_NONE;
1002 }
1003
1004 static RISCVException write_sscratch(CPURISCVState *env, int csrno,
1005                                      target_ulong val)
1006 {
1007     env->sscratch = val;
1008     return RISCV_EXCP_NONE;
1009 }
1010
1011 static RISCVException read_sepc(CPURISCVState *env, int csrno,
1012                                 target_ulong *val)
1013 {
1014     *val = env->sepc;
1015     return RISCV_EXCP_NONE;
1016 }
1017
1018 static RISCVException write_sepc(CPURISCVState *env, int csrno,
1019                                  target_ulong val)
1020 {
1021     env->sepc = val;
1022     return RISCV_EXCP_NONE;
1023 }
1024
1025 static RISCVException read_scause(CPURISCVState *env, int csrno,
1026                                   target_ulong *val)
1027 {
1028     *val = env->scause;
1029     return RISCV_EXCP_NONE;
1030 }
1031
1032 static RISCVException write_scause(CPURISCVState *env, int csrno,
1033                                    target_ulong val)
1034 {
1035     env->scause = val;
1036     return RISCV_EXCP_NONE;
1037 }
1038
1039 static RISCVException read_stval(CPURISCVState *env, int csrno,
1040                                  target_ulong *val)
1041 {
1042     *val = env->stval;
1043     return RISCV_EXCP_NONE;
1044 }
1045
1046 static RISCVException write_stval(CPURISCVState *env, int csrno,
1047                                   target_ulong val)
1048 {
1049     env->stval = val;
1050     return RISCV_EXCP_NONE;
1051 }
1052
1053 static RISCVException rmw_vsip(CPURISCVState *env, int csrno,
1054                                target_ulong *ret_value,
1055                                target_ulong new_value, target_ulong write_mask)
1056 {
1057     /* Shift the S bits to their VS bit location in mip */
1058     int ret = rmw_mip(env, 0, ret_value, new_value << 1,
1059                       (write_mask << 1) & vsip_writable_mask & env->hideleg);
1060
1061     if (ret_value) {
1062         *ret_value &= VS_MODE_INTERRUPTS;
1063         /* Shift the VS bits to their S bit location in vsip */
1064         *ret_value >>= 1;
1065     }
1066     return ret;
1067 }
1068
1069 static RISCVException rmw_sip(CPURISCVState *env, int csrno,
1070                               target_ulong *ret_value,
1071                               target_ulong new_value, target_ulong write_mask)
1072 {
1073     int ret;
1074
1075     if (riscv_cpu_virt_enabled(env)) {
1076         ret = rmw_vsip(env, CSR_VSIP, ret_value, new_value, write_mask);
1077     } else {
1078         ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
1079                       write_mask & env->mideleg & sip_writable_mask);
1080     }
1081
1082     if (ret_value) {
1083         *ret_value &= env->mideleg;
1084     }
1085     return ret;
1086 }
1087
1088 /* Supervisor Protection and Translation */
1089 static RISCVException read_satp(CPURISCVState *env, int csrno,
1090                                 target_ulong *val)
1091 {
1092     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1093         *val = 0;
1094         return RISCV_EXCP_NONE;
1095     }
1096
1097     if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1098         return RISCV_EXCP_ILLEGAL_INST;
1099     } else {
1100         *val = env->satp;
1101     }
1102
1103     return RISCV_EXCP_NONE;
1104 }
1105
1106 static RISCVException write_satp(CPURISCVState *env, int csrno,
1107                                  target_ulong val)
1108 {
1109     target_ulong vm, mask, asid;
1110
1111     if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
1112         return RISCV_EXCP_NONE;
1113     }
1114
1115     if (riscv_cpu_mxl(env) == MXL_RV32) {
1116         vm = validate_vm(env, get_field(val, SATP32_MODE));
1117         mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN);
1118         asid = (val ^ env->satp) & SATP32_ASID;
1119     } else {
1120         vm = validate_vm(env, get_field(val, SATP64_MODE));
1121         mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN);
1122         asid = (val ^ env->satp) & SATP64_ASID;
1123     }
1124
1125     if (vm && mask) {
1126         if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
1127             return RISCV_EXCP_ILLEGAL_INST;
1128         } else {
1129             if (asid) {
1130                 tlb_flush(env_cpu(env));
1131             }
1132             env->satp = val;
1133         }
1134     }
1135     return RISCV_EXCP_NONE;
1136 }
1137
1138 /* Hypervisor Extensions */
1139 static RISCVException read_hstatus(CPURISCVState *env, int csrno,
1140                                    target_ulong *val)
1141 {
1142     *val = env->hstatus;
1143     if (riscv_cpu_mxl(env) != MXL_RV32) {
1144         /* We only support 64-bit VSXL */
1145         *val = set_field(*val, HSTATUS_VSXL, 2);
1146     }
1147     /* We only support little endian */
1148     *val = set_field(*val, HSTATUS_VSBE, 0);
1149     return RISCV_EXCP_NONE;
1150 }
1151
1152 static RISCVException write_hstatus(CPURISCVState *env, int csrno,
1153                                     target_ulong val)
1154 {
1155     env->hstatus = val;
1156     if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) {
1157         qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN options.");
1158     }
1159     if (get_field(val, HSTATUS_VSBE) != 0) {
1160         qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
1161     }
1162     return RISCV_EXCP_NONE;
1163 }
1164
1165 static RISCVException read_hedeleg(CPURISCVState *env, int csrno,
1166                                    target_ulong *val)
1167 {
1168     *val = env->hedeleg;
1169     return RISCV_EXCP_NONE;
1170 }
1171
1172 static RISCVException write_hedeleg(CPURISCVState *env, int csrno,
1173                                     target_ulong val)
1174 {
1175     env->hedeleg = val & vs_delegable_excps;
1176     return RISCV_EXCP_NONE;
1177 }
1178
1179 static RISCVException read_hideleg(CPURISCVState *env, int csrno,
1180                                    target_ulong *val)
1181 {
1182     *val = env->hideleg;
1183     return RISCV_EXCP_NONE;
1184 }
1185
1186 static RISCVException write_hideleg(CPURISCVState *env, int csrno,
1187                                     target_ulong val)
1188 {
1189     env->hideleg = val & vs_delegable_ints;
1190     return RISCV_EXCP_NONE;
1191 }
1192
1193 static RISCVException rmw_hvip(CPURISCVState *env, int csrno,
1194                                target_ulong *ret_value,
1195                                target_ulong new_value, target_ulong write_mask)
1196 {
1197     int ret = rmw_mip(env, 0, ret_value, new_value,
1198                       write_mask & hvip_writable_mask);
1199
1200     if (ret_value) {
1201         *ret_value &= hvip_writable_mask;
1202     }
1203     return ret;
1204 }
1205
1206 static RISCVException rmw_hip(CPURISCVState *env, int csrno,
1207                               target_ulong *ret_value,
1208                               target_ulong new_value, target_ulong write_mask)
1209 {
1210     int ret = rmw_mip(env, 0, ret_value, new_value,
1211                       write_mask & hip_writable_mask);
1212
1213     if (ret_value) {
1214         *ret_value &= hip_writable_mask;
1215     }
1216     return ret;
1217 }
1218
1219 static RISCVException read_hie(CPURISCVState *env, int csrno,
1220                                target_ulong *val)
1221 {
1222     *val = env->mie & VS_MODE_INTERRUPTS;
1223     return RISCV_EXCP_NONE;
1224 }
1225
1226 static RISCVException write_hie(CPURISCVState *env, int csrno,
1227                                 target_ulong val)
1228 {
1229     target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
1230     return write_mie(env, CSR_MIE, newval);
1231 }
1232
1233 static RISCVException read_hcounteren(CPURISCVState *env, int csrno,
1234                                       target_ulong *val)
1235 {
1236     *val = env->hcounteren;
1237     return RISCV_EXCP_NONE;
1238 }
1239
1240 static RISCVException write_hcounteren(CPURISCVState *env, int csrno,
1241                                        target_ulong val)
1242 {
1243     env->hcounteren = val;
1244     return RISCV_EXCP_NONE;
1245 }
1246
1247 static RISCVException write_hgeie(CPURISCVState *env, int csrno,
1248                                   target_ulong val)
1249 {
1250     if (val) {
1251         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1252     }
1253     return RISCV_EXCP_NONE;
1254 }
1255
1256 static RISCVException read_htval(CPURISCVState *env, int csrno,
1257                                  target_ulong *val)
1258 {
1259     *val = env->htval;
1260     return RISCV_EXCP_NONE;
1261 }
1262
1263 static RISCVException write_htval(CPURISCVState *env, int csrno,
1264                                   target_ulong val)
1265 {
1266     env->htval = val;
1267     return RISCV_EXCP_NONE;
1268 }
1269
1270 static RISCVException read_htinst(CPURISCVState *env, int csrno,
1271                                   target_ulong *val)
1272 {
1273     *val = env->htinst;
1274     return RISCV_EXCP_NONE;
1275 }
1276
1277 static RISCVException write_htinst(CPURISCVState *env, int csrno,
1278                                    target_ulong val)
1279 {
1280     return RISCV_EXCP_NONE;
1281 }
1282
1283 static RISCVException write_hgeip(CPURISCVState *env, int csrno,
1284                                   target_ulong val)
1285 {
1286     if (val) {
1287         qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
1288     }
1289     return RISCV_EXCP_NONE;
1290 }
1291
1292 static RISCVException read_hgatp(CPURISCVState *env, int csrno,
1293                                  target_ulong *val)
1294 {
1295     *val = env->hgatp;
1296     return RISCV_EXCP_NONE;
1297 }
1298
1299 static RISCVException write_hgatp(CPURISCVState *env, int csrno,
1300                                   target_ulong val)
1301 {
1302     env->hgatp = val;
1303     return RISCV_EXCP_NONE;
1304 }
1305
1306 static RISCVException read_htimedelta(CPURISCVState *env, int csrno,
1307                                       target_ulong *val)
1308 {
1309     if (!env->rdtime_fn) {
1310         return RISCV_EXCP_ILLEGAL_INST;
1311     }
1312
1313     *val = env->htimedelta;
1314     return RISCV_EXCP_NONE;
1315 }
1316
1317 static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
1318                                        target_ulong val)
1319 {
1320     if (!env->rdtime_fn) {
1321         return RISCV_EXCP_ILLEGAL_INST;
1322     }
1323
1324     if (riscv_cpu_mxl(env) == MXL_RV32) {
1325         env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
1326     } else {
1327         env->htimedelta = val;
1328     }
1329     return RISCV_EXCP_NONE;
1330 }
1331
1332 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno,
1333                                        target_ulong *val)
1334 {
1335     if (!env->rdtime_fn) {
1336         return RISCV_EXCP_ILLEGAL_INST;
1337     }
1338
1339     *val = env->htimedelta >> 32;
1340     return RISCV_EXCP_NONE;
1341 }
1342
1343 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
1344                                         target_ulong val)
1345 {
1346     if (!env->rdtime_fn) {
1347         return RISCV_EXCP_ILLEGAL_INST;
1348     }
1349
1350     env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1351     return RISCV_EXCP_NONE;
1352 }
1353
1354 /* Virtual CSR Registers */
1355 static RISCVException read_vsstatus(CPURISCVState *env, int csrno,
1356                                     target_ulong *val)
1357 {
1358     *val = env->vsstatus;
1359     return RISCV_EXCP_NONE;
1360 }
1361
1362 static RISCVException write_vsstatus(CPURISCVState *env, int csrno,
1363                                      target_ulong val)
1364 {
1365     uint64_t mask = (target_ulong)-1;
1366     env->vsstatus = (env->vsstatus & ~mask) | (uint64_t)val;
1367     return RISCV_EXCP_NONE;
1368 }
1369
1370 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1371 {
1372     *val = env->vstvec;
1373     return RISCV_EXCP_NONE;
1374 }
1375
1376 static RISCVException write_vstvec(CPURISCVState *env, int csrno,
1377                                    target_ulong val)
1378 {
1379     env->vstvec = val;
1380     return RISCV_EXCP_NONE;
1381 }
1382
1383 static RISCVException read_vsscratch(CPURISCVState *env, int csrno,
1384                                      target_ulong *val)
1385 {
1386     *val = env->vsscratch;
1387     return RISCV_EXCP_NONE;
1388 }
1389
1390 static RISCVException write_vsscratch(CPURISCVState *env, int csrno,
1391                                       target_ulong val)
1392 {
1393     env->vsscratch = val;
1394     return RISCV_EXCP_NONE;
1395 }
1396
1397 static RISCVException read_vsepc(CPURISCVState *env, int csrno,
1398                                  target_ulong *val)
1399 {
1400     *val = env->vsepc;
1401     return RISCV_EXCP_NONE;
1402 }
1403
1404 static RISCVException write_vsepc(CPURISCVState *env, int csrno,
1405                                   target_ulong val)
1406 {
1407     env->vsepc = val;
1408     return RISCV_EXCP_NONE;
1409 }
1410
1411 static RISCVException read_vscause(CPURISCVState *env, int csrno,
1412                                    target_ulong *val)
1413 {
1414     *val = env->vscause;
1415     return RISCV_EXCP_NONE;
1416 }
1417
1418 static RISCVException write_vscause(CPURISCVState *env, int csrno,
1419                                     target_ulong val)
1420 {
1421     env->vscause = val;
1422     return RISCV_EXCP_NONE;
1423 }
1424
1425 static RISCVException read_vstval(CPURISCVState *env, int csrno,
1426                                   target_ulong *val)
1427 {
1428     *val = env->vstval;
1429     return RISCV_EXCP_NONE;
1430 }
1431
1432 static RISCVException write_vstval(CPURISCVState *env, int csrno,
1433                                    target_ulong val)
1434 {
1435     env->vstval = val;
1436     return RISCV_EXCP_NONE;
1437 }
1438
1439 static RISCVException read_vsatp(CPURISCVState *env, int csrno,
1440                                  target_ulong *val)
1441 {
1442     *val = env->vsatp;
1443     return RISCV_EXCP_NONE;
1444 }
1445
1446 static RISCVException write_vsatp(CPURISCVState *env, int csrno,
1447                                   target_ulong val)
1448 {
1449     env->vsatp = val;
1450     return RISCV_EXCP_NONE;
1451 }
1452
1453 static RISCVException read_mtval2(CPURISCVState *env, int csrno,
1454                                   target_ulong *val)
1455 {
1456     *val = env->mtval2;
1457     return RISCV_EXCP_NONE;
1458 }
1459
1460 static RISCVException write_mtval2(CPURISCVState *env, int csrno,
1461                                    target_ulong val)
1462 {
1463     env->mtval2 = val;
1464     return RISCV_EXCP_NONE;
1465 }
1466
1467 static RISCVException read_mtinst(CPURISCVState *env, int csrno,
1468                                   target_ulong *val)
1469 {
1470     *val = env->mtinst;
1471     return RISCV_EXCP_NONE;
1472 }
1473
1474 static RISCVException write_mtinst(CPURISCVState *env, int csrno,
1475                                    target_ulong val)
1476 {
1477     env->mtinst = val;
1478     return RISCV_EXCP_NONE;
1479 }
1480
1481 /* Physical Memory Protection */
1482 static RISCVException read_mseccfg(CPURISCVState *env, int csrno,
1483                                    target_ulong *val)
1484 {
1485     *val = mseccfg_csr_read(env);
1486     return RISCV_EXCP_NONE;
1487 }
1488
1489 static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
1490                          target_ulong val)
1491 {
1492     mseccfg_csr_write(env, val);
1493     return RISCV_EXCP_NONE;
1494 }
1495
1496 static RISCVException read_pmpcfg(CPURISCVState *env, int csrno,
1497                                   target_ulong *val)
1498 {
1499     *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1500     return RISCV_EXCP_NONE;
1501 }
1502
1503 static RISCVException write_pmpcfg(CPURISCVState *env, int csrno,
1504                                    target_ulong val)
1505 {
1506     pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1507     return RISCV_EXCP_NONE;
1508 }
1509
1510 static RISCVException read_pmpaddr(CPURISCVState *env, int csrno,
1511                                    target_ulong *val)
1512 {
1513     *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1514     return RISCV_EXCP_NONE;
1515 }
1516
1517 static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
1518                                     target_ulong val)
1519 {
1520     pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1521     return RISCV_EXCP_NONE;
1522 }
1523
1524 /*
1525  * Functions to access Pointer Masking feature registers
1526  * We have to check if current priv lvl could modify
1527  * csr in given mode
1528  */
1529 static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
1530 {
1531     int csr_priv = get_field(csrno, 0x300);
1532     int pm_current;
1533
1534     /*
1535      * If priv lvls differ that means we're accessing csr from higher priv lvl,
1536      * so allow the access
1537      */
1538     if (env->priv != csr_priv) {
1539         return false;
1540     }
1541     switch (env->priv) {
1542     case PRV_M:
1543         pm_current = get_field(env->mmte, M_PM_CURRENT);
1544         break;
1545     case PRV_S:
1546         pm_current = get_field(env->mmte, S_PM_CURRENT);
1547         break;
1548     case PRV_U:
1549         pm_current = get_field(env->mmte, U_PM_CURRENT);
1550         break;
1551     default:
1552         g_assert_not_reached();
1553     }
1554     /* It's same priv lvl, so we allow to modify csr only if pm.current==1 */
1555     return !pm_current;
1556 }
1557
1558 static RISCVException read_mmte(CPURISCVState *env, int csrno,
1559                                 target_ulong *val)
1560 {
1561     *val = env->mmte & MMTE_MASK;
1562     return RISCV_EXCP_NONE;
1563 }
1564
1565 static RISCVException write_mmte(CPURISCVState *env, int csrno,
1566                                  target_ulong val)
1567 {
1568     uint64_t mstatus;
1569     target_ulong wpri_val = val & MMTE_MASK;
1570
1571     if (val != wpri_val) {
1572         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1573                       "MMTE: WPRI violation written 0x", val,
1574                       "vs expected 0x", wpri_val);
1575     }
1576     /* for machine mode pm.current is hardwired to 1 */
1577     wpri_val |= MMTE_M_PM_CURRENT;
1578
1579     /* hardwiring pm.instruction bit to 0, since it's not supported yet */
1580     wpri_val &= ~(MMTE_M_PM_INSN | MMTE_S_PM_INSN | MMTE_U_PM_INSN);
1581     env->mmte = wpri_val | PM_EXT_DIRTY;
1582
1583     /* Set XS and SD bits, since PM CSRs are dirty */
1584     mstatus = env->mstatus | MSTATUS_XS;
1585     write_mstatus(env, csrno, mstatus);
1586     return RISCV_EXCP_NONE;
1587 }
1588
1589 static RISCVException read_smte(CPURISCVState *env, int csrno,
1590                                 target_ulong *val)
1591 {
1592     *val = env->mmte & SMTE_MASK;
1593     return RISCV_EXCP_NONE;
1594 }
1595
1596 static RISCVException write_smte(CPURISCVState *env, int csrno,
1597                                  target_ulong val)
1598 {
1599     target_ulong wpri_val = val & SMTE_MASK;
1600
1601     if (val != wpri_val) {
1602         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1603                       "SMTE: WPRI violation written 0x", val,
1604                       "vs expected 0x", wpri_val);
1605     }
1606
1607     /* if pm.current==0 we can't modify current PM CSRs */
1608     if (check_pm_current_disabled(env, csrno)) {
1609         return RISCV_EXCP_NONE;
1610     }
1611
1612     wpri_val |= (env->mmte & ~SMTE_MASK);
1613     write_mmte(env, csrno, wpri_val);
1614     return RISCV_EXCP_NONE;
1615 }
1616
1617 static RISCVException read_umte(CPURISCVState *env, int csrno,
1618                                 target_ulong *val)
1619 {
1620     *val = env->mmte & UMTE_MASK;
1621     return RISCV_EXCP_NONE;
1622 }
1623
1624 static RISCVException write_umte(CPURISCVState *env, int csrno,
1625                                  target_ulong val)
1626 {
1627     target_ulong wpri_val = val & UMTE_MASK;
1628
1629     if (val != wpri_val) {
1630         qemu_log_mask(LOG_GUEST_ERROR, "%s" TARGET_FMT_lx " %s" TARGET_FMT_lx "\n",
1631                       "UMTE: WPRI violation written 0x", val,
1632                       "vs expected 0x", wpri_val);
1633     }
1634
1635     if (check_pm_current_disabled(env, csrno)) {
1636         return RISCV_EXCP_NONE;
1637     }
1638
1639     wpri_val |= (env->mmte & ~UMTE_MASK);
1640     write_mmte(env, csrno, wpri_val);
1641     return RISCV_EXCP_NONE;
1642 }
1643
1644 static RISCVException read_mpmmask(CPURISCVState *env, int csrno,
1645                                    target_ulong *val)
1646 {
1647     *val = env->mpmmask;
1648     return RISCV_EXCP_NONE;
1649 }
1650
1651 static RISCVException write_mpmmask(CPURISCVState *env, int csrno,
1652                                     target_ulong val)
1653 {
1654     uint64_t mstatus;
1655
1656     env->mpmmask = val;
1657     env->mmte |= PM_EXT_DIRTY;
1658
1659     /* Set XS and SD bits, since PM CSRs are dirty */
1660     mstatus = env->mstatus | MSTATUS_XS;
1661     write_mstatus(env, csrno, mstatus);
1662     return RISCV_EXCP_NONE;
1663 }
1664
1665 static RISCVException read_spmmask(CPURISCVState *env, int csrno,
1666                                    target_ulong *val)
1667 {
1668     *val = env->spmmask;
1669     return RISCV_EXCP_NONE;
1670 }
1671
1672 static RISCVException write_spmmask(CPURISCVState *env, int csrno,
1673                                     target_ulong val)
1674 {
1675     uint64_t mstatus;
1676
1677     /* if pm.current==0 we can't modify current PM CSRs */
1678     if (check_pm_current_disabled(env, csrno)) {
1679         return RISCV_EXCP_NONE;
1680     }
1681     env->spmmask = val;
1682     env->mmte |= PM_EXT_DIRTY;
1683
1684     /* Set XS and SD bits, since PM CSRs are dirty */
1685     mstatus = env->mstatus | MSTATUS_XS;
1686     write_mstatus(env, csrno, mstatus);
1687     return RISCV_EXCP_NONE;
1688 }
1689
1690 static RISCVException read_upmmask(CPURISCVState *env, int csrno,
1691                                    target_ulong *val)
1692 {
1693     *val = env->upmmask;
1694     return RISCV_EXCP_NONE;
1695 }
1696
1697 static RISCVException write_upmmask(CPURISCVState *env, int csrno,
1698                                     target_ulong val)
1699 {
1700     uint64_t mstatus;
1701
1702     /* if pm.current==0 we can't modify current PM CSRs */
1703     if (check_pm_current_disabled(env, csrno)) {
1704         return RISCV_EXCP_NONE;
1705     }
1706     env->upmmask = val;
1707     env->mmte |= PM_EXT_DIRTY;
1708
1709     /* Set XS and SD bits, since PM CSRs are dirty */
1710     mstatus = env->mstatus | MSTATUS_XS;
1711     write_mstatus(env, csrno, mstatus);
1712     return RISCV_EXCP_NONE;
1713 }
1714
1715 static RISCVException read_mpmbase(CPURISCVState *env, int csrno,
1716                                    target_ulong *val)
1717 {
1718     *val = env->mpmbase;
1719     return RISCV_EXCP_NONE;
1720 }
1721
1722 static RISCVException write_mpmbase(CPURISCVState *env, int csrno,
1723                                     target_ulong val)
1724 {
1725     uint64_t mstatus;
1726
1727     env->mpmbase = val;
1728     env->mmte |= PM_EXT_DIRTY;
1729
1730     /* Set XS and SD bits, since PM CSRs are dirty */
1731     mstatus = env->mstatus | MSTATUS_XS;
1732     write_mstatus(env, csrno, mstatus);
1733     return RISCV_EXCP_NONE;
1734 }
1735
1736 static RISCVException read_spmbase(CPURISCVState *env, int csrno,
1737                                    target_ulong *val)
1738 {
1739     *val = env->spmbase;
1740     return RISCV_EXCP_NONE;
1741 }
1742
1743 static RISCVException write_spmbase(CPURISCVState *env, int csrno,
1744                                     target_ulong val)
1745 {
1746     uint64_t mstatus;
1747
1748     /* if pm.current==0 we can't modify current PM CSRs */
1749     if (check_pm_current_disabled(env, csrno)) {
1750         return RISCV_EXCP_NONE;
1751     }
1752     env->spmbase = val;
1753     env->mmte |= PM_EXT_DIRTY;
1754
1755     /* Set XS and SD bits, since PM CSRs are dirty */
1756     mstatus = env->mstatus | MSTATUS_XS;
1757     write_mstatus(env, csrno, mstatus);
1758     return RISCV_EXCP_NONE;
1759 }
1760
1761 static RISCVException read_upmbase(CPURISCVState *env, int csrno,
1762                                    target_ulong *val)
1763 {
1764     *val = env->upmbase;
1765     return RISCV_EXCP_NONE;
1766 }
1767
1768 static RISCVException write_upmbase(CPURISCVState *env, int csrno,
1769                                     target_ulong val)
1770 {
1771     uint64_t mstatus;
1772
1773     /* if pm.current==0 we can't modify current PM CSRs */
1774     if (check_pm_current_disabled(env, csrno)) {
1775         return RISCV_EXCP_NONE;
1776     }
1777     env->upmbase = val;
1778     env->mmte |= PM_EXT_DIRTY;
1779
1780     /* Set XS and SD bits, since PM CSRs are dirty */
1781     mstatus = env->mstatus | MSTATUS_XS;
1782     write_mstatus(env, csrno, mstatus);
1783     return RISCV_EXCP_NONE;
1784 }
1785
1786 #endif
1787
1788 /*
1789  * riscv_csrrw - read and/or update control and status register
1790  *
1791  * csrr   <->  riscv_csrrw(env, csrno, ret_value, 0, 0);
1792  * csrrw  <->  riscv_csrrw(env, csrno, ret_value, value, -1);
1793  * csrrs  <->  riscv_csrrw(env, csrno, ret_value, -1, value);
1794  * csrrc  <->  riscv_csrrw(env, csrno, ret_value, 0, value);
1795  */
1796
1797 static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
1798                                                int csrno,
1799                                                bool write_mask,
1800                                                RISCVCPU *cpu)
1801 {
1802     /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
1803     int read_only = get_field(csrno, 0xC00) == 3;
1804 #if !defined(CONFIG_USER_ONLY)
1805     int effective_priv = env->priv;
1806
1807     if (riscv_has_ext(env, RVH) &&
1808         env->priv == PRV_S &&
1809         !riscv_cpu_virt_enabled(env)) {
1810         /*
1811          * We are in S mode without virtualisation, therefore we are in HS Mode.
1812          * Add 1 to the effective privledge level to allow us to access the
1813          * Hypervisor CSRs.
1814          */
1815         effective_priv++;
1816     }
1817
1818     if (!env->debugger && (effective_priv < get_field(csrno, 0x300))) {
1819         return RISCV_EXCP_ILLEGAL_INST;
1820     }
1821 #endif
1822     if (write_mask && read_only) {
1823         return RISCV_EXCP_ILLEGAL_INST;
1824     }
1825
1826     /* ensure the CSR extension is enabled. */
1827     if (!cpu->cfg.ext_icsr) {
1828         return RISCV_EXCP_ILLEGAL_INST;
1829     }
1830
1831     /* check predicate */
1832     if (!csr_ops[csrno].predicate) {
1833         return RISCV_EXCP_ILLEGAL_INST;
1834     }
1835
1836     return csr_ops[csrno].predicate(env, csrno);
1837 }
1838
1839 static RISCVException riscv_csrrw_do64(CPURISCVState *env, int csrno,
1840                                        target_ulong *ret_value,
1841                                        target_ulong new_value,
1842                                        target_ulong write_mask)
1843 {
1844     RISCVException ret;
1845     target_ulong old_value;
1846
1847     /* execute combined read/write operation if it exists */
1848     if (csr_ops[csrno].op) {
1849         return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1850     }
1851
1852     /* if no accessor exists then return failure */
1853     if (!csr_ops[csrno].read) {
1854         return RISCV_EXCP_ILLEGAL_INST;
1855     }
1856     /* read old value */
1857     ret = csr_ops[csrno].read(env, csrno, &old_value);
1858     if (ret != RISCV_EXCP_NONE) {
1859         return ret;
1860     }
1861
1862     /* write value if writable and write mask set, otherwise drop writes */
1863     if (write_mask) {
1864         new_value = (old_value & ~write_mask) | (new_value & write_mask);
1865         if (csr_ops[csrno].write) {
1866             ret = csr_ops[csrno].write(env, csrno, new_value);
1867             if (ret != RISCV_EXCP_NONE) {
1868                 return ret;
1869             }
1870         }
1871     }
1872
1873     /* return old value */
1874     if (ret_value) {
1875         *ret_value = old_value;
1876     }
1877
1878     return RISCV_EXCP_NONE;
1879 }
1880
1881 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
1882                            target_ulong *ret_value,
1883                            target_ulong new_value, target_ulong write_mask)
1884 {
1885     RISCVCPU *cpu = env_archcpu(env);
1886
1887     RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
1888     if (ret != RISCV_EXCP_NONE) {
1889         return ret;
1890     }
1891
1892     return riscv_csrrw_do64(env, csrno, ret_value, new_value, write_mask);
1893 }
1894
1895 static RISCVException riscv_csrrw_do128(CPURISCVState *env, int csrno,
1896                                         Int128 *ret_value,
1897                                         Int128 new_value,
1898                                         Int128 write_mask)
1899 {
1900     RISCVException ret;
1901     Int128 old_value;
1902
1903     /* read old value */
1904     ret = csr_ops[csrno].read128(env, csrno, &old_value);
1905     if (ret != RISCV_EXCP_NONE) {
1906         return ret;
1907     }
1908
1909     /* write value if writable and write mask set, otherwise drop writes */
1910     if (int128_nz(write_mask)) {
1911         new_value = int128_or(int128_and(old_value, int128_not(write_mask)),
1912                               int128_and(new_value, write_mask));
1913         if (csr_ops[csrno].write128) {
1914             ret = csr_ops[csrno].write128(env, csrno, new_value);
1915             if (ret != RISCV_EXCP_NONE) {
1916                 return ret;
1917             }
1918         } else if (csr_ops[csrno].write) {
1919             /* avoids having to write wrappers for all registers */
1920             ret = csr_ops[csrno].write(env, csrno, int128_getlo(new_value));
1921             if (ret != RISCV_EXCP_NONE) {
1922                 return ret;
1923             }
1924         }
1925     }
1926
1927     /* return old value */
1928     if (ret_value) {
1929         *ret_value = old_value;
1930     }
1931
1932     return RISCV_EXCP_NONE;
1933 }
1934
1935 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
1936                                 Int128 *ret_value,
1937                                 Int128 new_value, Int128 write_mask)
1938 {
1939     RISCVException ret;
1940     RISCVCPU *cpu = env_archcpu(env);
1941
1942     ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu);
1943     if (ret != RISCV_EXCP_NONE) {
1944         return ret;
1945     }
1946
1947     if (csr_ops[csrno].read128) {
1948         return riscv_csrrw_do128(env, csrno, ret_value, new_value, write_mask);
1949     }
1950
1951     /*
1952      * Fall back to 64-bit version for now, if the 128-bit alternative isn't
1953      * at all defined.
1954      * Note, some CSRs don't need to extend to MXLEN (64 upper bits non
1955      * significant), for those, this fallback is correctly handling the accesses
1956      */
1957     target_ulong old_value;
1958     ret = riscv_csrrw_do64(env, csrno, &old_value,
1959                            int128_getlo(new_value),
1960                            int128_getlo(write_mask));
1961     if (ret == RISCV_EXCP_NONE && ret_value) {
1962         *ret_value = int128_make64(old_value);
1963     }
1964     return ret;
1965 }
1966
1967 /*
1968  * Debugger support.  If not in user mode, set env->debugger before the
1969  * riscv_csrrw call and clear it after the call.
1970  */
1971 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
1972                                  target_ulong *ret_value,
1973                                  target_ulong new_value,
1974                                  target_ulong write_mask)
1975 {
1976     RISCVException ret;
1977 #if !defined(CONFIG_USER_ONLY)
1978     env->debugger = true;
1979 #endif
1980     ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1981 #if !defined(CONFIG_USER_ONLY)
1982     env->debugger = false;
1983 #endif
1984     return ret;
1985 }
1986
1987 /* Control and Status Register function table */
1988 riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1989     /* User Floating-Point CSRs */
1990     [CSR_FFLAGS]   = { "fflags",   fs,     read_fflags,  write_fflags },
1991     [CSR_FRM]      = { "frm",      fs,     read_frm,     write_frm    },
1992     [CSR_FCSR]     = { "fcsr",     fs,     read_fcsr,    write_fcsr   },
1993     /* Vector CSRs */
1994     [CSR_VSTART]   = { "vstart",   vs,     read_vstart,  write_vstart },
1995     [CSR_VXSAT]    = { "vxsat",    vs,     read_vxsat,   write_vxsat  },
1996     [CSR_VXRM]     = { "vxrm",     vs,     read_vxrm,    write_vxrm   },
1997     [CSR_VCSR]     = { "vcsr",     vs,     read_vcsr,    write_vcsr   },
1998     [CSR_VL]       = { "vl",       vs,     read_vl                    },
1999     [CSR_VTYPE]    = { "vtype",    vs,     read_vtype                 },
2000     [CSR_VLENB]    = { "vlenb",    vs,     read_vlenb                 },
2001     /* User Timers and Counters */
2002     [CSR_CYCLE]    = { "cycle",    ctr,    read_instret  },
2003     [CSR_INSTRET]  = { "instret",  ctr,    read_instret  },
2004     [CSR_CYCLEH]   = { "cycleh",   ctr32,  read_instreth },
2005     [CSR_INSTRETH] = { "instreth", ctr32,  read_instreth },
2006
2007     /*
2008      * In privileged mode, the monitor will have to emulate TIME CSRs only if
2009      * rdtime callback is not provided by machine/platform emulation.
2010      */
2011     [CSR_TIME]  = { "time",  ctr,   read_time  },
2012     [CSR_TIMEH] = { "timeh", ctr32, read_timeh },
2013
2014 #if !defined(CONFIG_USER_ONLY)
2015     /* Machine Timers and Counters */
2016     [CSR_MCYCLE]    = { "mcycle",    any,   read_instret  },
2017     [CSR_MINSTRET]  = { "minstret",  any,   read_instret  },
2018     [CSR_MCYCLEH]   = { "mcycleh",   any32, read_instreth },
2019     [CSR_MINSTRETH] = { "minstreth", any32, read_instreth },
2020
2021     /* Machine Information Registers */
2022     [CSR_MVENDORID] = { "mvendorid", any,   read_zero    },
2023     [CSR_MARCHID]   = { "marchid",   any,   read_zero    },
2024     [CSR_MIMPID]    = { "mimpid",    any,   read_zero    },
2025     [CSR_MHARTID]   = { "mhartid",   any,   read_mhartid },
2026
2027     /* Machine Trap Setup */
2028     [CSR_MSTATUS]     = { "mstatus",    any,   read_mstatus,     write_mstatus, NULL,
2029                                                read_mstatus_i128                   },
2030     [CSR_MISA]        = { "misa",       any,   read_misa,        write_misa, NULL,
2031                                                read_misa_i128                      },
2032     [CSR_MIDELEG]     = { "mideleg",    any,   read_mideleg,     write_mideleg     },
2033     [CSR_MEDELEG]     = { "medeleg",    any,   read_medeleg,     write_medeleg     },
2034     [CSR_MIE]         = { "mie",        any,   read_mie,         write_mie         },
2035     [CSR_MTVEC]       = { "mtvec",      any,   read_mtvec,       write_mtvec       },
2036     [CSR_MCOUNTEREN]  = { "mcounteren", any,   read_mcounteren,  write_mcounteren  },
2037
2038     [CSR_MSTATUSH]    = { "mstatush",   any32, read_mstatush,    write_mstatush    },
2039
2040     /* Machine Trap Handling */
2041     [CSR_MSCRATCH] = { "mscratch", any,  read_mscratch,      write_mscratch, NULL,
2042                                          read_mscratch_i128, write_mscratch_i128   },
2043     [CSR_MEPC]     = { "mepc",     any,  read_mepc,     write_mepc     },
2044     [CSR_MCAUSE]   = { "mcause",   any,  read_mcause,   write_mcause   },
2045     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
2046     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
2047
2048     /* Supervisor Trap Setup */
2049     [CSR_SSTATUS]    = { "sstatus",    smode, read_sstatus,    write_sstatus, NULL,
2050                                               read_sstatus_i128                 },
2051     [CSR_SIE]        = { "sie",        smode, read_sie,        write_sie        },
2052     [CSR_STVEC]      = { "stvec",      smode, read_stvec,      write_stvec      },
2053     [CSR_SCOUNTEREN] = { "scounteren", smode, read_scounteren, write_scounteren },
2054
2055     /* Supervisor Trap Handling */
2056     [CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch, NULL,
2057                                           read_sscratch_i128, write_sscratch_i128  },
2058     [CSR_SEPC]     = { "sepc",     smode, read_sepc,     write_sepc     },
2059     [CSR_SCAUSE]   = { "scause",   smode, read_scause,   write_scause   },
2060     [CSR_STVAL]    = { "stval",    smode, read_stval,   write_stval   },
2061     [CSR_SIP]      = { "sip",      smode, NULL,    NULL, rmw_sip        },
2062
2063     /* Supervisor Protection and Translation */
2064     [CSR_SATP]     = { "satp",     smode, read_satp,    write_satp      },
2065
2066     [CSR_HSTATUS]     = { "hstatus",     hmode,   read_hstatus,     write_hstatus     },
2067     [CSR_HEDELEG]     = { "hedeleg",     hmode,   read_hedeleg,     write_hedeleg     },
2068     [CSR_HIDELEG]     = { "hideleg",     hmode,   read_hideleg,     write_hideleg     },
2069     [CSR_HVIP]        = { "hvip",        hmode,   NULL,   NULL,     rmw_hvip          },
2070     [CSR_HIP]         = { "hip",         hmode,   NULL,   NULL,     rmw_hip           },
2071     [CSR_HIE]         = { "hie",         hmode,   read_hie,         write_hie         },
2072     [CSR_HCOUNTEREN]  = { "hcounteren",  hmode,   read_hcounteren,  write_hcounteren  },
2073     [CSR_HGEIE]       = { "hgeie",       hmode,   read_zero,        write_hgeie       },
2074     [CSR_HTVAL]       = { "htval",       hmode,   read_htval,       write_htval       },
2075     [CSR_HTINST]      = { "htinst",      hmode,   read_htinst,      write_htinst      },
2076     [CSR_HGEIP]       = { "hgeip",       hmode,   read_zero,        write_hgeip       },
2077     [CSR_HGATP]       = { "hgatp",       hmode,   read_hgatp,       write_hgatp       },
2078     [CSR_HTIMEDELTA]  = { "htimedelta",  hmode,   read_htimedelta,  write_htimedelta  },
2079     [CSR_HTIMEDELTAH] = { "htimedeltah", hmode32, read_htimedeltah, write_htimedeltah },
2080
2081     [CSR_VSSTATUS]    = { "vsstatus",    hmode,   read_vsstatus,    write_vsstatus    },
2082     [CSR_VSIP]        = { "vsip",        hmode,   NULL,    NULL,    rmw_vsip          },
2083     [CSR_VSIE]        = { "vsie",        hmode,   read_vsie,        write_vsie        },
2084     [CSR_VSTVEC]      = { "vstvec",      hmode,   read_vstvec,      write_vstvec      },
2085     [CSR_VSSCRATCH]   = { "vsscratch",   hmode,   read_vsscratch,   write_vsscratch   },
2086     [CSR_VSEPC]       = { "vsepc",       hmode,   read_vsepc,       write_vsepc       },
2087     [CSR_VSCAUSE]     = { "vscause",     hmode,   read_vscause,     write_vscause     },
2088     [CSR_VSTVAL]      = { "vstval",      hmode,   read_vstval,      write_vstval      },
2089     [CSR_VSATP]       = { "vsatp",       hmode,   read_vsatp,       write_vsatp       },
2090
2091     [CSR_MTVAL2]      = { "mtval2",      hmode,   read_mtval2,      write_mtval2      },
2092     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
2093
2094     /* Physical Memory Protection */
2095     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg },
2096     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
2097     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
2098     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
2099     [CSR_PMPCFG3]    = { "pmpcfg3",   pmp, read_pmpcfg,  write_pmpcfg  },
2100     [CSR_PMPADDR0]   = { "pmpaddr0",  pmp, read_pmpaddr, write_pmpaddr },
2101     [CSR_PMPADDR1]   = { "pmpaddr1",  pmp, read_pmpaddr, write_pmpaddr },
2102     [CSR_PMPADDR2]   = { "pmpaddr2",  pmp, read_pmpaddr, write_pmpaddr },
2103     [CSR_PMPADDR3]   = { "pmpaddr3",  pmp, read_pmpaddr, write_pmpaddr },
2104     [CSR_PMPADDR4]   = { "pmpaddr4",  pmp, read_pmpaddr, write_pmpaddr },
2105     [CSR_PMPADDR5]   = { "pmpaddr5",  pmp, read_pmpaddr, write_pmpaddr },
2106     [CSR_PMPADDR6]   = { "pmpaddr6",  pmp, read_pmpaddr, write_pmpaddr },
2107     [CSR_PMPADDR7]   = { "pmpaddr7",  pmp, read_pmpaddr, write_pmpaddr },
2108     [CSR_PMPADDR8]   = { "pmpaddr8",  pmp, read_pmpaddr, write_pmpaddr },
2109     [CSR_PMPADDR9]   = { "pmpaddr9",  pmp, read_pmpaddr, write_pmpaddr },
2110     [CSR_PMPADDR10]  = { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr },
2111     [CSR_PMPADDR11]  = { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr },
2112     [CSR_PMPADDR12]  = { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr },
2113     [CSR_PMPADDR13]  = { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr },
2114     [CSR_PMPADDR14] =  { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
2115     [CSR_PMPADDR15] =  { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
2116
2117     /* User Pointer Masking */
2118     [CSR_UMTE]    =    { "umte",    pointer_masking, read_umte,    write_umte    },
2119     [CSR_UPMMASK] =    { "upmmask", pointer_masking, read_upmmask, write_upmmask },
2120     [CSR_UPMBASE] =    { "upmbase", pointer_masking, read_upmbase, write_upmbase },
2121     /* Machine Pointer Masking */
2122     [CSR_MMTE]    =    { "mmte",    pointer_masking, read_mmte,    write_mmte    },
2123     [CSR_MPMMASK] =    { "mpmmask", pointer_masking, read_mpmmask, write_mpmmask },
2124     [CSR_MPMBASE] =    { "mpmbase", pointer_masking, read_mpmbase, write_mpmbase },
2125     /* Supervisor Pointer Masking */
2126     [CSR_SMTE]    =    { "smte",    pointer_masking, read_smte,    write_smte    },
2127     [CSR_SPMMASK] =    { "spmmask", pointer_masking, read_spmmask, write_spmmask },
2128     [CSR_SPMBASE] =    { "spmbase", pointer_masking, read_spmbase, write_spmbase },
2129
2130     /* Performance Counters */
2131     [CSR_HPMCOUNTER3]    = { "hpmcounter3",    ctr,    read_zero },
2132     [CSR_HPMCOUNTER4]    = { "hpmcounter4",    ctr,    read_zero },
2133     [CSR_HPMCOUNTER5]    = { "hpmcounter5",    ctr,    read_zero },
2134     [CSR_HPMCOUNTER6]    = { "hpmcounter6",    ctr,    read_zero },
2135     [CSR_HPMCOUNTER7]    = { "hpmcounter7",    ctr,    read_zero },
2136     [CSR_HPMCOUNTER8]    = { "hpmcounter8",    ctr,    read_zero },
2137     [CSR_HPMCOUNTER9]    = { "hpmcounter9",    ctr,    read_zero },
2138     [CSR_HPMCOUNTER10]   = { "hpmcounter10",   ctr,    read_zero },
2139     [CSR_HPMCOUNTER11]   = { "hpmcounter11",   ctr,    read_zero },
2140     [CSR_HPMCOUNTER12]   = { "hpmcounter12",   ctr,    read_zero },
2141     [CSR_HPMCOUNTER13]   = { "hpmcounter13",   ctr,    read_zero },
2142     [CSR_HPMCOUNTER14]   = { "hpmcounter14",   ctr,    read_zero },
2143     [CSR_HPMCOUNTER15]   = { "hpmcounter15",   ctr,    read_zero },
2144     [CSR_HPMCOUNTER16]   = { "hpmcounter16",   ctr,    read_zero },
2145     [CSR_HPMCOUNTER17]   = { "hpmcounter17",   ctr,    read_zero },
2146     [CSR_HPMCOUNTER18]   = { "hpmcounter18",   ctr,    read_zero },
2147     [CSR_HPMCOUNTER19]   = { "hpmcounter19",   ctr,    read_zero },
2148     [CSR_HPMCOUNTER20]   = { "hpmcounter20",   ctr,    read_zero },
2149     [CSR_HPMCOUNTER21]   = { "hpmcounter21",   ctr,    read_zero },
2150     [CSR_HPMCOUNTER22]   = { "hpmcounter22",   ctr,    read_zero },
2151     [CSR_HPMCOUNTER23]   = { "hpmcounter23",   ctr,    read_zero },
2152     [CSR_HPMCOUNTER24]   = { "hpmcounter24",   ctr,    read_zero },
2153     [CSR_HPMCOUNTER25]   = { "hpmcounter25",   ctr,    read_zero },
2154     [CSR_HPMCOUNTER26]   = { "hpmcounter26",   ctr,    read_zero },
2155     [CSR_HPMCOUNTER27]   = { "hpmcounter27",   ctr,    read_zero },
2156     [CSR_HPMCOUNTER28]   = { "hpmcounter28",   ctr,    read_zero },
2157     [CSR_HPMCOUNTER29]   = { "hpmcounter29",   ctr,    read_zero },
2158     [CSR_HPMCOUNTER30]   = { "hpmcounter30",   ctr,    read_zero },
2159     [CSR_HPMCOUNTER31]   = { "hpmcounter31",   ctr,    read_zero },
2160
2161     [CSR_MHPMCOUNTER3]   = { "mhpmcounter3",   any,    read_zero },
2162     [CSR_MHPMCOUNTER4]   = { "mhpmcounter4",   any,    read_zero },
2163     [CSR_MHPMCOUNTER5]   = { "mhpmcounter5",   any,    read_zero },
2164     [CSR_MHPMCOUNTER6]   = { "mhpmcounter6",   any,    read_zero },
2165     [CSR_MHPMCOUNTER7]   = { "mhpmcounter7",   any,    read_zero },
2166     [CSR_MHPMCOUNTER8]   = { "mhpmcounter8",   any,    read_zero },
2167     [CSR_MHPMCOUNTER9]   = { "mhpmcounter9",   any,    read_zero },
2168     [CSR_MHPMCOUNTER10]  = { "mhpmcounter10",  any,    read_zero },
2169     [CSR_MHPMCOUNTER11]  = { "mhpmcounter11",  any,    read_zero },
2170     [CSR_MHPMCOUNTER12]  = { "mhpmcounter12",  any,    read_zero },
2171     [CSR_MHPMCOUNTER13]  = { "mhpmcounter13",  any,    read_zero },
2172     [CSR_MHPMCOUNTER14]  = { "mhpmcounter14",  any,    read_zero },
2173     [CSR_MHPMCOUNTER15]  = { "mhpmcounter15",  any,    read_zero },
2174     [CSR_MHPMCOUNTER16]  = { "mhpmcounter16",  any,    read_zero },
2175     [CSR_MHPMCOUNTER17]  = { "mhpmcounter17",  any,    read_zero },
2176     [CSR_MHPMCOUNTER18]  = { "mhpmcounter18",  any,    read_zero },
2177     [CSR_MHPMCOUNTER19]  = { "mhpmcounter19",  any,    read_zero },
2178     [CSR_MHPMCOUNTER20]  = { "mhpmcounter20",  any,    read_zero },
2179     [CSR_MHPMCOUNTER21]  = { "mhpmcounter21",  any,    read_zero },
2180     [CSR_MHPMCOUNTER22]  = { "mhpmcounter22",  any,    read_zero },
2181     [CSR_MHPMCOUNTER23]  = { "mhpmcounter23",  any,    read_zero },
2182     [CSR_MHPMCOUNTER24]  = { "mhpmcounter24",  any,    read_zero },
2183     [CSR_MHPMCOUNTER25]  = { "mhpmcounter25",  any,    read_zero },
2184     [CSR_MHPMCOUNTER26]  = { "mhpmcounter26",  any,    read_zero },
2185     [CSR_MHPMCOUNTER27]  = { "mhpmcounter27",  any,    read_zero },
2186     [CSR_MHPMCOUNTER28]  = { "mhpmcounter28",  any,    read_zero },
2187     [CSR_MHPMCOUNTER29]  = { "mhpmcounter29",  any,    read_zero },
2188     [CSR_MHPMCOUNTER30]  = { "mhpmcounter30",  any,    read_zero },
2189     [CSR_MHPMCOUNTER31]  = { "mhpmcounter31",  any,    read_zero },
2190
2191     [CSR_MHPMEVENT3]     = { "mhpmevent3",     any,    read_zero },
2192     [CSR_MHPMEVENT4]     = { "mhpmevent4",     any,    read_zero },
2193     [CSR_MHPMEVENT5]     = { "mhpmevent5",     any,    read_zero },
2194     [CSR_MHPMEVENT6]     = { "mhpmevent6",     any,    read_zero },
2195     [CSR_MHPMEVENT7]     = { "mhpmevent7",     any,    read_zero },
2196     [CSR_MHPMEVENT8]     = { "mhpmevent8",     any,    read_zero },
2197     [CSR_MHPMEVENT9]     = { "mhpmevent9",     any,    read_zero },
2198     [CSR_MHPMEVENT10]    = { "mhpmevent10",    any,    read_zero },
2199     [CSR_MHPMEVENT11]    = { "mhpmevent11",    any,    read_zero },
2200     [CSR_MHPMEVENT12]    = { "mhpmevent12",    any,    read_zero },
2201     [CSR_MHPMEVENT13]    = { "mhpmevent13",    any,    read_zero },
2202     [CSR_MHPMEVENT14]    = { "mhpmevent14",    any,    read_zero },
2203     [CSR_MHPMEVENT15]    = { "mhpmevent15",    any,    read_zero },
2204     [CSR_MHPMEVENT16]    = { "mhpmevent16",    any,    read_zero },
2205     [CSR_MHPMEVENT17]    = { "mhpmevent17",    any,    read_zero },
2206     [CSR_MHPMEVENT18]    = { "mhpmevent18",    any,    read_zero },
2207     [CSR_MHPMEVENT19]    = { "mhpmevent19",    any,    read_zero },
2208     [CSR_MHPMEVENT20]    = { "mhpmevent20",    any,    read_zero },
2209     [CSR_MHPMEVENT21]    = { "mhpmevent21",    any,    read_zero },
2210     [CSR_MHPMEVENT22]    = { "mhpmevent22",    any,    read_zero },
2211     [CSR_MHPMEVENT23]    = { "mhpmevent23",    any,    read_zero },
2212     [CSR_MHPMEVENT24]    = { "mhpmevent24",    any,    read_zero },
2213     [CSR_MHPMEVENT25]    = { "mhpmevent25",    any,    read_zero },
2214     [CSR_MHPMEVENT26]    = { "mhpmevent26",    any,    read_zero },
2215     [CSR_MHPMEVENT27]    = { "mhpmevent27",    any,    read_zero },
2216     [CSR_MHPMEVENT28]    = { "mhpmevent28",    any,    read_zero },
2217     [CSR_MHPMEVENT29]    = { "mhpmevent29",    any,    read_zero },
2218     [CSR_MHPMEVENT30]    = { "mhpmevent30",    any,    read_zero },
2219     [CSR_MHPMEVENT31]    = { "mhpmevent31",    any,    read_zero },
2220
2221     [CSR_HPMCOUNTER3H]   = { "hpmcounter3h",   ctr32,  read_zero },
2222     [CSR_HPMCOUNTER4H]   = { "hpmcounter4h",   ctr32,  read_zero },
2223     [CSR_HPMCOUNTER5H]   = { "hpmcounter5h",   ctr32,  read_zero },
2224     [CSR_HPMCOUNTER6H]   = { "hpmcounter6h",   ctr32,  read_zero },
2225     [CSR_HPMCOUNTER7H]   = { "hpmcounter7h",   ctr32,  read_zero },
2226     [CSR_HPMCOUNTER8H]   = { "hpmcounter8h",   ctr32,  read_zero },
2227     [CSR_HPMCOUNTER9H]   = { "hpmcounter9h",   ctr32,  read_zero },
2228     [CSR_HPMCOUNTER10H]  = { "hpmcounter10h",  ctr32,  read_zero },
2229     [CSR_HPMCOUNTER11H]  = { "hpmcounter11h",  ctr32,  read_zero },
2230     [CSR_HPMCOUNTER12H]  = { "hpmcounter12h",  ctr32,  read_zero },
2231     [CSR_HPMCOUNTER13H]  = { "hpmcounter13h",  ctr32,  read_zero },
2232     [CSR_HPMCOUNTER14H]  = { "hpmcounter14h",  ctr32,  read_zero },
2233     [CSR_HPMCOUNTER15H]  = { "hpmcounter15h",  ctr32,  read_zero },
2234     [CSR_HPMCOUNTER16H]  = { "hpmcounter16h",  ctr32,  read_zero },
2235     [CSR_HPMCOUNTER17H]  = { "hpmcounter17h",  ctr32,  read_zero },
2236     [CSR_HPMCOUNTER18H]  = { "hpmcounter18h",  ctr32,  read_zero },
2237     [CSR_HPMCOUNTER19H]  = { "hpmcounter19h",  ctr32,  read_zero },
2238     [CSR_HPMCOUNTER20H]  = { "hpmcounter20h",  ctr32,  read_zero },
2239     [CSR_HPMCOUNTER21H]  = { "hpmcounter21h",  ctr32,  read_zero },
2240     [CSR_HPMCOUNTER22H]  = { "hpmcounter22h",  ctr32,  read_zero },
2241     [CSR_HPMCOUNTER23H]  = { "hpmcounter23h",  ctr32,  read_zero },
2242     [CSR_HPMCOUNTER24H]  = { "hpmcounter24h",  ctr32,  read_zero },
2243     [CSR_HPMCOUNTER25H]  = { "hpmcounter25h",  ctr32,  read_zero },
2244     [CSR_HPMCOUNTER26H]  = { "hpmcounter26h",  ctr32,  read_zero },
2245     [CSR_HPMCOUNTER27H]  = { "hpmcounter27h",  ctr32,  read_zero },
2246     [CSR_HPMCOUNTER28H]  = { "hpmcounter28h",  ctr32,  read_zero },
2247     [CSR_HPMCOUNTER29H]  = { "hpmcounter29h",  ctr32,  read_zero },
2248     [CSR_HPMCOUNTER30H]  = { "hpmcounter30h",  ctr32,  read_zero },
2249     [CSR_HPMCOUNTER31H]  = { "hpmcounter31h",  ctr32,  read_zero },
2250
2251     [CSR_MHPMCOUNTER3H]  = { "mhpmcounter3h",  any32,  read_zero },
2252     [CSR_MHPMCOUNTER4H]  = { "mhpmcounter4h",  any32,  read_zero },
2253     [CSR_MHPMCOUNTER5H]  = { "mhpmcounter5h",  any32,  read_zero },
2254     [CSR_MHPMCOUNTER6H]  = { "mhpmcounter6h",  any32,  read_zero },
2255     [CSR_MHPMCOUNTER7H]  = { "mhpmcounter7h",  any32,  read_zero },
2256     [CSR_MHPMCOUNTER8H]  = { "mhpmcounter8h",  any32,  read_zero },
2257     [CSR_MHPMCOUNTER9H]  = { "mhpmcounter9h",  any32,  read_zero },
2258     [CSR_MHPMCOUNTER10H] = { "mhpmcounter10h", any32,  read_zero },
2259     [CSR_MHPMCOUNTER11H] = { "mhpmcounter11h", any32,  read_zero },
2260     [CSR_MHPMCOUNTER12H] = { "mhpmcounter12h", any32,  read_zero },
2261     [CSR_MHPMCOUNTER13H] = { "mhpmcounter13h", any32,  read_zero },
2262     [CSR_MHPMCOUNTER14H] = { "mhpmcounter14h", any32,  read_zero },
2263     [CSR_MHPMCOUNTER15H] = { "mhpmcounter15h", any32,  read_zero },
2264     [CSR_MHPMCOUNTER16H] = { "mhpmcounter16h", any32,  read_zero },
2265     [CSR_MHPMCOUNTER17H] = { "mhpmcounter17h", any32,  read_zero },
2266     [CSR_MHPMCOUNTER18H] = { "mhpmcounter18h", any32,  read_zero },
2267     [CSR_MHPMCOUNTER19H] = { "mhpmcounter19h", any32,  read_zero },
2268     [CSR_MHPMCOUNTER20H] = { "mhpmcounter20h", any32,  read_zero },
2269     [CSR_MHPMCOUNTER21H] = { "mhpmcounter21h", any32,  read_zero },
2270     [CSR_MHPMCOUNTER22H] = { "mhpmcounter22h", any32,  read_zero },
2271     [CSR_MHPMCOUNTER23H] = { "mhpmcounter23h", any32,  read_zero },
2272     [CSR_MHPMCOUNTER24H] = { "mhpmcounter24h", any32,  read_zero },
2273     [CSR_MHPMCOUNTER25H] = { "mhpmcounter25h", any32,  read_zero },
2274     [CSR_MHPMCOUNTER26H] = { "mhpmcounter26h", any32,  read_zero },
2275     [CSR_MHPMCOUNTER27H] = { "mhpmcounter27h", any32,  read_zero },
2276     [CSR_MHPMCOUNTER28H] = { "mhpmcounter28h", any32,  read_zero },
2277     [CSR_MHPMCOUNTER29H] = { "mhpmcounter29h", any32,  read_zero },
2278     [CSR_MHPMCOUNTER30H] = { "mhpmcounter30h", any32,  read_zero },
2279     [CSR_MHPMCOUNTER31H] = { "mhpmcounter31h", any32,  read_zero },
2280 #endif /* !CONFIG_USER_ONLY */
2281 };