hw/arm/aspeed_soc.c

   1 /*
   2  * ASPEED SoC family
   3  *
   4  * Andrew Jeffery <[email protected]>
   5  * Jeremy Kerr <[email protected]>
   6  *
   7  * Copyright 2016 IBM Corp.
   8  *
   9  * This code is licensed under the GPL version 2 or later.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "cpu.h"
  16 #include "exec/address-spaces.h"
  17 #include "hw/misc/unimp.h"
  18 #include "hw/arm/aspeed_soc.h"
  19 #include "hw/char/serial.h"
  20 #include "qemu/log.h"
  21 #include "qemu/module.h"
  22 #include "qemu/error-report.h"
  23 #include "hw/i2c/aspeed_i2c.h"
  24 #include "net/net.h"
  25 #include "sysemu/sysemu.h"
  26
  27 #define ASPEED_SOC_IOMEM_SIZE       0x00200000
  28
  29 static const hwaddr aspeed_soc_ast2400_memmap[] = {
  30     [ASPEED_IOMEM]  = 0x1E600000,
  31     [ASPEED_FMC]    = 0x1E620000,
  32     [ASPEED_SPI1]   = 0x1E630000,
  33     [ASPEED_EHCI1]  = 0x1E6A1000,
  34     [ASPEED_VIC]    = 0x1E6C0000,
  35     [ASPEED_SDMC]   = 0x1E6E0000,
  36     [ASPEED_SCU]    = 0x1E6E2000,
  37     [ASPEED_XDMA]   = 0x1E6E7000,
  38     [ASPEED_VIDEO]  = 0x1E700000,
  39     [ASPEED_ADC]    = 0x1E6E9000,
  40     [ASPEED_SRAM]   = 0x1E720000,
  41     [ASPEED_SDHCI]  = 0x1E740000,
  42     [ASPEED_GPIO]   = 0x1E780000,
  43     [ASPEED_RTC]    = 0x1E781000,
  44     [ASPEED_TIMER1] = 0x1E782000,
  45     [ASPEED_WDT]    = 0x1E785000,
  46     [ASPEED_PWM]    = 0x1E786000,
  47     [ASPEED_LPC]    = 0x1E789000,
  48     [ASPEED_IBT]    = 0x1E789140,
  49     [ASPEED_I2C]    = 0x1E78A000,
  50     [ASPEED_ETH1]   = 0x1E660000,
  51     [ASPEED_ETH2]   = 0x1E680000,
  52     [ASPEED_UART1]  = 0x1E783000,
  53     [ASPEED_UART5]  = 0x1E784000,
  54     [ASPEED_VUART]  = 0x1E787000,
  55     [ASPEED_SDRAM]  = 0x40000000,
  56 };
  57
  58 static const hwaddr aspeed_soc_ast2500_memmap[] = {
  59     [ASPEED_IOMEM]  = 0x1E600000,
  60     [ASPEED_FMC]    = 0x1E620000,
  61     [ASPEED_SPI1]   = 0x1E630000,
  62     [ASPEED_SPI2]   = 0x1E631000,
  63     [ASPEED_EHCI1]  = 0x1E6A1000,
  64     [ASPEED_EHCI2]  = 0x1E6A3000,
  65     [ASPEED_VIC]    = 0x1E6C0000,
  66     [ASPEED_SDMC]   = 0x1E6E0000,
  67     [ASPEED_SCU]    = 0x1E6E2000,
  68     [ASPEED_XDMA]   = 0x1E6E7000,
  69     [ASPEED_ADC]    = 0x1E6E9000,
  70     [ASPEED_VIDEO]  = 0x1E700000,
  71     [ASPEED_SRAM]   = 0x1E720000,
  72     [ASPEED_SDHCI]  = 0x1E740000,
  73     [ASPEED_GPIO]   = 0x1E780000,
  74     [ASPEED_RTC]    = 0x1E781000,
  75     [ASPEED_TIMER1] = 0x1E782000,
  76     [ASPEED_WDT]    = 0x1E785000,
  77     [ASPEED_PWM]    = 0x1E786000,
  78     [ASPEED_LPC]    = 0x1E789000,
  79     [ASPEED_IBT]    = 0x1E789140,
  80     [ASPEED_I2C]    = 0x1E78A000,
  81     [ASPEED_ETH1]   = 0x1E660000,
  82     [ASPEED_ETH2]   = 0x1E680000,
  83     [ASPEED_UART1]  = 0x1E783000,
  84     [ASPEED_UART5]  = 0x1E784000,
  85     [ASPEED_VUART]  = 0x1E787000,
  86     [ASPEED_SDRAM]  = 0x80000000,
  87 };
  88
  89 static const int aspeed_soc_ast2400_irqmap[] = {
  90     [ASPEED_UART1]  = 9,
  91     [ASPEED_UART2]  = 32,
  92     [ASPEED_UART3]  = 33,
  93     [ASPEED_UART4]  = 34,
  94     [ASPEED_UART5]  = 10,
  95     [ASPEED_VUART]  = 8,
  96     [ASPEED_FMC]    = 19,
  97     [ASPEED_EHCI1]  = 5,
  98     [ASPEED_EHCI2]  = 13,
  99     [ASPEED_SDMC]   = 0,
 100     [ASPEED_SCU]    = 21,
 101     [ASPEED_ADC]    = 31,
 102     [ASPEED_GPIO]   = 20,
 103     [ASPEED_RTC]    = 22,
 104     [ASPEED_TIMER1] = 16,
 105     [ASPEED_TIMER2] = 17,
 106     [ASPEED_TIMER3] = 18,
 107     [ASPEED_TIMER4] = 35,
 108     [ASPEED_TIMER5] = 36,
 109     [ASPEED_TIMER6] = 37,
 110     [ASPEED_TIMER7] = 38,
 111     [ASPEED_TIMER8] = 39,
 112     [ASPEED_WDT]    = 27,
 113     [ASPEED_PWM]    = 28,
 114     [ASPEED_LPC]    = 8,
 115     [ASPEED_IBT]    = 8, /* LPC */
 116     [ASPEED_I2C]    = 12,
 117     [ASPEED_ETH1]   = 2,
 118     [ASPEED_ETH2]   = 3,
 119     [ASPEED_XDMA]   = 6,
 120     [ASPEED_SDHCI]  = 26,
 121 };
 122
 123 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
 124
 125 static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
 126 {
 127     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 128
 129     return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]);
 130 }
 131
 132 static void aspeed_soc_init(Object *obj)
 133 {
 134     AspeedSoCState *s = ASPEED_SOC(obj);
 135     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 136     int i;
 137     char socname[8];
 138     char typename[64];
 139
 140     if (sscanf(sc->name, "%7s", socname) != 1) {
 141         g_assert_not_reached();
 142     }
 143
 144     for (i = 0; i < sc->num_cpus; i++) {
 145         object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
 146     }
 147
 148     snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
 149     object_initialize_child(obj, "scu", &s->scu, typename);
 150     qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
 151                          sc->silicon_rev);
 152     object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
 153                               "hw-strap1");
 154     object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
 155                               "hw-strap2");
 156     object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
 157                               "hw-prot-key");
 158
 159     object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
 160
 161     object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
 162
 163     snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
 164     object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
 165
 166     snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
 167     object_initialize_child(obj, "i2c", &s->i2c, typename);
 168
 169     snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
 170     object_initialize_child(obj, "fmc", &s->fmc, typename);
 171     object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs");
 172
 173     for (i = 0; i < sc->spis_num; i++) {
 174         snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
 175         object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
 176     }
 177
 178     for (i = 0; i < sc->ehcis_num; i++) {
 179         object_initialize_child(obj, "ehci[*]", &s->ehci[i],
 180                                 TYPE_PLATFORM_EHCI);
 181     }
 182
 183     snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
 184     object_initialize_child(obj, "sdmc", &s->sdmc, typename);
 185     object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
 186                               "ram-size");
 187     object_property_add_alias(obj, "max-ram-size", OBJECT(&s->sdmc),
 188                               "max-ram-size");
 189
 190     for (i = 0; i < sc->wdts_num; i++) {
 191         snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
 192         object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
 193     }
 194
 195     for (i = 0; i < sc->macs_num; i++) {
 196         object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
 197                                 TYPE_FTGMAC100);
 198     }
 199
 200     object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA);
 201
 202     snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
 203     object_initialize_child(obj, "gpio", &s->gpio, typename);
 204
 205     object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
 206
 207     object_property_set_int(OBJECT(&s->sdhci), 2, "num-slots", &error_abort);
 208
 209     /* Init sd card slot class here so that they're under the correct parent */
 210     for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
 211         object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
 212                                 TYPE_SYSBUS_SDHCI);
 213     }
 214 }
 215
 216 static void aspeed_soc_realize(DeviceState *dev, Error **errp)
 217 {
 218     int i;
 219     AspeedSoCState *s = ASPEED_SOC(dev);
 220     AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
 221     Error *err = NULL, *local_err = NULL;
 222
 223     /* IO space */
 224     create_unimplemented_device("aspeed_soc.io", sc->memmap[ASPEED_IOMEM],
 225                                 ASPEED_SOC_IOMEM_SIZE);
 226
 227     /* Video engine stub */
 228     create_unimplemented_device("aspeed.video", sc->memmap[ASPEED_VIDEO],
 229                                 0x1000);
 230
 231     /* CPU */
 232     for (i = 0; i < sc->num_cpus; i++) {
 233         qdev_realize(DEVICE(&s->cpu[i]), NULL, &err);
 234         if (err) {
 235             error_propagate(errp, err);
 236             return;
 237         }
 238     }
 239
 240     /* SRAM */
 241     memory_region_init_ram(&s->sram, OBJECT(dev), "aspeed.sram",
 242                            sc->sram_size, &err);
 243     if (err) {
 244         error_propagate(errp, err);
 245         return;
 246     }
 247     memory_region_add_subregion(get_system_memory(),
 248                                 sc->memmap[ASPEED_SRAM], &s->sram);
 249
 250     /* SCU */
 251     sysbus_realize(SYS_BUS_DEVICE(&s->scu), &err);
 252     if (err) {
 253         error_propagate(errp, err);
 254         return;
 255     }
 256     sysbus_mmio_map(SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_SCU]);
 257
 258     /* VIC */
 259     sysbus_realize(SYS_BUS_DEVICE(&s->vic), &err);
 260     if (err) {
 261         error_propagate(errp, err);
 262         return;
 263     }
 264     sysbus_mmio_map(SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_VIC]);
 265     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
 266                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
 267     sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
 268                        qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
 269
 270     /* RTC */
 271     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &err);
 272     if (err) {
 273         error_propagate(errp, err);
 274         return;
 275     }
 276     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_RTC]);
 277     sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
 278                        aspeed_soc_get_irq(s, ASPEED_RTC));
 279
 280     /* Timer */
 281     object_property_set_link(OBJECT(&s->timerctrl),
 282                              OBJECT(&s->scu), "scu", &error_abort);
 283     sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), &err);
 284     if (err) {
 285         error_propagate(errp, err);
 286         return;
 287     }
 288     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timerctrl), 0,
 289                     sc->memmap[ASPEED_TIMER1]);
 290     for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
 291         qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_TIMER1 + i);
 292         sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
 293     }
 294
 295     /* UART - attach an 8250 to the IO space as our UART5 */
 296     if (serial_hd(0)) {
 297         qemu_irq uart5 = aspeed_soc_get_irq(s, ASPEED_UART5);
 298         serial_mm_init(get_system_memory(), sc->memmap[ASPEED_UART5], 2,
 299                        uart5, 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN);
 300     }
 301
 302     /* I2C */
 303     object_property_set_link(OBJECT(&s->i2c), OBJECT(s->dram_mr), "dram", &err);
 304     if (err) {
 305         error_propagate(errp, err);
 306         return;
 307     }
 308     sysbus_realize(SYS_BUS_DEVICE(&s->i2c), &err);
 309     if (err) {
 310         error_propagate(errp, err);
 311         return;
 312     }
 313     sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_I2C]);
 314     sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
 315                        aspeed_soc_get_irq(s, ASPEED_I2C));
 316
 317     /* FMC, The number of CS is set at the board level */
 318     object_property_set_link(OBJECT(&s->fmc), OBJECT(s->dram_mr), "dram", &err);
 319     if (err) {
 320         error_propagate(errp, err);
 321         return;
 322     }
 323     object_property_set_int(OBJECT(&s->fmc), sc->memmap[ASPEED_SDRAM],
 324                             "sdram-base", &err);
 325     if (err) {
 326         error_propagate(errp, err);
 327         return;
 328     }
 329     sysbus_realize(SYS_BUS_DEVICE(&s->fmc), &err);
 330     if (err) {
 331         error_propagate(errp, err);
 332         return;
 333     }
 334     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_FMC]);
 335     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fmc), 1,
 336                     s->fmc.ctrl->flash_window_base);
 337     sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
 338                        aspeed_soc_get_irq(s, ASPEED_FMC));
 339
 340     /* SPI */
 341     for (i = 0; i < sc->spis_num; i++) {
 342         object_property_set_int(OBJECT(&s->spi[i]), 1, "num-cs", &err);
 343         sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), &local_err);
 344         error_propagate(&err, local_err);
 345         if (err) {
 346             error_propagate(errp, err);
 347             return;
 348         }
 349         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
 350                         sc->memmap[ASPEED_SPI1 + i]);
 351         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 1,
 352                         s->spi[i].ctrl->flash_window_base);
 353     }
 354
 355     /* EHCI */
 356     for (i = 0; i < sc->ehcis_num; i++) {
 357         sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), &err);
 358         if (err) {
 359             error_propagate(errp, err);
 360             return;
 361         }
 362         sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0,
 363                         sc->memmap[ASPEED_EHCI1 + i]);
 364         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
 365                            aspeed_soc_get_irq(s, ASPEED_EHCI1 + i));
 366     }
 367
 368     /* SDMC - SDRAM Memory Controller */
 369     sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), &err);
 370     if (err) {
 371         error_propagate(errp, err);
 372         return;
 373     }
 374     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, sc->memmap[ASPEED_SDMC]);
 375
 376     /* Watch dog */
 377     for (i = 0; i < sc->wdts_num; i++) {
 378         AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
 379
 380         object_property_set_link(OBJECT(&s->wdt[i]),
 381                                  OBJECT(&s->scu), "scu", &error_abort);
 382         sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), &err);
 383         if (err) {
 384             error_propagate(errp, err);
 385             return;
 386         }
 387         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0,
 388                         sc->memmap[ASPEED_WDT] + i * awc->offset);
 389     }
 390
 391     /* Net */
 392     for (i = 0; i < sc->macs_num; i++) {
 393         object_property_set_bool(OBJECT(&s->ftgmac100[i]), true, "aspeed",
 394                                  &err);
 395         sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), &local_err);
 396         error_propagate(&err, local_err);
 397         if (err) {
 398             error_propagate(errp, err);
 399            return;
 400         }
 401         sysbus_mmio_map(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
 402                         sc->memmap[ASPEED_ETH1 + i]);
 403         sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
 404                            aspeed_soc_get_irq(s, ASPEED_ETH1 + i));
 405     }
 406
 407     /* XDMA */
 408     sysbus_realize(SYS_BUS_DEVICE(&s->xdma), &err);
 409     if (err) {
 410         error_propagate(errp, err);
 411         return;
 412     }
 413     sysbus_mmio_map(SYS_BUS_DEVICE(&s->xdma), 0,
 414                     sc->memmap[ASPEED_XDMA]);
 415     sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
 416                        aspeed_soc_get_irq(s, ASPEED_XDMA));
 417
 418     /* GPIO */
 419     sysbus_realize(SYS_BUS_DEVICE(&s->gpio), &err);
 420     if (err) {
 421         error_propagate(errp, err);
 422         return;
 423     }
 424     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_GPIO]);
 425     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
 426                        aspeed_soc_get_irq(s, ASPEED_GPIO));
 427
 428     /* SDHCI */
 429     sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), &err);
 430     if (err) {
 431         error_propagate(errp, err);
 432         return;
 433     }
 434     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
 435                     sc->memmap[ASPEED_SDHCI]);
 436     sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
 437                        aspeed_soc_get_irq(s, ASPEED_SDHCI));
 438 }
 439 static Property aspeed_soc_properties[] = {
 440     DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
 441                      MemoryRegion *),
 442     DEFINE_PROP_END_OF_LIST(),
 443 };
 444
 445 static void aspeed_soc_class_init(ObjectClass *oc, void *data)
 446 {
 447     DeviceClass *dc = DEVICE_CLASS(oc);
 448
 449     dc->realize = aspeed_soc_realize;
 450     /* Reason: Uses serial_hds and nd_table in realize() directly */
 451     dc->user_creatable = false;
 452     device_class_set_props(dc, aspeed_soc_properties);
 453 }
 454
 455 static const TypeInfo aspeed_soc_type_info = {
 456     .name           = TYPE_ASPEED_SOC,
 457     .parent         = TYPE_DEVICE,
 458     .instance_size  = sizeof(AspeedSoCState),
 459     .class_size     = sizeof(AspeedSoCClass),
 460     .class_init     = aspeed_soc_class_init,
 461     .abstract       = true,
 462 };
 463
 464 static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
 465 {
 466     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 467
 468     sc->name         = "ast2400-a1";
 469     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm926");
 470     sc->silicon_rev  = AST2400_A1_SILICON_REV;
 471     sc->sram_size    = 0x8000;
 472     sc->spis_num     = 1;
 473     sc->ehcis_num    = 1;
 474     sc->wdts_num     = 2;
 475     sc->macs_num     = 2;
 476     sc->irqmap       = aspeed_soc_ast2400_irqmap;
 477     sc->memmap       = aspeed_soc_ast2400_memmap;
 478     sc->num_cpus     = 1;
 479 }
 480
 481 static const TypeInfo aspeed_soc_ast2400_type_info = {
 482     .name           = "ast2400-a1",
 483     .parent         = TYPE_ASPEED_SOC,
 484     .instance_init  = aspeed_soc_init,
 485     .instance_size  = sizeof(AspeedSoCState),
 486     .class_init     = aspeed_soc_ast2400_class_init,
 487 };
 488
 489 static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
 490 {
 491     AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
 492
 493     sc->name         = "ast2500-a1";
 494     sc->cpu_type     = ARM_CPU_TYPE_NAME("arm1176");
 495     sc->silicon_rev  = AST2500_A1_SILICON_REV;
 496     sc->sram_size    = 0x9000;
 497     sc->spis_num     = 2;
 498     sc->ehcis_num    = 2;
 499     sc->wdts_num     = 3;
 500     sc->macs_num     = 2;
 501     sc->irqmap       = aspeed_soc_ast2500_irqmap;
 502     sc->memmap       = aspeed_soc_ast2500_memmap;
 503     sc->num_cpus     = 1;
 504 }
 505
 506 static const TypeInfo aspeed_soc_ast2500_type_info = {
 507     .name           = "ast2500-a1",
 508     .parent         = TYPE_ASPEED_SOC,
 509     .instance_init  = aspeed_soc_init,
 510     .instance_size  = sizeof(AspeedSoCState),
 511     .class_init     = aspeed_soc_ast2500_class_init,
 512 };
 513 static void aspeed_soc_register_types(void)
 514 {
 515     type_register_static(&aspeed_soc_type_info);
 516     type_register_static(&aspeed_soc_ast2400_type_info);
 517     type_register_static(&aspeed_soc_ast2500_type_info);
 518 };
 519
 520 type_init(aspeed_soc_register_types)