target/ppc/fpu_helper.c

   1 /*
   2  *  PowerPC floating point and SPE emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "exec/exec-all.h"
  23 #include "internal.h"
  24
  25 static inline float128 float128_snan_to_qnan(float128 x)
  26 {
  27     float128 r;
  28
  29     r.high = x.high | 0x0000800000000000;
  30     r.low = x.low;
  31     return r;
  32 }
  33
  34 #define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
  35 #define float32_snan_to_qnan(x) ((x) | 0x00400000)
  36 #define float16_snan_to_qnan(x) ((x) | 0x0200)
  37
  38 /*****************************************************************************/
  39 /* Floating point operations helpers */
  40 uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg)
  41 {
  42     CPU_FloatU f;
  43     CPU_DoubleU d;
  44
  45     f.l = arg;
  46     d.d = float32_to_float64(f.f, &env->fp_status);
  47     return d.ll;
  48 }
  49
  50 uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
  51 {
  52     CPU_FloatU f;
  53     CPU_DoubleU d;
  54
  55     d.ll = arg;
  56     f.f = float64_to_float32(d.d, &env->fp_status);
  57     return f.l;
  58 }
  59
  60 static inline int ppc_float32_get_unbiased_exp(float32 f)
  61 {
  62     return ((f >> 23) & 0xFF) - 127;
  63 }
  64
  65 static inline int ppc_float64_get_unbiased_exp(float64 f)
  66 {
  67     return ((f >> 52) & 0x7FF) - 1023;
  68 }
  69
  70 #define COMPUTE_FPRF(tp)                                       \
  71 void helper_compute_fprf_##tp(CPUPPCState *env, tp arg)        \
  72 {                                                              \
  73     int isneg;                                                 \
  74     int fprf;                                                  \
  75                                                                \
  76     isneg = tp##_is_neg(arg);                                  \
  77     if (unlikely(tp##_is_any_nan(arg))) {                      \
  78         if (tp##_is_signaling_nan(arg, &env->fp_status)) {     \
  79             /* Signaling NaN: flags are undefined */           \
  80             fprf = 0x00;                                       \
  81         } else {                                               \
  82             /* Quiet NaN */                                    \
  83             fprf = 0x11;                                       \
  84         }                                                      \
  85     } else if (unlikely(tp##_is_infinity(arg))) {              \
  86         /* +/- infinity */                                     \
  87         if (isneg) {                                           \
  88             fprf = 0x09;                                       \
  89         } else {                                               \
  90             fprf = 0x05;                                       \
  91         }                                                      \
  92     } else {                                                   \
  93         if (tp##_is_zero(arg)) {                               \
  94             /* +/- zero */                                     \
  95             if (isneg) {                                       \
  96                 fprf = 0x12;                                   \
  97             } else {                                           \
  98                 fprf = 0x02;                                   \
  99             }                                                  \
 100         } else {                                               \
 101             if (tp##_is_zero_or_denormal(arg)) {               \
 102                 /* Denormalized numbers */                     \
 103                 fprf = 0x10;                                   \
 104             } else {                                           \
 105                 /* Normalized numbers */                       \
 106                 fprf = 0x00;                                   \
 107             }                                                  \
 108             if (isneg) {                                       \
 109                 fprf |= 0x08;                                  \
 110             } else {                                           \
 111                 fprf |= 0x04;                                  \
 112             }                                                  \
 113         }                                                      \
 114     }                                                          \
 115     /* We update FPSCR_FPRF */                                 \
 116     env->fpscr &= ~(0x1F << FPSCR_FPRF);                       \
 117     env->fpscr |= fprf << FPSCR_FPRF;                          \
 118 }
 119
 120 COMPUTE_FPRF(float16)
 121 COMPUTE_FPRF(float32)
 122 COMPUTE_FPRF(float64)
 123 COMPUTE_FPRF(float128)
 124
 125 /* Floating-point invalid operations exception */
 126 static inline __attribute__((__always_inline__))
 127 uint64_t float_invalid_op_excp(CPUPPCState *env, int op, int set_fpcc)
 128 {
 129     CPUState *cs = CPU(ppc_env_get_cpu(env));
 130     uint64_t ret = 0;
 131     int ve;
 132
 133     ve = fpscr_ve;
 134     switch (op) {
 135     case POWERPC_EXCP_FP_VXSNAN:
 136         env->fpscr |= 1 << FPSCR_VXSNAN;
 137         break;
 138     case POWERPC_EXCP_FP_VXSOFT:
 139         env->fpscr |= 1 << FPSCR_VXSOFT;
 140         break;
 141     case POWERPC_EXCP_FP_VXISI:
 142         /* Magnitude subtraction of infinities */
 143         env->fpscr |= 1 << FPSCR_VXISI;
 144         goto update_arith;
 145     case POWERPC_EXCP_FP_VXIDI:
 146         /* Division of infinity by infinity */
 147         env->fpscr |= 1 << FPSCR_VXIDI;
 148         goto update_arith;
 149     case POWERPC_EXCP_FP_VXZDZ:
 150         /* Division of zero by zero */
 151         env->fpscr |= 1 << FPSCR_VXZDZ;
 152         goto update_arith;
 153     case POWERPC_EXCP_FP_VXIMZ:
 154         /* Multiplication of zero by infinity */
 155         env->fpscr |= 1 << FPSCR_VXIMZ;
 156         goto update_arith;
 157     case POWERPC_EXCP_FP_VXVC:
 158         /* Ordered comparison of NaN */
 159         env->fpscr |= 1 << FPSCR_VXVC;
 160         if (set_fpcc) {
 161             env->fpscr &= ~(0xF << FPSCR_FPCC);
 162             env->fpscr |= 0x11 << FPSCR_FPCC;
 163         }
 164         /* We must update the target FPR before raising the exception */
 165         if (ve != 0) {
 166             cs->exception_index = POWERPC_EXCP_PROGRAM;
 167             env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
 168             /* Update the floating-point enabled exception summary */
 169             env->fpscr |= 1 << FPSCR_FEX;
 170             /* Exception is differed */
 171             ve = 0;
 172         }
 173         break;
 174     case POWERPC_EXCP_FP_VXSQRT:
 175         /* Square root of a negative number */
 176         env->fpscr |= 1 << FPSCR_VXSQRT;
 177     update_arith:
 178         env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 179         if (ve == 0) {
 180             /* Set the result to quiet NaN */
 181             ret = 0x7FF8000000000000ULL;
 182             if (set_fpcc) {
 183                 env->fpscr &= ~(0xF << FPSCR_FPCC);
 184                 env->fpscr |= 0x11 << FPSCR_FPCC;
 185             }
 186         }
 187         break;
 188     case POWERPC_EXCP_FP_VXCVI:
 189         /* Invalid conversion */
 190         env->fpscr |= 1 << FPSCR_VXCVI;
 191         env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 192         if (ve == 0) {
 193             /* Set the result to quiet NaN */
 194             ret = 0x7FF8000000000000ULL;
 195             if (set_fpcc) {
 196                 env->fpscr &= ~(0xF << FPSCR_FPCC);
 197                 env->fpscr |= 0x11 << FPSCR_FPCC;
 198             }
 199         }
 200         break;
 201     }
 202     /* Update the floating-point invalid operation summary */
 203     env->fpscr |= 1 << FPSCR_VX;
 204     /* Update the floating-point exception summary */
 205     env->fpscr |= FP_FX;
 206     if (ve != 0) {
 207         /* Update the floating-point enabled exception summary */
 208         env->fpscr |= 1 << FPSCR_FEX;
 209         if (msr_fe0 != 0 || msr_fe1 != 0) {
 210             /* GETPC() works here because this is inline */
 211             raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
 212                                    POWERPC_EXCP_FP | op, GETPC());
 213         }
 214     }
 215     return ret;
 216 }
 217
 218 static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
 219 {
 220     env->fpscr |= 1 << FPSCR_ZX;
 221     env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
 222     /* Update the floating-point exception summary */
 223     env->fpscr |= FP_FX;
 224     if (fpscr_ze != 0) {
 225         /* Update the floating-point enabled exception summary */
 226         env->fpscr |= 1 << FPSCR_FEX;
 227         if (msr_fe0 != 0 || msr_fe1 != 0) {
 228             raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
 229                                    POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX,
 230                                    raddr);
 231         }
 232     }
 233 }
 234
 235 static inline void float_overflow_excp(CPUPPCState *env)
 236 {
 237     CPUState *cs = CPU(ppc_env_get_cpu(env));
 238
 239     env->fpscr |= 1 << FPSCR_OX;
 240     /* Update the floating-point exception summary */
 241     env->fpscr |= FP_FX;
 242     if (fpscr_oe != 0) {
 243         /* XXX: should adjust the result */
 244         /* Update the floating-point enabled exception summary */
 245         env->fpscr |= 1 << FPSCR_FEX;
 246         /* We must update the target FPR before raising the exception */
 247         cs->exception_index = POWERPC_EXCP_PROGRAM;
 248         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
 249     } else {
 250         env->fpscr |= 1 << FPSCR_XX;
 251         env->fpscr |= 1 << FPSCR_FI;
 252     }
 253 }
 254
 255 static inline void float_underflow_excp(CPUPPCState *env)
 256 {
 257     CPUState *cs = CPU(ppc_env_get_cpu(env));
 258
 259     env->fpscr |= 1 << FPSCR_UX;
 260     /* Update the floating-point exception summary */
 261     env->fpscr |= FP_FX;
 262     if (fpscr_ue != 0) {
 263         /* XXX: should adjust the result */
 264         /* Update the floating-point enabled exception summary */
 265         env->fpscr |= 1 << FPSCR_FEX;
 266         /* We must update the target FPR before raising the exception */
 267         cs->exception_index = POWERPC_EXCP_PROGRAM;
 268         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
 269     }
 270 }
 271
 272 static inline void float_inexact_excp(CPUPPCState *env)
 273 {
 274     CPUState *cs = CPU(ppc_env_get_cpu(env));
 275
 276     env->fpscr |= 1 << FPSCR_XX;
 277     /* Update the floating-point exception summary */
 278     env->fpscr |= FP_FX;
 279     if (fpscr_xe != 0) {
 280         /* Update the floating-point enabled exception summary */
 281         env->fpscr |= 1 << FPSCR_FEX;
 282         /* We must update the target FPR before raising the exception */
 283         cs->exception_index = POWERPC_EXCP_PROGRAM;
 284         env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
 285     }
 286 }
 287
 288 static inline void fpscr_set_rounding_mode(CPUPPCState *env)
 289 {
 290     int rnd_type;
 291
 292     /* Set rounding mode */
 293     switch (fpscr_rn) {
 294     case 0:
 295         /* Best approximation (round to nearest) */
 296         rnd_type = float_round_nearest_even;
 297         break;
 298     case 1:
 299         /* Smaller magnitude (round toward zero) */
 300         rnd_type = float_round_to_zero;
 301         break;
 302     case 2:
 303         /* Round toward +infinite */
 304         rnd_type = float_round_up;
 305         break;
 306     default:
 307     case 3:
 308         /* Round toward -infinite */
 309         rnd_type = float_round_down;
 310         break;
 311     }
 312     set_float_rounding_mode(rnd_type, &env->fp_status);
 313 }
 314
 315 void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
 316 {
 317     int prev;
 318
 319     prev = (env->fpscr >> bit) & 1;
 320     env->fpscr &= ~(1 << bit);
 321     if (prev == 1) {
 322         switch (bit) {
 323         case FPSCR_RN1:
 324         case FPSCR_RN:
 325             fpscr_set_rounding_mode(env);
 326             break;
 327         default:
 328             break;
 329         }
 330     }
 331 }
 332
 333 void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
 334 {
 335     CPUState *cs = CPU(ppc_env_get_cpu(env));
 336     int prev;
 337
 338     prev = (env->fpscr >> bit) & 1;
 339     env->fpscr |= 1 << bit;
 340     if (prev == 0) {
 341         switch (bit) {
 342         case FPSCR_VX:
 343             env->fpscr |= FP_FX;
 344             if (fpscr_ve) {
 345                 goto raise_ve;
 346             }
 347             break;
 348         case FPSCR_OX:
 349             env->fpscr |= FP_FX;
 350             if (fpscr_oe) {
 351                 goto raise_oe;
 352             }
 353             break;
 354         case FPSCR_UX:
 355             env->fpscr |= FP_FX;
 356             if (fpscr_ue) {
 357                 goto raise_ue;
 358             }
 359             break;
 360         case FPSCR_ZX:
 361             env->fpscr |= FP_FX;
 362             if (fpscr_ze) {
 363                 goto raise_ze;
 364             }
 365             break;
 366         case FPSCR_XX:
 367             env->fpscr |= FP_FX;
 368             if (fpscr_xe) {
 369                 goto raise_xe;
 370             }
 371             break;
 372         case FPSCR_VXSNAN:
 373         case FPSCR_VXISI:
 374         case FPSCR_VXIDI:
 375         case FPSCR_VXZDZ:
 376         case FPSCR_VXIMZ:
 377         case FPSCR_VXVC:
 378         case FPSCR_VXSOFT:
 379         case FPSCR_VXSQRT:
 380         case FPSCR_VXCVI:
 381             env->fpscr |= 1 << FPSCR_VX;
 382             env->fpscr |= FP_FX;
 383             if (fpscr_ve != 0) {
 384                 goto raise_ve;
 385             }
 386             break;
 387         case FPSCR_VE:
 388             if (fpscr_vx != 0) {
 389             raise_ve:
 390                 env->error_code = POWERPC_EXCP_FP;
 391                 if (fpscr_vxsnan) {
 392                     env->error_code |= POWERPC_EXCP_FP_VXSNAN;
 393                 }
 394                 if (fpscr_vxisi) {
 395                     env->error_code |= POWERPC_EXCP_FP_VXISI;
 396                 }
 397                 if (fpscr_vxidi) {
 398                     env->error_code |= POWERPC_EXCP_FP_VXIDI;
 399                 }
 400                 if (fpscr_vxzdz) {
 401                     env->error_code |= POWERPC_EXCP_FP_VXZDZ;
 402                 }
 403                 if (fpscr_vximz) {
 404                     env->error_code |= POWERPC_EXCP_FP_VXIMZ;
 405                 }
 406                 if (fpscr_vxvc) {
 407                     env->error_code |= POWERPC_EXCP_FP_VXVC;
 408                 }
 409                 if (fpscr_vxsoft) {
 410                     env->error_code |= POWERPC_EXCP_FP_VXSOFT;
 411                 }
 412                 if (fpscr_vxsqrt) {
 413                     env->error_code |= POWERPC_EXCP_FP_VXSQRT;
 414                 }
 415                 if (fpscr_vxcvi) {
 416                     env->error_code |= POWERPC_EXCP_FP_VXCVI;
 417                 }
 418                 goto raise_excp;
 419             }
 420             break;
 421         case FPSCR_OE:
 422             if (fpscr_ox != 0) {
 423             raise_oe:
 424                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
 425                 goto raise_excp;
 426             }
 427             break;
 428         case FPSCR_UE:
 429             if (fpscr_ux != 0) {
 430             raise_ue:
 431                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
 432                 goto raise_excp;
 433             }
 434             break;
 435         case FPSCR_ZE:
 436             if (fpscr_zx != 0) {
 437             raise_ze:
 438                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
 439                 goto raise_excp;
 440             }
 441             break;
 442         case FPSCR_XE:
 443             if (fpscr_xx != 0) {
 444             raise_xe:
 445                 env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
 446                 goto raise_excp;
 447             }
 448             break;
 449         case FPSCR_RN1:
 450         case FPSCR_RN:
 451             fpscr_set_rounding_mode(env);
 452             break;
 453         default:
 454             break;
 455         raise_excp:
 456             /* Update the floating-point enabled exception summary */
 457             env->fpscr |= 1 << FPSCR_FEX;
 458             /* We have to update Rc1 before raising the exception */
 459             cs->exception_index = POWERPC_EXCP_PROGRAM;
 460             break;
 461         }
 462     }
 463 }
 464
 465 void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 466 {
 467     CPUState *cs = CPU(ppc_env_get_cpu(env));
 468     target_ulong prev, new;
 469     int i;
 470
 471     prev = env->fpscr;
 472     new = (target_ulong)arg;
 473     new &= ~0x60000000LL;
 474     new |= prev & 0x60000000LL;
 475     for (i = 0; i < sizeof(target_ulong) * 2; i++) {
 476         if (mask & (1 << i)) {
 477             env->fpscr &= ~(0xFLL << (4 * i));
 478             env->fpscr |= new & (0xFLL << (4 * i));
 479         }
 480     }
 481     /* Update VX and FEX */
 482     if (fpscr_ix != 0) {
 483         env->fpscr |= 1 << FPSCR_VX;
 484     } else {
 485         env->fpscr &= ~(1 << FPSCR_VX);
 486     }
 487     if ((fpscr_ex & fpscr_eex) != 0) {
 488         env->fpscr |= 1 << FPSCR_FEX;
 489         cs->exception_index = POWERPC_EXCP_PROGRAM;
 490         /* XXX: we should compute it properly */
 491         env->error_code = POWERPC_EXCP_FP;
 492     } else {
 493         env->fpscr &= ~(1 << FPSCR_FEX);
 494     }
 495     fpscr_set_rounding_mode(env);
 496 }
 497
 498 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
 499 {
 500     helper_store_fpscr(env, arg, mask);
 501 }
 502
 503 static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
 504 {
 505     CPUState *cs = CPU(ppc_env_get_cpu(env));
 506     int status = get_float_exception_flags(&env->fp_status);
 507
 508     if (status & float_flag_divbyzero) {
 509         float_zero_divide_excp(env, raddr);
 510     } else if (status & float_flag_overflow) {
 511         float_overflow_excp(env);
 512     } else if (status & float_flag_underflow) {
 513         float_underflow_excp(env);
 514     } else if (status & float_flag_inexact) {
 515         float_inexact_excp(env);
 516     }
 517
 518     if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
 519         (env->error_code & POWERPC_EXCP_FP)) {
 520         /* Differred floating-point exception after target FPR update */
 521         if (msr_fe0 != 0 || msr_fe1 != 0) {
 522             raise_exception_err_ra(env, cs->exception_index,
 523                                    env->error_code, raddr);
 524         }
 525     }
 526 }
 527
 528 static inline  __attribute__((__always_inline__))
 529 void float_check_status(CPUPPCState *env)
 530 {
 531     /* GETPC() works here because this is inline */
 532     do_float_check_status(env, GETPC());
 533 }
 534
 535 void helper_float_check_status(CPUPPCState *env)
 536 {
 537     do_float_check_status(env, GETPC());
 538 }
 539
 540 void helper_reset_fpstatus(CPUPPCState *env)
 541 {
 542     set_float_exception_flags(0, &env->fp_status);
 543 }
 544
 545 /* fadd - fadd. */
 546 uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 547 {
 548     CPU_DoubleU farg1, farg2;
 549
 550     farg1.ll = arg1;
 551     farg2.ll = arg2;
 552
 553     if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
 554                  float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
 555         /* Magnitude subtraction of infinities */
 556         farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 557     } else {
 558         if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
 559                      float64_is_signaling_nan(farg2.d, &env->fp_status))) {
 560             /* sNaN addition */
 561             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 562         }
 563         farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
 564     }
 565
 566     return farg1.ll;
 567 }
 568
 569 /* fsub - fsub. */
 570 uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 571 {
 572     CPU_DoubleU farg1, farg2;
 573
 574     farg1.ll = arg1;
 575     farg2.ll = arg2;
 576
 577     if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
 578                  float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
 579         /* Magnitude subtraction of infinities */
 580         farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
 581     } else {
 582         if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
 583                      float64_is_signaling_nan(farg2.d, &env->fp_status))) {
 584             /* sNaN subtraction */
 585             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 586         }
 587         farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
 588     }
 589
 590     return farg1.ll;
 591 }
 592
 593 /* fmul - fmul. */
 594 uint64_t helper_fmul(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 595 {
 596     CPU_DoubleU farg1, farg2;
 597
 598     farg1.ll = arg1;
 599     farg2.ll = arg2;
 600
 601     if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
 602                  (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
 603         /* Multiplication of zero by infinity */
 604         farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
 605     } else {
 606         if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
 607                      float64_is_signaling_nan(farg2.d, &env->fp_status))) {
 608             /* sNaN multiplication */
 609             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 610         }
 611         farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
 612     }
 613
 614     return farg1.ll;
 615 }
 616
 617 /* fdiv - fdiv. */
 618 uint64_t helper_fdiv(CPUPPCState *env, uint64_t arg1, uint64_t arg2)
 619 {
 620     CPU_DoubleU farg1, farg2;
 621
 622     farg1.ll = arg1;
 623     farg2.ll = arg2;
 624
 625     if (unlikely(float64_is_infinity(farg1.d) &&
 626                  float64_is_infinity(farg2.d))) {
 627         /* Division of infinity by infinity */
 628         farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1);
 629     } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
 630         /* Division of zero by zero */
 631         farg1.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
 632     } else {
 633         if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) ||
 634                      float64_is_signaling_nan(farg2.d, &env->fp_status))) {
 635             /* sNaN division */
 636             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 637         }
 638         farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
 639     }
 640
 641     return farg1.ll;
 642 }
 643
 644
 645 #define FPU_FCTI(op, cvt, nanval)                                      \
 646 uint64_t helper_##op(CPUPPCState *env, uint64_t arg)                   \
 647 {                                                                      \
 648     CPU_DoubleU farg;                                                  \
 649                                                                        \
 650     farg.ll = arg;                                                     \
 651     farg.ll = float64_to_##cvt(farg.d, &env->fp_status);               \
 652                                                                        \
 653     if (unlikely(env->fp_status.float_exception_flags)) {              \
 654         if (float64_is_any_nan(arg)) {                                 \
 655             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);      \
 656             if (float64_is_signaling_nan(arg, &env->fp_status)) {      \
 657                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); \
 658             }                                                          \
 659             farg.ll = nanval;                                          \
 660         } else if (env->fp_status.float_exception_flags &              \
 661                    float_flag_invalid) {                               \
 662             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 1);      \
 663         }                                                              \
 664         float_check_status(env);                                       \
 665     }                                                                  \
 666     return farg.ll;                                                    \
 667  }
 668
 669 FPU_FCTI(fctiw, int32, 0x80000000U)
 670 FPU_FCTI(fctiwz, int32_round_to_zero, 0x80000000U)
 671 FPU_FCTI(fctiwu, uint32, 0x00000000U)
 672 FPU_FCTI(fctiwuz, uint32_round_to_zero, 0x00000000U)
 673 FPU_FCTI(fctid, int64, 0x8000000000000000ULL)
 674 FPU_FCTI(fctidz, int64_round_to_zero, 0x8000000000000000ULL)
 675 FPU_FCTI(fctidu, uint64, 0x0000000000000000ULL)
 676 FPU_FCTI(fctiduz, uint64_round_to_zero, 0x0000000000000000ULL)
 677
 678 #define FPU_FCFI(op, cvtr, is_single)                      \
 679 uint64_t helper_##op(CPUPPCState *env, uint64_t arg)       \
 680 {                                                          \
 681     CPU_DoubleU farg;                                      \
 682                                                            \
 683     if (is_single) {                                       \
 684         float32 tmp = cvtr(arg, &env->fp_status);          \
 685         farg.d = float32_to_float64(tmp, &env->fp_status); \
 686     } else {                                               \
 687         farg.d = cvtr(arg, &env->fp_status);               \
 688     }                                                      \
 689     float_check_status(env);                               \
 690     return farg.ll;                                        \
 691 }
 692
 693 FPU_FCFI(fcfid, int64_to_float64, 0)
 694 FPU_FCFI(fcfids, int64_to_float32, 1)
 695 FPU_FCFI(fcfidu, uint64_to_float64, 0)
 696 FPU_FCFI(fcfidus, uint64_to_float32, 1)
 697
 698 static inline uint64_t do_fri(CPUPPCState *env, uint64_t arg,
 699                               int rounding_mode)
 700 {
 701     CPU_DoubleU farg;
 702
 703     farg.ll = arg;
 704
 705     if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
 706         /* sNaN round */
 707         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 708         farg.ll = arg | 0x0008000000000000ULL;
 709     } else {
 710         int inexact = get_float_exception_flags(&env->fp_status) &
 711                       float_flag_inexact;
 712         set_float_rounding_mode(rounding_mode, &env->fp_status);
 713         farg.ll = float64_round_to_int(farg.d, &env->fp_status);
 714         /* Restore rounding mode from FPSCR */
 715         fpscr_set_rounding_mode(env);
 716
 717         /* fri* does not set FPSCR[XX] */
 718         if (!inexact) {
 719             env->fp_status.float_exception_flags &= ~float_flag_inexact;
 720         }
 721     }
 722     float_check_status(env);
 723     return farg.ll;
 724 }
 725
 726 uint64_t helper_frin(CPUPPCState *env, uint64_t arg)
 727 {
 728     return do_fri(env, arg, float_round_ties_away);
 729 }
 730
 731 uint64_t helper_friz(CPUPPCState *env, uint64_t arg)
 732 {
 733     return do_fri(env, arg, float_round_to_zero);
 734 }
 735
 736 uint64_t helper_frip(CPUPPCState *env, uint64_t arg)
 737 {
 738     return do_fri(env, arg, float_round_up);
 739 }
 740
 741 uint64_t helper_frim(CPUPPCState *env, uint64_t arg)
 742 {
 743     return do_fri(env, arg, float_round_down);
 744 }
 745
 746 #define FPU_MADDSUB_UPDATE(NAME, TP)                                    \
 747 static void NAME(CPUPPCState *env, TP arg1, TP arg2, TP arg3,           \
 748                  unsigned int madd_flags)                               \
 749 {                                                                       \
 750     if (TP##_is_signaling_nan(arg1, &env->fp_status) ||                 \
 751         TP##_is_signaling_nan(arg2, &env->fp_status) ||                 \
 752         TP##_is_signaling_nan(arg3, &env->fp_status)) {                 \
 753         /* sNaN operation */                                            \
 754         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);          \
 755     }                                                                   \
 756     if ((TP##_is_infinity(arg1) && TP##_is_zero(arg2)) ||               \
 757         (TP##_is_zero(arg1) && TP##_is_infinity(arg2))) {               \
 758         /* Multiplication of zero by infinity */                        \
 759         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);           \
 760     }                                                                   \
 761     if ((TP##_is_infinity(arg1) || TP##_is_infinity(arg2)) &&           \
 762         TP##_is_infinity(arg3)) {                                       \
 763         uint8_t aSign, bSign, cSign;                                    \
 764                                                                         \
 765         aSign = TP##_is_neg(arg1);                                      \
 766         bSign = TP##_is_neg(arg2);                                      \
 767         cSign = TP##_is_neg(arg3);                                      \
 768         if (madd_flags & float_muladd_negate_c) {                       \
 769             cSign ^= 1;                                                 \
 770         }                                                               \
 771         if (aSign ^ bSign ^ cSign) {                                    \
 772             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);       \
 773         }                                                               \
 774     }                                                                   \
 775 }
 776 FPU_MADDSUB_UPDATE(float64_maddsub_update_excp, float64)
 777
 778 #define FPU_FMADD(op, madd_flags)                                       \
 779 uint64_t helper_##op(CPUPPCState *env, uint64_t arg1,                   \
 780                      uint64_t arg2, uint64_t arg3)                      \
 781 {                                                                       \
 782     uint32_t flags;                                                     \
 783     float64 ret = float64_muladd(arg1, arg2, arg3, madd_flags,          \
 784                                  &env->fp_status);                      \
 785     flags = get_float_exception_flags(&env->fp_status);                 \
 786     if (flags) {                                                        \
 787         if (flags & float_flag_invalid) {                               \
 788             float64_maddsub_update_excp(env, arg1, arg2, arg3,          \
 789                                         madd_flags);                    \
 790         }                                                               \
 791         float_check_status(env);                                        \
 792     }                                                                   \
 793     return ret;                                                         \
 794 }
 795
 796 #define MADD_FLGS 0
 797 #define MSUB_FLGS float_muladd_negate_c
 798 #define NMADD_FLGS float_muladd_negate_result
 799 #define NMSUB_FLGS (float_muladd_negate_c | float_muladd_negate_result)
 800
 801 FPU_FMADD(fmadd, MADD_FLGS)
 802 FPU_FMADD(fnmadd, NMADD_FLGS)
 803 FPU_FMADD(fmsub, MSUB_FLGS)
 804 FPU_FMADD(fnmsub, NMSUB_FLGS)
 805
 806 /* frsp - frsp. */
 807 uint64_t helper_frsp(CPUPPCState *env, uint64_t arg)
 808 {
 809     CPU_DoubleU farg;
 810     float32 f32;
 811
 812     farg.ll = arg;
 813
 814     if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
 815         /* sNaN square root */
 816         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 817     }
 818     f32 = float64_to_float32(farg.d, &env->fp_status);
 819     farg.d = float32_to_float64(f32, &env->fp_status);
 820
 821     return farg.ll;
 822 }
 823
 824 /* fsqrt - fsqrt. */
 825 uint64_t helper_fsqrt(CPUPPCState *env, uint64_t arg)
 826 {
 827     CPU_DoubleU farg;
 828
 829     farg.ll = arg;
 830
 831     if (unlikely(float64_is_any_nan(farg.d))) {
 832         if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
 833             /* sNaN reciprocal square root */
 834             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 835             farg.ll = float64_snan_to_qnan(farg.ll);
 836         }
 837     } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
 838         /* Square root of a negative nonzero number */
 839         farg.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
 840     } else {
 841         farg.d = float64_sqrt(farg.d, &env->fp_status);
 842     }
 843     return farg.ll;
 844 }
 845
 846 /* fre - fre. */
 847 uint64_t helper_fre(CPUPPCState *env, uint64_t arg)
 848 {
 849     CPU_DoubleU farg;
 850
 851     farg.ll = arg;
 852
 853     if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
 854         /* sNaN reciprocal */
 855         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 856     }
 857     farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 858     return farg.d;
 859 }
 860
 861 /* fres - fres. */
 862 uint64_t helper_fres(CPUPPCState *env, uint64_t arg)
 863 {
 864     CPU_DoubleU farg;
 865     float32 f32;
 866
 867     farg.ll = arg;
 868
 869     if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
 870         /* sNaN reciprocal */
 871         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 872     }
 873     farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 874     f32 = float64_to_float32(farg.d, &env->fp_status);
 875     farg.d = float32_to_float64(f32, &env->fp_status);
 876
 877     return farg.ll;
 878 }
 879
 880 /* frsqrte  - frsqrte. */
 881 uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg)
 882 {
 883     CPU_DoubleU farg;
 884
 885     farg.ll = arg;
 886
 887     if (unlikely(float64_is_any_nan(farg.d))) {
 888         if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) {
 889             /* sNaN reciprocal square root */
 890             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
 891             farg.ll = float64_snan_to_qnan(farg.ll);
 892         }
 893     } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
 894         /* Reciprocal square root of a negative nonzero number */
 895         farg.ll = float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
 896     } else {
 897         farg.d = float64_sqrt(farg.d, &env->fp_status);
 898         farg.d = float64_div(float64_one, farg.d, &env->fp_status);
 899     }
 900
 901     return farg.ll;
 902 }
 903
 904 /* fsel - fsel. */
 905 uint64_t helper_fsel(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 906                      uint64_t arg3)
 907 {
 908     CPU_DoubleU farg1;
 909
 910     farg1.ll = arg1;
 911
 912     if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) &&
 913         !float64_is_any_nan(farg1.d)) {
 914         return arg2;
 915     } else {
 916         return arg3;
 917     }
 918 }
 919
 920 uint32_t helper_ftdiv(uint64_t fra, uint64_t frb)
 921 {
 922     int fe_flag = 0;
 923     int fg_flag = 0;
 924
 925     if (unlikely(float64_is_infinity(fra) ||
 926                  float64_is_infinity(frb) ||
 927                  float64_is_zero(frb))) {
 928         fe_flag = 1;
 929         fg_flag = 1;
 930     } else {
 931         int e_a = ppc_float64_get_unbiased_exp(fra);
 932         int e_b = ppc_float64_get_unbiased_exp(frb);
 933
 934         if (unlikely(float64_is_any_nan(fra) ||
 935                      float64_is_any_nan(frb))) {
 936             fe_flag = 1;
 937         } else if ((e_b <= -1022) || (e_b >= 1021)) {
 938             fe_flag = 1;
 939         } else if (!float64_is_zero(fra) &&
 940                    (((e_a - e_b) >= 1023) ||
 941                     ((e_a - e_b) <= -1021) ||
 942                     (e_a <= -970))) {
 943             fe_flag = 1;
 944         }
 945
 946         if (unlikely(float64_is_zero_or_denormal(frb))) {
 947             /* XB is not zero because of the above check and */
 948             /* so must be denormalized.                      */
 949             fg_flag = 1;
 950         }
 951     }
 952
 953     return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
 954 }
 955
 956 uint32_t helper_ftsqrt(uint64_t frb)
 957 {
 958     int fe_flag = 0;
 959     int fg_flag = 0;
 960
 961     if (unlikely(float64_is_infinity(frb) || float64_is_zero(frb))) {
 962         fe_flag = 1;
 963         fg_flag = 1;
 964     } else {
 965         int e_b = ppc_float64_get_unbiased_exp(frb);
 966
 967         if (unlikely(float64_is_any_nan(frb))) {
 968             fe_flag = 1;
 969         } else if (unlikely(float64_is_zero(frb))) {
 970             fe_flag = 1;
 971         } else if (unlikely(float64_is_neg(frb))) {
 972             fe_flag = 1;
 973         } else if (!float64_is_zero(frb) && (e_b <= (-1022+52))) {
 974             fe_flag = 1;
 975         }
 976
 977         if (unlikely(float64_is_zero_or_denormal(frb))) {
 978             /* XB is not zero because of the above check and */
 979             /* therefore must be denormalized.               */
 980             fg_flag = 1;
 981         }
 982     }
 983
 984     return 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0);
 985 }
 986
 987 void helper_fcmpu(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
 988                   uint32_t crfD)
 989 {
 990     CPU_DoubleU farg1, farg2;
 991     uint32_t ret = 0;
 992
 993     farg1.ll = arg1;
 994     farg2.ll = arg2;
 995
 996     if (unlikely(float64_is_any_nan(farg1.d) ||
 997                  float64_is_any_nan(farg2.d))) {
 998         ret = 0x01UL;
 999     } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1000         ret = 0x08UL;
1001     } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1002         ret = 0x04UL;
1003     } else {
1004         ret = 0x02UL;
1005     }
1006
1007     env->fpscr &= ~(0x0F << FPSCR_FPRF);
1008     env->fpscr |= ret << FPSCR_FPRF;
1009     env->crf[crfD] = ret;
1010     if (unlikely(ret == 0x01UL
1011                  && (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
1012                      float64_is_signaling_nan(farg2.d, &env->fp_status)))) {
1013         /* sNaN comparison */
1014         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
1015     }
1016 }
1017
1018 void helper_fcmpo(CPUPPCState *env, uint64_t arg1, uint64_t arg2,
1019                   uint32_t crfD)
1020 {
1021     CPU_DoubleU farg1, farg2;
1022     uint32_t ret = 0;
1023
1024     farg1.ll = arg1;
1025     farg2.ll = arg2;
1026
1027     if (unlikely(float64_is_any_nan(farg1.d) ||
1028                  float64_is_any_nan(farg2.d))) {
1029         ret = 0x01UL;
1030     } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
1031         ret = 0x08UL;
1032     } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
1033         ret = 0x04UL;
1034     } else {
1035         ret = 0x02UL;
1036     }
1037
1038     env->fpscr &= ~(0x0F << FPSCR_FPRF);
1039     env->fpscr |= ret << FPSCR_FPRF;
1040     env->crf[crfD] = ret;
1041     if (unlikely(ret == 0x01UL)) {
1042         if (float64_is_signaling_nan(farg1.d, &env->fp_status) ||
1043             float64_is_signaling_nan(farg2.d, &env->fp_status)) {
1044             /* sNaN comparison */
1045             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN |
1046                                   POWERPC_EXCP_FP_VXVC, 1);
1047         } else {
1048             /* qNaN comparison */
1049             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 1);
1050         }
1051     }
1052 }
1053
1054 /* Single-precision floating-point conversions */
1055 static inline uint32_t efscfsi(CPUPPCState *env, uint32_t val)
1056 {
1057     CPU_FloatU u;
1058
1059     u.f = int32_to_float32(val, &env->vec_status);
1060
1061     return u.l;
1062 }
1063
1064 static inline uint32_t efscfui(CPUPPCState *env, uint32_t val)
1065 {
1066     CPU_FloatU u;
1067
1068     u.f = uint32_to_float32(val, &env->vec_status);
1069
1070     return u.l;
1071 }
1072
1073 static inline int32_t efsctsi(CPUPPCState *env, uint32_t val)
1074 {
1075     CPU_FloatU u;
1076
1077     u.l = val;
1078     /* NaN are not treated the same way IEEE 754 does */
1079     if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1080         return 0;
1081     }
1082
1083     return float32_to_int32(u.f, &env->vec_status);
1084 }
1085
1086 static inline uint32_t efsctui(CPUPPCState *env, uint32_t val)
1087 {
1088     CPU_FloatU u;
1089
1090     u.l = val;
1091     /* NaN are not treated the same way IEEE 754 does */
1092     if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1093         return 0;
1094     }
1095
1096     return float32_to_uint32(u.f, &env->vec_status);
1097 }
1098
1099 static inline uint32_t efsctsiz(CPUPPCState *env, uint32_t val)
1100 {
1101     CPU_FloatU u;
1102
1103     u.l = val;
1104     /* NaN are not treated the same way IEEE 754 does */
1105     if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1106         return 0;
1107     }
1108
1109     return float32_to_int32_round_to_zero(u.f, &env->vec_status);
1110 }
1111
1112 static inline uint32_t efsctuiz(CPUPPCState *env, uint32_t val)
1113 {
1114     CPU_FloatU u;
1115
1116     u.l = val;
1117     /* NaN are not treated the same way IEEE 754 does */
1118     if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1119         return 0;
1120     }
1121
1122     return float32_to_uint32_round_to_zero(u.f, &env->vec_status);
1123 }
1124
1125 static inline uint32_t efscfsf(CPUPPCState *env, uint32_t val)
1126 {
1127     CPU_FloatU u;
1128     float32 tmp;
1129
1130     u.f = int32_to_float32(val, &env->vec_status);
1131     tmp = int64_to_float32(1ULL << 32, &env->vec_status);
1132     u.f = float32_div(u.f, tmp, &env->vec_status);
1133
1134     return u.l;
1135 }
1136
1137 static inline uint32_t efscfuf(CPUPPCState *env, uint32_t val)
1138 {
1139     CPU_FloatU u;
1140     float32 tmp;
1141
1142     u.f = uint32_to_float32(val, &env->vec_status);
1143     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1144     u.f = float32_div(u.f, tmp, &env->vec_status);
1145
1146     return u.l;
1147 }
1148
1149 static inline uint32_t efsctsf(CPUPPCState *env, uint32_t val)
1150 {
1151     CPU_FloatU u;
1152     float32 tmp;
1153
1154     u.l = val;
1155     /* NaN are not treated the same way IEEE 754 does */
1156     if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1157         return 0;
1158     }
1159     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1160     u.f = float32_mul(u.f, tmp, &env->vec_status);
1161
1162     return float32_to_int32(u.f, &env->vec_status);
1163 }
1164
1165 static inline uint32_t efsctuf(CPUPPCState *env, uint32_t val)
1166 {
1167     CPU_FloatU u;
1168     float32 tmp;
1169
1170     u.l = val;
1171     /* NaN are not treated the same way IEEE 754 does */
1172     if (unlikely(float32_is_quiet_nan(u.f, &env->vec_status))) {
1173         return 0;
1174     }
1175     tmp = uint64_to_float32(1ULL << 32, &env->vec_status);
1176     u.f = float32_mul(u.f, tmp, &env->vec_status);
1177
1178     return float32_to_uint32(u.f, &env->vec_status);
1179 }
1180
1181 #define HELPER_SPE_SINGLE_CONV(name)                              \
1182     uint32_t helper_e##name(CPUPPCState *env, uint32_t val)       \
1183     {                                                             \
1184         return e##name(env, val);                                 \
1185     }
1186 /* efscfsi */
1187 HELPER_SPE_SINGLE_CONV(fscfsi);
1188 /* efscfui */
1189 HELPER_SPE_SINGLE_CONV(fscfui);
1190 /* efscfuf */
1191 HELPER_SPE_SINGLE_CONV(fscfuf);
1192 /* efscfsf */
1193 HELPER_SPE_SINGLE_CONV(fscfsf);
1194 /* efsctsi */
1195 HELPER_SPE_SINGLE_CONV(fsctsi);
1196 /* efsctui */
1197 HELPER_SPE_SINGLE_CONV(fsctui);
1198 /* efsctsiz */
1199 HELPER_SPE_SINGLE_CONV(fsctsiz);
1200 /* efsctuiz */
1201 HELPER_SPE_SINGLE_CONV(fsctuiz);
1202 /* efsctsf */
1203 HELPER_SPE_SINGLE_CONV(fsctsf);
1204 /* efsctuf */
1205 HELPER_SPE_SINGLE_CONV(fsctuf);
1206
1207 #define HELPER_SPE_VECTOR_CONV(name)                            \
1208     uint64_t helper_ev##name(CPUPPCState *env, uint64_t val)    \
1209     {                                                           \
1210         return ((uint64_t)e##name(env, val >> 32) << 32) |      \
1211             (uint64_t)e##name(env, val);                        \
1212     }
1213 /* evfscfsi */
1214 HELPER_SPE_VECTOR_CONV(fscfsi);
1215 /* evfscfui */
1216 HELPER_SPE_VECTOR_CONV(fscfui);
1217 /* evfscfuf */
1218 HELPER_SPE_VECTOR_CONV(fscfuf);
1219 /* evfscfsf */
1220 HELPER_SPE_VECTOR_CONV(fscfsf);
1221 /* evfsctsi */
1222 HELPER_SPE_VECTOR_CONV(fsctsi);
1223 /* evfsctui */
1224 HELPER_SPE_VECTOR_CONV(fsctui);
1225 /* evfsctsiz */
1226 HELPER_SPE_VECTOR_CONV(fsctsiz);
1227 /* evfsctuiz */
1228 HELPER_SPE_VECTOR_CONV(fsctuiz);
1229 /* evfsctsf */
1230 HELPER_SPE_VECTOR_CONV(fsctsf);
1231 /* evfsctuf */
1232 HELPER_SPE_VECTOR_CONV(fsctuf);
1233
1234 /* Single-precision floating-point arithmetic */
1235 static inline uint32_t efsadd(CPUPPCState *env, uint32_t op1, uint32_t op2)
1236 {
1237     CPU_FloatU u1, u2;
1238
1239     u1.l = op1;
1240     u2.l = op2;
1241     u1.f = float32_add(u1.f, u2.f, &env->vec_status);
1242     return u1.l;
1243 }
1244
1245 static inline uint32_t efssub(CPUPPCState *env, uint32_t op1, uint32_t op2)
1246 {
1247     CPU_FloatU u1, u2;
1248
1249     u1.l = op1;
1250     u2.l = op2;
1251     u1.f = float32_sub(u1.f, u2.f, &env->vec_status);
1252     return u1.l;
1253 }
1254
1255 static inline uint32_t efsmul(CPUPPCState *env, uint32_t op1, uint32_t op2)
1256 {
1257     CPU_FloatU u1, u2;
1258
1259     u1.l = op1;
1260     u2.l = op2;
1261     u1.f = float32_mul(u1.f, u2.f, &env->vec_status);
1262     return u1.l;
1263 }
1264
1265 static inline uint32_t efsdiv(CPUPPCState *env, uint32_t op1, uint32_t op2)
1266 {
1267     CPU_FloatU u1, u2;
1268
1269     u1.l = op1;
1270     u2.l = op2;
1271     u1.f = float32_div(u1.f, u2.f, &env->vec_status);
1272     return u1.l;
1273 }
1274
1275 #define HELPER_SPE_SINGLE_ARITH(name)                                   \
1276     uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1277     {                                                                   \
1278         return e##name(env, op1, op2);                                  \
1279     }
1280 /* efsadd */
1281 HELPER_SPE_SINGLE_ARITH(fsadd);
1282 /* efssub */
1283 HELPER_SPE_SINGLE_ARITH(fssub);
1284 /* efsmul */
1285 HELPER_SPE_SINGLE_ARITH(fsmul);
1286 /* efsdiv */
1287 HELPER_SPE_SINGLE_ARITH(fsdiv);
1288
1289 #define HELPER_SPE_VECTOR_ARITH(name)                                   \
1290     uint64_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1291     {                                                                   \
1292         return ((uint64_t)e##name(env, op1 >> 32, op2 >> 32) << 32) |   \
1293             (uint64_t)e##name(env, op1, op2);                           \
1294     }
1295 /* evfsadd */
1296 HELPER_SPE_VECTOR_ARITH(fsadd);
1297 /* evfssub */
1298 HELPER_SPE_VECTOR_ARITH(fssub);
1299 /* evfsmul */
1300 HELPER_SPE_VECTOR_ARITH(fsmul);
1301 /* evfsdiv */
1302 HELPER_SPE_VECTOR_ARITH(fsdiv);
1303
1304 /* Single-precision floating-point comparisons */
1305 static inline uint32_t efscmplt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1306 {
1307     CPU_FloatU u1, u2;
1308
1309     u1.l = op1;
1310     u2.l = op2;
1311     return float32_lt(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1312 }
1313
1314 static inline uint32_t efscmpgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1315 {
1316     CPU_FloatU u1, u2;
1317
1318     u1.l = op1;
1319     u2.l = op2;
1320     return float32_le(u1.f, u2.f, &env->vec_status) ? 0 : 4;
1321 }
1322
1323 static inline uint32_t efscmpeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1324 {
1325     CPU_FloatU u1, u2;
1326
1327     u1.l = op1;
1328     u2.l = op2;
1329     return float32_eq(u1.f, u2.f, &env->vec_status) ? 4 : 0;
1330 }
1331
1332 static inline uint32_t efststlt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1333 {
1334     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1335     return efscmplt(env, op1, op2);
1336 }
1337
1338 static inline uint32_t efststgt(CPUPPCState *env, uint32_t op1, uint32_t op2)
1339 {
1340     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1341     return efscmpgt(env, op1, op2);
1342 }
1343
1344 static inline uint32_t efststeq(CPUPPCState *env, uint32_t op1, uint32_t op2)
1345 {
1346     /* XXX: TODO: ignore special values (NaN, infinites, ...) */
1347     return efscmpeq(env, op1, op2);
1348 }
1349
1350 #define HELPER_SINGLE_SPE_CMP(name)                                     \
1351     uint32_t helper_e##name(CPUPPCState *env, uint32_t op1, uint32_t op2) \
1352     {                                                                   \
1353         return e##name(env, op1, op2);                                  \
1354     }
1355 /* efststlt */
1356 HELPER_SINGLE_SPE_CMP(fststlt);
1357 /* efststgt */
1358 HELPER_SINGLE_SPE_CMP(fststgt);
1359 /* efststeq */
1360 HELPER_SINGLE_SPE_CMP(fststeq);
1361 /* efscmplt */
1362 HELPER_SINGLE_SPE_CMP(fscmplt);
1363 /* efscmpgt */
1364 HELPER_SINGLE_SPE_CMP(fscmpgt);
1365 /* efscmpeq */
1366 HELPER_SINGLE_SPE_CMP(fscmpeq);
1367
1368 static inline uint32_t evcmp_merge(int t0, int t1)
1369 {
1370     return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
1371 }
1372
1373 #define HELPER_VECTOR_SPE_CMP(name)                                     \
1374     uint32_t helper_ev##name(CPUPPCState *env, uint64_t op1, uint64_t op2) \
1375     {                                                                   \
1376         return evcmp_merge(e##name(env, op1 >> 32, op2 >> 32),          \
1377                            e##name(env, op1, op2));                     \
1378     }
1379 /* evfststlt */
1380 HELPER_VECTOR_SPE_CMP(fststlt);
1381 /* evfststgt */
1382 HELPER_VECTOR_SPE_CMP(fststgt);
1383 /* evfststeq */
1384 HELPER_VECTOR_SPE_CMP(fststeq);
1385 /* evfscmplt */
1386 HELPER_VECTOR_SPE_CMP(fscmplt);
1387 /* evfscmpgt */
1388 HELPER_VECTOR_SPE_CMP(fscmpgt);
1389 /* evfscmpeq */
1390 HELPER_VECTOR_SPE_CMP(fscmpeq);
1391
1392 /* Double-precision floating-point conversion */
1393 uint64_t helper_efdcfsi(CPUPPCState *env, uint32_t val)
1394 {
1395     CPU_DoubleU u;
1396
1397     u.d = int32_to_float64(val, &env->vec_status);
1398
1399     return u.ll;
1400 }
1401
1402 uint64_t helper_efdcfsid(CPUPPCState *env, uint64_t val)
1403 {
1404     CPU_DoubleU u;
1405
1406     u.d = int64_to_float64(val, &env->vec_status);
1407
1408     return u.ll;
1409 }
1410
1411 uint64_t helper_efdcfui(CPUPPCState *env, uint32_t val)
1412 {
1413     CPU_DoubleU u;
1414
1415     u.d = uint32_to_float64(val, &env->vec_status);
1416
1417     return u.ll;
1418 }
1419
1420 uint64_t helper_efdcfuid(CPUPPCState *env, uint64_t val)
1421 {
1422     CPU_DoubleU u;
1423
1424     u.d = uint64_to_float64(val, &env->vec_status);
1425
1426     return u.ll;
1427 }
1428
1429 uint32_t helper_efdctsi(CPUPPCState *env, uint64_t val)
1430 {
1431     CPU_DoubleU u;
1432
1433     u.ll = val;
1434     /* NaN are not treated the same way IEEE 754 does */
1435     if (unlikely(float64_is_any_nan(u.d))) {
1436         return 0;
1437     }
1438
1439     return float64_to_int32(u.d, &env->vec_status);
1440 }
1441
1442 uint32_t helper_efdctui(CPUPPCState *env, uint64_t val)
1443 {
1444     CPU_DoubleU u;
1445
1446     u.ll = val;
1447     /* NaN are not treated the same way IEEE 754 does */
1448     if (unlikely(float64_is_any_nan(u.d))) {
1449         return 0;
1450     }
1451
1452     return float64_to_uint32(u.d, &env->vec_status);
1453 }
1454
1455 uint32_t helper_efdctsiz(CPUPPCState *env, uint64_t val)
1456 {
1457     CPU_DoubleU u;
1458
1459     u.ll = val;
1460     /* NaN are not treated the same way IEEE 754 does */
1461     if (unlikely(float64_is_any_nan(u.d))) {
1462         return 0;
1463     }
1464
1465     return float64_to_int32_round_to_zero(u.d, &env->vec_status);
1466 }
1467
1468 uint64_t helper_efdctsidz(CPUPPCState *env, uint64_t val)
1469 {
1470     CPU_DoubleU u;
1471
1472     u.ll = val;
1473     /* NaN are not treated the same way IEEE 754 does */
1474     if (unlikely(float64_is_any_nan(u.d))) {
1475         return 0;
1476     }
1477
1478     return float64_to_int64_round_to_zero(u.d, &env->vec_status);
1479 }
1480
1481 uint32_t helper_efdctuiz(CPUPPCState *env, uint64_t val)
1482 {
1483     CPU_DoubleU u;
1484
1485     u.ll = val;
1486     /* NaN are not treated the same way IEEE 754 does */
1487     if (unlikely(float64_is_any_nan(u.d))) {
1488         return 0;
1489     }
1490
1491     return float64_to_uint32_round_to_zero(u.d, &env->vec_status);
1492 }
1493
1494 uint64_t helper_efdctuidz(CPUPPCState *env, uint64_t val)
1495 {
1496     CPU_DoubleU u;
1497
1498     u.ll = val;
1499     /* NaN are not treated the same way IEEE 754 does */
1500     if (unlikely(float64_is_any_nan(u.d))) {
1501         return 0;
1502     }
1503
1504     return float64_to_uint64_round_to_zero(u.d, &env->vec_status);
1505 }
1506
1507 uint64_t helper_efdcfsf(CPUPPCState *env, uint32_t val)
1508 {
1509     CPU_DoubleU u;
1510     float64 tmp;
1511
1512     u.d = int32_to_float64(val, &env->vec_status);
1513     tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1514     u.d = float64_div(u.d, tmp, &env->vec_status);
1515
1516     return u.ll;
1517 }
1518
1519 uint64_t helper_efdcfuf(CPUPPCState *env, uint32_t val)
1520 {
1521     CPU_DoubleU u;
1522     float64 tmp;
1523
1524     u.d = uint32_to_float64(val, &env->vec_status);
1525     tmp = int64_to_float64(1ULL << 32, &env->vec_status);
1526     u.d = float64_div(u.d, tmp, &env->vec_status);
1527
1528     return u.ll;
1529 }
1530
1531 uint32_t helper_efdctsf(CPUPPCState *env, uint64_t val)
1532 {
1533     CPU_DoubleU u;
1534     float64 tmp;
1535
1536     u.ll = val;
1537     /* NaN are not treated the same way IEEE 754 does */
1538     if (unlikely(float64_is_any_nan(u.d))) {
1539         return 0;
1540     }
1541     tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1542     u.d = float64_mul(u.d, tmp, &env->vec_status);
1543
1544     return float64_to_int32(u.d, &env->vec_status);
1545 }
1546
1547 uint32_t helper_efdctuf(CPUPPCState *env, uint64_t val)
1548 {
1549     CPU_DoubleU u;
1550     float64 tmp;
1551
1552     u.ll = val;
1553     /* NaN are not treated the same way IEEE 754 does */
1554     if (unlikely(float64_is_any_nan(u.d))) {
1555         return 0;
1556     }
1557     tmp = uint64_to_float64(1ULL << 32, &env->vec_status);
1558     u.d = float64_mul(u.d, tmp, &env->vec_status);
1559
1560     return float64_to_uint32(u.d, &env->vec_status);
1561 }
1562
1563 uint32_t helper_efscfd(CPUPPCState *env, uint64_t val)
1564 {
1565     CPU_DoubleU u1;
1566     CPU_FloatU u2;
1567
1568     u1.ll = val;
1569     u2.f = float64_to_float32(u1.d, &env->vec_status);
1570
1571     return u2.l;
1572 }
1573
1574 uint64_t helper_efdcfs(CPUPPCState *env, uint32_t val)
1575 {
1576     CPU_DoubleU u2;
1577     CPU_FloatU u1;
1578
1579     u1.l = val;
1580     u2.d = float32_to_float64(u1.f, &env->vec_status);
1581
1582     return u2.ll;
1583 }
1584
1585 /* Double precision fixed-point arithmetic */
1586 uint64_t helper_efdadd(CPUPPCState *env, uint64_t op1, uint64_t op2)
1587 {
1588     CPU_DoubleU u1, u2;
1589
1590     u1.ll = op1;
1591     u2.ll = op2;
1592     u1.d = float64_add(u1.d, u2.d, &env->vec_status);
1593     return u1.ll;
1594 }
1595
1596 uint64_t helper_efdsub(CPUPPCState *env, uint64_t op1, uint64_t op2)
1597 {
1598     CPU_DoubleU u1, u2;
1599
1600     u1.ll = op1;
1601     u2.ll = op2;
1602     u1.d = float64_sub(u1.d, u2.d, &env->vec_status);
1603     return u1.ll;
1604 }
1605
1606 uint64_t helper_efdmul(CPUPPCState *env, uint64_t op1, uint64_t op2)
1607 {
1608     CPU_DoubleU u1, u2;
1609
1610     u1.ll = op1;
1611     u2.ll = op2;
1612     u1.d = float64_mul(u1.d, u2.d, &env->vec_status);
1613     return u1.ll;
1614 }
1615
1616 uint64_t helper_efddiv(CPUPPCState *env, uint64_t op1, uint64_t op2)
1617 {
1618     CPU_DoubleU u1, u2;
1619
1620     u1.ll = op1;
1621     u2.ll = op2;
1622     u1.d = float64_div(u1.d, u2.d, &env->vec_status);
1623     return u1.ll;
1624 }
1625
1626 /* Double precision floating point helpers */
1627 uint32_t helper_efdtstlt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1628 {
1629     CPU_DoubleU u1, u2;
1630
1631     u1.ll = op1;
1632     u2.ll = op2;
1633     return float64_lt(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1634 }
1635
1636 uint32_t helper_efdtstgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1637 {
1638     CPU_DoubleU u1, u2;
1639
1640     u1.ll = op1;
1641     u2.ll = op2;
1642     return float64_le(u1.d, u2.d, &env->vec_status) ? 0 : 4;
1643 }
1644
1645 uint32_t helper_efdtsteq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1646 {
1647     CPU_DoubleU u1, u2;
1648
1649     u1.ll = op1;
1650     u2.ll = op2;
1651     return float64_eq_quiet(u1.d, u2.d, &env->vec_status) ? 4 : 0;
1652 }
1653
1654 uint32_t helper_efdcmplt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1655 {
1656     /* XXX: TODO: test special values (NaN, infinites, ...) */
1657     return helper_efdtstlt(env, op1, op2);
1658 }
1659
1660 uint32_t helper_efdcmpgt(CPUPPCState *env, uint64_t op1, uint64_t op2)
1661 {
1662     /* XXX: TODO: test special values (NaN, infinites, ...) */
1663     return helper_efdtstgt(env, op1, op2);
1664 }
1665
1666 uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
1667 {
1668     /* XXX: TODO: test special values (NaN, infinites, ...) */
1669     return helper_efdtsteq(env, op1, op2);
1670 }
1671
1672 #define float64_to_float64(x, env) x
1673
1674
1675 /* VSX_ADD_SUB - VSX floating point add/subract
1676  *   name  - instruction mnemonic
1677  *   op    - operation (add or sub)
1678  *   nels  - number of elements (1, 2 or 4)
1679  *   tp    - type (float32 or float64)
1680  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1681  *   sfprf - set FPRF
1682  */
1683 #define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp)                    \
1684 void helper_##name(CPUPPCState *env, uint32_t opcode)                        \
1685 {                                                                            \
1686     ppc_vsr_t xt, xa, xb;                                                    \
1687     int i;                                                                   \
1688                                                                              \
1689     getVSR(xA(opcode), &xa, env);                                            \
1690     getVSR(xB(opcode), &xb, env);                                            \
1691     getVSR(xT(opcode), &xt, env);                                            \
1692     helper_reset_fpstatus(env);                                              \
1693                                                                              \
1694     for (i = 0; i < nels; i++) {                                             \
1695         float_status tstat = env->fp_status;                                 \
1696         set_float_exception_flags(0, &tstat);                                \
1697         xt.fld = tp##_##op(xa.fld, xb.fld, &tstat);                          \
1698         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1699                                                                              \
1700         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
1701             if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) {      \
1702                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf);    \
1703             } else if (tp##_is_signaling_nan(xa.fld, &tstat) ||              \
1704                        tp##_is_signaling_nan(xb.fld, &tstat)) {              \
1705                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
1706             }                                                                \
1707         }                                                                    \
1708                                                                              \
1709         if (r2sp) {                                                          \
1710             xt.fld = helper_frsp(env, xt.fld);                               \
1711         }                                                                    \
1712                                                                              \
1713         if (sfprf) {                                                         \
1714             helper_compute_fprf_float64(env, xt.fld);                        \
1715         }                                                                    \
1716     }                                                                        \
1717     putVSR(xT(opcode), &xt, env);                                            \
1718     float_check_status(env);                                                 \
1719 }
1720
1721 VSX_ADD_SUB(xsadddp, add, 1, float64, VsrD(0), 1, 0)
1722 VSX_ADD_SUB(xsaddsp, add, 1, float64, VsrD(0), 1, 1)
1723 VSX_ADD_SUB(xvadddp, add, 2, float64, VsrD(i), 0, 0)
1724 VSX_ADD_SUB(xvaddsp, add, 4, float32, VsrW(i), 0, 0)
1725 VSX_ADD_SUB(xssubdp, sub, 1, float64, VsrD(0), 1, 0)
1726 VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
1727 VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
1728 VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
1729
1730 void helper_xsaddqp(CPUPPCState *env, uint32_t opcode)
1731 {
1732     ppc_vsr_t xt, xa, xb;
1733     float_status tstat;
1734
1735     getVSR(rA(opcode) + 32, &xa, env);
1736     getVSR(rB(opcode) + 32, &xb, env);
1737     getVSR(rD(opcode) + 32, &xt, env);
1738     helper_reset_fpstatus(env);
1739
1740     tstat = env->fp_status;
1741     if (unlikely(Rc(opcode) != 0)) {
1742         tstat.float_rounding_mode = float_round_to_odd;
1743     }
1744
1745     set_float_exception_flags(0, &tstat);
1746     xt.f128 = float128_add(xa.f128, xb.f128, &tstat);
1747     env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1748
1749     if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1750         if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
1751             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
1752         } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
1753                    float128_is_signaling_nan(xb.f128, &tstat)) {
1754             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
1755         }
1756     }
1757
1758     helper_compute_fprf_float128(env, xt.f128);
1759
1760     putVSR(rD(opcode) + 32, &xt, env);
1761     float_check_status(env);
1762 }
1763
1764 /* VSX_MUL - VSX floating point multiply
1765  *   op    - instruction mnemonic
1766  *   nels  - number of elements (1, 2 or 4)
1767  *   tp    - type (float32 or float64)
1768  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1769  *   sfprf - set FPRF
1770  */
1771 #define VSX_MUL(op, nels, tp, fld, sfprf, r2sp)                              \
1772 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
1773 {                                                                            \
1774     ppc_vsr_t xt, xa, xb;                                                    \
1775     int i;                                                                   \
1776                                                                              \
1777     getVSR(xA(opcode), &xa, env);                                            \
1778     getVSR(xB(opcode), &xb, env);                                            \
1779     getVSR(xT(opcode), &xt, env);                                            \
1780     helper_reset_fpstatus(env);                                              \
1781                                                                              \
1782     for (i = 0; i < nels; i++) {                                             \
1783         float_status tstat = env->fp_status;                                 \
1784         set_float_exception_flags(0, &tstat);                                \
1785         xt.fld = tp##_mul(xa.fld, xb.fld, &tstat);                           \
1786         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
1787                                                                              \
1788         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
1789             if ((tp##_is_infinity(xa.fld) && tp##_is_zero(xb.fld)) ||        \
1790                 (tp##_is_infinity(xb.fld) && tp##_is_zero(xa.fld))) {        \
1791                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, sfprf);    \
1792             } else if (tp##_is_signaling_nan(xa.fld, &tstat) ||              \
1793                        tp##_is_signaling_nan(xb.fld, &tstat)) {              \
1794                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
1795             }                                                                \
1796         }                                                                    \
1797                                                                              \
1798         if (r2sp) {                                                          \
1799             xt.fld = helper_frsp(env, xt.fld);                               \
1800         }                                                                    \
1801                                                                              \
1802         if (sfprf) {                                                         \
1803             helper_compute_fprf_float64(env, xt.fld);                        \
1804         }                                                                    \
1805     }                                                                        \
1806                                                                              \
1807     putVSR(xT(opcode), &xt, env);                                            \
1808     float_check_status(env);                                                 \
1809 }
1810
1811 VSX_MUL(xsmuldp, 1, float64, VsrD(0), 1, 0)
1812 VSX_MUL(xsmulsp, 1, float64, VsrD(0), 1, 1)
1813 VSX_MUL(xvmuldp, 2, float64, VsrD(i), 0, 0)
1814 VSX_MUL(xvmulsp, 4, float32, VsrW(i), 0, 0)
1815
1816 void helper_xsmulqp(CPUPPCState *env, uint32_t opcode)
1817 {
1818     ppc_vsr_t xt, xa, xb;
1819     float_status tstat;
1820
1821     getVSR(rA(opcode) + 32, &xa, env);
1822     getVSR(rB(opcode) + 32, &xb, env);
1823     getVSR(rD(opcode) + 32, &xt, env);
1824
1825     helper_reset_fpstatus(env);
1826     tstat = env->fp_status;
1827     if (unlikely(Rc(opcode) != 0)) {
1828         tstat.float_rounding_mode = float_round_to_odd;
1829     }
1830
1831     set_float_exception_flags(0, &tstat);
1832     xt.f128 = float128_mul(xa.f128, xb.f128, &tstat);
1833     env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1834
1835     if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1836         if ((float128_is_infinity(xa.f128) && float128_is_zero(xb.f128)) ||
1837             (float128_is_infinity(xb.f128) && float128_is_zero(xa.f128))) {
1838             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIMZ, 1);
1839         } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
1840                    float128_is_signaling_nan(xb.f128, &tstat)) {
1841             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
1842         }
1843     }
1844     helper_compute_fprf_float128(env, xt.f128);
1845
1846     putVSR(rD(opcode) + 32, &xt, env);
1847     float_check_status(env);
1848 }
1849
1850 /* VSX_DIV - VSX floating point divide
1851  *   op    - instruction mnemonic
1852  *   nels  - number of elements (1, 2 or 4)
1853  *   tp    - type (float32 or float64)
1854  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1855  *   sfprf - set FPRF
1856  */
1857 #define VSX_DIV(op, nels, tp, fld, sfprf, r2sp)                               \
1858 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
1859 {                                                                             \
1860     ppc_vsr_t xt, xa, xb;                                                     \
1861     int i;                                                                    \
1862                                                                               \
1863     getVSR(xA(opcode), &xa, env);                                             \
1864     getVSR(xB(opcode), &xb, env);                                             \
1865     getVSR(xT(opcode), &xt, env);                                             \
1866     helper_reset_fpstatus(env);                                               \
1867                                                                               \
1868     for (i = 0; i < nels; i++) {                                              \
1869         float_status tstat = env->fp_status;                                  \
1870         set_float_exception_flags(0, &tstat);                                 \
1871         xt.fld = tp##_div(xa.fld, xb.fld, &tstat);                            \
1872         env->fp_status.float_exception_flags |= tstat.float_exception_flags;  \
1873                                                                               \
1874         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {     \
1875             if (tp##_is_infinity(xa.fld) && tp##_is_infinity(xb.fld)) {       \
1876                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, sfprf);     \
1877             } else if (tp##_is_zero(xa.fld) &&                                \
1878                 tp##_is_zero(xb.fld)) {                                       \
1879                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, sfprf);     \
1880             } else if (tp##_is_signaling_nan(xa.fld, &tstat) ||               \
1881                 tp##_is_signaling_nan(xb.fld, &tstat)) {                      \
1882                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
1883             }                                                                 \
1884         }                                                                     \
1885                                                                               \
1886         if (r2sp) {                                                           \
1887             xt.fld = helper_frsp(env, xt.fld);                                \
1888         }                                                                     \
1889                                                                               \
1890         if (sfprf) {                                                          \
1891             helper_compute_fprf_float64(env, xt.fld);                         \
1892         }                                                                     \
1893     }                                                                         \
1894                                                                               \
1895     putVSR(xT(opcode), &xt, env);                                             \
1896     float_check_status(env);                                                  \
1897 }
1898
1899 VSX_DIV(xsdivdp, 1, float64, VsrD(0), 1, 0)
1900 VSX_DIV(xsdivsp, 1, float64, VsrD(0), 1, 1)
1901 VSX_DIV(xvdivdp, 2, float64, VsrD(i), 0, 0)
1902 VSX_DIV(xvdivsp, 4, float32, VsrW(i), 0, 0)
1903
1904 void helper_xsdivqp(CPUPPCState *env, uint32_t opcode)
1905 {
1906     ppc_vsr_t xt, xa, xb;
1907     float_status tstat;
1908
1909     getVSR(rA(opcode) + 32, &xa, env);
1910     getVSR(rB(opcode) + 32, &xb, env);
1911     getVSR(rD(opcode) + 32, &xt, env);
1912
1913     helper_reset_fpstatus(env);
1914     tstat = env->fp_status;
1915     if (unlikely(Rc(opcode) != 0)) {
1916         tstat.float_rounding_mode = float_round_to_odd;
1917     }
1918
1919     set_float_exception_flags(0, &tstat);
1920     xt.f128 = float128_div(xa.f128, xb.f128, &tstat);
1921     env->fp_status.float_exception_flags |= tstat.float_exception_flags;
1922
1923     if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
1924         if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
1925             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXIDI, 1);
1926         } else if (float128_is_zero(xa.f128) &&
1927             float128_is_zero(xb.f128)) {
1928             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXZDZ, 1);
1929         } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
1930             float128_is_signaling_nan(xb.f128, &tstat)) {
1931             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
1932         }
1933     }
1934
1935     helper_compute_fprf_float128(env, xt.f128);
1936     putVSR(rD(opcode) + 32, &xt, env);
1937     float_check_status(env);
1938 }
1939
1940 /* VSX_RE  - VSX floating point reciprocal estimate
1941  *   op    - instruction mnemonic
1942  *   nels  - number of elements (1, 2 or 4)
1943  *   tp    - type (float32 or float64)
1944  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1945  *   sfprf - set FPRF
1946  */
1947 #define VSX_RE(op, nels, tp, fld, sfprf, r2sp)                                \
1948 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
1949 {                                                                             \
1950     ppc_vsr_t xt, xb;                                                         \
1951     int i;                                                                    \
1952                                                                               \
1953     getVSR(xB(opcode), &xb, env);                                             \
1954     getVSR(xT(opcode), &xt, env);                                             \
1955     helper_reset_fpstatus(env);                                               \
1956                                                                               \
1957     for (i = 0; i < nels; i++) {                                              \
1958         if (unlikely(tp##_is_signaling_nan(xb.fld, &env->fp_status))) {       \
1959                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
1960         }                                                                     \
1961         xt.fld = tp##_div(tp##_one, xb.fld, &env->fp_status);                 \
1962                                                                               \
1963         if (r2sp) {                                                           \
1964             xt.fld = helper_frsp(env, xt.fld);                                \
1965         }                                                                     \
1966                                                                               \
1967         if (sfprf) {                                                          \
1968             helper_compute_fprf_float64(env, xt.fld);                         \
1969         }                                                                     \
1970     }                                                                         \
1971                                                                               \
1972     putVSR(xT(opcode), &xt, env);                                             \
1973     float_check_status(env);                                                  \
1974 }
1975
1976 VSX_RE(xsredp, 1, float64, VsrD(0), 1, 0)
1977 VSX_RE(xsresp, 1, float64, VsrD(0), 1, 1)
1978 VSX_RE(xvredp, 2, float64, VsrD(i), 0, 0)
1979 VSX_RE(xvresp, 4, float32, VsrW(i), 0, 0)
1980
1981 /* VSX_SQRT - VSX floating point square root
1982  *   op    - instruction mnemonic
1983  *   nels  - number of elements (1, 2 or 4)
1984  *   tp    - type (float32 or float64)
1985  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
1986  *   sfprf - set FPRF
1987  */
1988 #define VSX_SQRT(op, nels, tp, fld, sfprf, r2sp)                             \
1989 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
1990 {                                                                            \
1991     ppc_vsr_t xt, xb;                                                        \
1992     int i;                                                                   \
1993                                                                              \
1994     getVSR(xB(opcode), &xb, env);                                            \
1995     getVSR(xT(opcode), &xt, env);                                            \
1996     helper_reset_fpstatus(env);                                              \
1997                                                                              \
1998     for (i = 0; i < nels; i++) {                                             \
1999         float_status tstat = env->fp_status;                                 \
2000         set_float_exception_flags(0, &tstat);                                \
2001         xt.fld = tp##_sqrt(xb.fld, &tstat);                                  \
2002         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2003                                                                              \
2004         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
2005             if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) {              \
2006                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf);   \
2007             } else if (tp##_is_signaling_nan(xb.fld, &tstat)) {              \
2008                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
2009             }                                                                \
2010         }                                                                    \
2011                                                                              \
2012         if (r2sp) {                                                          \
2013             xt.fld = helper_frsp(env, xt.fld);                               \
2014         }                                                                    \
2015                                                                              \
2016         if (sfprf) {                                                         \
2017             helper_compute_fprf_float64(env, xt.fld);                        \
2018         }                                                                    \
2019     }                                                                        \
2020                                                                              \
2021     putVSR(xT(opcode), &xt, env);                                            \
2022     float_check_status(env);                                                 \
2023 }
2024
2025 VSX_SQRT(xssqrtdp, 1, float64, VsrD(0), 1, 0)
2026 VSX_SQRT(xssqrtsp, 1, float64, VsrD(0), 1, 1)
2027 VSX_SQRT(xvsqrtdp, 2, float64, VsrD(i), 0, 0)
2028 VSX_SQRT(xvsqrtsp, 4, float32, VsrW(i), 0, 0)
2029
2030 /* VSX_RSQRTE - VSX floating point reciprocal square root estimate
2031  *   op    - instruction mnemonic
2032  *   nels  - number of elements (1, 2 or 4)
2033  *   tp    - type (float32 or float64)
2034  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2035  *   sfprf - set FPRF
2036  */
2037 #define VSX_RSQRTE(op, nels, tp, fld, sfprf, r2sp)                           \
2038 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2039 {                                                                            \
2040     ppc_vsr_t xt, xb;                                                        \
2041     int i;                                                                   \
2042                                                                              \
2043     getVSR(xB(opcode), &xb, env);                                            \
2044     getVSR(xT(opcode), &xt, env);                                            \
2045     helper_reset_fpstatus(env);                                              \
2046                                                                              \
2047     for (i = 0; i < nels; i++) {                                             \
2048         float_status tstat = env->fp_status;                                 \
2049         set_float_exception_flags(0, &tstat);                                \
2050         xt.fld = tp##_sqrt(xb.fld, &tstat);                                  \
2051         xt.fld = tp##_div(tp##_one, xt.fld, &tstat);                         \
2052         env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
2053                                                                              \
2054         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {    \
2055             if (tp##_is_neg(xb.fld) && !tp##_is_zero(xb.fld)) {              \
2056                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, sfprf);   \
2057             } else if (tp##_is_signaling_nan(xb.fld, &tstat)) {              \
2058                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);   \
2059             }                                                                \
2060         }                                                                    \
2061                                                                              \
2062         if (r2sp) {                                                          \
2063             xt.fld = helper_frsp(env, xt.fld);                               \
2064         }                                                                    \
2065                                                                              \
2066         if (sfprf) {                                                         \
2067             helper_compute_fprf_float64(env, xt.fld);                        \
2068         }                                                                    \
2069     }                                                                        \
2070                                                                              \
2071     putVSR(xT(opcode), &xt, env);                                            \
2072     float_check_status(env);                                                 \
2073 }
2074
2075 VSX_RSQRTE(xsrsqrtedp, 1, float64, VsrD(0), 1, 0)
2076 VSX_RSQRTE(xsrsqrtesp, 1, float64, VsrD(0), 1, 1)
2077 VSX_RSQRTE(xvrsqrtedp, 2, float64, VsrD(i), 0, 0)
2078 VSX_RSQRTE(xvrsqrtesp, 4, float32, VsrW(i), 0, 0)
2079
2080 /* VSX_TDIV - VSX floating point test for divide
2081  *   op    - instruction mnemonic
2082  *   nels  - number of elements (1, 2 or 4)
2083  *   tp    - type (float32 or float64)
2084  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2085  *   emin  - minimum unbiased exponent
2086  *   emax  - maximum unbiased exponent
2087  *   nbits - number of fraction bits
2088  */
2089 #define VSX_TDIV(op, nels, tp, fld, emin, emax, nbits)                  \
2090 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2091 {                                                                       \
2092     ppc_vsr_t xa, xb;                                                   \
2093     int i;                                                              \
2094     int fe_flag = 0;                                                    \
2095     int fg_flag = 0;                                                    \
2096                                                                         \
2097     getVSR(xA(opcode), &xa, env);                                       \
2098     getVSR(xB(opcode), &xb, env);                                       \
2099                                                                         \
2100     for (i = 0; i < nels; i++) {                                        \
2101         if (unlikely(tp##_is_infinity(xa.fld) ||                        \
2102                      tp##_is_infinity(xb.fld) ||                        \
2103                      tp##_is_zero(xb.fld))) {                           \
2104             fe_flag = 1;                                                \
2105             fg_flag = 1;                                                \
2106         } else {                                                        \
2107             int e_a = ppc_##tp##_get_unbiased_exp(xa.fld);              \
2108             int e_b = ppc_##tp##_get_unbiased_exp(xb.fld);              \
2109                                                                         \
2110             if (unlikely(tp##_is_any_nan(xa.fld) ||                     \
2111                          tp##_is_any_nan(xb.fld))) {                    \
2112                 fe_flag = 1;                                            \
2113             } else if ((e_b <= emin) || (e_b >= (emax-2))) {            \
2114                 fe_flag = 1;                                            \
2115             } else if (!tp##_is_zero(xa.fld) &&                         \
2116                        (((e_a - e_b) >= emax) ||                        \
2117                         ((e_a - e_b) <= (emin+1)) ||                    \
2118                          (e_a <= (emin+nbits)))) {                      \
2119                 fe_flag = 1;                                            \
2120             }                                                           \
2121                                                                         \
2122             if (unlikely(tp##_is_zero_or_denormal(xb.fld))) {           \
2123                 /* XB is not zero because of the above check and */     \
2124                 /* so must be denormalized.                      */     \
2125                 fg_flag = 1;                                            \
2126             }                                                           \
2127         }                                                               \
2128     }                                                                   \
2129                                                                         \
2130     env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2131 }
2132
2133 VSX_TDIV(xstdivdp, 1, float64, VsrD(0), -1022, 1023, 52)
2134 VSX_TDIV(xvtdivdp, 2, float64, VsrD(i), -1022, 1023, 52)
2135 VSX_TDIV(xvtdivsp, 4, float32, VsrW(i), -126, 127, 23)
2136
2137 /* VSX_TSQRT - VSX floating point test for square root
2138  *   op    - instruction mnemonic
2139  *   nels  - number of elements (1, 2 or 4)
2140  *   tp    - type (float32 or float64)
2141  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2142  *   emin  - minimum unbiased exponent
2143  *   emax  - maximum unbiased exponent
2144  *   nbits - number of fraction bits
2145  */
2146 #define VSX_TSQRT(op, nels, tp, fld, emin, nbits)                       \
2147 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2148 {                                                                       \
2149     ppc_vsr_t xa, xb;                                                   \
2150     int i;                                                              \
2151     int fe_flag = 0;                                                    \
2152     int fg_flag = 0;                                                    \
2153                                                                         \
2154     getVSR(xA(opcode), &xa, env);                                       \
2155     getVSR(xB(opcode), &xb, env);                                       \
2156                                                                         \
2157     for (i = 0; i < nels; i++) {                                        \
2158         if (unlikely(tp##_is_infinity(xb.fld) ||                        \
2159                      tp##_is_zero(xb.fld))) {                           \
2160             fe_flag = 1;                                                \
2161             fg_flag = 1;                                                \
2162         } else {                                                        \
2163             int e_b = ppc_##tp##_get_unbiased_exp(xb.fld);              \
2164                                                                         \
2165             if (unlikely(tp##_is_any_nan(xb.fld))) {                    \
2166                 fe_flag = 1;                                            \
2167             } else if (unlikely(tp##_is_zero(xb.fld))) {                \
2168                 fe_flag = 1;                                            \
2169             } else if (unlikely(tp##_is_neg(xb.fld))) {                 \
2170                 fe_flag = 1;                                            \
2171             } else if (!tp##_is_zero(xb.fld) &&                         \
2172                       (e_b <= (emin+nbits))) {                          \
2173                 fe_flag = 1;                                            \
2174             }                                                           \
2175                                                                         \
2176             if (unlikely(tp##_is_zero_or_denormal(xb.fld))) {           \
2177                 /* XB is not zero because of the above check and */     \
2178                 /* therefore must be denormalized.               */     \
2179                 fg_flag = 1;                                            \
2180             }                                                           \
2181         }                                                               \
2182     }                                                                   \
2183                                                                         \
2184     env->crf[BF(opcode)] = 0x8 | (fg_flag ? 4 : 0) | (fe_flag ? 2 : 0); \
2185 }
2186
2187 VSX_TSQRT(xstsqrtdp, 1, float64, VsrD(0), -1022, 52)
2188 VSX_TSQRT(xvtsqrtdp, 2, float64, VsrD(i), -1022, 52)
2189 VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
2190
2191 /* VSX_MADD - VSX floating point muliply/add variations
2192  *   op    - instruction mnemonic
2193  *   nels  - number of elements (1, 2 or 4)
2194  *   tp    - type (float32 or float64)
2195  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2196  *   maddflgs - flags for the float*muladd routine that control the
2197  *           various forms (madd, msub, nmadd, nmsub)
2198  *   afrm  - A form (1=A, 0=M)
2199  *   sfprf - set FPRF
2200  */
2201 #define VSX_MADD(op, nels, tp, fld, maddflgs, afrm, sfprf, r2sp)              \
2202 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
2203 {                                                                             \
2204     ppc_vsr_t xt_in, xa, xb, xt_out;                                          \
2205     ppc_vsr_t *b, *c;                                                         \
2206     int i;                                                                    \
2207                                                                               \
2208     if (afrm) { /* AxB + T */                                                 \
2209         b = &xb;                                                              \
2210         c = &xt_in;                                                           \
2211     } else { /* AxT + B */                                                    \
2212         b = &xt_in;                                                           \
2213         c = &xb;                                                              \
2214     }                                                                         \
2215                                                                               \
2216     getVSR(xA(opcode), &xa, env);                                             \
2217     getVSR(xB(opcode), &xb, env);                                             \
2218     getVSR(xT(opcode), &xt_in, env);                                          \
2219                                                                               \
2220     xt_out = xt_in;                                                           \
2221                                                                               \
2222     helper_reset_fpstatus(env);                                               \
2223                                                                               \
2224     for (i = 0; i < nels; i++) {                                              \
2225         float_status tstat = env->fp_status;                                  \
2226         set_float_exception_flags(0, &tstat);                                 \
2227         if (r2sp && (tstat.float_rounding_mode == float_round_nearest_even)) {\
2228             /* Avoid double rounding errors by rounding the intermediate */   \
2229             /* result to odd.                                            */   \
2230             set_float_rounding_mode(float_round_to_zero, &tstat);             \
2231             xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld,                  \
2232                                        maddflgs, &tstat);                     \
2233             xt_out.fld |= (get_float_exception_flags(&tstat) &                \
2234                               float_flag_inexact) != 0;                       \
2235         } else {                                                              \
2236             xt_out.fld = tp##_muladd(xa.fld, b->fld, c->fld,                  \
2237                                         maddflgs, &tstat);                    \
2238         }                                                                     \
2239         env->fp_status.float_exception_flags |= tstat.float_exception_flags;  \
2240                                                                               \
2241         if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {     \
2242             if (tp##_is_signaling_nan(xa.fld, &tstat) ||                      \
2243                 tp##_is_signaling_nan(b->fld, &tstat) ||                      \
2244                 tp##_is_signaling_nan(c->fld, &tstat)) {                      \
2245                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, sfprf);    \
2246                 tstat.float_exception_flags &= ~float_flag_invalid;           \
2247             }                                                                 \
2248             if ((tp##_is_infinity(xa.fld) && tp##_is_zero(b->fld)) ||         \
2249                 (tp##_is_zero(xa.fld) && tp##_is_infinity(b->fld))) {         \
2250                 xt_out.fld = float64_to_##tp(float_invalid_op_excp(env,       \
2251                     POWERPC_EXCP_FP_VXIMZ, sfprf), &env->fp_status);          \
2252                 tstat.float_exception_flags &= ~float_flag_invalid;           \
2253             }                                                                 \
2254             if ((tstat.float_exception_flags & float_flag_invalid) &&         \
2255                 ((tp##_is_infinity(xa.fld) ||                                 \
2256                   tp##_is_infinity(b->fld)) &&                                \
2257                   tp##_is_infinity(c->fld))) {                                \
2258                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, sfprf);     \
2259             }                                                                 \
2260         }                                                                     \
2261                                                                               \
2262         if (r2sp) {                                                           \
2263             xt_out.fld = helper_frsp(env, xt_out.fld);                        \
2264         }                                                                     \
2265                                                                               \
2266         if (sfprf) {                                                          \
2267             helper_compute_fprf_float64(env, xt_out.fld);                     \
2268         }                                                                     \
2269     }                                                                         \
2270     putVSR(xT(opcode), &xt_out, env);                                         \
2271     float_check_status(env);                                                  \
2272 }
2273
2274 VSX_MADD(xsmaddadp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 0)
2275 VSX_MADD(xsmaddmdp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 0)
2276 VSX_MADD(xsmsubadp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 0)
2277 VSX_MADD(xsmsubmdp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 0)
2278 VSX_MADD(xsnmaddadp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 0)
2279 VSX_MADD(xsnmaddmdp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 0)
2280 VSX_MADD(xsnmsubadp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 0)
2281 VSX_MADD(xsnmsubmdp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 0)
2282
2283 VSX_MADD(xsmaddasp, 1, float64, VsrD(0), MADD_FLGS, 1, 1, 1)
2284 VSX_MADD(xsmaddmsp, 1, float64, VsrD(0), MADD_FLGS, 0, 1, 1)
2285 VSX_MADD(xsmsubasp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1, 1)
2286 VSX_MADD(xsmsubmsp, 1, float64, VsrD(0), MSUB_FLGS, 0, 1, 1)
2287 VSX_MADD(xsnmaddasp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1, 1)
2288 VSX_MADD(xsnmaddmsp, 1, float64, VsrD(0), NMADD_FLGS, 0, 1, 1)
2289 VSX_MADD(xsnmsubasp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1, 1)
2290 VSX_MADD(xsnmsubmsp, 1, float64, VsrD(0), NMSUB_FLGS, 0, 1, 1)
2291
2292 VSX_MADD(xvmaddadp, 2, float64, VsrD(i), MADD_FLGS, 1, 0, 0)
2293 VSX_MADD(xvmaddmdp, 2, float64, VsrD(i), MADD_FLGS, 0, 0, 0)
2294 VSX_MADD(xvmsubadp, 2, float64, VsrD(i), MSUB_FLGS, 1, 0, 0)
2295 VSX_MADD(xvmsubmdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0, 0)
2296 VSX_MADD(xvnmaddadp, 2, float64, VsrD(i), NMADD_FLGS, 1, 0, 0)
2297 VSX_MADD(xvnmaddmdp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0, 0)
2298 VSX_MADD(xvnmsubadp, 2, float64, VsrD(i), NMSUB_FLGS, 1, 0, 0)
2299 VSX_MADD(xvnmsubmdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0, 0)
2300
2301 VSX_MADD(xvmaddasp, 4, float32, VsrW(i), MADD_FLGS, 1, 0, 0)
2302 VSX_MADD(xvmaddmsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0, 0)
2303 VSX_MADD(xvmsubasp, 4, float32, VsrW(i), MSUB_FLGS, 1, 0, 0)
2304 VSX_MADD(xvmsubmsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0, 0)
2305 VSX_MADD(xvnmaddasp, 4, float32, VsrW(i), NMADD_FLGS, 1, 0, 0)
2306 VSX_MADD(xvnmaddmsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0, 0)
2307 VSX_MADD(xvnmsubasp, 4, float32, VsrW(i), NMSUB_FLGS, 1, 0, 0)
2308 VSX_MADD(xvnmsubmsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0, 0)
2309
2310 /* VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
2311  *   op    - instruction mnemonic
2312  *   cmp   - comparison operation
2313  *   exp   - expected result of comparison
2314  *   svxvc - set VXVC bit
2315  */
2316 #define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc)                                \
2317 void helper_##op(CPUPPCState *env, uint32_t opcode)                           \
2318 {                                                                             \
2319     ppc_vsr_t xt, xa, xb;                                                     \
2320     bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false;            \
2321                                                                               \
2322     getVSR(xA(opcode), &xa, env);                                             \
2323     getVSR(xB(opcode), &xb, env);                                             \
2324     getVSR(xT(opcode), &xt, env);                                             \
2325                                                                               \
2326     if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) ||              \
2327         float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) {              \
2328         vxsnan_flag = true;                                                   \
2329         if (fpscr_ve == 0 && svxvc) {                                         \
2330             vxvc_flag = true;                                                 \
2331         }                                                                     \
2332     } else if (svxvc) {                                                       \
2333         vxvc_flag = float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) ||      \
2334             float64_is_quiet_nan(xb.VsrD(0), &env->fp_status);                \
2335     }                                                                         \
2336     if (vxsnan_flag) {                                                        \
2337         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);                \
2338     }                                                                         \
2339     if (vxvc_flag) {                                                          \
2340         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);                  \
2341     }                                                                         \
2342     vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag);                        \
2343                                                                               \
2344     if (!vex_flag) {                                                          \
2345         if (float64_##cmp(xb.VsrD(0), xa.VsrD(0), &env->fp_status) == exp) {  \
2346             xt.VsrD(0) = -1;                                                  \
2347             xt.VsrD(1) = 0;                                                   \
2348         } else {                                                              \
2349             xt.VsrD(0) = 0;                                                   \
2350             xt.VsrD(1) = 0;                                                   \
2351         }                                                                     \
2352     }                                                                         \
2353     putVSR(xT(opcode), &xt, env);                                             \
2354     helper_float_check_status(env);                                           \
2355 }
2356
2357 VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
2358 VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
2359 VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
2360 VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
2361
2362 void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode)
2363 {
2364     ppc_vsr_t xa, xb;
2365     int64_t exp_a, exp_b;
2366     uint32_t cc;
2367
2368     getVSR(xA(opcode), &xa, env);
2369     getVSR(xB(opcode), &xb, env);
2370
2371     exp_a = extract64(xa.VsrD(0), 52, 11);
2372     exp_b = extract64(xb.VsrD(0), 52, 11);
2373
2374     if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||
2375                  float64_is_any_nan(xb.VsrD(0)))) {
2376         cc = CRF_SO;
2377     } else {
2378         if (exp_a < exp_b) {
2379             cc = CRF_LT;
2380         } else if (exp_a > exp_b) {
2381             cc = CRF_GT;
2382         } else {
2383             cc = CRF_EQ;
2384         }
2385     }
2386
2387     env->fpscr &= ~(0x0F << FPSCR_FPRF);
2388     env->fpscr |= cc << FPSCR_FPRF;
2389     env->crf[BF(opcode)] = cc;
2390
2391     helper_float_check_status(env);
2392 }
2393
2394 void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode)
2395 {
2396     ppc_vsr_t xa, xb;
2397     int64_t exp_a, exp_b;
2398     uint32_t cc;
2399
2400     getVSR(rA(opcode) + 32, &xa, env);
2401     getVSR(rB(opcode) + 32, &xb, env);
2402
2403     exp_a = extract64(xa.VsrD(0), 48, 15);
2404     exp_b = extract64(xb.VsrD(0), 48, 15);
2405
2406     if (unlikely(float128_is_any_nan(xa.f128) ||
2407                  float128_is_any_nan(xb.f128))) {
2408         cc = CRF_SO;
2409     } else {
2410         if (exp_a < exp_b) {
2411             cc = CRF_LT;
2412         } else if (exp_a > exp_b) {
2413             cc = CRF_GT;
2414         } else {
2415             cc = CRF_EQ;
2416         }
2417     }
2418
2419     env->fpscr &= ~(0x0F << FPSCR_FPRF);
2420     env->fpscr |= cc << FPSCR_FPRF;
2421     env->crf[BF(opcode)] = cc;
2422
2423     helper_float_check_status(env);
2424 }
2425
2426 #define VSX_SCALAR_CMP(op, ordered)                                      \
2427 void helper_##op(CPUPPCState *env, uint32_t opcode)                      \
2428 {                                                                        \
2429     ppc_vsr_t xa, xb;                                                    \
2430     uint32_t cc = 0;                                                     \
2431     bool vxsnan_flag = false, vxvc_flag = false;                         \
2432                                                                          \
2433     helper_reset_fpstatus(env);                                          \
2434     getVSR(xA(opcode), &xa, env);                                        \
2435     getVSR(xB(opcode), &xb, env);                                        \
2436                                                                          \
2437     if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) ||         \
2438         float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) {         \
2439         vxsnan_flag = true;                                              \
2440         cc = CRF_SO;                                                     \
2441         if (fpscr_ve == 0 && ordered) {                                  \
2442             vxvc_flag = true;                                            \
2443         }                                                                \
2444     } else if (float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) ||      \
2445                float64_is_quiet_nan(xb.VsrD(0), &env->fp_status)) {      \
2446         cc = CRF_SO;                                                     \
2447         if (ordered) {                                                   \
2448             vxvc_flag = true;                                            \
2449         }                                                                \
2450     }                                                                    \
2451     if (vxsnan_flag) {                                                   \
2452         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);           \
2453     }                                                                    \
2454     if (vxvc_flag) {                                                     \
2455         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);             \
2456     }                                                                    \
2457                                                                          \
2458     if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) {           \
2459         cc |= CRF_LT;                                                    \
2460     } else if (!float64_le(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) {   \
2461         cc |= CRF_GT;                                                    \
2462     } else {                                                             \
2463         cc |= CRF_EQ;                                                    \
2464     }                                                                    \
2465                                                                          \
2466     env->fpscr &= ~(0x0F << FPSCR_FPRF);                                 \
2467     env->fpscr |= cc << FPSCR_FPRF;                                      \
2468     env->crf[BF(opcode)] = cc;                                           \
2469                                                                          \
2470     float_check_status(env);                                             \
2471 }
2472
2473 VSX_SCALAR_CMP(xscmpodp, 1)
2474 VSX_SCALAR_CMP(xscmpudp, 0)
2475
2476 #define VSX_SCALAR_CMPQ(op, ordered)                                    \
2477 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2478 {                                                                       \
2479     ppc_vsr_t xa, xb;                                                   \
2480     uint32_t cc = 0;                                                    \
2481     bool vxsnan_flag = false, vxvc_flag = false;                        \
2482                                                                         \
2483     helper_reset_fpstatus(env);                                         \
2484     getVSR(rA(opcode) + 32, &xa, env);                                  \
2485     getVSR(rB(opcode) + 32, &xb, env);                                  \
2486                                                                         \
2487     if (float128_is_signaling_nan(xa.f128, &env->fp_status) ||          \
2488         float128_is_signaling_nan(xb.f128, &env->fp_status)) {          \
2489         vxsnan_flag = true;                                             \
2490         cc = CRF_SO;                                                    \
2491         if (fpscr_ve == 0 && ordered) {                                 \
2492             vxvc_flag = true;                                           \
2493         }                                                               \
2494     } else if (float128_is_quiet_nan(xa.f128, &env->fp_status) ||       \
2495                float128_is_quiet_nan(xb.f128, &env->fp_status)) {       \
2496         cc = CRF_SO;                                                    \
2497         if (ordered) {                                                  \
2498             vxvc_flag = true;                                           \
2499         }                                                               \
2500     }                                                                   \
2501     if (vxsnan_flag) {                                                  \
2502         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);          \
2503     }                                                                   \
2504     if (vxvc_flag) {                                                    \
2505         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);            \
2506     }                                                                   \
2507                                                                         \
2508     if (float128_lt(xa.f128, xb.f128, &env->fp_status)) {               \
2509         cc |= CRF_LT;                                                   \
2510     } else if (!float128_le(xa.f128, xb.f128, &env->fp_status)) {       \
2511         cc |= CRF_GT;                                                   \
2512     } else {                                                            \
2513         cc |= CRF_EQ;                                                   \
2514     }                                                                   \
2515                                                                         \
2516     env->fpscr &= ~(0x0F << FPSCR_FPRF);                                \
2517     env->fpscr |= cc << FPSCR_FPRF;                                     \
2518     env->crf[BF(opcode)] = cc;                                          \
2519                                                                         \
2520     float_check_status(env);                                            \
2521 }
2522
2523 VSX_SCALAR_CMPQ(xscmpoqp, 1)
2524 VSX_SCALAR_CMPQ(xscmpuqp, 0)
2525
2526 /* VSX_MAX_MIN - VSX floating point maximum/minimum
2527  *   name  - instruction mnemonic
2528  *   op    - operation (max or min)
2529  *   nels  - number of elements (1, 2 or 4)
2530  *   tp    - type (float32 or float64)
2531  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2532  */
2533 #define VSX_MAX_MIN(name, op, nels, tp, fld)                                  \
2534 void helper_##name(CPUPPCState *env, uint32_t opcode)                         \
2535 {                                                                             \
2536     ppc_vsr_t xt, xa, xb;                                                     \
2537     int i;                                                                    \
2538                                                                               \
2539     getVSR(xA(opcode), &xa, env);                                             \
2540     getVSR(xB(opcode), &xb, env);                                             \
2541     getVSR(xT(opcode), &xt, env);                                             \
2542                                                                               \
2543     for (i = 0; i < nels; i++) {                                              \
2544         xt.fld = tp##_##op(xa.fld, xb.fld, &env->fp_status);                  \
2545         if (unlikely(tp##_is_signaling_nan(xa.fld, &env->fp_status) ||        \
2546                      tp##_is_signaling_nan(xb.fld, &env->fp_status))) {       \
2547             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);            \
2548         }                                                                     \
2549     }                                                                         \
2550                                                                               \
2551     putVSR(xT(opcode), &xt, env);                                             \
2552     float_check_status(env);                                                  \
2553 }
2554
2555 VSX_MAX_MIN(xsmaxdp, maxnum, 1, float64, VsrD(0))
2556 VSX_MAX_MIN(xvmaxdp, maxnum, 2, float64, VsrD(i))
2557 VSX_MAX_MIN(xvmaxsp, maxnum, 4, float32, VsrW(i))
2558 VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
2559 VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
2560 VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
2561
2562 #define VSX_MAX_MINC(name, max)                                               \
2563 void helper_##name(CPUPPCState *env, uint32_t opcode)                         \
2564 {                                                                             \
2565     ppc_vsr_t xt, xa, xb;                                                     \
2566     bool vxsnan_flag = false, vex_flag = false;                               \
2567                                                                               \
2568     getVSR(rA(opcode) + 32, &xa, env);                                        \
2569     getVSR(rB(opcode) + 32, &xb, env);                                        \
2570     getVSR(rD(opcode) + 32, &xt, env);                                        \
2571                                                                               \
2572     if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||                            \
2573                  float64_is_any_nan(xb.VsrD(0)))) {                           \
2574         if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) ||          \
2575             float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) {          \
2576             vxsnan_flag = true;                                               \
2577         }                                                                     \
2578         xt.VsrD(0) = xb.VsrD(0);                                              \
2579     } else if ((max &&                                                        \
2580                !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) ||       \
2581                (!max &&                                                       \
2582                float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) {        \
2583         xt.VsrD(0) = xa.VsrD(0);                                              \
2584     } else {                                                                  \
2585         xt.VsrD(0) = xb.VsrD(0);                                              \
2586     }                                                                         \
2587                                                                               \
2588     vex_flag = fpscr_ve & vxsnan_flag;                                        \
2589     if (vxsnan_flag) {                                                        \
2590             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);            \
2591     }                                                                         \
2592     if (!vex_flag) {                                                          \
2593         putVSR(rD(opcode) + 32, &xt, env);                                    \
2594     }                                                                         \
2595 }                                                                             \
2596
2597 VSX_MAX_MINC(xsmaxcdp, 1);
2598 VSX_MAX_MINC(xsmincdp, 0);
2599
2600 #define VSX_MAX_MINJ(name, max)                                               \
2601 void helper_##name(CPUPPCState *env, uint32_t opcode)                         \
2602 {                                                                             \
2603     ppc_vsr_t xt, xa, xb;                                                     \
2604     bool vxsnan_flag = false, vex_flag = false;                               \
2605                                                                               \
2606     getVSR(rA(opcode) + 32, &xa, env);                                        \
2607     getVSR(rB(opcode) + 32, &xb, env);                                        \
2608     getVSR(rD(opcode) + 32, &xt, env);                                        \
2609                                                                               \
2610     if (unlikely(float64_is_any_nan(xa.VsrD(0)))) {                           \
2611         if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status)) {          \
2612             vxsnan_flag = true;                                               \
2613         }                                                                     \
2614         xt.VsrD(0) = xa.VsrD(0);                                              \
2615     } else if (unlikely(float64_is_any_nan(xb.VsrD(0)))) {                    \
2616         if (float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) {          \
2617             vxsnan_flag = true;                                               \
2618         }                                                                     \
2619         xt.VsrD(0) = xb.VsrD(0);                                              \
2620     } else if (float64_is_zero(xa.VsrD(0)) && float64_is_zero(xb.VsrD(0))) {  \
2621         if (max) {                                                            \
2622             if (!float64_is_neg(xa.VsrD(0)) || !float64_is_neg(xb.VsrD(0))) { \
2623                 xt.VsrD(0) = 0ULL;                                            \
2624             } else {                                                          \
2625                 xt.VsrD(0) = 0x8000000000000000ULL;                           \
2626             }                                                                 \
2627         } else {                                                              \
2628             if (float64_is_neg(xa.VsrD(0)) || float64_is_neg(xb.VsrD(0))) {   \
2629                 xt.VsrD(0) = 0x8000000000000000ULL;                           \
2630             } else {                                                          \
2631                 xt.VsrD(0) = 0ULL;                                            \
2632             }                                                                 \
2633         }                                                                     \
2634     } else if ((max &&                                                        \
2635                !float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) ||       \
2636                (!max &&                                                       \
2637                float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status))) {        \
2638         xt.VsrD(0) = xa.VsrD(0);                                              \
2639     } else {                                                                  \
2640         xt.VsrD(0) = xb.VsrD(0);                                              \
2641     }                                                                         \
2642                                                                               \
2643     vex_flag = fpscr_ve & vxsnan_flag;                                        \
2644     if (vxsnan_flag) {                                                        \
2645             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);            \
2646     }                                                                         \
2647     if (!vex_flag) {                                                          \
2648         putVSR(rD(opcode) + 32, &xt, env);                                    \
2649     }                                                                         \
2650 }                                                                             \
2651
2652 VSX_MAX_MINJ(xsmaxjdp, 1);
2653 VSX_MAX_MINJ(xsminjdp, 0);
2654
2655 /* VSX_CMP - VSX floating point compare
2656  *   op    - instruction mnemonic
2657  *   nels  - number of elements (1, 2 or 4)
2658  *   tp    - type (float32 or float64)
2659  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
2660  *   cmp   - comparison operation
2661  *   svxvc - set VXVC bit
2662  *   exp   - expected result of comparison
2663  */
2664 #define VSX_CMP(op, nels, tp, fld, cmp, svxvc, exp)                       \
2665 void helper_##op(CPUPPCState *env, uint32_t opcode)                       \
2666 {                                                                         \
2667     ppc_vsr_t xt, xa, xb;                                                 \
2668     int i;                                                                \
2669     int all_true = 1;                                                     \
2670     int all_false = 1;                                                    \
2671                                                                           \
2672     getVSR(xA(opcode), &xa, env);                                         \
2673     getVSR(xB(opcode), &xb, env);                                         \
2674     getVSR(xT(opcode), &xt, env);                                         \
2675                                                                           \
2676     for (i = 0; i < nels; i++) {                                          \
2677         if (unlikely(tp##_is_any_nan(xa.fld) ||                           \
2678                      tp##_is_any_nan(xb.fld))) {                          \
2679             if (tp##_is_signaling_nan(xa.fld, &env->fp_status) ||         \
2680                 tp##_is_signaling_nan(xb.fld, &env->fp_status)) {         \
2681                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);    \
2682             }                                                             \
2683             if (svxvc) {                                                  \
2684                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0);      \
2685             }                                                             \
2686             xt.fld = 0;                                                   \
2687             all_true = 0;                                                 \
2688         } else {                                                          \
2689             if (tp##_##cmp(xb.fld, xa.fld, &env->fp_status) == exp) {     \
2690                 xt.fld = -1;                                              \
2691                 all_false = 0;                                            \
2692             } else {                                                      \
2693                 xt.fld = 0;                                               \
2694                 all_true = 0;                                             \
2695             }                                                             \
2696         }                                                                 \
2697     }                                                                     \
2698                                                                           \
2699     putVSR(xT(opcode), &xt, env);                                         \
2700     if ((opcode >> (31-21)) & 1) {                                        \
2701         env->crf[6] = (all_true ? 0x8 : 0) | (all_false ? 0x2 : 0);       \
2702     }                                                                     \
2703     float_check_status(env);                                              \
2704  }
2705
2706 VSX_CMP(xvcmpeqdp, 2, float64, VsrD(i), eq, 0, 1)
2707 VSX_CMP(xvcmpgedp, 2, float64, VsrD(i), le, 1, 1)
2708 VSX_CMP(xvcmpgtdp, 2, float64, VsrD(i), lt, 1, 1)
2709 VSX_CMP(xvcmpnedp, 2, float64, VsrD(i), eq, 0, 0)
2710 VSX_CMP(xvcmpeqsp, 4, float32, VsrW(i), eq, 0, 1)
2711 VSX_CMP(xvcmpgesp, 4, float32, VsrW(i), le, 1, 1)
2712 VSX_CMP(xvcmpgtsp, 4, float32, VsrW(i), lt, 1, 1)
2713 VSX_CMP(xvcmpnesp, 4, float32, VsrW(i), eq, 0, 0)
2714
2715 /* VSX_CVT_FP_TO_FP - VSX floating point/floating point conversion
2716  *   op    - instruction mnemonic
2717  *   nels  - number of elements (1, 2 or 4)
2718  *   stp   - source type (float32 or float64)
2719  *   ttp   - target type (float32 or float64)
2720  *   sfld  - source vsr_t field
2721  *   tfld  - target vsr_t field (f32 or f64)
2722  *   sfprf - set FPRF
2723  */
2724 #define VSX_CVT_FP_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf)    \
2725 void helper_##op(CPUPPCState *env, uint32_t opcode)                \
2726 {                                                                  \
2727     ppc_vsr_t xt, xb;                                              \
2728     int i;                                                         \
2729                                                                    \
2730     getVSR(xB(opcode), &xb, env);                                  \
2731     getVSR(xT(opcode), &xt, env);                                  \
2732                                                                    \
2733     for (i = 0; i < nels; i++) {                                   \
2734         xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);        \
2735         if (unlikely(stp##_is_signaling_nan(xb.sfld,               \
2736                                             &env->fp_status))) {   \
2737             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2738             xt.tfld = ttp##_snan_to_qnan(xt.tfld);                 \
2739         }                                                          \
2740         if (sfprf) {                                               \
2741             helper_compute_fprf_##ttp(env, xt.tfld);               \
2742         }                                                          \
2743     }                                                              \
2744                                                                    \
2745     putVSR(xT(opcode), &xt, env);                                  \
2746     float_check_status(env);                                       \
2747 }
2748
2749 VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
2750 VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
2751 VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
2752 VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
2753
2754 /* VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
2755  *   op    - instruction mnemonic
2756  *   nels  - number of elements (1, 2 or 4)
2757  *   stp   - source type (float32 or float64)
2758  *   ttp   - target type (float32 or float64)
2759  *   sfld  - source vsr_t field
2760  *   tfld  - target vsr_t field (f32 or f64)
2761  *   sfprf - set FPRF
2762  */
2763 #define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf)    \
2764 void helper_##op(CPUPPCState *env, uint32_t opcode)                       \
2765 {                                                                       \
2766     ppc_vsr_t xt, xb;                                                   \
2767     int i;                                                              \
2768                                                                         \
2769     getVSR(rB(opcode) + 32, &xb, env);                                  \
2770     getVSR(rD(opcode) + 32, &xt, env);                                  \
2771                                                                         \
2772     for (i = 0; i < nels; i++) {                                        \
2773         xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);             \
2774         if (unlikely(stp##_is_signaling_nan(xb.sfld,                    \
2775                                             &env->fp_status))) {        \
2776             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);      \
2777             xt.tfld = ttp##_snan_to_qnan(xt.tfld);                      \
2778         }                                                               \
2779         if (sfprf) {                                                    \
2780             helper_compute_fprf_##ttp(env, xt.tfld);                    \
2781         }                                                               \
2782     }                                                                   \
2783                                                                         \
2784     putVSR(rD(opcode) + 32, &xt, env);                                  \
2785     float_check_status(env);                                            \
2786 }
2787
2788 VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
2789
2790 /* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
2791  *                       involving one half precision value
2792  *   op    - instruction mnemonic
2793  *   nels  - number of elements (1, 2 or 4)
2794  *   stp   - source type
2795  *   ttp   - target type
2796  *   sfld  - source vsr_t field
2797  *   tfld  - target vsr_t field
2798  *   sfprf - set FPRF
2799  */
2800 #define VSX_CVT_FP_TO_FP_HP(op, nels, stp, ttp, sfld, tfld, sfprf) \
2801 void helper_##op(CPUPPCState *env, uint32_t opcode)                \
2802 {                                                                  \
2803     ppc_vsr_t xt, xb;                                              \
2804     int i;                                                         \
2805                                                                    \
2806     getVSR(xB(opcode), &xb, env);                                  \
2807     memset(&xt, 0, sizeof(xt));                                    \
2808                                                                    \
2809     for (i = 0; i < nels; i++) {                                   \
2810         xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status);     \
2811         if (unlikely(stp##_is_signaling_nan(xb.sfld,               \
2812                                             &env->fp_status))) {   \
2813             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
2814             xt.tfld = ttp##_snan_to_qnan(xt.tfld);                 \
2815         }                                                          \
2816         if (sfprf) {                                               \
2817             helper_compute_fprf_##ttp(env, xt.tfld);               \
2818         }                                                          \
2819     }                                                              \
2820                                                                    \
2821     putVSR(xT(opcode), &xt, env);                                  \
2822     float_check_status(env);                                       \
2823 }
2824
2825 VSX_CVT_FP_TO_FP_HP(xscvdphp, 1, float64, float16, VsrD(0), VsrH(3), 1)
2826 VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
2827 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i  + 1), 0)
2828 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
2829
2830 /*
2831  * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
2832  * added to this later.
2833  */
2834 void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode)
2835 {
2836     ppc_vsr_t xt, xb;
2837     float_status tstat;
2838
2839     getVSR(rB(opcode) + 32, &xb, env);
2840     memset(&xt, 0, sizeof(xt));
2841
2842     tstat = env->fp_status;
2843     if (unlikely(Rc(opcode) != 0)) {
2844         tstat.float_rounding_mode = float_round_to_odd;
2845     }
2846
2847     xt.VsrD(0) = float128_to_float64(xb.f128, &tstat);
2848     env->fp_status.float_exception_flags |= tstat.float_exception_flags;
2849     if (unlikely(float128_is_signaling_nan(xb.f128,
2850                                            &tstat))) {
2851         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);
2852         xt.VsrD(0) = float64_snan_to_qnan(xt.VsrD(0));
2853     }
2854     helper_compute_fprf_float64(env, xt.VsrD(0));
2855
2856     putVSR(rD(opcode) + 32, &xt, env);
2857     float_check_status(env);
2858 }
2859
2860 uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
2861 {
2862     float_status tstat = env->fp_status;
2863     set_float_exception_flags(0, &tstat);
2864
2865     return (uint64_t)float64_to_float32(xb, &tstat) << 32;
2866 }
2867
2868 uint64_t helper_xscvspdpn(CPUPPCState *env, uint64_t xb)
2869 {
2870     float_status tstat = env->fp_status;
2871     set_float_exception_flags(0, &tstat);
2872
2873     return float32_to_float64(xb >> 32, &tstat);
2874 }
2875
2876 /* VSX_CVT_FP_TO_INT - VSX floating point to integer conversion
2877  *   op    - instruction mnemonic
2878  *   nels  - number of elements (1, 2 or 4)
2879  *   stp   - source type (float32 or float64)
2880  *   ttp   - target type (int32, uint32, int64 or uint64)
2881  *   sfld  - source vsr_t field
2882  *   tfld  - target vsr_t field
2883  *   rnan  - resulting NaN
2884  */
2885 #define VSX_CVT_FP_TO_INT(op, nels, stp, ttp, sfld, tfld, rnan)              \
2886 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2887 {                                                                            \
2888     ppc_vsr_t xt, xb;                                                        \
2889     int i;                                                                   \
2890                                                                              \
2891     getVSR(xB(opcode), &xb, env);                                            \
2892     getVSR(xT(opcode), &xt, env);                                            \
2893                                                                              \
2894     for (i = 0; i < nels; i++) {                                             \
2895         if (unlikely(stp##_is_any_nan(xb.sfld))) {                           \
2896             if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) {          \
2897                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);       \
2898             }                                                                \
2899             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);            \
2900             xt.tfld = rnan;                                                  \
2901         } else {                                                             \
2902             xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld,                \
2903                           &env->fp_status);                                  \
2904             if (env->fp_status.float_exception_flags & float_flag_invalid) { \
2905                 float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);        \
2906             }                                                                \
2907         }                                                                    \
2908     }                                                                        \
2909                                                                              \
2910     putVSR(xT(opcode), &xt, env);                                            \
2911     float_check_status(env);                                                 \
2912 }
2913
2914 VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
2915                   0x8000000000000000ULL)
2916 VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
2917                   0x80000000U)
2918 VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
2919 VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
2920 VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
2921                   0x8000000000000000ULL)
2922 VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2*i), \
2923                   0x80000000U)
2924 VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
2925 VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2*i), 0U)
2926 VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2*i), VsrD(i), \
2927                   0x8000000000000000ULL)
2928 VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
2929 VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2*i), VsrD(i), 0ULL)
2930 VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
2931
2932 /* VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
2933  *   op    - instruction mnemonic
2934  *   stp   - source type (float32 or float64)
2935  *   ttp   - target type (int32, uint32, int64 or uint64)
2936  *   sfld  - source vsr_t field
2937  *   tfld  - target vsr_t field
2938  *   rnan  - resulting NaN
2939  */
2940 #define VSX_CVT_FP_TO_INT_VECTOR(op, stp, ttp, sfld, tfld, rnan)             \
2941 void helper_##op(CPUPPCState *env, uint32_t opcode)                          \
2942 {                                                                            \
2943     ppc_vsr_t xt, xb;                                                        \
2944                                                                              \
2945     getVSR(rB(opcode) + 32, &xb, env);                                       \
2946     memset(&xt, 0, sizeof(xt));                                              \
2947                                                                              \
2948     if (unlikely(stp##_is_any_nan(xb.sfld))) {                               \
2949         if (stp##_is_signaling_nan(xb.sfld, &env->fp_status)) {              \
2950             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);           \
2951         }                                                                    \
2952         float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);                \
2953         xt.tfld = rnan;                                                      \
2954     } else {                                                                 \
2955         xt.tfld = stp##_to_##ttp##_round_to_zero(xb.sfld,                    \
2956                       &env->fp_status);                                      \
2957         if (env->fp_status.float_exception_flags & float_flag_invalid) {     \
2958             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXCVI, 0);            \
2959         }                                                                    \
2960     }                                                                        \
2961                                                                              \
2962     putVSR(rD(opcode) + 32, &xt, env);                                       \
2963     float_check_status(env);                                                 \
2964 }
2965
2966 VSX_CVT_FP_TO_INT_VECTOR(xscvqpsdz, float128, int64, f128, VsrD(0),          \
2967                   0x8000000000000000ULL)
2968
2969 VSX_CVT_FP_TO_INT_VECTOR(xscvqpswz, float128, int32, f128, VsrD(0),          \
2970                   0xffffffff80000000ULL)
2971 VSX_CVT_FP_TO_INT_VECTOR(xscvqpudz, float128, uint64, f128, VsrD(0), 0x0ULL)
2972 VSX_CVT_FP_TO_INT_VECTOR(xscvqpuwz, float128, uint32, f128, VsrD(0), 0x0ULL)
2973
2974 /* VSX_CVT_INT_TO_FP - VSX integer to floating point conversion
2975  *   op    - instruction mnemonic
2976  *   nels  - number of elements (1, 2 or 4)
2977  *   stp   - source type (int32, uint32, int64 or uint64)
2978  *   ttp   - target type (float32 or float64)
2979  *   sfld  - source vsr_t field
2980  *   tfld  - target vsr_t field
2981  *   jdef  - definition of the j index (i or 2*i)
2982  *   sfprf - set FPRF
2983  */
2984 #define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, sfprf, r2sp)  \
2985 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
2986 {                                                                       \
2987     ppc_vsr_t xt, xb;                                                   \
2988     int i;                                                              \
2989                                                                         \
2990     getVSR(xB(opcode), &xb, env);                                       \
2991     getVSR(xT(opcode), &xt, env);                                       \
2992                                                                         \
2993     for (i = 0; i < nels; i++) {                                        \
2994         xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);             \
2995         if (r2sp) {                                                     \
2996             xt.tfld = helper_frsp(env, xt.tfld);                        \
2997         }                                                               \
2998         if (sfprf) {                                                    \
2999             helper_compute_fprf_float64(env, xt.tfld);                  \
3000         }                                                               \
3001     }                                                                   \
3002                                                                         \
3003     putVSR(xT(opcode), &xt, env);                                       \
3004     float_check_status(env);                                            \
3005 }
3006
3007 VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, VsrD(0), VsrD(0), 1, 0)
3008 VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 0)
3009 VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, VsrD(0), VsrD(0), 1, 1)
3010 VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, VsrD(0), VsrD(0), 1, 1)
3011 VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
3012 VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
3013 VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2*i), VsrD(i), 0, 0)
3014 VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2*i), VsrD(i), 0, 0)
3015 VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2*i), 0, 0)
3016 VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2*i), 0, 0)
3017 VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
3018 VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
3019
3020 /* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
3021  *   op    - instruction mnemonic
3022  *   stp   - source type (int32, uint32, int64 or uint64)
3023  *   ttp   - target type (float32 or float64)
3024  *   sfld  - source vsr_t field
3025  *   tfld  - target vsr_t field
3026  */
3027 #define VSX_CVT_INT_TO_FP_VECTOR(op, stp, ttp, sfld, tfld)              \
3028 void helper_##op(CPUPPCState *env, uint32_t opcode)                     \
3029 {                                                                       \
3030     ppc_vsr_t xt, xb;                                                   \
3031                                                                         \
3032     getVSR(rB(opcode) + 32, &xb, env);                                  \
3033     getVSR(rD(opcode) + 32, &xt, env);                                  \
3034                                                                         \
3035     xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status);                 \
3036     helper_compute_fprf_##ttp(env, xt.tfld);                            \
3037                                                                         \
3038     putVSR(xT(opcode) + 32, &xt, env);                                  \
3039     float_check_status(env);                                            \
3040 }
3041
3042 VSX_CVT_INT_TO_FP_VECTOR(xscvsdqp, int64, float128, VsrD(0), f128)
3043 VSX_CVT_INT_TO_FP_VECTOR(xscvudqp, uint64, float128, VsrD(0), f128)
3044
3045 /* For "use current rounding mode", define a value that will not be one of
3046  * the existing rounding model enums.
3047  */
3048 #define FLOAT_ROUND_CURRENT (float_round_nearest_even + float_round_down + \
3049   float_round_up + float_round_to_zero)
3050
3051 /* VSX_ROUND - VSX floating point round
3052  *   op    - instruction mnemonic
3053  *   nels  - number of elements (1, 2 or 4)
3054  *   tp    - type (float32 or float64)
3055  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
3056  *   rmode - rounding mode
3057  *   sfprf - set FPRF
3058  */
3059 #define VSX_ROUND(op, nels, tp, fld, rmode, sfprf)                     \
3060 void helper_##op(CPUPPCState *env, uint32_t opcode)                    \
3061 {                                                                      \
3062     ppc_vsr_t xt, xb;                                                  \
3063     int i;                                                             \
3064     getVSR(xB(opcode), &xb, env);                                      \
3065     getVSR(xT(opcode), &xt, env);                                      \
3066                                                                        \
3067     if (rmode != FLOAT_ROUND_CURRENT) {                                \
3068         set_float_rounding_mode(rmode, &env->fp_status);               \
3069     }                                                                  \
3070                                                                        \
3071     for (i = 0; i < nels; i++) {                                       \
3072         if (unlikely(tp##_is_signaling_nan(xb.fld,                     \
3073                                            &env->fp_status))) {        \
3074             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);     \
3075             xt.fld = tp##_snan_to_qnan(xb.fld);                        \
3076         } else {                                                       \
3077             xt.fld = tp##_round_to_int(xb.fld, &env->fp_status);       \
3078         }                                                              \
3079         if (sfprf) {                                                   \
3080             helper_compute_fprf_float64(env, xt.fld);                  \
3081         }                                                              \
3082     }                                                                  \
3083                                                                        \
3084     /* If this is not a "use current rounding mode" instruction,       \
3085      * then inhibit setting of the XX bit and restore rounding         \
3086      * mode from FPSCR */                                              \
3087     if (rmode != FLOAT_ROUND_CURRENT) {                                \
3088         fpscr_set_rounding_mode(env);                                  \
3089         env->fp_status.float_exception_flags &= ~float_flag_inexact;   \
3090     }                                                                  \
3091                                                                        \
3092     putVSR(xT(opcode), &xt, env);                                      \
3093     float_check_status(env);                                           \
3094 }
3095
3096 VSX_ROUND(xsrdpi, 1, float64, VsrD(0), float_round_ties_away, 1)
3097 VSX_ROUND(xsrdpic, 1, float64, VsrD(0), FLOAT_ROUND_CURRENT, 1)
3098 VSX_ROUND(xsrdpim, 1, float64, VsrD(0), float_round_down, 1)
3099 VSX_ROUND(xsrdpip, 1, float64, VsrD(0), float_round_up, 1)
3100 VSX_ROUND(xsrdpiz, 1, float64, VsrD(0), float_round_to_zero, 1)
3101
3102 VSX_ROUND(xvrdpi, 2, float64, VsrD(i), float_round_ties_away, 0)
3103 VSX_ROUND(xvrdpic, 2, float64, VsrD(i), FLOAT_ROUND_CURRENT, 0)
3104 VSX_ROUND(xvrdpim, 2, float64, VsrD(i), float_round_down, 0)
3105 VSX_ROUND(xvrdpip, 2, float64, VsrD(i), float_round_up, 0)
3106 VSX_ROUND(xvrdpiz, 2, float64, VsrD(i), float_round_to_zero, 0)
3107
3108 VSX_ROUND(xvrspi, 4, float32, VsrW(i), float_round_ties_away, 0)
3109 VSX_ROUND(xvrspic, 4, float32, VsrW(i), FLOAT_ROUND_CURRENT, 0)
3110 VSX_ROUND(xvrspim, 4, float32, VsrW(i), float_round_down, 0)
3111 VSX_ROUND(xvrspip, 4, float32, VsrW(i), float_round_up, 0)
3112 VSX_ROUND(xvrspiz, 4, float32, VsrW(i), float_round_to_zero, 0)
3113
3114 uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
3115 {
3116     helper_reset_fpstatus(env);
3117
3118     uint64_t xt = helper_frsp(env, xb);
3119
3120     helper_compute_fprf_float64(env, xt);
3121     float_check_status(env);
3122     return xt;
3123 }
3124
3125 #define VSX_XXPERM(op, indexed)                                       \
3126 void helper_##op(CPUPPCState *env, uint32_t opcode)                   \
3127 {                                                                     \
3128     ppc_vsr_t xt, xa, pcv, xto;                                       \
3129     int i, idx;                                                       \
3130                                                                       \
3131     getVSR(xA(opcode), &xa, env);                                     \
3132     getVSR(xT(opcode), &xt, env);                                     \
3133     getVSR(xB(opcode), &pcv, env);                                    \
3134                                                                       \
3135     for (i = 0; i < 16; i++) {                                        \
3136         idx = pcv.VsrB(i) & 0x1F;                                     \
3137         if (indexed) {                                                \
3138             idx = 31 - idx;                                           \
3139         }                                                             \
3140         xto.VsrB(i) = (idx <= 15) ? xa.VsrB(idx) : xt.VsrB(idx - 16); \
3141     }                                                                 \
3142     putVSR(xT(opcode), &xto, env);                                    \
3143 }
3144
3145 VSX_XXPERM(xxperm, 0)
3146 VSX_XXPERM(xxpermr, 1)
3147
3148 void helper_xvxsigsp(CPUPPCState *env, uint32_t opcode)
3149 {
3150     ppc_vsr_t xt, xb;
3151     uint32_t exp, i, fraction;
3152
3153     getVSR(xB(opcode), &xb, env);
3154     memset(&xt, 0, sizeof(xt));
3155
3156     for (i = 0; i < 4; i++) {
3157         exp = (xb.VsrW(i) >> 23) & 0xFF;
3158         fraction = xb.VsrW(i) & 0x7FFFFF;
3159         if (exp != 0 && exp != 255) {
3160             xt.VsrW(i) = fraction | 0x00800000;
3161         } else {
3162             xt.VsrW(i) = fraction;
3163         }
3164     }
3165     putVSR(xT(opcode), &xt, env);
3166 }
3167
3168 /* VSX_TEST_DC - VSX floating point test data class
3169  *   op    - instruction mnemonic
3170  *   nels  - number of elements (1, 2 or 4)
3171  *   xbn   - VSR register number
3172  *   tp    - type (float32 or float64)
3173  *   fld   - vsr_t field (VsrD(*) or VsrW(*))
3174  *   tfld   - target vsr_t field (VsrD(*) or VsrW(*))
3175  *   fld_max - target field max
3176  *   scrf - set result in CR and FPCC
3177  */
3178 #define VSX_TEST_DC(op, nels, xbn, tp, fld, tfld, fld_max, scrf)  \
3179 void helper_##op(CPUPPCState *env, uint32_t opcode)         \
3180 {                                                           \
3181     ppc_vsr_t xt, xb;                                       \
3182     uint32_t i, sign, dcmx;                                 \
3183     uint32_t cc, match = 0;                                 \
3184                                                             \
3185     getVSR(xbn, &xb, env);                                  \
3186     if (!scrf) {                                            \
3187         memset(&xt, 0, sizeof(xt));                         \
3188         dcmx = DCMX_XV(opcode);                             \
3189     } else {                                                \
3190         dcmx = DCMX(opcode);                                \
3191     }                                                       \
3192                                                             \
3193     for (i = 0; i < nels; i++) {                            \
3194         sign = tp##_is_neg(xb.fld);                         \
3195         if (tp##_is_any_nan(xb.fld)) {                      \
3196             match = extract32(dcmx, 6, 1);                  \
3197         } else if (tp##_is_infinity(xb.fld)) {              \
3198             match = extract32(dcmx, 4 + !sign, 1);          \
3199         } else if (tp##_is_zero(xb.fld)) {                  \
3200             match = extract32(dcmx, 2 + !sign, 1);          \
3201         } else if (tp##_is_zero_or_denormal(xb.fld)) {      \
3202             match = extract32(dcmx, 0 + !sign, 1);          \
3203         }                                                   \
3204                                                             \
3205         if (scrf) {                                         \
3206             cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT;  \
3207             env->fpscr &= ~(0x0F << FPSCR_FPRF);            \
3208             env->fpscr |= cc << FPSCR_FPRF;                 \
3209             env->crf[BF(opcode)] = cc;                      \
3210         } else {                                            \
3211             xt.tfld = match ? fld_max : 0;                  \
3212         }                                                   \
3213         match = 0;                                          \
3214     }                                                       \
3215     if (!scrf) {                                            \
3216         putVSR(xT(opcode), &xt, env);                       \
3217     }                                                       \
3218 }
3219
3220 VSX_TEST_DC(xvtstdcdp, 2, xB(opcode), float64, VsrD(i), VsrD(i), UINT64_MAX, 0)
3221 VSX_TEST_DC(xvtstdcsp, 4, xB(opcode), float32, VsrW(i), VsrW(i), UINT32_MAX, 0)
3222 VSX_TEST_DC(xststdcdp, 1, xB(opcode), float64, VsrD(0), VsrD(0), 0, 1)
3223 VSX_TEST_DC(xststdcqp, 1, (rB(opcode) + 32), float128, f128, VsrD(0), 0, 1)
3224
3225 void helper_xststdcsp(CPUPPCState *env, uint32_t opcode)
3226 {
3227     ppc_vsr_t xb;
3228     uint32_t dcmx, sign, exp;
3229     uint32_t cc, match = 0, not_sp = 0;
3230
3231     getVSR(xB(opcode), &xb, env);
3232     dcmx = DCMX(opcode);
3233     exp = (xb.VsrD(0) >> 52) & 0x7FF;
3234
3235     sign = float64_is_neg(xb.VsrD(0));
3236     if (float64_is_any_nan(xb.VsrD(0))) {
3237         match = extract32(dcmx, 6, 1);
3238     } else if (float64_is_infinity(xb.VsrD(0))) {
3239         match = extract32(dcmx, 4 + !sign, 1);
3240     } else if (float64_is_zero(xb.VsrD(0))) {
3241         match = extract32(dcmx, 2 + !sign, 1);
3242     } else if (float64_is_zero_or_denormal(xb.VsrD(0)) ||
3243                (exp > 0 && exp < 0x381)) {
3244         match = extract32(dcmx, 0 + !sign, 1);
3245     }
3246
3247     not_sp = !float64_eq(xb.VsrD(0),
3248                          float32_to_float64(
3249                              float64_to_float32(xb.VsrD(0), &env->fp_status),
3250                              &env->fp_status), &env->fp_status);
3251
3252     cc = sign << CRF_LT_BIT | match << CRF_EQ_BIT | not_sp << CRF_SO_BIT;
3253     env->fpscr &= ~(0x0F << FPSCR_FPRF);
3254     env->fpscr |= cc << FPSCR_FPRF;
3255     env->crf[BF(opcode)] = cc;
3256 }
3257
3258 void helper_xsrqpi(CPUPPCState *env, uint32_t opcode)
3259 {
3260     ppc_vsr_t xb;
3261     ppc_vsr_t xt;
3262     uint8_t r = Rrm(opcode);
3263     uint8_t ex = Rc(opcode);
3264     uint8_t rmc = RMC(opcode);
3265     uint8_t rmode = 0;
3266     float_status tstat;
3267
3268     getVSR(rB(opcode) + 32, &xb, env);
3269     memset(&xt, 0, sizeof(xt));
3270     helper_reset_fpstatus(env);
3271
3272     if (r == 0 && rmc == 0) {
3273         rmode = float_round_ties_away;
3274     } else if (r == 0 && rmc == 0x3) {
3275         rmode = fpscr_rn;
3276     } else if (r == 1) {
3277         switch (rmc) {
3278         case 0:
3279             rmode = float_round_nearest_even;
3280             break;
3281         case 1:
3282             rmode = float_round_to_zero;
3283             break;
3284         case 2:
3285             rmode = float_round_up;
3286             break;
3287         case 3:
3288             rmode = float_round_down;
3289             break;
3290         default:
3291             abort();
3292         }
3293     }
3294
3295     tstat = env->fp_status;
3296     set_float_exception_flags(0, &tstat);
3297     set_float_rounding_mode(rmode, &tstat);
3298     xt.f128 = float128_round_to_int(xb.f128, &tstat);
3299     env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3300
3301     if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3302         if (float128_is_signaling_nan(xb.f128, &tstat)) {
3303             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);
3304             xt.f128 = float128_snan_to_qnan(xt.f128);
3305         }
3306     }
3307
3308     if (ex == 0 && (tstat.float_exception_flags & float_flag_inexact)) {
3309         env->fp_status.float_exception_flags &= ~float_flag_inexact;
3310     }
3311
3312     helper_compute_fprf_float128(env, xt.f128);
3313     float_check_status(env);
3314     putVSR(rD(opcode) + 32, &xt, env);
3315 }
3316
3317 void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode)
3318 {
3319     ppc_vsr_t xb;
3320     ppc_vsr_t xt;
3321     uint8_t r = Rrm(opcode);
3322     uint8_t rmc = RMC(opcode);
3323     uint8_t rmode = 0;
3324     floatx80 round_res;
3325     float_status tstat;
3326
3327     getVSR(rB(opcode) + 32, &xb, env);
3328     memset(&xt, 0, sizeof(xt));
3329     helper_reset_fpstatus(env);
3330
3331     if (r == 0 && rmc == 0) {
3332         rmode = float_round_ties_away;
3333     } else if (r == 0 && rmc == 0x3) {
3334         rmode = fpscr_rn;
3335     } else if (r == 1) {
3336         switch (rmc) {
3337         case 0:
3338             rmode = float_round_nearest_even;
3339             break;
3340         case 1:
3341             rmode = float_round_to_zero;
3342             break;
3343         case 2:
3344             rmode = float_round_up;
3345             break;
3346         case 3:
3347             rmode = float_round_down;
3348             break;
3349         default:
3350             abort();
3351         }
3352     }
3353
3354     tstat = env->fp_status;
3355     set_float_exception_flags(0, &tstat);
3356     set_float_rounding_mode(rmode, &tstat);
3357     round_res = float128_to_floatx80(xb.f128, &tstat);
3358     xt.f128 = floatx80_to_float128(round_res, &tstat);
3359     env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3360
3361     if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3362         if (float128_is_signaling_nan(xb.f128, &tstat)) {
3363             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);
3364             xt.f128 = float128_snan_to_qnan(xt.f128);
3365         }
3366     }
3367
3368     helper_compute_fprf_float128(env, xt.f128);
3369     putVSR(rD(opcode) + 32, &xt, env);
3370     float_check_status(env);
3371 }
3372
3373 void helper_xssqrtqp(CPUPPCState *env, uint32_t opcode)
3374 {
3375     ppc_vsr_t xb;
3376     ppc_vsr_t xt;
3377     float_status tstat;
3378
3379     getVSR(rB(opcode) + 32, &xb, env);
3380     memset(&xt, 0, sizeof(xt));
3381     helper_reset_fpstatus(env);
3382
3383     tstat = env->fp_status;
3384     if (unlikely(Rc(opcode) != 0)) {
3385         tstat.float_rounding_mode = float_round_to_odd;
3386     }
3387
3388     set_float_exception_flags(0, &tstat);
3389     xt.f128 = float128_sqrt(xb.f128, &tstat);
3390     env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3391
3392     if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3393         if (float128_is_signaling_nan(xb.f128, &tstat)) {
3394             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
3395             xt.f128 = float128_snan_to_qnan(xb.f128);
3396         } else if  (float128_is_quiet_nan(xb.f128, &tstat)) {
3397             xt.f128 = xb.f128;
3398         } else if (float128_is_neg(xb.f128) && !float128_is_zero(xb.f128)) {
3399             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1);
3400             set_snan_bit_is_one(0, &env->fp_status);
3401             xt.f128 = float128_default_nan(&env->fp_status);
3402         }
3403     }
3404
3405     helper_compute_fprf_float128(env, xt.f128);
3406     putVSR(rD(opcode) + 32, &xt, env);
3407     float_check_status(env);
3408 }
3409
3410 void helper_xssubqp(CPUPPCState *env, uint32_t opcode)
3411 {
3412     ppc_vsr_t xt, xa, xb;
3413     float_status tstat;
3414
3415     getVSR(rA(opcode) + 32, &xa, env);
3416     getVSR(rB(opcode) + 32, &xb, env);
3417     getVSR(rD(opcode) + 32, &xt, env);
3418     helper_reset_fpstatus(env);
3419
3420     tstat = env->fp_status;
3421     if (unlikely(Rc(opcode) != 0)) {
3422         tstat.float_rounding_mode = float_round_to_odd;
3423     }
3424
3425     set_float_exception_flags(0, &tstat);
3426     xt.f128 = float128_sub(xa.f128, xb.f128, &tstat);
3427     env->fp_status.float_exception_flags |= tstat.float_exception_flags;
3428
3429     if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
3430         if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
3431             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
3432         } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
3433                    float128_is_signaling_nan(xb.f128, &tstat)) {
3434             float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
3435         }
3436     }
3437
3438     helper_compute_fprf_float128(env, xt.f128);
3439     putVSR(rD(opcode) + 32, &xt, env);
3440     float_check_status(env);
3441 }