target-i386/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "hw/pc.h"
   4 #include "hw/isa.h"
   5
   6 #include "cpu.h"
   7 #include "sysemu/kvm.h"
   8
   9 static const VMStateDescription vmstate_segment = {
  10     .name = "segment",
  11     .version_id = 1,
  12     .minimum_version_id = 1,
  13     .minimum_version_id_old = 1,
  14     .fields      = (VMStateField []) {
  15         VMSTATE_UINT32(selector, SegmentCache),
  16         VMSTATE_UINTTL(base, SegmentCache),
  17         VMSTATE_UINT32(limit, SegmentCache),
  18         VMSTATE_UINT32(flags, SegmentCache),
  19         VMSTATE_END_OF_LIST()
  20     }
  21 };
  22
  23 #define VMSTATE_SEGMENT(_field, _state) {                            \
  24     .name       = (stringify(_field)),                               \
  25     .size       = sizeof(SegmentCache),                              \
  26     .vmsd       = &vmstate_segment,                                  \
  27     .flags      = VMS_STRUCT,                                        \
  28     .offset     = offsetof(_state, _field)                           \
  29             + type_check(SegmentCache,typeof_field(_state, _field))  \
  30 }
  31
  32 #define VMSTATE_SEGMENT_ARRAY(_field, _state, _n)                    \
  33     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
  34
  35 static const VMStateDescription vmstate_xmm_reg = {
  36     .name = "xmm_reg",
  37     .version_id = 1,
  38     .minimum_version_id = 1,
  39     .minimum_version_id_old = 1,
  40     .fields      = (VMStateField []) {
  41         VMSTATE_UINT64(XMM_Q(0), XMMReg),
  42         VMSTATE_UINT64(XMM_Q(1), XMMReg),
  43         VMSTATE_END_OF_LIST()
  44     }
  45 };
  46
  47 #define VMSTATE_XMM_REGS(_field, _state, _n)                         \
  48     VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_xmm_reg, XMMReg)
  49
  50 /* YMMH format is the same as XMM */
  51 static const VMStateDescription vmstate_ymmh_reg = {
  52     .name = "ymmh_reg",
  53     .version_id = 1,
  54     .minimum_version_id = 1,
  55     .minimum_version_id_old = 1,
  56     .fields      = (VMStateField []) {
  57         VMSTATE_UINT64(XMM_Q(0), XMMReg),
  58         VMSTATE_UINT64(XMM_Q(1), XMMReg),
  59         VMSTATE_END_OF_LIST()
  60     }
  61 };
  62
  63 #define VMSTATE_YMMH_REGS_VARS(_field, _state, _n, _v)                         \
  64     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_ymmh_reg, XMMReg)
  65
  66 static const VMStateDescription vmstate_mtrr_var = {
  67     .name = "mtrr_var",
  68     .version_id = 1,
  69     .minimum_version_id = 1,
  70     .minimum_version_id_old = 1,
  71     .fields      = (VMStateField []) {
  72         VMSTATE_UINT64(base, MTRRVar),
  73         VMSTATE_UINT64(mask, MTRRVar),
  74         VMSTATE_END_OF_LIST()
  75     }
  76 };
  77
  78 #define VMSTATE_MTRR_VARS(_field, _state, _n, _v)                    \
  79     VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
  80
  81 static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
  82 {
  83     fprintf(stderr, "call put_fpreg() with invalid arguments\n");
  84     exit(0);
  85 }
  86
  87 /* XXX: add that in a FPU generic layer */
  88 union x86_longdouble {
  89     uint64_t mant;
  90     uint16_t exp;
  91 };
  92
  93 #define MANTD1(fp)      (fp & ((1LL << 52) - 1))
  94 #define EXPBIAS1 1023
  95 #define EXPD1(fp)       ((fp >> 52) & 0x7FF)
  96 #define SIGND1(fp)      ((fp >> 32) & 0x80000000)
  97
  98 static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
  99 {
 100     int e;
 101     /* mantissa */
 102     p->mant = (MANTD1(temp) << 11) | (1LL << 63);
 103     /* exponent + sign */
 104     e = EXPD1(temp) - EXPBIAS1 + 16383;
 105     e |= SIGND1(temp) >> 16;
 106     p->exp = e;
 107 }
 108
 109 static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
 110 {
 111     FPReg *fp_reg = opaque;
 112     uint64_t mant;
 113     uint16_t exp;
 114
 115     qemu_get_be64s(f, &mant);
 116     qemu_get_be16s(f, &exp);
 117     fp_reg->d = cpu_set_fp80(mant, exp);
 118     return 0;
 119 }
 120
 121 static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
 122 {
 123     FPReg *fp_reg = opaque;
 124     uint64_t mant;
 125     uint16_t exp;
 126     /* we save the real CPU data (in case of MMX usage only 'mant'
 127        contains the MMX register */
 128     cpu_get_fp80(&mant, &exp, fp_reg->d);
 129     qemu_put_be64s(f, &mant);
 130     qemu_put_be16s(f, &exp);
 131 }
 132
 133 static const VMStateInfo vmstate_fpreg = {
 134     .name = "fpreg",
 135     .get  = get_fpreg,
 136     .put  = put_fpreg,
 137 };
 138
 139 static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
 140 {
 141     union x86_longdouble *p = opaque;
 142     uint64_t mant;
 143
 144     qemu_get_be64s(f, &mant);
 145     p->mant = mant;
 146     p->exp = 0xffff;
 147     return 0;
 148 }
 149
 150 static const VMStateInfo vmstate_fpreg_1_mmx = {
 151     .name = "fpreg_1_mmx",
 152     .get  = get_fpreg_1_mmx,
 153     .put  = put_fpreg_error,
 154 };
 155
 156 static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
 157 {
 158     union x86_longdouble *p = opaque;
 159     uint64_t mant;
 160
 161     qemu_get_be64s(f, &mant);
 162     fp64_to_fp80(p, mant);
 163     return 0;
 164 }
 165
 166 static const VMStateInfo vmstate_fpreg_1_no_mmx = {
 167     .name = "fpreg_1_no_mmx",
 168     .get  = get_fpreg_1_no_mmx,
 169     .put  = put_fpreg_error,
 170 };
 171
 172 static bool fpregs_is_0(void *opaque, int version_id)
 173 {
 174     X86CPU *cpu = opaque;
 175     CPUX86State *env = &cpu->env;
 176
 177     return (env->fpregs_format_vmstate == 0);
 178 }
 179
 180 static bool fpregs_is_1_mmx(void *opaque, int version_id)
 181 {
 182     X86CPU *cpu = opaque;
 183     CPUX86State *env = &cpu->env;
 184     int guess_mmx;
 185
 186     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 187                  (env->fpus_vmstate & 0x3800) == 0);
 188     return (guess_mmx && (env->fpregs_format_vmstate == 1));
 189 }
 190
 191 static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
 192 {
 193     X86CPU *cpu = opaque;
 194     CPUX86State *env = &cpu->env;
 195     int guess_mmx;
 196
 197     guess_mmx = ((env->fptag_vmstate == 0xff) &&
 198                  (env->fpus_vmstate & 0x3800) == 0);
 199     return (!guess_mmx && (env->fpregs_format_vmstate == 1));
 200 }
 201
 202 #define VMSTATE_FP_REGS(_field, _state, _n)                               \
 203     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
 204     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
 205     VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
 206
 207 static bool version_is_5(void *opaque, int version_id)
 208 {
 209     return version_id == 5;
 210 }
 211
 212 #ifdef TARGET_X86_64
 213 static bool less_than_7(void *opaque, int version_id)
 214 {
 215     return version_id < 7;
 216 }
 217
 218 static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 219 {
 220     uint64_t *v = pv;
 221     *v = qemu_get_be32(f);
 222     return 0;
 223 }
 224
 225 static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
 226 {
 227     uint64_t *v = pv;
 228     qemu_put_be32(f, *v);
 229 }
 230
 231 static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
 232     .name = "uint64_as_uint32",
 233     .get  = get_uint64_as_uint32,
 234     .put  = put_uint64_as_uint32,
 235 };
 236
 237 #define VMSTATE_HACK_UINT32(_f, _s, _t)                                  \
 238     VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
 239 #endif
 240
 241 static void cpu_pre_save(void *opaque)
 242 {
 243     X86CPU *cpu = opaque;
 244     CPUX86State *env = &cpu->env;
 245     int i;
 246
 247     /* FPU */
 248     env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
 249     env->fptag_vmstate = 0;
 250     for(i = 0; i < 8; i++) {
 251         env->fptag_vmstate |= ((!env->fptags[i]) << i);
 252     }
 253
 254     env->fpregs_format_vmstate = 0;
 255 }
 256
 257 static int cpu_post_load(void *opaque, int version_id)
 258 {
 259     X86CPU *cpu = opaque;
 260     CPUX86State *env = &cpu->env;
 261     int i;
 262
 263     /* XXX: restore FPU round state */
 264     env->fpstt = (env->fpus_vmstate >> 11) & 7;
 265     env->fpus = env->fpus_vmstate & ~0x3800;
 266     env->fptag_vmstate ^= 0xff;
 267     for(i = 0; i < 8; i++) {
 268         env->fptags[i] = (env->fptag_vmstate >> i) & 1;
 269     }
 270
 271     cpu_breakpoint_remove_all(env, BP_CPU);
 272     cpu_watchpoint_remove_all(env, BP_CPU);
 273     for (i = 0; i < DR7_MAX_BP; i++) {
 274         hw_breakpoint_insert(env, i);
 275     }
 276     tlb_flush(env, 1);
 277
 278     return 0;
 279 }
 280
 281 static bool async_pf_msr_needed(void *opaque)
 282 {
 283     X86CPU *cpu = opaque;
 284
 285     return cpu->env.async_pf_en_msr != 0;
 286 }
 287
 288 static bool pv_eoi_msr_needed(void *opaque)
 289 {
 290     X86CPU *cpu = opaque;
 291
 292     return cpu->env.pv_eoi_en_msr != 0;
 293 }
 294
 295 static const VMStateDescription vmstate_async_pf_msr = {
 296     .name = "cpu/async_pf_msr",
 297     .version_id = 1,
 298     .minimum_version_id = 1,
 299     .minimum_version_id_old = 1,
 300     .fields      = (VMStateField []) {
 301         VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
 302         VMSTATE_END_OF_LIST()
 303     }
 304 };
 305
 306 static const VMStateDescription vmstate_pv_eoi_msr = {
 307     .name = "cpu/async_pv_eoi_msr",
 308     .version_id = 1,
 309     .minimum_version_id = 1,
 310     .minimum_version_id_old = 1,
 311     .fields      = (VMStateField []) {
 312         VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
 313         VMSTATE_END_OF_LIST()
 314     }
 315 };
 316
 317 static bool fpop_ip_dp_needed(void *opaque)
 318 {
 319     X86CPU *cpu = opaque;
 320     CPUX86State *env = &cpu->env;
 321
 322     return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
 323 }
 324
 325 static const VMStateDescription vmstate_fpop_ip_dp = {
 326     .name = "cpu/fpop_ip_dp",
 327     .version_id = 1,
 328     .minimum_version_id = 1,
 329     .minimum_version_id_old = 1,
 330     .fields      = (VMStateField []) {
 331         VMSTATE_UINT16(env.fpop, X86CPU),
 332         VMSTATE_UINT64(env.fpip, X86CPU),
 333         VMSTATE_UINT64(env.fpdp, X86CPU),
 334         VMSTATE_END_OF_LIST()
 335     }
 336 };
 337
 338 static bool tsc_adjust_needed(void *opaque)
 339 {
 340     X86CPU *cpu = opaque;
 341     CPUX86State *env = &cpu->env;
 342
 343     return env->tsc_adjust != 0;
 344 }
 345
 346 static const VMStateDescription vmstate_msr_tsc_adjust = {
 347     .name = "cpu/msr_tsc_adjust",
 348     .version_id = 1,
 349     .minimum_version_id = 1,
 350     .minimum_version_id_old = 1,
 351     .fields      = (VMStateField[]) {
 352         VMSTATE_UINT64(env.tsc_adjust, X86CPU),
 353         VMSTATE_END_OF_LIST()
 354     }
 355 };
 356
 357 static bool tscdeadline_needed(void *opaque)
 358 {
 359     X86CPU *cpu = opaque;
 360     CPUX86State *env = &cpu->env;
 361
 362     return env->tsc_deadline != 0;
 363 }
 364
 365 static const VMStateDescription vmstate_msr_tscdeadline = {
 366     .name = "cpu/msr_tscdeadline",
 367     .version_id = 1,
 368     .minimum_version_id = 1,
 369     .minimum_version_id_old = 1,
 370     .fields      = (VMStateField []) {
 371         VMSTATE_UINT64(env.tsc_deadline, X86CPU),
 372         VMSTATE_END_OF_LIST()
 373     }
 374 };
 375
 376 static bool misc_enable_needed(void *opaque)
 377 {
 378     X86CPU *cpu = opaque;
 379     CPUX86State *env = &cpu->env;
 380
 381     return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
 382 }
 383
 384 static const VMStateDescription vmstate_msr_ia32_misc_enable = {
 385     .name = "cpu/msr_ia32_misc_enable",
 386     .version_id = 1,
 387     .minimum_version_id = 1,
 388     .minimum_version_id_old = 1,
 389     .fields      = (VMStateField []) {
 390         VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
 391         VMSTATE_END_OF_LIST()
 392     }
 393 };
 394
 395 const VMStateDescription vmstate_x86_cpu = {
 396     .name = "cpu",
 397     .version_id = 12,
 398     .minimum_version_id = 3,
 399     .minimum_version_id_old = 3,
 400     .pre_save = cpu_pre_save,
 401     .post_load = cpu_post_load,
 402     .fields      = (VMStateField []) {
 403         VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
 404         VMSTATE_UINTTL(env.eip, X86CPU),
 405         VMSTATE_UINTTL(env.eflags, X86CPU),
 406         VMSTATE_UINT32(env.hflags, X86CPU),
 407         /* FPU */
 408         VMSTATE_UINT16(env.fpuc, X86CPU),
 409         VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
 410         VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
 411         VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
 412         VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
 413
 414         VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
 415         VMSTATE_SEGMENT(env.ldt, X86CPU),
 416         VMSTATE_SEGMENT(env.tr, X86CPU),
 417         VMSTATE_SEGMENT(env.gdt, X86CPU),
 418         VMSTATE_SEGMENT(env.idt, X86CPU),
 419
 420         VMSTATE_UINT32(env.sysenter_cs, X86CPU),
 421 #ifdef TARGET_X86_64
 422         /* Hack: In v7 size changed from 32 to 64 bits on x86_64 */
 423         VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
 424         VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
 425         VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
 426         VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
 427 #else
 428         VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
 429         VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
 430 #endif
 431
 432         VMSTATE_UINTTL(env.cr[0], X86CPU),
 433         VMSTATE_UINTTL(env.cr[2], X86CPU),
 434         VMSTATE_UINTTL(env.cr[3], X86CPU),
 435         VMSTATE_UINTTL(env.cr[4], X86CPU),
 436         VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
 437         /* MMU */
 438         VMSTATE_INT32(env.a20_mask, X86CPU),
 439         /* XMM */
 440         VMSTATE_UINT32(env.mxcsr, X86CPU),
 441         VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, CPU_NB_REGS),
 442
 443 #ifdef TARGET_X86_64
 444         VMSTATE_UINT64(env.efer, X86CPU),
 445         VMSTATE_UINT64(env.star, X86CPU),
 446         VMSTATE_UINT64(env.lstar, X86CPU),
 447         VMSTATE_UINT64(env.cstar, X86CPU),
 448         VMSTATE_UINT64(env.fmask, X86CPU),
 449         VMSTATE_UINT64(env.kernelgsbase, X86CPU),
 450 #endif
 451         VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
 452
 453         VMSTATE_UINT64_V(env.pat, X86CPU, 5),
 454         VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
 455
 456         VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5),
 457         VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
 458         VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
 459         VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
 460         VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
 461         VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
 462         VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
 463         VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
 464         VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
 465         VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
 466         VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
 467         /* MTRRs */
 468         VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
 469         VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
 470         VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, 8, 8),
 471         /* KVM-related states */
 472         VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
 473         VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
 474         VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
 475         VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
 476         VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
 477         VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
 478         VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
 479         VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
 480         VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
 481         /* MCE */
 482         VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
 483         VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
 484         VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
 485         VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
 486         /* rdtscp */
 487         VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
 488         /* KVM pvclock msr */
 489         VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
 490         VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
 491         /* XSAVE related fields */
 492         VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
 493         VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
 494         VMSTATE_YMMH_REGS_VARS(env.ymmh_regs, X86CPU, CPU_NB_REGS, 12),
 495         VMSTATE_END_OF_LIST()
 496         /* The above list is not sorted /wrt version numbers, watch out! */
 497     },
 498     .subsections = (VMStateSubsection []) {
 499         {
 500             .vmsd = &vmstate_async_pf_msr,
 501             .needed = async_pf_msr_needed,
 502         } , {
 503             .vmsd = &vmstate_pv_eoi_msr,
 504             .needed = pv_eoi_msr_needed,
 505         } , {
 506             .vmsd = &vmstate_fpop_ip_dp,
 507             .needed = fpop_ip_dp_needed,
 508         }, {
 509             .vmsd = &vmstate_msr_tsc_adjust,
 510             .needed = tsc_adjust_needed,
 511         }, {
 512             .vmsd = &vmstate_msr_tscdeadline,
 513             .needed = tscdeadline_needed,
 514         }, {
 515             .vmsd = &vmstate_msr_ia32_misc_enable,
 516             .needed = misc_enable_needed,
 517         } , {
 518             /* empty */
 519         }
 520     }
 521 };