target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu-qom.h"
  22 #include "qemu-common.h"
  23 #if !defined(CONFIG_USER_ONLY)
  24 #include "hw/loader.h"
  25 #endif
  26
  27 /* CPUClass::reset() */
  28 static void arm_cpu_reset(CPUState *s)
  29 {
  30     ARMCPU *cpu = ARM_CPU(s);
  31     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  32     CPUARMState *env = &cpu->env;
  33     uint32_t tmp = 0;
  34
  35     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
  36         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
  37         log_cpu_state(env, 0);
  38     }
  39
  40     acc->parent_reset(s);
  41
  42     tmp = env->cp15.c15_config_base_address;
  43     memset(env, 0, offsetof(CPUARMState, breakpoints));
  44     env->cp15.c15_config_base_address = tmp;
  45     env->cp15.c0_cpuid = cpu->midr;
  46     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  47     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  48     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  49     env->cp15.c0_cachetype = cpu->ctr;
  50     env->cp15.c1_sys = cpu->reset_sctlr;
  51     env->cp15.c0_c1[0] = cpu->id_pfr0;
  52     env->cp15.c0_c1[1] = cpu->id_pfr1;
  53     env->cp15.c0_c1[2] = cpu->id_dfr0;
  54     env->cp15.c0_c1[3] = cpu->id_afr0;
  55     env->cp15.c0_c1[4] = cpu->id_mmfr0;
  56     env->cp15.c0_c1[5] = cpu->id_mmfr1;
  57     env->cp15.c0_c1[6] = cpu->id_mmfr2;
  58     env->cp15.c0_c1[7] = cpu->id_mmfr3;
  59     env->cp15.c0_c2[0] = cpu->id_isar0;
  60     env->cp15.c0_c2[1] = cpu->id_isar1;
  61     env->cp15.c0_c2[2] = cpu->id_isar2;
  62     env->cp15.c0_c2[3] = cpu->id_isar3;
  63     env->cp15.c0_c2[4] = cpu->id_isar4;
  64     env->cp15.c0_c2[5] = cpu->id_isar5;
  65     env->cp15.c15_i_min = 0xff0;
  66     env->cp15.c0_clid = cpu->clidr;
  67     memcpy(env->cp15.c0_ccsid, cpu->ccsidr, ARRAY_SIZE(cpu->ccsidr));
  68
  69     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  70         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
  71     }
  72
  73 #if defined(CONFIG_USER_ONLY)
  74     env->uncached_cpsr = ARM_CPU_MODE_USR;
  75     /* For user mode we must enable access to coprocessors */
  76     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
  77     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  78         env->cp15.c15_cpar = 3;
  79     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
  80         env->cp15.c15_cpar = 1;
  81     }
  82 #else
  83     /* SVC mode with interrupts disabled.  */
  84     env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
  85     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
  86        clear at reset.  Initial SP and PC are loaded from ROM.  */
  87     if (IS_M(env)) {
  88         uint32_t pc;
  89         uint8_t *rom;
  90         env->uncached_cpsr &= ~CPSR_I;
  91         rom = rom_ptr(0);
  92         if (rom) {
  93             /* We should really use ldl_phys here, in case the guest
  94                modified flash and reset itself.  However images
  95                loaded via -kernel have not been copied yet, so load the
  96                values directly from there.  */
  97             env->regs[13] = ldl_p(rom);
  98             pc = ldl_p(rom + 4);
  99             env->thumb = pc & 1;
 100             env->regs[15] = pc & ~1;
 101         }
 102     }
 103     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 104     env->cp15.c2_base_mask = 0xffffc000u;
 105     /* v7 performance monitor control register: same implementor
 106      * field as main ID register, and we implement no event counters.
 107      */
 108     env->cp15.c9_pmcr = (cpu->midr & 0xff000000);
 109 #endif
 110     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 111     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 112     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 113     set_float_detect_tininess(float_tininess_before_rounding,
 114                               &env->vfp.fp_status);
 115     set_float_detect_tininess(float_tininess_before_rounding,
 116                               &env->vfp.standard_fp_status);
 117     tlb_flush(env, 1);
 118     /* Reset is a state change for some CPUARMState fields which we
 119      * bake assumptions about into translated code, so we need to
 120      * tb_flush().
 121      */
 122     tb_flush(env);
 123 }
 124
 125 static inline void set_feature(CPUARMState *env, int feature)
 126 {
 127     env->features |= 1u << feature;
 128 }
 129
 130 static void arm_cpu_initfn(Object *obj)
 131 {
 132     ARMCPU *cpu = ARM_CPU(obj);
 133
 134     cpu_exec_init(&cpu->env);
 135 }
 136
 137 void arm_cpu_realize(ARMCPU *cpu)
 138 {
 139     /* This function is called by cpu_arm_init() because it
 140      * needs to do common actions based on feature bits, etc
 141      * that have been set by the subclass init functions.
 142      * When we have QOM realize support it should become
 143      * a true realize function instead.
 144      */
 145     CPUARMState *env = &cpu->env;
 146     /* Some features automatically imply others: */
 147     if (arm_feature(env, ARM_FEATURE_V7)) {
 148         set_feature(env, ARM_FEATURE_VAPA);
 149         set_feature(env, ARM_FEATURE_THUMB2);
 150         if (!arm_feature(env, ARM_FEATURE_M)) {
 151             set_feature(env, ARM_FEATURE_V6K);
 152         } else {
 153             set_feature(env, ARM_FEATURE_V6);
 154         }
 155     }
 156     if (arm_feature(env, ARM_FEATURE_V6K)) {
 157         set_feature(env, ARM_FEATURE_V6);
 158         set_feature(env, ARM_FEATURE_MVFR);
 159     }
 160     if (arm_feature(env, ARM_FEATURE_V6)) {
 161         set_feature(env, ARM_FEATURE_V5);
 162         if (!arm_feature(env, ARM_FEATURE_M)) {
 163             set_feature(env, ARM_FEATURE_AUXCR);
 164         }
 165     }
 166     if (arm_feature(env, ARM_FEATURE_V5)) {
 167         set_feature(env, ARM_FEATURE_V4T);
 168     }
 169     if (arm_feature(env, ARM_FEATURE_M)) {
 170         set_feature(env, ARM_FEATURE_THUMB_DIV);
 171     }
 172     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 173         set_feature(env, ARM_FEATURE_THUMB_DIV);
 174     }
 175     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 176         set_feature(env, ARM_FEATURE_VFP3);
 177     }
 178     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 179         set_feature(env, ARM_FEATURE_VFP);
 180     }
 181 }
 182
 183 /* CPU models */
 184
 185 static void arm926_initfn(Object *obj)
 186 {
 187     ARMCPU *cpu = ARM_CPU(obj);
 188     set_feature(&cpu->env, ARM_FEATURE_V5);
 189     set_feature(&cpu->env, ARM_FEATURE_VFP);
 190     cpu->midr = ARM_CPUID_ARM926;
 191     cpu->reset_fpsid = 0x41011090;
 192     cpu->ctr = 0x1dd20d2;
 193     cpu->reset_sctlr = 0x00090078;
 194 }
 195
 196 static void arm946_initfn(Object *obj)
 197 {
 198     ARMCPU *cpu = ARM_CPU(obj);
 199     set_feature(&cpu->env, ARM_FEATURE_V5);
 200     set_feature(&cpu->env, ARM_FEATURE_MPU);
 201     cpu->midr = ARM_CPUID_ARM946;
 202     cpu->ctr = 0x0f004006;
 203     cpu->reset_sctlr = 0x00000078;
 204 }
 205
 206 static void arm1026_initfn(Object *obj)
 207 {
 208     ARMCPU *cpu = ARM_CPU(obj);
 209     set_feature(&cpu->env, ARM_FEATURE_V5);
 210     set_feature(&cpu->env, ARM_FEATURE_VFP);
 211     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 212     cpu->midr = ARM_CPUID_ARM1026;
 213     cpu->reset_fpsid = 0x410110a0;
 214     cpu->ctr = 0x1dd20d2;
 215     cpu->reset_sctlr = 0x00090078;
 216 }
 217
 218 static void arm1136_r2_initfn(Object *obj)
 219 {
 220     ARMCPU *cpu = ARM_CPU(obj);
 221     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 222      * older core than plain "arm1136". In particular this does not
 223      * have the v6K features.
 224      * These ID register values are correct for 1136 but may be wrong
 225      * for 1136_r2 (in particular r0p2 does not actually implement most
 226      * of the ID registers).
 227      */
 228     set_feature(&cpu->env, ARM_FEATURE_V6);
 229     set_feature(&cpu->env, ARM_FEATURE_VFP);
 230     cpu->midr = ARM_CPUID_ARM1136_R2;
 231     cpu->reset_fpsid = 0x410120b4;
 232     cpu->mvfr0 = 0x11111111;
 233     cpu->mvfr1 = 0x00000000;
 234     cpu->ctr = 0x1dd20d2;
 235     cpu->reset_sctlr = 0x00050078;
 236     cpu->id_pfr0 = 0x111;
 237     cpu->id_pfr1 = 0x1;
 238     cpu->id_dfr0 = 0x2;
 239     cpu->id_afr0 = 0x3;
 240     cpu->id_mmfr0 = 0x01130003;
 241     cpu->id_mmfr1 = 0x10030302;
 242     cpu->id_mmfr2 = 0x01222110;
 243     cpu->id_isar0 = 0x00140011;
 244     cpu->id_isar1 = 0x12002111;
 245     cpu->id_isar2 = 0x11231111;
 246     cpu->id_isar3 = 0x01102131;
 247     cpu->id_isar4 = 0x141;
 248 }
 249
 250 static void arm1136_initfn(Object *obj)
 251 {
 252     ARMCPU *cpu = ARM_CPU(obj);
 253     set_feature(&cpu->env, ARM_FEATURE_V6K);
 254     set_feature(&cpu->env, ARM_FEATURE_V6);
 255     set_feature(&cpu->env, ARM_FEATURE_VFP);
 256     cpu->midr = ARM_CPUID_ARM1136;
 257     cpu->reset_fpsid = 0x410120b4;
 258     cpu->mvfr0 = 0x11111111;
 259     cpu->mvfr1 = 0x00000000;
 260     cpu->ctr = 0x1dd20d2;
 261     cpu->reset_sctlr = 0x00050078;
 262     cpu->id_pfr0 = 0x111;
 263     cpu->id_pfr1 = 0x1;
 264     cpu->id_dfr0 = 0x2;
 265     cpu->id_afr0 = 0x3;
 266     cpu->id_mmfr0 = 0x01130003;
 267     cpu->id_mmfr1 = 0x10030302;
 268     cpu->id_mmfr2 = 0x01222110;
 269     cpu->id_isar0 = 0x00140011;
 270     cpu->id_isar1 = 0x12002111;
 271     cpu->id_isar2 = 0x11231111;
 272     cpu->id_isar3 = 0x01102131;
 273     cpu->id_isar4 = 0x141;
 274 }
 275
 276 static void arm1176_initfn(Object *obj)
 277 {
 278     ARMCPU *cpu = ARM_CPU(obj);
 279     set_feature(&cpu->env, ARM_FEATURE_V6K);
 280     set_feature(&cpu->env, ARM_FEATURE_VFP);
 281     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 282     cpu->midr = ARM_CPUID_ARM1176;
 283     cpu->reset_fpsid = 0x410120b5;
 284     cpu->mvfr0 = 0x11111111;
 285     cpu->mvfr1 = 0x00000000;
 286     cpu->ctr = 0x1dd20d2;
 287     cpu->reset_sctlr = 0x00050078;
 288     cpu->id_pfr0 = 0x111;
 289     cpu->id_pfr1 = 0x11;
 290     cpu->id_dfr0 = 0x33;
 291     cpu->id_afr0 = 0;
 292     cpu->id_mmfr0 = 0x01130003;
 293     cpu->id_mmfr1 = 0x10030302;
 294     cpu->id_mmfr2 = 0x01222100;
 295     cpu->id_isar0 = 0x0140011;
 296     cpu->id_isar1 = 0x12002111;
 297     cpu->id_isar2 = 0x11231121;
 298     cpu->id_isar3 = 0x01102131;
 299     cpu->id_isar4 = 0x01141;
 300 }
 301
 302 static void arm11mpcore_initfn(Object *obj)
 303 {
 304     ARMCPU *cpu = ARM_CPU(obj);
 305     set_feature(&cpu->env, ARM_FEATURE_V6K);
 306     set_feature(&cpu->env, ARM_FEATURE_VFP);
 307     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 308     cpu->midr = ARM_CPUID_ARM11MPCORE;
 309     cpu->reset_fpsid = 0x410120b4;
 310     cpu->mvfr0 = 0x11111111;
 311     cpu->mvfr1 = 0x00000000;
 312     cpu->ctr = 0x1dd20d2;
 313     cpu->id_pfr0 = 0x111;
 314     cpu->id_pfr1 = 0x1;
 315     cpu->id_dfr0 = 0;
 316     cpu->id_afr0 = 0x2;
 317     cpu->id_mmfr0 = 0x01100103;
 318     cpu->id_mmfr1 = 0x10020302;
 319     cpu->id_mmfr2 = 0x01222000;
 320     cpu->id_isar0 = 0x00100011;
 321     cpu->id_isar1 = 0x12002111;
 322     cpu->id_isar2 = 0x11221011;
 323     cpu->id_isar3 = 0x01102131;
 324     cpu->id_isar4 = 0x141;
 325 }
 326
 327 static void cortex_m3_initfn(Object *obj)
 328 {
 329     ARMCPU *cpu = ARM_CPU(obj);
 330     set_feature(&cpu->env, ARM_FEATURE_V7);
 331     set_feature(&cpu->env, ARM_FEATURE_M);
 332     cpu->midr = ARM_CPUID_CORTEXM3;
 333 }
 334
 335 static void cortex_a8_initfn(Object *obj)
 336 {
 337     ARMCPU *cpu = ARM_CPU(obj);
 338     set_feature(&cpu->env, ARM_FEATURE_V7);
 339     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 340     set_feature(&cpu->env, ARM_FEATURE_NEON);
 341     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 342     cpu->midr = ARM_CPUID_CORTEXA8;
 343     cpu->reset_fpsid = 0x410330c0;
 344     cpu->mvfr0 = 0x11110222;
 345     cpu->mvfr1 = 0x00011100;
 346     cpu->ctr = 0x82048004;
 347     cpu->reset_sctlr = 0x00c50078;
 348     cpu->id_pfr0 = 0x1031;
 349     cpu->id_pfr1 = 0x11;
 350     cpu->id_dfr0 = 0x400;
 351     cpu->id_afr0 = 0;
 352     cpu->id_mmfr0 = 0x31100003;
 353     cpu->id_mmfr1 = 0x20000000;
 354     cpu->id_mmfr2 = 0x01202000;
 355     cpu->id_mmfr3 = 0x11;
 356     cpu->id_isar0 = 0x00101111;
 357     cpu->id_isar1 = 0x12112111;
 358     cpu->id_isar2 = 0x21232031;
 359     cpu->id_isar3 = 0x11112131;
 360     cpu->id_isar4 = 0x00111142;
 361     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 362     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 363     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 364     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 365 }
 366
 367 static void cortex_a9_initfn(Object *obj)
 368 {
 369     ARMCPU *cpu = ARM_CPU(obj);
 370     set_feature(&cpu->env, ARM_FEATURE_V7);
 371     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 372     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 373     set_feature(&cpu->env, ARM_FEATURE_NEON);
 374     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 375     /* Note that A9 supports the MP extensions even for
 376      * A9UP and single-core A9MP (which are both different
 377      * and valid configurations; we don't model A9UP).
 378      */
 379     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 380     cpu->midr = ARM_CPUID_CORTEXA9;
 381     cpu->reset_fpsid = 0x41033090;
 382     cpu->mvfr0 = 0x11110222;
 383     cpu->mvfr1 = 0x01111111;
 384     cpu->ctr = 0x80038003;
 385     cpu->reset_sctlr = 0x00c50078;
 386     cpu->id_pfr0 = 0x1031;
 387     cpu->id_pfr1 = 0x11;
 388     cpu->id_dfr0 = 0x000;
 389     cpu->id_afr0 = 0;
 390     cpu->id_mmfr0 = 0x00100103;
 391     cpu->id_mmfr1 = 0x20000000;
 392     cpu->id_mmfr2 = 0x01230000;
 393     cpu->id_mmfr3 = 0x00002111;
 394     cpu->id_isar0 = 0x00101111;
 395     cpu->id_isar1 = 0x13112111;
 396     cpu->id_isar2 = 0x21232041;
 397     cpu->id_isar3 = 0x11112131;
 398     cpu->id_isar4 = 0x00111142;
 399     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 400     cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
 401     cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
 402 }
 403
 404 static void cortex_a15_initfn(Object *obj)
 405 {
 406     ARMCPU *cpu = ARM_CPU(obj);
 407     set_feature(&cpu->env, ARM_FEATURE_V7);
 408     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 409     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 410     set_feature(&cpu->env, ARM_FEATURE_NEON);
 411     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 412     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 413     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 414     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 415     cpu->midr = ARM_CPUID_CORTEXA15;
 416     cpu->reset_fpsid = 0x410430f0;
 417     cpu->mvfr0 = 0x10110222;
 418     cpu->mvfr1 = 0x11111111;
 419     cpu->ctr = 0x8444c004;
 420     cpu->reset_sctlr = 0x00c50078;
 421     cpu->id_pfr0 = 0x00001131;
 422     cpu->id_pfr1 = 0x00011011;
 423     cpu->id_dfr0 = 0x02010555;
 424     cpu->id_afr0 = 0x00000000;
 425     cpu->id_mmfr0 = 0x10201105;
 426     cpu->id_mmfr1 = 0x20000000;
 427     cpu->id_mmfr2 = 0x01240000;
 428     cpu->id_mmfr3 = 0x02102211;
 429     cpu->id_isar0 = 0x02101110;
 430     cpu->id_isar1 = 0x13112111;
 431     cpu->id_isar2 = 0x21232041;
 432     cpu->id_isar3 = 0x11112131;
 433     cpu->id_isar4 = 0x10011142;
 434     cpu->clidr = 0x0a200023;
 435     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 436     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 437     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 438 }
 439
 440 static void ti925t_initfn(Object *obj)
 441 {
 442     ARMCPU *cpu = ARM_CPU(obj);
 443     set_feature(&cpu->env, ARM_FEATURE_V4T);
 444     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 445     cpu->midr = ARM_CPUID_TI925T;
 446     cpu->ctr = 0x5109149;
 447     cpu->reset_sctlr = 0x00000070;
 448 }
 449
 450 static void sa1100_initfn(Object *obj)
 451 {
 452     ARMCPU *cpu = ARM_CPU(obj);
 453     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 454     cpu->midr = ARM_CPUID_SA1100;
 455     cpu->reset_sctlr = 0x00000070;
 456 }
 457
 458 static void sa1110_initfn(Object *obj)
 459 {
 460     ARMCPU *cpu = ARM_CPU(obj);
 461     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 462     cpu->midr = ARM_CPUID_SA1110;
 463     cpu->reset_sctlr = 0x00000070;
 464 }
 465
 466 static void pxa250_initfn(Object *obj)
 467 {
 468     ARMCPU *cpu = ARM_CPU(obj);
 469     set_feature(&cpu->env, ARM_FEATURE_V5);
 470     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 471     cpu->midr = ARM_CPUID_PXA250;
 472     cpu->ctr = 0xd172172;
 473     cpu->reset_sctlr = 0x00000078;
 474 }
 475
 476 static void pxa255_initfn(Object *obj)
 477 {
 478     ARMCPU *cpu = ARM_CPU(obj);
 479     set_feature(&cpu->env, ARM_FEATURE_V5);
 480     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 481     cpu->midr = ARM_CPUID_PXA255;
 482     cpu->ctr = 0xd172172;
 483     cpu->reset_sctlr = 0x00000078;
 484 }
 485
 486 static void pxa260_initfn(Object *obj)
 487 {
 488     ARMCPU *cpu = ARM_CPU(obj);
 489     set_feature(&cpu->env, ARM_FEATURE_V5);
 490     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 491     cpu->midr = ARM_CPUID_PXA260;
 492     cpu->ctr = 0xd172172;
 493     cpu->reset_sctlr = 0x00000078;
 494 }
 495
 496 static void pxa261_initfn(Object *obj)
 497 {
 498     ARMCPU *cpu = ARM_CPU(obj);
 499     set_feature(&cpu->env, ARM_FEATURE_V5);
 500     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 501     cpu->midr = ARM_CPUID_PXA261;
 502     cpu->ctr = 0xd172172;
 503     cpu->reset_sctlr = 0x00000078;
 504 }
 505
 506 static void pxa262_initfn(Object *obj)
 507 {
 508     ARMCPU *cpu = ARM_CPU(obj);
 509     set_feature(&cpu->env, ARM_FEATURE_V5);
 510     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 511     cpu->midr = ARM_CPUID_PXA262;
 512     cpu->ctr = 0xd172172;
 513     cpu->reset_sctlr = 0x00000078;
 514 }
 515
 516 static void pxa270a0_initfn(Object *obj)
 517 {
 518     ARMCPU *cpu = ARM_CPU(obj);
 519     set_feature(&cpu->env, ARM_FEATURE_V5);
 520     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 521     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 522     cpu->midr = ARM_CPUID_PXA270_A0;
 523     cpu->ctr = 0xd172172;
 524     cpu->reset_sctlr = 0x00000078;
 525 }
 526
 527 static void pxa270a1_initfn(Object *obj)
 528 {
 529     ARMCPU *cpu = ARM_CPU(obj);
 530     set_feature(&cpu->env, ARM_FEATURE_V5);
 531     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 532     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 533     cpu->midr = ARM_CPUID_PXA270_A1;
 534     cpu->ctr = 0xd172172;
 535     cpu->reset_sctlr = 0x00000078;
 536 }
 537
 538 static void pxa270b0_initfn(Object *obj)
 539 {
 540     ARMCPU *cpu = ARM_CPU(obj);
 541     set_feature(&cpu->env, ARM_FEATURE_V5);
 542     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 543     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 544     cpu->midr = ARM_CPUID_PXA270_B0;
 545     cpu->ctr = 0xd172172;
 546     cpu->reset_sctlr = 0x00000078;
 547 }
 548
 549 static void pxa270b1_initfn(Object *obj)
 550 {
 551     ARMCPU *cpu = ARM_CPU(obj);
 552     set_feature(&cpu->env, ARM_FEATURE_V5);
 553     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 554     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 555     cpu->midr = ARM_CPUID_PXA270_B1;
 556     cpu->ctr = 0xd172172;
 557     cpu->reset_sctlr = 0x00000078;
 558 }
 559
 560 static void pxa270c0_initfn(Object *obj)
 561 {
 562     ARMCPU *cpu = ARM_CPU(obj);
 563     set_feature(&cpu->env, ARM_FEATURE_V5);
 564     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 565     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 566     cpu->midr = ARM_CPUID_PXA270_C0;
 567     cpu->ctr = 0xd172172;
 568     cpu->reset_sctlr = 0x00000078;
 569 }
 570
 571 static void pxa270c5_initfn(Object *obj)
 572 {
 573     ARMCPU *cpu = ARM_CPU(obj);
 574     set_feature(&cpu->env, ARM_FEATURE_V5);
 575     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 576     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 577     cpu->midr = ARM_CPUID_PXA270_C5;
 578     cpu->ctr = 0xd172172;
 579     cpu->reset_sctlr = 0x00000078;
 580 }
 581
 582 static void arm_any_initfn(Object *obj)
 583 {
 584     ARMCPU *cpu = ARM_CPU(obj);
 585     set_feature(&cpu->env, ARM_FEATURE_V7);
 586     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 587     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 588     set_feature(&cpu->env, ARM_FEATURE_NEON);
 589     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 590     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 591     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 592     cpu->midr = ARM_CPUID_ANY;
 593 }
 594
 595 typedef struct ARMCPUInfo {
 596     const char *name;
 597     void (*initfn)(Object *obj);
 598 } ARMCPUInfo;
 599
 600 static const ARMCPUInfo arm_cpus[] = {
 601     { .name = "arm926",      .initfn = arm926_initfn },
 602     { .name = "arm946",      .initfn = arm946_initfn },
 603     { .name = "arm1026",     .initfn = arm1026_initfn },
 604     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
 605      * older core than plain "arm1136". In particular this does not
 606      * have the v6K features.
 607      */
 608     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
 609     { .name = "arm1136",     .initfn = arm1136_initfn },
 610     { .name = "arm1176",     .initfn = arm1176_initfn },
 611     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
 612     { .name = "cortex-m3",   .initfn = cortex_m3_initfn },
 613     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
 614     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
 615     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
 616     { .name = "ti925t",      .initfn = ti925t_initfn },
 617     { .name = "sa1100",      .initfn = sa1100_initfn },
 618     { .name = "sa1110",      .initfn = sa1110_initfn },
 619     { .name = "pxa250",      .initfn = pxa250_initfn },
 620     { .name = "pxa255",      .initfn = pxa255_initfn },
 621     { .name = "pxa260",      .initfn = pxa260_initfn },
 622     { .name = "pxa261",      .initfn = pxa261_initfn },
 623     { .name = "pxa262",      .initfn = pxa262_initfn },
 624     /* "pxa270" is an alias for "pxa270-a0" */
 625     { .name = "pxa270",      .initfn = pxa270a0_initfn },
 626     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
 627     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
 628     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
 629     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
 630     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
 631     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
 632     { .name = "any",         .initfn = arm_any_initfn },
 633 };
 634
 635 static void arm_cpu_class_init(ObjectClass *oc, void *data)
 636 {
 637     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
 638     CPUClass *cc = CPU_CLASS(acc);
 639
 640     acc->parent_reset = cc->reset;
 641     cc->reset = arm_cpu_reset;
 642 }
 643
 644 static void cpu_register(const ARMCPUInfo *info)
 645 {
 646     TypeInfo type_info = {
 647         .name = info->name,
 648         .parent = TYPE_ARM_CPU,
 649         .instance_size = sizeof(ARMCPU),
 650         .instance_init = info->initfn,
 651         .class_size = sizeof(ARMCPUClass),
 652     };
 653
 654     type_register_static(&type_info);
 655 }
 656
 657 static const TypeInfo arm_cpu_type_info = {
 658     .name = TYPE_ARM_CPU,
 659     .parent = TYPE_CPU,
 660     .instance_size = sizeof(ARMCPU),
 661     .instance_init = arm_cpu_initfn,
 662     .abstract = true,
 663     .class_size = sizeof(ARMCPUClass),
 664     .class_init = arm_cpu_class_init,
 665 };
 666
 667 static void arm_cpu_register_types(void)
 668 {
 669     int i;
 670
 671     type_register_static(&arm_cpu_type_info);
 672     for (i = 0; i < ARRAY_SIZE(arm_cpus); i++) {
 673         cpu_register(&arm_cpus[i]);
 674     }
 675 }
 676
 677 type_init(arm_cpu_register_types)