hw/tcx.c

   1 /*
   2  * QEMU TCX Frame buffer
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27 #include "pixel_ops.h"
  28
  29 #define MAXX 1024
  30 #define MAXY 768
  31 #define TCX_DAC_NREGS 16
  32 #define TCX_THC_NREGS_8  0x081c
  33 #define TCX_THC_NREGS_24 0x1000
  34 #define TCX_TEC_NREGS    0x1000
  35
  36 typedef struct TCXState {
  37     target_phys_addr_t addr;
  38     DisplayState *ds;
  39     uint8_t *vram;
  40     uint32_t *vram24, *cplane;
  41     ram_addr_t vram_offset, vram24_offset, cplane_offset;
  42     uint16_t width, height, depth;
  43     uint8_t r[256], g[256], b[256];
  44     uint32_t palette[256];
  45     uint8_t dac_index, dac_state;
  46 } TCXState;
  47
  48 static void tcx_screen_dump(void *opaque, const char *filename);
  49 static void tcx24_screen_dump(void *opaque, const char *filename);
  50 static void tcx_invalidate_display(void *opaque);
  51 static void tcx24_invalidate_display(void *opaque);
  52
  53 static void update_palette_entries(TCXState *s, int start, int end)
  54 {
  55     int i;
  56     for(i = start; i < end; i++) {
  57         switch(s->ds->depth) {
  58         default:
  59         case 8:
  60             s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
  61             break;
  62         case 15:
  63             if (s->ds->bgr)
  64                 s->palette[i] = rgb_to_pixel15bgr(s->r[i], s->g[i], s->b[i]);
  65             else
  66                 s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
  67             break;
  68         case 16:
  69             if (s->ds->bgr)
  70                 s->palette[i] = rgb_to_pixel16bgr(s->r[i], s->g[i], s->b[i]);
  71             else
  72                 s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
  73             break;
  74         case 32:
  75             if (s->ds->bgr)
  76                 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
  77             else
  78                 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
  79             break;
  80         }
  81     }
  82     if (s->depth == 24)
  83         tcx24_invalidate_display(s);
  84     else
  85         tcx_invalidate_display(s);
  86 }
  87
  88 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
  89                             const uint8_t *s, int width)
  90 {
  91     int x;
  92     uint8_t val;
  93     uint32_t *p = (uint32_t *)d;
  94
  95     for(x = 0; x < width; x++) {
  96         val = *s++;
  97         *p++ = s1->palette[val];
  98     }
  99 }
 100
 101 static void tcx_draw_line16(TCXState *s1, uint8_t *d,
 102                             const uint8_t *s, int width)
 103 {
 104     int x;
 105     uint8_t val;
 106     uint16_t *p = (uint16_t *)d;
 107
 108     for(x = 0; x < width; x++) {
 109         val = *s++;
 110         *p++ = s1->palette[val];
 111     }
 112 }
 113
 114 static void tcx_draw_line8(TCXState *s1, uint8_t *d,
 115                            const uint8_t *s, int width)
 116 {
 117     int x;
 118     uint8_t val;
 119
 120     for(x = 0; x < width; x++) {
 121         val = *s++;
 122         *d++ = s1->palette[val];
 123     }
 124 }
 125
 126 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
 127                                      const uint8_t *s, int width,
 128                                      const uint32_t *cplane,
 129                                      const uint32_t *s24)
 130 {
 131     int x;
 132     uint8_t val;
 133     uint32_t *p = (uint32_t *)d;
 134     uint32_t dval;
 135
 136     for(x = 0; x < width; x++, s++, s24++) {
 137         if ((bswap32(*cplane++) & 0xff000000) == 0x03000000) { // 24-bit direct
 138             dval = bswap32(*s24) & 0x00ffffff;
 139         } else {
 140             val = *s;
 141             dval = s1->palette[val];
 142         }
 143         *p++ = dval;
 144     }
 145 }
 146
 147 static inline int check_dirty(ram_addr_t page, ram_addr_t page24,
 148                               ram_addr_t cpage)
 149 {
 150     int ret;
 151     unsigned int off;
 152
 153     ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG);
 154     for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
 155         ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG);
 156         ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG);
 157     }
 158     return ret;
 159 }
 160
 161 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
 162                                ram_addr_t page_max, ram_addr_t page24,
 163                               ram_addr_t cpage)
 164 {
 165     cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
 166                                     VGA_DIRTY_FLAG);
 167     page_min -= ts->vram_offset;
 168     page_max -= ts->vram_offset;
 169     cpu_physical_memory_reset_dirty(page24 + page_min * 4,
 170                                     page24 + page_max * 4 + TARGET_PAGE_SIZE,
 171                                     VGA_DIRTY_FLAG);
 172     cpu_physical_memory_reset_dirty(cpage + page_min * 4,
 173                                     cpage + page_max * 4 + TARGET_PAGE_SIZE,
 174                                     VGA_DIRTY_FLAG);
 175 }
 176
 177 /* Fixed line length 1024 allows us to do nice tricks not possible on
 178    VGA... */
 179 static void tcx_update_display(void *opaque)
 180 {
 181     TCXState *ts = opaque;
 182     ram_addr_t page, page_min, page_max;
 183     int y, y_start, dd, ds;
 184     uint8_t *d, *s;
 185     void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
 186
 187     if (ts->ds->depth == 0)
 188         return;
 189     if (ts->ds->width != ts->width || ts->ds->height != ts->height)
 190         dpy_resize(ts->ds, ts->width, ts->height);
 191     page = ts->vram_offset;
 192     y_start = -1;
 193     page_min = 0xffffffff;
 194     page_max = 0;
 195     d = ts->ds->data;
 196     s = ts->vram;
 197     dd = ts->ds->linesize;
 198     ds = 1024;
 199
 200     switch (ts->ds->depth) {
 201     case 32:
 202         f = tcx_draw_line32;
 203         break;
 204     case 15:
 205     case 16:
 206         f = tcx_draw_line16;
 207         break;
 208     default:
 209     case 8:
 210         f = tcx_draw_line8;
 211         break;
 212     case 0:
 213         return;
 214     }
 215
 216     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
 217         if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) {
 218             if (y_start < 0)
 219                 y_start = y;
 220             if (page < page_min)
 221                 page_min = page;
 222             if (page > page_max)
 223                 page_max = page;
 224             f(ts, d, s, ts->width);
 225             d += dd;
 226             s += ds;
 227             f(ts, d, s, ts->width);
 228             d += dd;
 229             s += ds;
 230             f(ts, d, s, ts->width);
 231             d += dd;
 232             s += ds;
 233             f(ts, d, s, ts->width);
 234             d += dd;
 235             s += ds;
 236         } else {
 237             if (y_start >= 0) {
 238                 /* flush to display */
 239                 dpy_update(ts->ds, 0, y_start,
 240                            ts->width, y - y_start);
 241                 y_start = -1;
 242             }
 243             d += dd * 4;
 244             s += ds * 4;
 245         }
 246     }
 247     if (y_start >= 0) {
 248         /* flush to display */
 249         dpy_update(ts->ds, 0, y_start,
 250                    ts->width, y - y_start);
 251     }
 252     /* reset modified pages */
 253     if (page_min <= page_max) {
 254         cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
 255                                         VGA_DIRTY_FLAG);
 256     }
 257 }
 258
 259 static void tcx24_update_display(void *opaque)
 260 {
 261     TCXState *ts = opaque;
 262     ram_addr_t page, page_min, page_max, cpage, page24;
 263     int y, y_start, dd, ds;
 264     uint8_t *d, *s;
 265     uint32_t *cptr, *s24;
 266
 267     if (ts->ds->depth != 32)
 268             return;
 269     if (ts->ds->width != ts->width || ts->ds->height != ts->height)
 270         dpy_resize(ts->ds, ts->width, ts->height);
 271     page = ts->vram_offset;
 272     page24 = ts->vram24_offset;
 273     cpage = ts->cplane_offset;
 274     y_start = -1;
 275     page_min = 0xffffffff;
 276     page_max = 0;
 277     d = ts->ds->data;
 278     s = ts->vram;
 279     s24 = ts->vram24;
 280     cptr = ts->cplane;
 281     dd = ts->ds->linesize;
 282     ds = 1024;
 283
 284     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
 285             page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
 286         if (check_dirty(page, page24, cpage)) {
 287             if (y_start < 0)
 288                 y_start = y;
 289             if (page < page_min)
 290                 page_min = page;
 291             if (page > page_max)
 292                 page_max = page;
 293             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 294             d += dd;
 295             s += ds;
 296             cptr += ds;
 297             s24 += ds;
 298             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 299             d += dd;
 300             s += ds;
 301             cptr += ds;
 302             s24 += ds;
 303             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 304             d += dd;
 305             s += ds;
 306             cptr += ds;
 307             s24 += ds;
 308             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 309             d += dd;
 310             s += ds;
 311             cptr += ds;
 312             s24 += ds;
 313         } else {
 314             if (y_start >= 0) {
 315                 /* flush to display */
 316                 dpy_update(ts->ds, 0, y_start,
 317                            ts->width, y - y_start);
 318                 y_start = -1;
 319             }
 320             d += dd * 4;
 321             s += ds * 4;
 322             cptr += ds * 4;
 323             s24 += ds * 4;
 324         }
 325     }
 326     if (y_start >= 0) {
 327         /* flush to display */
 328         dpy_update(ts->ds, 0, y_start,
 329                    ts->width, y - y_start);
 330     }
 331     /* reset modified pages */
 332     if (page_min <= page_max) {
 333         reset_dirty(ts, page_min, page_max, page24, cpage);
 334     }
 335 }
 336
 337 static void tcx_invalidate_display(void *opaque)
 338 {
 339     TCXState *s = opaque;
 340     int i;
 341
 342     for (i = 0; i < MAXX*MAXY; i += TARGET_PAGE_SIZE) {
 343         cpu_physical_memory_set_dirty(s->vram_offset + i);
 344     }
 345 }
 346
 347 static void tcx24_invalidate_display(void *opaque)
 348 {
 349     TCXState *s = opaque;
 350     int i;
 351
 352     tcx_invalidate_display(s);
 353     for (i = 0; i < MAXX*MAXY * 4; i += TARGET_PAGE_SIZE) {
 354         cpu_physical_memory_set_dirty(s->vram24_offset + i);
 355         cpu_physical_memory_set_dirty(s->cplane_offset + i);
 356     }
 357 }
 358
 359 static void tcx_save(QEMUFile *f, void *opaque)
 360 {
 361     TCXState *s = opaque;
 362
 363     qemu_put_be16s(f, (uint16_t *)&s->height);
 364     qemu_put_be16s(f, (uint16_t *)&s->width);
 365     qemu_put_be16s(f, (uint16_t *)&s->depth);
 366     qemu_put_buffer(f, s->r, 256);
 367     qemu_put_buffer(f, s->g, 256);
 368     qemu_put_buffer(f, s->b, 256);
 369     qemu_put_8s(f, &s->dac_index);
 370     qemu_put_8s(f, &s->dac_state);
 371 }
 372
 373 static int tcx_load(QEMUFile *f, void *opaque, int version_id)
 374 {
 375     TCXState *s = opaque;
 376     uint32_t dummy;
 377
 378     if (version_id != 3 && version_id != 4)
 379         return -EINVAL;
 380
 381     if (version_id == 3) {
 382         qemu_get_be32s(f, (uint32_t *)&dummy);
 383         qemu_get_be32s(f, (uint32_t *)&dummy);
 384         qemu_get_be32s(f, (uint32_t *)&dummy);
 385     }
 386     qemu_get_be16s(f, (uint16_t *)&s->height);
 387     qemu_get_be16s(f, (uint16_t *)&s->width);
 388     qemu_get_be16s(f, (uint16_t *)&s->depth);
 389     qemu_get_buffer(f, s->r, 256);
 390     qemu_get_buffer(f, s->g, 256);
 391     qemu_get_buffer(f, s->b, 256);
 392     qemu_get_8s(f, &s->dac_index);
 393     qemu_get_8s(f, &s->dac_state);
 394     update_palette_entries(s, 0, 256);
 395     if (s->depth == 24)
 396         tcx24_invalidate_display(s);
 397     else
 398         tcx_invalidate_display(s);
 399
 400     return 0;
 401 }
 402
 403 static void tcx_reset(void *opaque)
 404 {
 405     TCXState *s = opaque;
 406
 407     /* Initialize palette */
 408     memset(s->r, 0, 256);
 409     memset(s->g, 0, 256);
 410     memset(s->b, 0, 256);
 411     s->r[255] = s->g[255] = s->b[255] = 255;
 412     update_palette_entries(s, 0, 256);
 413     memset(s->vram, 0, MAXX*MAXY);
 414     cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset +
 415                                     MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG);
 416     s->dac_index = 0;
 417     s->dac_state = 0;
 418 }
 419
 420 static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr)
 421 {
 422     return 0;
 423 }
 424
 425 static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 426 {
 427     TCXState *s = opaque;
 428     uint32_t saddr;
 429
 430     saddr = (addr & (TCX_DAC_NREGS - 1)) >> 2;
 431     switch (saddr) {
 432     case 0:
 433         s->dac_index = val >> 24;
 434         s->dac_state = 0;
 435         break;
 436     case 1:
 437         switch (s->dac_state) {
 438         case 0:
 439             s->r[s->dac_index] = val >> 24;
 440             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 441             s->dac_state++;
 442             break;
 443         case 1:
 444             s->g[s->dac_index] = val >> 24;
 445             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 446             s->dac_state++;
 447             break;
 448         case 2:
 449             s->b[s->dac_index] = val >> 24;
 450             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 451             s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
 452         default:
 453             s->dac_state = 0;
 454             break;
 455         }
 456         break;
 457     default:
 458         break;
 459     }
 460     return;
 461 }
 462
 463 static CPUReadMemoryFunc *tcx_dac_read[3] = {
 464     NULL,
 465     NULL,
 466     tcx_dac_readl,
 467 };
 468
 469 static CPUWriteMemoryFunc *tcx_dac_write[3] = {
 470     NULL,
 471     NULL,
 472     tcx_dac_writel,
 473 };
 474
 475 static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr)
 476 {
 477     return 0;
 478 }
 479
 480 static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr,
 481                              uint32_t val)
 482 {
 483 }
 484
 485 static CPUReadMemoryFunc *tcx_dummy_read[3] = {
 486     NULL,
 487     NULL,
 488     tcx_dummy_readl,
 489 };
 490
 491 static CPUWriteMemoryFunc *tcx_dummy_write[3] = {
 492     NULL,
 493     NULL,
 494     tcx_dummy_writel,
 495 };
 496
 497 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
 498               unsigned long vram_offset, int vram_size, int width, int height,
 499               int depth)
 500 {
 501     TCXState *s;
 502     int io_memory, dummy_memory;
 503     int size;
 504
 505     s = qemu_mallocz(sizeof(TCXState));
 506     if (!s)
 507         return;
 508     s->ds = ds;
 509     s->addr = addr;
 510     s->vram_offset = vram_offset;
 511     s->width = width;
 512     s->height = height;
 513     s->depth = depth;
 514
 515     // 8-bit plane
 516     s->vram = vram_base;
 517     size = vram_size;
 518     cpu_register_physical_memory(addr + 0x00800000ULL, size, vram_offset);
 519     vram_offset += size;
 520     vram_base += size;
 521
 522     io_memory = cpu_register_io_memory(0, tcx_dac_read, tcx_dac_write, s);
 523     cpu_register_physical_memory(addr + 0x00200000ULL, TCX_DAC_NREGS,
 524                                  io_memory);
 525
 526     dummy_memory = cpu_register_io_memory(0, tcx_dummy_read, tcx_dummy_write,
 527                                           s);
 528     cpu_register_physical_memory(addr + 0x00700000ULL, TCX_TEC_NREGS,
 529                                  dummy_memory);
 530     if (depth == 24) {
 531         // 24-bit plane
 532         size = vram_size * 4;
 533         s->vram24 = (uint32_t *)vram_base;
 534         s->vram24_offset = vram_offset;
 535         cpu_register_physical_memory(addr + 0x02000000ULL, size, vram_offset);
 536         vram_offset += size;
 537         vram_base += size;
 538
 539         // Control plane
 540         size = vram_size * 4;
 541         s->cplane = (uint32_t *)vram_base;
 542         s->cplane_offset = vram_offset;
 543         cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
 544         graphic_console_init(s->ds, tcx24_update_display,
 545                              tcx24_invalidate_display,
 546                              tcx24_screen_dump, NULL, s);
 547     } else {
 548         cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
 549                                      dummy_memory);
 550         graphic_console_init(s->ds, tcx_update_display, tcx_invalidate_display,
 551                              tcx_screen_dump, NULL, s);
 552     }
 553     // NetBSD writes here even with 8-bit display
 554     cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
 555                                  dummy_memory);
 556
 557     register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
 558     qemu_register_reset(tcx_reset, s);
 559     tcx_reset(s);
 560     dpy_resize(s->ds, width, height);
 561 }
 562
 563 static void tcx_screen_dump(void *opaque, const char *filename)
 564 {
 565     TCXState *s = opaque;
 566     FILE *f;
 567     uint8_t *d, *d1, v;
 568     int y, x;
 569
 570     f = fopen(filename, "wb");
 571     if (!f)
 572         return;
 573     fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
 574     d1 = s->vram;
 575     for(y = 0; y < s->height; y++) {
 576         d = d1;
 577         for(x = 0; x < s->width; x++) {
 578             v = *d;
 579             fputc(s->r[v], f);
 580             fputc(s->g[v], f);
 581             fputc(s->b[v], f);
 582             d++;
 583         }
 584         d1 += MAXX;
 585     }
 586     fclose(f);
 587     return;
 588 }
 589
 590 static void tcx24_screen_dump(void *opaque, const char *filename)
 591 {
 592     TCXState *s = opaque;
 593     FILE *f;
 594     uint8_t *d, *d1, v;
 595     uint32_t *s24, *cptr, dval;
 596     int y, x;
 597
 598     f = fopen(filename, "wb");
 599     if (!f)
 600         return;
 601     fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
 602     d1 = s->vram;
 603     s24 = s->vram24;
 604     cptr = s->cplane;
 605     for(y = 0; y < s->height; y++) {
 606         d = d1;
 607         for(x = 0; x < s->width; x++, d++, s24++) {
 608             if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
 609                 dval = *s24 & 0x00ffffff;
 610                 fputc((dval >> 16) & 0xff, f);
 611                 fputc((dval >> 8) & 0xff, f);
 612                 fputc(dval & 0xff, f);
 613             } else {
 614                 v = *d;
 615                 fputc(s->r[v], f);
 616                 fputc(s->g[v], f);
 617                 fputc(s->b[v], f);
 618             }
 619         }
 620         d1 += MAXX;
 621     }
 622     fclose(f);
 623     return;
 624 }