hw/arm/fsl-imx7.c

   1 /*
   2  * Copyright (c) 2018, Impinj, Inc.
   3  *
   4  * i.MX7 SoC definitions
   5  *
   6  * Author: Andrey Smirnov <[email protected]>
   7  *
   8  * Based on hw/arm/fsl-imx6.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "qapi/error.h"
  23 #include "hw/arm/fsl-imx7.h"
  24 #include "hw/misc/unimp.h"
  25 #include "hw/boards.h"
  26 #include "sysemu/sysemu.h"
  27 #include "qemu/error-report.h"
  28 #include "qemu/module.h"
  29
  30 #define NAME_SIZE 20
  31
  32 static void fsl_imx7_init(Object *obj)
  33 {
  34     MachineState *ms = MACHINE(qdev_get_machine());
  35     FslIMX7State *s = FSL_IMX7(obj);
  36     char name[NAME_SIZE];
  37     int i;
  38
  39     for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX7_NUM_CPUS); i++) {
  40         snprintf(name, NAME_SIZE, "cpu%d", i);
  41         object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
  42                                 ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort,
  43                                 NULL);
  44     }
  45
  46     /*
  47      * A7MPCORE
  48      */
  49     sysbus_init_child_obj(obj, "a7mpcore", &s->a7mpcore, sizeof(s->a7mpcore),
  50                           TYPE_A15MPCORE_PRIV);
  51
  52     /*
  53      * GPIOs 1 to 7
  54      */
  55     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
  56         snprintf(name, NAME_SIZE, "gpio%d", i);
  57         sysbus_init_child_obj(obj, name, &s->gpio[i], sizeof(s->gpio[i]),
  58                           TYPE_IMX_GPIO);
  59     }
  60
  61     /*
  62      * GPT1, 2, 3, 4
  63      */
  64     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
  65         snprintf(name, NAME_SIZE, "gpt%d", i);
  66         sysbus_init_child_obj(obj, name, &s->gpt[i], sizeof(s->gpt[i]),
  67                               TYPE_IMX7_GPT);
  68     }
  69
  70     /*
  71      * CCM
  72      */
  73     sysbus_init_child_obj(obj, "ccm", &s->ccm, sizeof(s->ccm), TYPE_IMX7_CCM);
  74
  75     /*
  76      * Analog
  77      */
  78     sysbus_init_child_obj(obj, "analog", &s->analog, sizeof(s->analog),
  79                           TYPE_IMX7_ANALOG);
  80
  81     /*
  82      * GPCv2
  83      */
  84     sysbus_init_child_obj(obj, "gpcv2", &s->gpcv2, sizeof(s->gpcv2),
  85                           TYPE_IMX_GPCV2);
  86
  87     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
  88         snprintf(name, NAME_SIZE, "spi%d", i + 1);
  89         sysbus_init_child_obj(obj, name, &s->spi[i], sizeof(s->spi[i]),
  90                               TYPE_IMX_SPI);
  91     }
  92
  93
  94     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
  95         snprintf(name, NAME_SIZE, "i2c%d", i + 1);
  96         sysbus_init_child_obj(obj, name, &s->i2c[i], sizeof(s->i2c[i]),
  97                               TYPE_IMX_I2C);
  98     }
  99
 100     /*
 101      * UART
 102      */
 103     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
 104             snprintf(name, NAME_SIZE, "uart%d", i);
 105             sysbus_init_child_obj(obj, name, &s->uart[i], sizeof(s->uart[i]),
 106                                   TYPE_IMX_SERIAL);
 107     }
 108
 109     /*
 110      * Ethernet
 111      */
 112     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
 113             snprintf(name, NAME_SIZE, "eth%d", i);
 114             sysbus_init_child_obj(obj, name, &s->eth[i], sizeof(s->eth[i]),
 115                                   TYPE_IMX_ENET);
 116     }
 117
 118     /*
 119      * SDHCI
 120      */
 121     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
 122             snprintf(name, NAME_SIZE, "usdhc%d", i);
 123             sysbus_init_child_obj(obj, name, &s->usdhc[i], sizeof(s->usdhc[i]),
 124                               TYPE_IMX_USDHC);
 125     }
 126
 127     /*
 128      * SNVS
 129      */
 130     sysbus_init_child_obj(obj, "snvs", &s->snvs, sizeof(s->snvs),
 131                           TYPE_IMX7_SNVS);
 132
 133     /*
 134      * Watchdog
 135      */
 136     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
 137             snprintf(name, NAME_SIZE, "wdt%d", i);
 138             sysbus_init_child_obj(obj, name, &s->wdt[i], sizeof(s->wdt[i]),
 139                                   TYPE_IMX2_WDT);
 140     }
 141
 142     /*
 143      * GPR
 144      */
 145     sysbus_init_child_obj(obj, "gpr", &s->gpr, sizeof(s->gpr), TYPE_IMX7_GPR);
 146
 147     sysbus_init_child_obj(obj, "pcie", &s->pcie, sizeof(s->pcie),
 148                           TYPE_DESIGNWARE_PCIE_HOST);
 149
 150     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
 151         snprintf(name, NAME_SIZE, "usb%d", i);
 152         sysbus_init_child_obj(obj, name, &s->usb[i], sizeof(s->usb[i]),
 153                               TYPE_CHIPIDEA);
 154     }
 155 }
 156
 157 static void fsl_imx7_realize(DeviceState *dev, Error **errp)
 158 {
 159     MachineState *ms = MACHINE(qdev_get_machine());
 160     FslIMX7State *s = FSL_IMX7(dev);
 161     Object *o;
 162     int i;
 163     qemu_irq irq;
 164     char name[NAME_SIZE];
 165     unsigned int smp_cpus = ms->smp.cpus;
 166
 167     if (smp_cpus > FSL_IMX7_NUM_CPUS) {
 168         error_setg(errp, "%s: Only %d CPUs are supported (%d requested)",
 169                    TYPE_FSL_IMX7, FSL_IMX7_NUM_CPUS, smp_cpus);
 170         return;
 171     }
 172
 173     for (i = 0; i < smp_cpus; i++) {
 174         o = OBJECT(&s->cpu[i]);
 175
 176         object_property_set_int(o, QEMU_PSCI_CONDUIT_SMC,
 177                                 "psci-conduit", &error_abort);
 178
 179         /* On uniprocessor, the CBAR is set to 0 */
 180         if (smp_cpus > 1) {
 181             object_property_set_int(o, FSL_IMX7_A7MPCORE_ADDR,
 182                                     "reset-cbar", &error_abort);
 183         }
 184
 185         if (i) {
 186             /* Secondary CPUs start in PSCI powered-down state */
 187             object_property_set_bool(o, true,
 188                                      "start-powered-off", &error_abort);
 189         }
 190
 191         object_property_set_bool(o, true, "realized", &error_abort);
 192     }
 193
 194     /*
 195      * A7MPCORE
 196      */
 197     object_property_set_int(OBJECT(&s->a7mpcore), smp_cpus, "num-cpu",
 198                             &error_abort);
 199     object_property_set_int(OBJECT(&s->a7mpcore),
 200                             FSL_IMX7_MAX_IRQ + GIC_INTERNAL,
 201                             "num-irq", &error_abort);
 202
 203     object_property_set_bool(OBJECT(&s->a7mpcore), true, "realized",
 204                              &error_abort);
 205     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a7mpcore), 0, FSL_IMX7_A7MPCORE_ADDR);
 206
 207     for (i = 0; i < smp_cpus; i++) {
 208         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->a7mpcore);
 209         DeviceState  *d   = DEVICE(qemu_get_cpu(i));
 210
 211         irq = qdev_get_gpio_in(d, ARM_CPU_IRQ);
 212         sysbus_connect_irq(sbd, i, irq);
 213         irq = qdev_get_gpio_in(d, ARM_CPU_FIQ);
 214         sysbus_connect_irq(sbd, i + smp_cpus, irq);
 215         irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ);
 216         sysbus_connect_irq(sbd, i + 2 * smp_cpus, irq);
 217         irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ);
 218         sysbus_connect_irq(sbd, i + 3 * smp_cpus, irq);
 219     }
 220
 221     /*
 222      * A7MPCORE DAP
 223      */
 224     create_unimplemented_device("a7mpcore-dap", FSL_IMX7_A7MPCORE_DAP_ADDR,
 225                                 0x100000);
 226
 227     /*
 228      * GPT1, 2, 3, 4
 229      */
 230     for (i = 0; i < FSL_IMX7_NUM_GPTS; i++) {
 231         static const hwaddr FSL_IMX7_GPTn_ADDR[FSL_IMX7_NUM_GPTS] = {
 232             FSL_IMX7_GPT1_ADDR,
 233             FSL_IMX7_GPT2_ADDR,
 234             FSL_IMX7_GPT3_ADDR,
 235             FSL_IMX7_GPT4_ADDR,
 236         };
 237
 238         s->gpt[i].ccm = IMX_CCM(&s->ccm);
 239         object_property_set_bool(OBJECT(&s->gpt[i]), true, "realized",
 240                                  &error_abort);
 241         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpt[i]), 0, FSL_IMX7_GPTn_ADDR[i]);
 242     }
 243
 244     for (i = 0; i < FSL_IMX7_NUM_GPIOS; i++) {
 245         static const hwaddr FSL_IMX7_GPIOn_ADDR[FSL_IMX7_NUM_GPIOS] = {
 246             FSL_IMX7_GPIO1_ADDR,
 247             FSL_IMX7_GPIO2_ADDR,
 248             FSL_IMX7_GPIO3_ADDR,
 249             FSL_IMX7_GPIO4_ADDR,
 250             FSL_IMX7_GPIO5_ADDR,
 251             FSL_IMX7_GPIO6_ADDR,
 252             FSL_IMX7_GPIO7_ADDR,
 253         };
 254
 255         object_property_set_bool(OBJECT(&s->gpio[i]), true, "realized",
 256                                  &error_abort);
 257         sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0, FSL_IMX7_GPIOn_ADDR[i]);
 258     }
 259
 260     /*
 261      * IOMUXC and IOMUXC_LPSR
 262      */
 263     for (i = 0; i < FSL_IMX7_NUM_IOMUXCS; i++) {
 264         static const hwaddr FSL_IMX7_IOMUXCn_ADDR[FSL_IMX7_NUM_IOMUXCS] = {
 265             FSL_IMX7_IOMUXC_ADDR,
 266             FSL_IMX7_IOMUXC_LPSR_ADDR,
 267         };
 268
 269         snprintf(name, NAME_SIZE, "iomuxc%d", i);
 270         create_unimplemented_device(name, FSL_IMX7_IOMUXCn_ADDR[i],
 271                                     FSL_IMX7_IOMUXCn_SIZE);
 272     }
 273
 274     /*
 275      * CCM
 276      */
 277     object_property_set_bool(OBJECT(&s->ccm), true, "realized", &error_abort);
 278     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccm), 0, FSL_IMX7_CCM_ADDR);
 279
 280     /*
 281      * Analog
 282      */
 283     object_property_set_bool(OBJECT(&s->analog), true, "realized",
 284                              &error_abort);
 285     sysbus_mmio_map(SYS_BUS_DEVICE(&s->analog), 0, FSL_IMX7_ANALOG_ADDR);
 286
 287     /*
 288      * GPCv2
 289      */
 290     object_property_set_bool(OBJECT(&s->gpcv2), true,
 291                              "realized", &error_abort);
 292     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpcv2), 0, FSL_IMX7_GPC_ADDR);
 293
 294     /* Initialize all ECSPI */
 295     for (i = 0; i < FSL_IMX7_NUM_ECSPIS; i++) {
 296         static const hwaddr FSL_IMX7_SPIn_ADDR[FSL_IMX7_NUM_ECSPIS] = {
 297             FSL_IMX7_ECSPI1_ADDR,
 298             FSL_IMX7_ECSPI2_ADDR,
 299             FSL_IMX7_ECSPI3_ADDR,
 300             FSL_IMX7_ECSPI4_ADDR,
 301         };
 302
 303         static const int FSL_IMX7_SPIn_IRQ[FSL_IMX7_NUM_ECSPIS] = {
 304             FSL_IMX7_ECSPI1_IRQ,
 305             FSL_IMX7_ECSPI2_IRQ,
 306             FSL_IMX7_ECSPI3_IRQ,
 307             FSL_IMX7_ECSPI4_IRQ,
 308         };
 309
 310         /* Initialize the SPI */
 311         object_property_set_bool(OBJECT(&s->spi[i]), true, "realized",
 312                                  &error_abort);
 313         sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0,
 314                         FSL_IMX7_SPIn_ADDR[i]);
 315         sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
 316                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 317                                             FSL_IMX7_SPIn_IRQ[i]));
 318     }
 319
 320     for (i = 0; i < FSL_IMX7_NUM_I2CS; i++) {
 321         static const hwaddr FSL_IMX7_I2Cn_ADDR[FSL_IMX7_NUM_I2CS] = {
 322             FSL_IMX7_I2C1_ADDR,
 323             FSL_IMX7_I2C2_ADDR,
 324             FSL_IMX7_I2C3_ADDR,
 325             FSL_IMX7_I2C4_ADDR,
 326         };
 327
 328         static const int FSL_IMX7_I2Cn_IRQ[FSL_IMX7_NUM_I2CS] = {
 329             FSL_IMX7_I2C1_IRQ,
 330             FSL_IMX7_I2C2_IRQ,
 331             FSL_IMX7_I2C3_IRQ,
 332             FSL_IMX7_I2C4_IRQ,
 333         };
 334
 335         object_property_set_bool(OBJECT(&s->i2c[i]), true, "realized",
 336                                  &error_abort);
 337         sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c[i]), 0, FSL_IMX7_I2Cn_ADDR[i]);
 338
 339         sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c[i]), 0,
 340                            qdev_get_gpio_in(DEVICE(&s->a7mpcore),
 341                                             FSL_IMX7_I2Cn_IRQ[i]));
 342     }
 343
 344     /*
 345      * UART
 346      */
 347     for (i = 0; i < FSL_IMX7_NUM_UARTS; i++) {
 348         static const hwaddr FSL_IMX7_UARTn_ADDR[FSL_IMX7_NUM_UARTS] = {
 349             FSL_IMX7_UART1_ADDR,
 350             FSL_IMX7_UART2_ADDR,
 351             FSL_IMX7_UART3_ADDR,
 352             FSL_IMX7_UART4_ADDR,
 353             FSL_IMX7_UART5_ADDR,
 354             FSL_IMX7_UART6_ADDR,
 355             FSL_IMX7_UART7_ADDR,
 356         };
 357
 358         static const int FSL_IMX7_UARTn_IRQ[FSL_IMX7_NUM_UARTS] = {
 359             FSL_IMX7_UART1_IRQ,
 360             FSL_IMX7_UART2_IRQ,
 361             FSL_IMX7_UART3_IRQ,
 362             FSL_IMX7_UART4_IRQ,
 363             FSL_IMX7_UART5_IRQ,
 364             FSL_IMX7_UART6_IRQ,
 365             FSL_IMX7_UART7_IRQ,
 366         };
 367
 368
 369         qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", serial_hd(i));
 370
 371         object_property_set_bool(OBJECT(&s->uart[i]), true, "realized",
 372                                  &error_abort);
 373
 374         sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, FSL_IMX7_UARTn_ADDR[i]);
 375
 376         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_UARTn_IRQ[i]);
 377         sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, irq);
 378     }
 379
 380     /*
 381      * Ethernet
 382      */
 383     for (i = 0; i < FSL_IMX7_NUM_ETHS; i++) {
 384         static const hwaddr FSL_IMX7_ENETn_ADDR[FSL_IMX7_NUM_ETHS] = {
 385             FSL_IMX7_ENET1_ADDR,
 386             FSL_IMX7_ENET2_ADDR,
 387         };
 388
 389         object_property_set_uint(OBJECT(&s->eth[i]), FSL_IMX7_ETH_NUM_TX_RINGS,
 390                                  "tx-ring-num", &error_abort);
 391         qdev_set_nic_properties(DEVICE(&s->eth[i]), &nd_table[i]);
 392         object_property_set_bool(OBJECT(&s->eth[i]), true, "realized",
 393                                  &error_abort);
 394
 395         sysbus_mmio_map(SYS_BUS_DEVICE(&s->eth[i]), 0, FSL_IMX7_ENETn_ADDR[i]);
 396
 397         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 0));
 398         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 0, irq);
 399         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_ENET_IRQ(i, 3));
 400         sysbus_connect_irq(SYS_BUS_DEVICE(&s->eth[i]), 1, irq);
 401     }
 402
 403     /*
 404      * USDHC
 405      */
 406     for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) {
 407         static const hwaddr FSL_IMX7_USDHCn_ADDR[FSL_IMX7_NUM_USDHCS] = {
 408             FSL_IMX7_USDHC1_ADDR,
 409             FSL_IMX7_USDHC2_ADDR,
 410             FSL_IMX7_USDHC3_ADDR,
 411         };
 412
 413         static const int FSL_IMX7_USDHCn_IRQ[FSL_IMX7_NUM_USDHCS] = {
 414             FSL_IMX7_USDHC1_IRQ,
 415             FSL_IMX7_USDHC2_IRQ,
 416             FSL_IMX7_USDHC3_IRQ,
 417         };
 418
 419         object_property_set_bool(OBJECT(&s->usdhc[i]), true, "realized",
 420                                  &error_abort);
 421
 422         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
 423                         FSL_IMX7_USDHCn_ADDR[i]);
 424
 425         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USDHCn_IRQ[i]);
 426         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usdhc[i]), 0, irq);
 427     }
 428
 429     /*
 430      * SNVS
 431      */
 432     object_property_set_bool(OBJECT(&s->snvs), true, "realized", &error_abort);
 433     sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, FSL_IMX7_SNVS_ADDR);
 434
 435     /*
 436      * SRC
 437      */
 438     create_unimplemented_device("src", FSL_IMX7_SRC_ADDR, FSL_IMX7_SRC_SIZE);
 439
 440     /*
 441      * Watchdog
 442      */
 443     for (i = 0; i < FSL_IMX7_NUM_WDTS; i++) {
 444         static const hwaddr FSL_IMX7_WDOGn_ADDR[FSL_IMX7_NUM_WDTS] = {
 445             FSL_IMX7_WDOG1_ADDR,
 446             FSL_IMX7_WDOG2_ADDR,
 447             FSL_IMX7_WDOG3_ADDR,
 448             FSL_IMX7_WDOG4_ADDR,
 449         };
 450
 451         object_property_set_bool(OBJECT(&s->wdt[i]), true, "realized",
 452                                  &error_abort);
 453
 454         sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, FSL_IMX7_WDOGn_ADDR[i]);
 455     }
 456
 457     /*
 458      * SDMA
 459      */
 460     create_unimplemented_device("sdma", FSL_IMX7_SDMA_ADDR, FSL_IMX7_SDMA_SIZE);
 461
 462
 463     object_property_set_bool(OBJECT(&s->gpr), true, "realized",
 464                              &error_abort);
 465     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpr), 0, FSL_IMX7_GPR_ADDR);
 466
 467     object_property_set_bool(OBJECT(&s->pcie), true,
 468                              "realized", &error_abort);
 469     sysbus_mmio_map(SYS_BUS_DEVICE(&s->pcie), 0, FSL_IMX7_PCIE_REG_ADDR);
 470
 471     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTA_IRQ);
 472     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 0, irq);
 473     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTB_IRQ);
 474     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 1, irq);
 475     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTC_IRQ);
 476     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 2, irq);
 477     irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_PCI_INTD_IRQ);
 478     sysbus_connect_irq(SYS_BUS_DEVICE(&s->pcie), 3, irq);
 479
 480
 481     for (i = 0; i < FSL_IMX7_NUM_USBS; i++) {
 482         static const hwaddr FSL_IMX7_USBMISCn_ADDR[FSL_IMX7_NUM_USBS] = {
 483             FSL_IMX7_USBMISC1_ADDR,
 484             FSL_IMX7_USBMISC2_ADDR,
 485             FSL_IMX7_USBMISC3_ADDR,
 486         };
 487
 488         static const hwaddr FSL_IMX7_USBn_ADDR[FSL_IMX7_NUM_USBS] = {
 489             FSL_IMX7_USB1_ADDR,
 490             FSL_IMX7_USB2_ADDR,
 491             FSL_IMX7_USB3_ADDR,
 492         };
 493
 494         static const int FSL_IMX7_USBn_IRQ[FSL_IMX7_NUM_USBS] = {
 495             FSL_IMX7_USB1_IRQ,
 496             FSL_IMX7_USB2_IRQ,
 497             FSL_IMX7_USB3_IRQ,
 498         };
 499
 500         object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
 501                                  &error_abort);
 502         sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0,
 503                         FSL_IMX7_USBn_ADDR[i]);
 504
 505         irq = qdev_get_gpio_in(DEVICE(&s->a7mpcore), FSL_IMX7_USBn_IRQ[i]);
 506         sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0, irq);
 507
 508         snprintf(name, NAME_SIZE, "usbmisc%d", i);
 509         create_unimplemented_device(name, FSL_IMX7_USBMISCn_ADDR[i],
 510                                     FSL_IMX7_USBMISCn_SIZE);
 511     }
 512
 513     /*
 514      * ADCs
 515      */
 516     for (i = 0; i < FSL_IMX7_NUM_ADCS; i++) {
 517         static const hwaddr FSL_IMX7_ADCn_ADDR[FSL_IMX7_NUM_ADCS] = {
 518             FSL_IMX7_ADC1_ADDR,
 519             FSL_IMX7_ADC2_ADDR,
 520         };
 521
 522         snprintf(name, NAME_SIZE, "adc%d", i);
 523         create_unimplemented_device(name, FSL_IMX7_ADCn_ADDR[i],
 524                                     FSL_IMX7_ADCn_SIZE);
 525     }
 526
 527     /*
 528      * LCD
 529      */
 530     create_unimplemented_device("lcdif", FSL_IMX7_LCDIF_ADDR,
 531                                 FSL_IMX7_LCDIF_SIZE);
 532
 533     /*
 534      * DMA APBH
 535      */
 536     create_unimplemented_device("dma-apbh", FSL_IMX7_DMA_APBH_ADDR,
 537                                 FSL_IMX7_DMA_APBH_SIZE);
 538     /*
 539      * PCIe PHY
 540      */
 541     create_unimplemented_device("pcie-phy", FSL_IMX7_PCIE_PHY_ADDR,
 542                                 FSL_IMX7_PCIE_PHY_SIZE);
 543 }
 544
 545 static void fsl_imx7_class_init(ObjectClass *oc, void *data)
 546 {
 547     DeviceClass *dc = DEVICE_CLASS(oc);
 548
 549     dc->realize = fsl_imx7_realize;
 550
 551     /* Reason: Uses serial_hds and nd_table in realize() directly */
 552     dc->user_creatable = false;
 553     dc->desc = "i.MX7 SOC";
 554 }
 555
 556 static const TypeInfo fsl_imx7_type_info = {
 557     .name = TYPE_FSL_IMX7,
 558     .parent = TYPE_DEVICE,
 559     .instance_size = sizeof(FslIMX7State),
 560     .instance_init = fsl_imx7_init,
 561     .class_init = fsl_imx7_class_init,
 562 };
 563
 564 static void fsl_imx7_register_types(void)
 565 {
 566     type_register_static(&fsl_imx7_type_info);
 567 }
 568 type_init(fsl_imx7_register_types)