target/i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/units.h"
  22 #include "qemu/cutils.h"
  23 #include "qemu/bitops.h"
  24 #include "qemu/qemu-print.h"
  25
  26 #include "cpu.h"
  27 #include "exec/exec-all.h"
  28 #include "sysemu/kvm.h"
  29 #include "sysemu/reset.h"
  30 #include "sysemu/hvf.h"
  31 #include "sysemu/cpus.h"
  32 #include "sysemu/xen.h"
  33 #include "kvm_i386.h"
  34 #include "sev_i386.h"
  35
  36 #include "qemu/error-report.h"
  37 #include "qemu/module.h"
  38 #include "qemu/option.h"
  39 #include "qemu/config-file.h"
  40 #include "qapi/error.h"
  41 #include "qapi/qapi-visit-machine.h"
  42 #include "qapi/qapi-visit-run-state.h"
  43 #include "qapi/qmp/qdict.h"
  44 #include "qapi/qmp/qerror.h"
  45 #include "qapi/visitor.h"
  46 #include "qom/qom-qobject.h"
  47 #include "sysemu/arch_init.h"
  48 #include "qapi/qapi-commands-machine-target.h"
  49
  50 #include "standard-headers/asm-x86/kvm_para.h"
  51
  52 #include "sysemu/sysemu.h"
  53 #include "sysemu/tcg.h"
  54 #include "hw/qdev-properties.h"
  55 #include "hw/i386/topology.h"
  56 #ifndef CONFIG_USER_ONLY
  57 #include "exec/address-spaces.h"
  58 #include "hw/i386/apic_internal.h"
  59 #include "hw/boards.h"
  60 #endif
  61
  62 #include "disas/capstone.h"
  63
  64 /* Helpers for building CPUID[2] descriptors: */
  65
  66 struct CPUID2CacheDescriptorInfo {
  67     enum CacheType type;
  68     int level;
  69     int size;
  70     int line_size;
  71     int associativity;
  72 };
  73
  74 /*
  75  * Known CPUID 2 cache descriptors.
  76  * From Intel SDM Volume 2A, CPUID instruction
  77  */
  78 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
  79     [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size =   8 * KiB,
  80                .associativity = 4,  .line_size = 32, },
  81     [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  16 * KiB,
  82                .associativity = 4,  .line_size = 32, },
  83     [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
  84                .associativity = 4,  .line_size = 64, },
  85     [0x0A] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
  86                .associativity = 2,  .line_size = 32, },
  87     [0x0C] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
  88                .associativity = 4,  .line_size = 32, },
  89     [0x0D] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
  90                .associativity = 4,  .line_size = 64, },
  91     [0x0E] = { .level = 1, .type = DATA_CACHE,        .size =  24 * KiB,
  92                .associativity = 6,  .line_size = 64, },
  93     [0x1D] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
  94                .associativity = 2,  .line_size = 64, },
  95     [0x21] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
  96                .associativity = 8,  .line_size = 64, },
  97     /* lines per sector is not supported cpuid2_cache_descriptor(),
  98     * so descriptors 0x22, 0x23 are not included
  99     */
 100     [0x24] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 101                .associativity = 16, .line_size = 64, },
 102     /* lines per sector is not supported cpuid2_cache_descriptor(),
 103     * so descriptors 0x25, 0x20 are not included
 104     */
 105     [0x2C] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
 106                .associativity = 8,  .line_size = 64, },
 107     [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
 108                .associativity = 8,  .line_size = 64, },
 109     [0x41] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
 110                .associativity = 4,  .line_size = 32, },
 111     [0x42] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
 112                .associativity = 4,  .line_size = 32, },
 113     [0x43] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 114                .associativity = 4,  .line_size = 32, },
 115     [0x44] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 116                .associativity = 4,  .line_size = 32, },
 117     [0x45] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 118                .associativity = 4,  .line_size = 32, },
 119     [0x46] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
 120                .associativity = 4,  .line_size = 64, },
 121     [0x47] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
 122                .associativity = 8,  .line_size = 64, },
 123     [0x48] = { .level = 2, .type = UNIFIED_CACHE,     .size =   3 * MiB,
 124                .associativity = 12, .line_size = 64, },
 125     /* Descriptor 0x49 depends on CPU family/model, so it is not included */
 126     [0x4A] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
 127                .associativity = 12, .line_size = 64, },
 128     [0x4B] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
 129                .associativity = 16, .line_size = 64, },
 130     [0x4C] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
 131                .associativity = 12, .line_size = 64, },
 132     [0x4D] = { .level = 3, .type = UNIFIED_CACHE,     .size =  16 * MiB,
 133                .associativity = 16, .line_size = 64, },
 134     [0x4E] = { .level = 2, .type = UNIFIED_CACHE,     .size =   6 * MiB,
 135                .associativity = 24, .line_size = 64, },
 136     [0x60] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
 137                .associativity = 8,  .line_size = 64, },
 138     [0x66] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
 139                .associativity = 4,  .line_size = 64, },
 140     [0x67] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
 141                .associativity = 4,  .line_size = 64, },
 142     [0x68] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
 143                .associativity = 4,  .line_size = 64, },
 144     [0x78] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 145                .associativity = 4,  .line_size = 64, },
 146     /* lines per sector is not supported cpuid2_cache_descriptor(),
 147     * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
 148     */
 149     [0x7D] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 150                .associativity = 8,  .line_size = 64, },
 151     [0x7F] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 152                .associativity = 2,  .line_size = 64, },
 153     [0x80] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 154                .associativity = 8,  .line_size = 64, },
 155     [0x82] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
 156                .associativity = 8,  .line_size = 32, },
 157     [0x83] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 158                .associativity = 8,  .line_size = 32, },
 159     [0x84] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 160                .associativity = 8,  .line_size = 32, },
 161     [0x85] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 162                .associativity = 8,  .line_size = 32, },
 163     [0x86] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 164                .associativity = 4,  .line_size = 64, },
 165     [0x87] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 166                .associativity = 8,  .line_size = 64, },
 167     [0xD0] = { .level = 3, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 168                .associativity = 4,  .line_size = 64, },
 169     [0xD1] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 170                .associativity = 4,  .line_size = 64, },
 171     [0xD2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 172                .associativity = 4,  .line_size = 64, },
 173     [0xD6] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 174                .associativity = 8,  .line_size = 64, },
 175     [0xD7] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 176                .associativity = 8,  .line_size = 64, },
 177     [0xD8] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
 178                .associativity = 8,  .line_size = 64, },
 179     [0xDC] = { .level = 3, .type = UNIFIED_CACHE,     .size = 1.5 * MiB,
 180                .associativity = 12, .line_size = 64, },
 181     [0xDD] = { .level = 3, .type = UNIFIED_CACHE,     .size =   3 * MiB,
 182                .associativity = 12, .line_size = 64, },
 183     [0xDE] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
 184                .associativity = 12, .line_size = 64, },
 185     [0xE2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 186                .associativity = 16, .line_size = 64, },
 187     [0xE3] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
 188                .associativity = 16, .line_size = 64, },
 189     [0xE4] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
 190                .associativity = 16, .line_size = 64, },
 191     [0xEA] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
 192                .associativity = 24, .line_size = 64, },
 193     [0xEB] = { .level = 3, .type = UNIFIED_CACHE,     .size =  18 * MiB,
 194                .associativity = 24, .line_size = 64, },
 195     [0xEC] = { .level = 3, .type = UNIFIED_CACHE,     .size =  24 * MiB,
 196                .associativity = 24, .line_size = 64, },
 197 };
 198
 199 /*
 200  * "CPUID leaf 2 does not report cache descriptor information,
 201  * use CPUID leaf 4 to query cache parameters"
 202  */
 203 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
 204
 205 /*
 206  * Return a CPUID 2 cache descriptor for a given cache.
 207  * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
 208  */
 209 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
 210 {
 211     int i;
 212
 213     assert(cache->size > 0);
 214     assert(cache->level > 0);
 215     assert(cache->line_size > 0);
 216     assert(cache->associativity > 0);
 217     for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
 218         struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
 219         if (d->level == cache->level && d->type == cache->type &&
 220             d->size == cache->size && d->line_size == cache->line_size &&
 221             d->associativity == cache->associativity) {
 222                 return i;
 223             }
 224     }
 225
 226     return CACHE_DESCRIPTOR_UNAVAILABLE;
 227 }
 228
 229 /* CPUID Leaf 4 constants: */
 230
 231 /* EAX: */
 232 #define CACHE_TYPE_D    1
 233 #define CACHE_TYPE_I    2
 234 #define CACHE_TYPE_UNIFIED   3
 235
 236 #define CACHE_LEVEL(l)        (l << 5)
 237
 238 #define CACHE_SELF_INIT_LEVEL (1 << 8)
 239
 240 /* EDX: */
 241 #define CACHE_NO_INVD_SHARING   (1 << 0)
 242 #define CACHE_INCLUSIVE       (1 << 1)
 243 #define CACHE_COMPLEX_IDX     (1 << 2)
 244
 245 /* Encode CacheType for CPUID[4].EAX */
 246 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
 247                        ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
 248                        ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
 249                        0 /* Invalid value */)
 250
 251
 252 /* Encode cache info for CPUID[4] */
 253 static void encode_cache_cpuid4(CPUCacheInfo *cache,
 254                                 int num_apic_ids, int num_cores,
 255                                 uint32_t *eax, uint32_t *ebx,
 256                                 uint32_t *ecx, uint32_t *edx)
 257 {
 258     assert(cache->size == cache->line_size * cache->associativity *
 259                           cache->partitions * cache->sets);
 260
 261     assert(num_apic_ids > 0);
 262     *eax = CACHE_TYPE(cache->type) |
 263            CACHE_LEVEL(cache->level) |
 264            (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
 265            ((num_cores - 1) << 26) |
 266            ((num_apic_ids - 1) << 14);
 267
 268     assert(cache->line_size > 0);
 269     assert(cache->partitions > 0);
 270     assert(cache->associativity > 0);
 271     /* We don't implement fully-associative caches */
 272     assert(cache->associativity < cache->sets);
 273     *ebx = (cache->line_size - 1) |
 274            ((cache->partitions - 1) << 12) |
 275            ((cache->associativity - 1) << 22);
 276
 277     assert(cache->sets > 0);
 278     *ecx = cache->sets - 1;
 279
 280     *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
 281            (cache->inclusive ? CACHE_INCLUSIVE : 0) |
 282            (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
 283 }
 284
 285 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
 286 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
 287 {
 288     assert(cache->size % 1024 == 0);
 289     assert(cache->lines_per_tag > 0);
 290     assert(cache->associativity > 0);
 291     assert(cache->line_size > 0);
 292     return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
 293            (cache->lines_per_tag << 8) | (cache->line_size);
 294 }
 295
 296 #define ASSOC_FULL 0xFF
 297
 298 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
 299 #define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
 300                           a ==   2 ? 0x2 : \
 301                           a ==   4 ? 0x4 : \
 302                           a ==   8 ? 0x6 : \
 303                           a ==  16 ? 0x8 : \
 304                           a ==  32 ? 0xA : \
 305                           a ==  48 ? 0xB : \
 306                           a ==  64 ? 0xC : \
 307                           a ==  96 ? 0xD : \
 308                           a == 128 ? 0xE : \
 309                           a == ASSOC_FULL ? 0xF : \
 310                           0 /* invalid value */)
 311
 312 /*
 313  * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
 314  * @l3 can be NULL.
 315  */
 316 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
 317                                        CPUCacheInfo *l3,
 318                                        uint32_t *ecx, uint32_t *edx)
 319 {
 320     assert(l2->size % 1024 == 0);
 321     assert(l2->associativity > 0);
 322     assert(l2->lines_per_tag > 0);
 323     assert(l2->line_size > 0);
 324     *ecx = ((l2->size / 1024) << 16) |
 325            (AMD_ENC_ASSOC(l2->associativity) << 12) |
 326            (l2->lines_per_tag << 8) | (l2->line_size);
 327
 328     if (l3) {
 329         assert(l3->size % (512 * 1024) == 0);
 330         assert(l3->associativity > 0);
 331         assert(l3->lines_per_tag > 0);
 332         assert(l3->line_size > 0);
 333         *edx = ((l3->size / (512 * 1024)) << 18) |
 334                (AMD_ENC_ASSOC(l3->associativity) << 12) |
 335                (l3->lines_per_tag << 8) | (l3->line_size);
 336     } else {
 337         *edx = 0;
 338     }
 339 }
 340
 341 /* Encode cache info for CPUID[8000001D] */
 342 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
 343                                        X86CPUTopoInfo *topo_info,
 344                                        uint32_t *eax, uint32_t *ebx,
 345                                        uint32_t *ecx, uint32_t *edx)
 346 {
 347     uint32_t l3_threads;
 348     assert(cache->size == cache->line_size * cache->associativity *
 349                           cache->partitions * cache->sets);
 350
 351     *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
 352                (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
 353
 354     /* L3 is shared among multiple cores */
 355     if (cache->level == 3) {
 356         l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
 357         *eax |= (l3_threads - 1) << 14;
 358     } else {
 359         *eax |= ((topo_info->threads_per_core - 1) << 14);
 360     }
 361
 362     assert(cache->line_size > 0);
 363     assert(cache->partitions > 0);
 364     assert(cache->associativity > 0);
 365     /* We don't implement fully-associative caches */
 366     assert(cache->associativity < cache->sets);
 367     *ebx = (cache->line_size - 1) |
 368            ((cache->partitions - 1) << 12) |
 369            ((cache->associativity - 1) << 22);
 370
 371     assert(cache->sets > 0);
 372     *ecx = cache->sets - 1;
 373
 374     *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
 375            (cache->inclusive ? CACHE_INCLUSIVE : 0) |
 376            (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
 377 }
 378
 379 /* Encode cache info for CPUID[8000001E] */
 380 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
 381                                       uint32_t *eax, uint32_t *ebx,
 382                                       uint32_t *ecx, uint32_t *edx)
 383 {
 384     X86CPUTopoIDs topo_ids;
 385
 386     x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
 387
 388     *eax = cpu->apic_id;
 389
 390     /*
 391      * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
 392      * Read-only. Reset: 0000_XXXXh.
 393      * See Core::X86::Cpuid::ExtApicId.
 394      * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
 395      * Bits Description
 396      * 31:16 Reserved.
 397      * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
 398      *      The number of threads per core is ThreadsPerCore+1.
 399      *  7:0 CoreId: core ID. Read-only. Reset: XXh.
 400      *
 401      *  NOTE: CoreId is already part of apic_id. Just use it. We can
 402      *  use all the 8 bits to represent the core_id here.
 403      */
 404     *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
 405
 406     /*
 407      * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
 408      * Read-only. Reset: 0000_0XXXh.
 409      * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
 410      * Bits Description
 411      * 31:11 Reserved.
 412      * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
 413      *      ValidValues:
 414      *      Value Description
 415      *      000b  1 node per processor.
 416      *      001b  2 nodes per processor.
 417      *      010b Reserved.
 418      *      011b 4 nodes per processor.
 419      *      111b-100b Reserved.
 420      *  7:0 NodeId: Node ID. Read-only. Reset: XXh.
 421      *
 422      * NOTE: Hardware reserves 3 bits for number of nodes per processor.
 423      * But users can create more nodes than the actual hardware can
 424      * support. To genaralize we can use all the upper 8 bits for nodes.
 425      * NodeId is combination of node and socket_id which is already decoded
 426      * in apic_id. Just use it by shifting.
 427      */
 428     *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
 429            ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
 430
 431     *edx = 0;
 432 }
 433
 434 /*
 435  * Definitions of the hardcoded cache entries we expose:
 436  * These are legacy cache values. If there is a need to change any
 437  * of these values please use builtin_x86_defs
 438  */
 439
 440 /* L1 data cache: */
 441 static CPUCacheInfo legacy_l1d_cache = {
 442     .type = DATA_CACHE,
 443     .level = 1,
 444     .size = 32 * KiB,
 445     .self_init = 1,
 446     .line_size = 64,
 447     .associativity = 8,
 448     .sets = 64,
 449     .partitions = 1,
 450     .no_invd_sharing = true,
 451 };
 452
 453 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 454 static CPUCacheInfo legacy_l1d_cache_amd = {
 455     .type = DATA_CACHE,
 456     .level = 1,
 457     .size = 64 * KiB,
 458     .self_init = 1,
 459     .line_size = 64,
 460     .associativity = 2,
 461     .sets = 512,
 462     .partitions = 1,
 463     .lines_per_tag = 1,
 464     .no_invd_sharing = true,
 465 };
 466
 467 /* L1 instruction cache: */
 468 static CPUCacheInfo legacy_l1i_cache = {
 469     .type = INSTRUCTION_CACHE,
 470     .level = 1,
 471     .size = 32 * KiB,
 472     .self_init = 1,
 473     .line_size = 64,
 474     .associativity = 8,
 475     .sets = 64,
 476     .partitions = 1,
 477     .no_invd_sharing = true,
 478 };
 479
 480 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 481 static CPUCacheInfo legacy_l1i_cache_amd = {
 482     .type = INSTRUCTION_CACHE,
 483     .level = 1,
 484     .size = 64 * KiB,
 485     .self_init = 1,
 486     .line_size = 64,
 487     .associativity = 2,
 488     .sets = 512,
 489     .partitions = 1,
 490     .lines_per_tag = 1,
 491     .no_invd_sharing = true,
 492 };
 493
 494 /* Level 2 unified cache: */
 495 static CPUCacheInfo legacy_l2_cache = {
 496     .type = UNIFIED_CACHE,
 497     .level = 2,
 498     .size = 4 * MiB,
 499     .self_init = 1,
 500     .line_size = 64,
 501     .associativity = 16,
 502     .sets = 4096,
 503     .partitions = 1,
 504     .no_invd_sharing = true,
 505 };
 506
 507 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
 508 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
 509     .type = UNIFIED_CACHE,
 510     .level = 2,
 511     .size = 2 * MiB,
 512     .line_size = 64,
 513     .associativity = 8,
 514 };
 515
 516
 517 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
 518 static CPUCacheInfo legacy_l2_cache_amd = {
 519     .type = UNIFIED_CACHE,
 520     .level = 2,
 521     .size = 512 * KiB,
 522     .line_size = 64,
 523     .lines_per_tag = 1,
 524     .associativity = 16,
 525     .sets = 512,
 526     .partitions = 1,
 527 };
 528
 529 /* Level 3 unified cache: */
 530 static CPUCacheInfo legacy_l3_cache = {
 531     .type = UNIFIED_CACHE,
 532     .level = 3,
 533     .size = 16 * MiB,
 534     .line_size = 64,
 535     .associativity = 16,
 536     .sets = 16384,
 537     .partitions = 1,
 538     .lines_per_tag = 1,
 539     .self_init = true,
 540     .inclusive = true,
 541     .complex_indexing = true,
 542 };
 543
 544 /* TLB definitions: */
 545
 546 #define L1_DTLB_2M_ASSOC       1
 547 #define L1_DTLB_2M_ENTRIES   255
 548 #define L1_DTLB_4K_ASSOC       1
 549 #define L1_DTLB_4K_ENTRIES   255
 550
 551 #define L1_ITLB_2M_ASSOC       1
 552 #define L1_ITLB_2M_ENTRIES   255
 553 #define L1_ITLB_4K_ASSOC       1
 554 #define L1_ITLB_4K_ENTRIES   255
 555
 556 #define L2_DTLB_2M_ASSOC       0 /* disabled */
 557 #define L2_DTLB_2M_ENTRIES     0 /* disabled */
 558 #define L2_DTLB_4K_ASSOC       4
 559 #define L2_DTLB_4K_ENTRIES   512
 560
 561 #define L2_ITLB_2M_ASSOC       0 /* disabled */
 562 #define L2_ITLB_2M_ENTRIES     0 /* disabled */
 563 #define L2_ITLB_4K_ASSOC       4
 564 #define L2_ITLB_4K_ENTRIES   512
 565
 566 /* CPUID Leaf 0x14 constants: */
 567 #define INTEL_PT_MAX_SUBLEAF     0x1
 568 /*
 569  * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
 570  *          MSR can be accessed;
 571  * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
 572  * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
 573  *          of Intel PT MSRs across warm reset;
 574  * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
 575  */
 576 #define INTEL_PT_MINIMAL_EBX     0xf
 577 /*
 578  * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
 579  *          IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
 580  *          accessed;
 581  * bit[01]: ToPA tables can hold any number of output entries, up to the
 582  *          maximum allowed by the MaskOrTableOffset field of
 583  *          IA32_RTIT_OUTPUT_MASK_PTRS;
 584  * bit[02]: Support Single-Range Output scheme;
 585  */
 586 #define INTEL_PT_MINIMAL_ECX     0x7
 587 /* generated packets which contain IP payloads have LIP values */
 588 #define INTEL_PT_IP_LIP          (1 << 31)
 589 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
 590 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
 591 #define INTEL_PT_MTC_BITMAP      (0x0249 << 16) /* Support ART(0,3,6,9) */
 592 #define INTEL_PT_CYCLE_BITMAP    0x1fff         /* Support 0,2^(0~11) */
 593 #define INTEL_PT_PSB_BITMAP      (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
 594
 595 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 596                                      uint32_t vendor2, uint32_t vendor3)
 597 {
 598     int i;
 599     for (i = 0; i < 4; i++) {
 600         dst[i] = vendor1 >> (8 * i);
 601         dst[i + 4] = vendor2 >> (8 * i);
 602         dst[i + 8] = vendor3 >> (8 * i);
 603     }
 604     dst[CPUID_VENDOR_SZ] = '\0';
 605 }
 606
 607 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 608 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 609           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 610 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 611           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 612           CPUID_PSE36 | CPUID_FXSR)
 613 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 614 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 615           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 616           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 617           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 618
 619 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 620           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 621           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 622           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 623           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
 624           /* partly implemented:
 625           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
 626           /* missing:
 627           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 628 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 629           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 630           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 631           CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */   \
 632           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
 633           CPUID_EXT_RDRAND)
 634           /* missing:
 635           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 636           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 637           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 638           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
 639           CPUID_EXT_F16C */
 640
 641 #ifdef TARGET_X86_64
 642 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
 643 #else
 644 #define TCG_EXT2_X86_64_FEATURES 0
 645 #endif
 646
 647 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 648           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 649           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
 650           TCG_EXT2_X86_64_FEATURES)
 651 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 652           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 653 #define TCG_EXT4_FEATURES 0
 654 #define TCG_SVM_FEATURES CPUID_SVM_NPT
 655 #define TCG_KVM_FEATURES 0
 656 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
 657           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
 658           CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT |            \
 659           CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
 660           CPUID_7_0_EBX_ERMS)
 661           /* missing:
 662           CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 663           CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 664           CPUID_7_0_EBX_RDSEED */
 665 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
 666           /* CPUID_7_0_ECX_OSPKE is dynamic */ \
 667           CPUID_7_0_ECX_LA57)
 668 #define TCG_7_0_EDX_FEATURES 0
 669 #define TCG_7_1_EAX_FEATURES 0
 670 #define TCG_APM_FEATURES 0
 671 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
 672 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
 673           /* missing:
 674           CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
 675 #define TCG_14_0_ECX_FEATURES 0
 676
 677 typedef enum FeatureWordType {
 678    CPUID_FEATURE_WORD,
 679    MSR_FEATURE_WORD,
 680 } FeatureWordType;
 681
 682 typedef struct FeatureWordInfo {
 683     FeatureWordType type;
 684     /* feature flags names are taken from "Intel Processor Identification and
 685      * the CPUID Instruction" and AMD's "CPUID Specification".
 686      * In cases of disagreement between feature naming conventions,
 687      * aliases may be added.
 688      */
 689     const char *feat_names[64];
 690     union {
 691         /* If type==CPUID_FEATURE_WORD */
 692         struct {
 693             uint32_t eax;   /* Input EAX for CPUID */
 694             bool needs_ecx; /* CPUID instruction uses ECX as input */
 695             uint32_t ecx;   /* Input ECX value for CPUID */
 696             int reg;        /* output register (R_* constant) */
 697         } cpuid;
 698         /* If type==MSR_FEATURE_WORD */
 699         struct {
 700             uint32_t index;
 701         } msr;
 702     };
 703     uint64_t tcg_features; /* Feature flags supported by TCG */
 704     uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
 705     uint64_t migratable_flags; /* Feature flags known to be migratable */
 706     /* Features that shouldn't be auto-enabled by "-cpu host" */
 707     uint64_t no_autoenable_flags;
 708 } FeatureWordInfo;
 709
 710 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 711     [FEAT_1_EDX] = {
 712         .type = CPUID_FEATURE_WORD,
 713         .feat_names = {
 714             "fpu", "vme", "de", "pse",
 715             "tsc", "msr", "pae", "mce",
 716             "cx8", "apic", NULL, "sep",
 717             "mtrr", "pge", "mca", "cmov",
 718             "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
 719             NULL, "ds" /* Intel dts */, "acpi", "mmx",
 720             "fxsr", "sse", "sse2", "ss",
 721             "ht" /* Intel htt */, "tm", "ia64", "pbe",
 722         },
 723         .cpuid = {.eax = 1, .reg = R_EDX, },
 724         .tcg_features = TCG_FEATURES,
 725     },
 726     [FEAT_1_ECX] = {
 727         .type = CPUID_FEATURE_WORD,
 728         .feat_names = {
 729             "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
 730             "ds-cpl", "vmx", "smx", "est",
 731             "tm2", "ssse3", "cid", NULL,
 732             "fma", "cx16", "xtpr", "pdcm",
 733             NULL, "pcid", "dca", "sse4.1",
 734             "sse4.2", "x2apic", "movbe", "popcnt",
 735             "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
 736             "avx", "f16c", "rdrand", "hypervisor",
 737         },
 738         .cpuid = { .eax = 1, .reg = R_ECX, },
 739         .tcg_features = TCG_EXT_FEATURES,
 740     },
 741     /* Feature names that are already defined on feature_name[] but
 742      * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
 743      * names on feat_names below. They are copied automatically
 744      * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
 745      */
 746     [FEAT_8000_0001_EDX] = {
 747         .type = CPUID_FEATURE_WORD,
 748         .feat_names = {
 749             NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
 750             NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
 751             NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
 752             NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
 753             NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
 754             "nx", NULL, "mmxext", NULL /* mmx */,
 755             NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
 756             NULL, "lm", "3dnowext", "3dnow",
 757         },
 758         .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
 759         .tcg_features = TCG_EXT2_FEATURES,
 760     },
 761     [FEAT_8000_0001_ECX] = {
 762         .type = CPUID_FEATURE_WORD,
 763         .feat_names = {
 764             "lahf-lm", "cmp-legacy", "svm", "extapic",
 765             "cr8legacy", "abm", "sse4a", "misalignsse",
 766             "3dnowprefetch", "osvw", "ibs", "xop",
 767             "skinit", "wdt", NULL, "lwp",
 768             "fma4", "tce", NULL, "nodeid-msr",
 769             NULL, "tbm", "topoext", "perfctr-core",
 770             "perfctr-nb", NULL, NULL, NULL,
 771             NULL, NULL, NULL, NULL,
 772         },
 773         .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
 774         .tcg_features = TCG_EXT3_FEATURES,
 775         /*
 776          * TOPOEXT is always allowed but can't be enabled blindly by
 777          * "-cpu host", as it requires consistent cache topology info
 778          * to be provided so it doesn't confuse guests.
 779          */
 780         .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
 781     },
 782     [FEAT_C000_0001_EDX] = {
 783         .type = CPUID_FEATURE_WORD,
 784         .feat_names = {
 785             NULL, NULL, "xstore", "xstore-en",
 786             NULL, NULL, "xcrypt", "xcrypt-en",
 787             "ace2", "ace2-en", "phe", "phe-en",
 788             "pmm", "pmm-en", NULL, NULL,
 789             NULL, NULL, NULL, NULL,
 790             NULL, NULL, NULL, NULL,
 791             NULL, NULL, NULL, NULL,
 792             NULL, NULL, NULL, NULL,
 793         },
 794         .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
 795         .tcg_features = TCG_EXT4_FEATURES,
 796     },
 797     [FEAT_KVM] = {
 798         .type = CPUID_FEATURE_WORD,
 799         .feat_names = {
 800             "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
 801             "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
 802             NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
 803             "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", NULL,
 804             NULL, NULL, NULL, NULL,
 805             NULL, NULL, NULL, NULL,
 806             "kvmclock-stable-bit", NULL, NULL, NULL,
 807             NULL, NULL, NULL, NULL,
 808         },
 809         .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
 810         .tcg_features = TCG_KVM_FEATURES,
 811     },
 812     [FEAT_KVM_HINTS] = {
 813         .type = CPUID_FEATURE_WORD,
 814         .feat_names = {
 815             "kvm-hint-dedicated", NULL, NULL, NULL,
 816             NULL, NULL, NULL, NULL,
 817             NULL, NULL, NULL, NULL,
 818             NULL, NULL, NULL, NULL,
 819             NULL, NULL, NULL, NULL,
 820             NULL, NULL, NULL, NULL,
 821             NULL, NULL, NULL, NULL,
 822             NULL, NULL, NULL, NULL,
 823         },
 824         .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
 825         .tcg_features = TCG_KVM_FEATURES,
 826         /*
 827          * KVM hints aren't auto-enabled by -cpu host, they need to be
 828          * explicitly enabled in the command-line.
 829          */
 830         .no_autoenable_flags = ~0U,
 831     },
 832     /*
 833      * .feat_names are commented out for Hyper-V enlightenments because we
 834      * don't want to have two different ways for enabling them on QEMU command
 835      * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
 836      * enabling several feature bits simultaneously, exposing these bits
 837      * individually may just confuse guests.
 838      */
 839     [FEAT_HYPERV_EAX] = {
 840         .type = CPUID_FEATURE_WORD,
 841         .feat_names = {
 842             NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
 843             NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
 844             NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
 845             NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
 846             NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
 847             NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
 848             NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
 849             NULL, NULL,
 850             NULL, NULL, NULL, NULL,
 851             NULL, NULL, NULL, NULL,
 852             NULL, NULL, NULL, NULL,
 853             NULL, NULL, NULL, NULL,
 854         },
 855         .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
 856     },
 857     [FEAT_HYPERV_EBX] = {
 858         .type = CPUID_FEATURE_WORD,
 859         .feat_names = {
 860             NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
 861             NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
 862             NULL /* hv_post_messages */, NULL /* hv_signal_events */,
 863             NULL /* hv_create_port */, NULL /* hv_connect_port */,
 864             NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
 865             NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
 866             NULL, NULL,
 867             NULL, NULL, NULL, NULL,
 868             NULL, NULL, NULL, NULL,
 869             NULL, NULL, NULL, NULL,
 870             NULL, NULL, NULL, NULL,
 871         },
 872         .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
 873     },
 874     [FEAT_HYPERV_EDX] = {
 875         .type = CPUID_FEATURE_WORD,
 876         .feat_names = {
 877             NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
 878             NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
 879             NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
 880             NULL, NULL,
 881             NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
 882             NULL, NULL, NULL, NULL,
 883             NULL, NULL, NULL, NULL,
 884             NULL, NULL, NULL, NULL,
 885             NULL, NULL, NULL, NULL,
 886             NULL, NULL, NULL, NULL,
 887         },
 888         .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
 889     },
 890     [FEAT_HV_RECOMM_EAX] = {
 891         .type = CPUID_FEATURE_WORD,
 892         .feat_names = {
 893             NULL /* hv_recommend_pv_as_switch */,
 894             NULL /* hv_recommend_pv_tlbflush_local */,
 895             NULL /* hv_recommend_pv_tlbflush_remote */,
 896             NULL /* hv_recommend_msr_apic_access */,
 897             NULL /* hv_recommend_msr_reset */,
 898             NULL /* hv_recommend_relaxed_timing */,
 899             NULL /* hv_recommend_dma_remapping */,
 900             NULL /* hv_recommend_int_remapping */,
 901             NULL /* hv_recommend_x2apic_msrs */,
 902             NULL /* hv_recommend_autoeoi_deprecation */,
 903             NULL /* hv_recommend_pv_ipi */,
 904             NULL /* hv_recommend_ex_hypercalls */,
 905             NULL /* hv_hypervisor_is_nested */,
 906             NULL /* hv_recommend_int_mbec */,
 907             NULL /* hv_recommend_evmcs */,
 908             NULL,
 909             NULL, NULL, NULL, NULL,
 910             NULL, NULL, NULL, NULL,
 911             NULL, NULL, NULL, NULL,
 912             NULL, NULL, NULL, NULL,
 913         },
 914         .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
 915     },
 916     [FEAT_HV_NESTED_EAX] = {
 917         .type = CPUID_FEATURE_WORD,
 918         .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
 919     },
 920     [FEAT_SVM] = {
 921         .type = CPUID_FEATURE_WORD,
 922         .feat_names = {
 923             "npt", "lbrv", "svm-lock", "nrip-save",
 924             "tsc-scale", "vmcb-clean",  "flushbyasid", "decodeassists",
 925             NULL, NULL, "pause-filter", NULL,
 926             "pfthreshold", NULL, NULL, NULL,
 927             NULL, NULL, NULL, NULL,
 928             NULL, NULL, NULL, NULL,
 929             NULL, NULL, NULL, NULL,
 930             NULL, NULL, NULL, NULL,
 931         },
 932         .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
 933         .tcg_features = TCG_SVM_FEATURES,
 934     },
 935     [FEAT_7_0_EBX] = {
 936         .type = CPUID_FEATURE_WORD,
 937         .feat_names = {
 938             "fsgsbase", "tsc-adjust", NULL, "bmi1",
 939             "hle", "avx2", NULL, "smep",
 940             "bmi2", "erms", "invpcid", "rtm",
 941             NULL, NULL, "mpx", NULL,
 942             "avx512f", "avx512dq", "rdseed", "adx",
 943             "smap", "avx512ifma", "pcommit", "clflushopt",
 944             "clwb", "intel-pt", "avx512pf", "avx512er",
 945             "avx512cd", "sha-ni", "avx512bw", "avx512vl",
 946         },
 947         .cpuid = {
 948             .eax = 7,
 949             .needs_ecx = true, .ecx = 0,
 950             .reg = R_EBX,
 951         },
 952         .tcg_features = TCG_7_0_EBX_FEATURES,
 953     },
 954     [FEAT_7_0_ECX] = {
 955         .type = CPUID_FEATURE_WORD,
 956         .feat_names = {
 957             NULL, "avx512vbmi", "umip", "pku",
 958             NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
 959             "gfni", "vaes", "vpclmulqdq", "avx512vnni",
 960             "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
 961             "la57", NULL, NULL, NULL,
 962             NULL, NULL, "rdpid", NULL,
 963             NULL, "cldemote", NULL, "movdiri",
 964             "movdir64b", NULL, NULL, NULL,
 965         },
 966         .cpuid = {
 967             .eax = 7,
 968             .needs_ecx = true, .ecx = 0,
 969             .reg = R_ECX,
 970         },
 971         .tcg_features = TCG_7_0_ECX_FEATURES,
 972     },
 973     [FEAT_7_0_EDX] = {
 974         .type = CPUID_FEATURE_WORD,
 975         .feat_names = {
 976             NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
 977             "fsrm", NULL, NULL, NULL,
 978             "avx512-vp2intersect", NULL, "md-clear", NULL,
 979             NULL, NULL, "serialize", NULL,
 980             "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
 981             NULL, NULL, NULL, NULL,
 982             NULL, NULL, "spec-ctrl", "stibp",
 983             NULL, "arch-capabilities", "core-capability", "ssbd",
 984         },
 985         .cpuid = {
 986             .eax = 7,
 987             .needs_ecx = true, .ecx = 0,
 988             .reg = R_EDX,
 989         },
 990         .tcg_features = TCG_7_0_EDX_FEATURES,
 991     },
 992     [FEAT_7_1_EAX] = {
 993         .type = CPUID_FEATURE_WORD,
 994         .feat_names = {
 995             NULL, NULL, NULL, NULL,
 996             NULL, "avx512-bf16", NULL, NULL,
 997             NULL, NULL, NULL, NULL,
 998             NULL, NULL, NULL, NULL,
 999             NULL, NULL, NULL, NULL,
1000             NULL, NULL, NULL, NULL,
1001             NULL, NULL, NULL, NULL,
1002             NULL, NULL, NULL, NULL,
1003         },
1004         .cpuid = {
1005             .eax = 7,
1006             .needs_ecx = true, .ecx = 1,
1007             .reg = R_EAX,
1008         },
1009         .tcg_features = TCG_7_1_EAX_FEATURES,
1010     },
1011     [FEAT_8000_0007_EDX] = {
1012         .type = CPUID_FEATURE_WORD,
1013         .feat_names = {
1014             NULL, NULL, NULL, NULL,
1015             NULL, NULL, NULL, NULL,
1016             "invtsc", NULL, NULL, NULL,
1017             NULL, NULL, NULL, NULL,
1018             NULL, NULL, NULL, NULL,
1019             NULL, NULL, NULL, NULL,
1020             NULL, NULL, NULL, NULL,
1021             NULL, NULL, NULL, NULL,
1022         },
1023         .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1024         .tcg_features = TCG_APM_FEATURES,
1025         .unmigratable_flags = CPUID_APM_INVTSC,
1026     },
1027     [FEAT_8000_0008_EBX] = {
1028         .type = CPUID_FEATURE_WORD,
1029         .feat_names = {
1030             "clzero", NULL, "xsaveerptr", NULL,
1031             NULL, NULL, NULL, NULL,
1032             NULL, "wbnoinvd", NULL, NULL,
1033             "ibpb", NULL, NULL, "amd-stibp",
1034             NULL, NULL, NULL, NULL,
1035             NULL, NULL, NULL, NULL,
1036             "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1037             NULL, NULL, NULL, NULL,
1038         },
1039         .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1040         .tcg_features = 0,
1041         .unmigratable_flags = 0,
1042     },
1043     [FEAT_XSAVE] = {
1044         .type = CPUID_FEATURE_WORD,
1045         .feat_names = {
1046             "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1047             NULL, NULL, NULL, NULL,
1048             NULL, NULL, NULL, NULL,
1049             NULL, NULL, NULL, NULL,
1050             NULL, NULL, NULL, NULL,
1051             NULL, NULL, NULL, NULL,
1052             NULL, NULL, NULL, NULL,
1053             NULL, NULL, NULL, NULL,
1054         },
1055         .cpuid = {
1056             .eax = 0xd,
1057             .needs_ecx = true, .ecx = 1,
1058             .reg = R_EAX,
1059         },
1060         .tcg_features = TCG_XSAVE_FEATURES,
1061     },
1062     [FEAT_6_EAX] = {
1063         .type = CPUID_FEATURE_WORD,
1064         .feat_names = {
1065             NULL, NULL, "arat", NULL,
1066             NULL, NULL, NULL, NULL,
1067             NULL, NULL, NULL, NULL,
1068             NULL, NULL, NULL, NULL,
1069             NULL, NULL, NULL, NULL,
1070             NULL, NULL, NULL, NULL,
1071             NULL, NULL, NULL, NULL,
1072             NULL, NULL, NULL, NULL,
1073         },
1074         .cpuid = { .eax = 6, .reg = R_EAX, },
1075         .tcg_features = TCG_6_EAX_FEATURES,
1076     },
1077     [FEAT_XSAVE_COMP_LO] = {
1078         .type = CPUID_FEATURE_WORD,
1079         .cpuid = {
1080             .eax = 0xD,
1081             .needs_ecx = true, .ecx = 0,
1082             .reg = R_EAX,
1083         },
1084         .tcg_features = ~0U,
1085         .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1086             XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1087             XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1088             XSTATE_PKRU_MASK,
1089     },
1090     [FEAT_XSAVE_COMP_HI] = {
1091         .type = CPUID_FEATURE_WORD,
1092         .cpuid = {
1093             .eax = 0xD,
1094             .needs_ecx = true, .ecx = 0,
1095             .reg = R_EDX,
1096         },
1097         .tcg_features = ~0U,
1098     },
1099     /*Below are MSR exposed features*/
1100     [FEAT_ARCH_CAPABILITIES] = {
1101         .type = MSR_FEATURE_WORD,
1102         .feat_names = {
1103             "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1104             "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1105             "taa-no", NULL, NULL, NULL,
1106             NULL, NULL, NULL, NULL,
1107             NULL, NULL, NULL, NULL,
1108             NULL, NULL, NULL, NULL,
1109             NULL, NULL, NULL, NULL,
1110             NULL, NULL, NULL, NULL,
1111         },
1112         .msr = {
1113             .index = MSR_IA32_ARCH_CAPABILITIES,
1114         },
1115     },
1116     [FEAT_CORE_CAPABILITY] = {
1117         .type = MSR_FEATURE_WORD,
1118         .feat_names = {
1119             NULL, NULL, NULL, NULL,
1120             NULL, "split-lock-detect", NULL, NULL,
1121             NULL, NULL, NULL, NULL,
1122             NULL, NULL, NULL, NULL,
1123             NULL, NULL, NULL, NULL,
1124             NULL, NULL, NULL, NULL,
1125             NULL, NULL, NULL, NULL,
1126             NULL, NULL, NULL, NULL,
1127         },
1128         .msr = {
1129             .index = MSR_IA32_CORE_CAPABILITY,
1130         },
1131     },
1132     [FEAT_PERF_CAPABILITIES] = {
1133         .type = MSR_FEATURE_WORD,
1134         .feat_names = {
1135             NULL, NULL, NULL, NULL,
1136             NULL, NULL, NULL, NULL,
1137             NULL, NULL, NULL, NULL,
1138             NULL, "full-width-write", NULL, NULL,
1139             NULL, NULL, NULL, NULL,
1140             NULL, NULL, NULL, NULL,
1141             NULL, NULL, NULL, NULL,
1142             NULL, NULL, NULL, NULL,
1143         },
1144         .msr = {
1145             .index = MSR_IA32_PERF_CAPABILITIES,
1146         },
1147     },
1148
1149     [FEAT_VMX_PROCBASED_CTLS] = {
1150         .type = MSR_FEATURE_WORD,
1151         .feat_names = {
1152             NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1153             NULL, NULL, NULL, "vmx-hlt-exit",
1154             NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1155             "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1156             "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1157             "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1158             "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1159             "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1160         },
1161         .msr = {
1162             .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1163         }
1164     },
1165
1166     [FEAT_VMX_SECONDARY_CTLS] = {
1167         .type = MSR_FEATURE_WORD,
1168         .feat_names = {
1169             "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1170             "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1171             "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1172             "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1173             "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1174             "vmx-xsaves", NULL, NULL, NULL,
1175             NULL, NULL, NULL, NULL,
1176             NULL, NULL, NULL, NULL,
1177         },
1178         .msr = {
1179             .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1180         }
1181     },
1182
1183     [FEAT_VMX_PINBASED_CTLS] = {
1184         .type = MSR_FEATURE_WORD,
1185         .feat_names = {
1186             "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1187             NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1188             NULL, NULL, NULL, NULL,
1189             NULL, NULL, NULL, NULL,
1190             NULL, NULL, NULL, NULL,
1191             NULL, NULL, NULL, NULL,
1192             NULL, NULL, NULL, NULL,
1193             NULL, NULL, NULL, NULL,
1194         },
1195         .msr = {
1196             .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1197         }
1198     },
1199
1200     [FEAT_VMX_EXIT_CTLS] = {
1201         .type = MSR_FEATURE_WORD,
1202         /*
1203          * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1204          * the LM CPUID bit.
1205          */
1206         .feat_names = {
1207             NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1208             NULL, NULL, NULL, NULL,
1209             NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1210             "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1211             NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1212             "vmx-exit-save-efer", "vmx-exit-load-efer",
1213                 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1214             NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1215             NULL, NULL, NULL, NULL,
1216         },
1217         .msr = {
1218             .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1219         }
1220     },
1221
1222     [FEAT_VMX_ENTRY_CTLS] = {
1223         .type = MSR_FEATURE_WORD,
1224         .feat_names = {
1225             NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1226             NULL, NULL, NULL, NULL,
1227             NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1228             NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1229             "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1230             NULL, NULL, NULL, NULL,
1231             NULL, NULL, NULL, NULL,
1232             NULL, NULL, NULL, NULL,
1233         },
1234         .msr = {
1235             .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1236         }
1237     },
1238
1239     [FEAT_VMX_MISC] = {
1240         .type = MSR_FEATURE_WORD,
1241         .feat_names = {
1242             NULL, NULL, NULL, NULL,
1243             NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1244             "vmx-activity-wait-sipi", NULL, NULL, NULL,
1245             NULL, NULL, NULL, NULL,
1246             NULL, NULL, NULL, NULL,
1247             NULL, NULL, NULL, NULL,
1248             NULL, NULL, NULL, NULL,
1249             NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1250         },
1251         .msr = {
1252             .index = MSR_IA32_VMX_MISC,
1253         }
1254     },
1255
1256     [FEAT_VMX_EPT_VPID_CAPS] = {
1257         .type = MSR_FEATURE_WORD,
1258         .feat_names = {
1259             "vmx-ept-execonly", NULL, NULL, NULL,
1260             NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1261             NULL, NULL, NULL, NULL,
1262             NULL, NULL, NULL, NULL,
1263             "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1264             "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1265             NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1266             NULL, NULL, NULL, NULL,
1267             "vmx-invvpid", NULL, NULL, NULL,
1268             NULL, NULL, NULL, NULL,
1269             "vmx-invvpid-single-addr", "vmx-invept-single-context",
1270                 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1271             NULL, NULL, NULL, NULL,
1272             NULL, NULL, NULL, NULL,
1273             NULL, NULL, NULL, NULL,
1274             NULL, NULL, NULL, NULL,
1275             NULL, NULL, NULL, NULL,
1276         },
1277         .msr = {
1278             .index = MSR_IA32_VMX_EPT_VPID_CAP,
1279         }
1280     },
1281
1282     [FEAT_VMX_BASIC] = {
1283         .type = MSR_FEATURE_WORD,
1284         .feat_names = {
1285             [54] = "vmx-ins-outs",
1286             [55] = "vmx-true-ctls",
1287         },
1288         .msr = {
1289             .index = MSR_IA32_VMX_BASIC,
1290         },
1291         /* Just to be safe - we don't support setting the MSEG version field.  */
1292         .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1293     },
1294
1295     [FEAT_VMX_VMFUNC] = {
1296         .type = MSR_FEATURE_WORD,
1297         .feat_names = {
1298             [0] = "vmx-eptp-switching",
1299         },
1300         .msr = {
1301             .index = MSR_IA32_VMX_VMFUNC,
1302         }
1303     },
1304
1305     [FEAT_14_0_ECX] = {
1306         .type = CPUID_FEATURE_WORD,
1307         .feat_names = {
1308             NULL, NULL, NULL, NULL,
1309             NULL, NULL, NULL, NULL,
1310             NULL, NULL, NULL, NULL,
1311             NULL, NULL, NULL, NULL,
1312             NULL, NULL, NULL, NULL,
1313             NULL, NULL, NULL, NULL,
1314             NULL, NULL, NULL, NULL,
1315             NULL, NULL, NULL, "intel-pt-lip",
1316         },
1317         .cpuid = {
1318             .eax = 0x14,
1319             .needs_ecx = true, .ecx = 0,
1320             .reg = R_ECX,
1321         },
1322         .tcg_features = TCG_14_0_ECX_FEATURES,
1323      },
1324
1325 };
1326
1327 typedef struct FeatureMask {
1328     FeatureWord index;
1329     uint64_t mask;
1330 } FeatureMask;
1331
1332 typedef struct FeatureDep {
1333     FeatureMask from, to;
1334 } FeatureDep;
1335
1336 static FeatureDep feature_dependencies[] = {
1337     {
1338         .from = { FEAT_7_0_EDX,             CPUID_7_0_EDX_ARCH_CAPABILITIES },
1339         .to = { FEAT_ARCH_CAPABILITIES,     ~0ull },
1340     },
1341     {
1342         .from = { FEAT_7_0_EDX,             CPUID_7_0_EDX_CORE_CAPABILITY },
1343         .to = { FEAT_CORE_CAPABILITY,       ~0ull },
1344     },
1345     {
1346         .from = { FEAT_1_ECX,             CPUID_EXT_PDCM },
1347         .to = { FEAT_PERF_CAPABILITIES,       ~0ull },
1348     },
1349     {
1350         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1351         .to = { FEAT_VMX_PROCBASED_CTLS,    ~0ull },
1352     },
1353     {
1354         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1355         .to = { FEAT_VMX_PINBASED_CTLS,     ~0ull },
1356     },
1357     {
1358         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1359         .to = { FEAT_VMX_EXIT_CTLS,         ~0ull },
1360     },
1361     {
1362         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1363         .to = { FEAT_VMX_ENTRY_CTLS,        ~0ull },
1364     },
1365     {
1366         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1367         .to = { FEAT_VMX_MISC,              ~0ull },
1368     },
1369     {
1370         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1371         .to = { FEAT_VMX_BASIC,             ~0ull },
1372     },
1373     {
1374         .from = { FEAT_8000_0001_EDX,       CPUID_EXT2_LM },
1375         .to = { FEAT_VMX_ENTRY_CTLS,        VMX_VM_ENTRY_IA32E_MODE },
1376     },
1377     {
1378         .from = { FEAT_VMX_PROCBASED_CTLS,  VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1379         .to = { FEAT_VMX_SECONDARY_CTLS,    ~0ull },
1380     },
1381     {
1382         .from = { FEAT_XSAVE,               CPUID_XSAVE_XSAVES },
1383         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_XSAVES },
1384     },
1385     {
1386         .from = { FEAT_1_ECX,               CPUID_EXT_RDRAND },
1387         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_RDRAND_EXITING },
1388     },
1389     {
1390         .from = { FEAT_7_0_EBX,             CPUID_7_0_EBX_INVPCID },
1391         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1392     },
1393     {
1394         .from = { FEAT_7_0_EBX,             CPUID_7_0_EBX_RDSEED },
1395         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_RDSEED_EXITING },
1396     },
1397     {
1398         .from = { FEAT_7_0_EBX,             CPUID_7_0_EBX_INTEL_PT },
1399         .to = { FEAT_14_0_ECX,              ~0ull },
1400     },
1401     {
1402         .from = { FEAT_8000_0001_EDX,       CPUID_EXT2_RDTSCP },
1403         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_RDTSCP },
1404     },
1405     {
1406         .from = { FEAT_VMX_SECONDARY_CTLS,  VMX_SECONDARY_EXEC_ENABLE_EPT },
1407         .to = { FEAT_VMX_EPT_VPID_CAPS,     0xffffffffull },
1408     },
1409     {
1410         .from = { FEAT_VMX_SECONDARY_CTLS,  VMX_SECONDARY_EXEC_ENABLE_EPT },
1411         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1412     },
1413     {
1414         .from = { FEAT_VMX_SECONDARY_CTLS,  VMX_SECONDARY_EXEC_ENABLE_VPID },
1415         .to = { FEAT_VMX_EPT_VPID_CAPS,     0xffffffffull << 32 },
1416     },
1417     {
1418         .from = { FEAT_VMX_SECONDARY_CTLS,  VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1419         .to = { FEAT_VMX_VMFUNC,            ~0ull },
1420     },
1421     {
1422         .from = { FEAT_8000_0001_ECX,       CPUID_EXT3_SVM },
1423         .to = { FEAT_SVM,                   ~0ull },
1424     },
1425 };
1426
1427 typedef struct X86RegisterInfo32 {
1428     /* Name of register */
1429     const char *name;
1430     /* QAPI enum value register */
1431     X86CPURegister32 qapi_enum;
1432 } X86RegisterInfo32;
1433
1434 #define REGISTER(reg) \
1435     [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1436 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1437     REGISTER(EAX),
1438     REGISTER(ECX),
1439     REGISTER(EDX),
1440     REGISTER(EBX),
1441     REGISTER(ESP),
1442     REGISTER(EBP),
1443     REGISTER(ESI),
1444     REGISTER(EDI),
1445 };
1446 #undef REGISTER
1447
1448 typedef struct ExtSaveArea {
1449     uint32_t feature, bits;
1450     uint32_t offset, size;
1451 } ExtSaveArea;
1452
1453 static const ExtSaveArea x86_ext_save_areas[] = {
1454     [XSTATE_FP_BIT] = {
1455         /* x87 FP state component is always enabled if XSAVE is supported */
1456         .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1457         /* x87 state is in the legacy region of the XSAVE area */
1458         .offset = 0,
1459         .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1460     },
1461     [XSTATE_SSE_BIT] = {
1462         /* SSE state component is always enabled if XSAVE is supported */
1463         .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1464         /* SSE state is in the legacy region of the XSAVE area */
1465         .offset = 0,
1466         .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1467     },
1468     [XSTATE_YMM_BIT] =
1469           { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1470             .offset = offsetof(X86XSaveArea, avx_state),
1471             .size = sizeof(XSaveAVX) },
1472     [XSTATE_BNDREGS_BIT] =
1473           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1474             .offset = offsetof(X86XSaveArea, bndreg_state),
1475             .size = sizeof(XSaveBNDREG)  },
1476     [XSTATE_BNDCSR_BIT] =
1477           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1478             .offset = offsetof(X86XSaveArea, bndcsr_state),
1479             .size = sizeof(XSaveBNDCSR)  },
1480     [XSTATE_OPMASK_BIT] =
1481           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1482             .offset = offsetof(X86XSaveArea, opmask_state),
1483             .size = sizeof(XSaveOpmask) },
1484     [XSTATE_ZMM_Hi256_BIT] =
1485           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1486             .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1487             .size = sizeof(XSaveZMM_Hi256) },
1488     [XSTATE_Hi16_ZMM_BIT] =
1489           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1490             .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1491             .size = sizeof(XSaveHi16_ZMM) },
1492     [XSTATE_PKRU_BIT] =
1493           { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1494             .offset = offsetof(X86XSaveArea, pkru_state),
1495             .size = sizeof(XSavePKRU) },
1496 };
1497
1498 static uint32_t xsave_area_size(uint64_t mask)
1499 {
1500     int i;
1501     uint64_t ret = 0;
1502
1503     for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1504         const ExtSaveArea *esa = &x86_ext_save_areas[i];
1505         if ((mask >> i) & 1) {
1506             ret = MAX(ret, esa->offset + esa->size);
1507         }
1508     }
1509     return ret;
1510 }
1511
1512 static inline bool accel_uses_host_cpuid(void)
1513 {
1514     return kvm_enabled() || hvf_enabled();
1515 }
1516
1517 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1518 {
1519     return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1520            cpu->env.features[FEAT_XSAVE_COMP_LO];
1521 }
1522
1523 const char *get_register_name_32(unsigned int reg)
1524 {
1525     if (reg >= CPU_NB_REGS32) {
1526         return NULL;
1527     }
1528     return x86_reg_info_32[reg].name;
1529 }
1530
1531 /*
1532  * Returns the set of feature flags that are supported and migratable by
1533  * QEMU, for a given FeatureWord.
1534  */
1535 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1536 {
1537     FeatureWordInfo *wi = &feature_word_info[w];
1538     uint64_t r = 0;
1539     int i;
1540
1541     for (i = 0; i < 64; i++) {
1542         uint64_t f = 1ULL << i;
1543
1544         /* If the feature name is known, it is implicitly considered migratable,
1545          * unless it is explicitly set in unmigratable_flags */
1546         if ((wi->migratable_flags & f) ||
1547             (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1548             r |= f;
1549         }
1550     }
1551     return r;
1552 }
1553
1554 void host_cpuid(uint32_t function, uint32_t count,
1555                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1556 {
1557     uint32_t vec[4];
1558
1559 #ifdef __x86_64__
1560     asm volatile("cpuid"
1561                  : "=a"(vec[0]), "=b"(vec[1]),
1562                    "=c"(vec[2]), "=d"(vec[3])
1563                  : "0"(function), "c"(count) : "cc");
1564 #elif defined(__i386__)
1565     asm volatile("pusha \n\t"
1566                  "cpuid \n\t"
1567                  "mov %%eax, 0(%2) \n\t"
1568                  "mov %%ebx, 4(%2) \n\t"
1569                  "mov %%ecx, 8(%2) \n\t"
1570                  "mov %%edx, 12(%2) \n\t"
1571                  "popa"
1572                  : : "a"(function), "c"(count), "S"(vec)
1573                  : "memory", "cc");
1574 #else
1575     abort();
1576 #endif
1577
1578     if (eax)
1579         *eax = vec[0];
1580     if (ebx)
1581         *ebx = vec[1];
1582     if (ecx)
1583         *ecx = vec[2];
1584     if (edx)
1585         *edx = vec[3];
1586 }
1587
1588 void host_vendor_fms(char *vendor, int *family, int *model, int *stepping)
1589 {
1590     uint32_t eax, ebx, ecx, edx;
1591
1592     host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1593     x86_cpu_vendor_words2str(vendor, ebx, edx, ecx);
1594
1595     host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1596     if (family) {
1597         *family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1598     }
1599     if (model) {
1600         *model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1601     }
1602     if (stepping) {
1603         *stepping = eax & 0x0F;
1604     }
1605 }
1606
1607 /* CPU class name definitions: */
1608
1609 /* Return type name for a given CPU model name
1610  * Caller is responsible for freeing the returned string.
1611  */
1612 static char *x86_cpu_type_name(const char *model_name)
1613 {
1614     return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1615 }
1616
1617 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1618 {
1619     g_autofree char *typename = x86_cpu_type_name(cpu_model);
1620     return object_class_by_name(typename);
1621 }
1622
1623 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1624 {
1625     const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1626     assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1627     return g_strndup(class_name,
1628                      strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1629 }
1630
1631 typedef struct PropValue {
1632     const char *prop, *value;
1633 } PropValue;
1634
1635 typedef struct X86CPUVersionDefinition {
1636     X86CPUVersion version;
1637     const char *alias;
1638     const char *note;
1639     PropValue *props;
1640 } X86CPUVersionDefinition;
1641
1642 /* Base definition for a CPU model */
1643 typedef struct X86CPUDefinition {
1644     const char *name;
1645     uint32_t level;
1646     uint32_t xlevel;
1647     /* vendor is zero-terminated, 12 character ASCII string */
1648     char vendor[CPUID_VENDOR_SZ + 1];
1649     int family;
1650     int model;
1651     int stepping;
1652     FeatureWordArray features;
1653     const char *model_id;
1654     CPUCaches *cache_info;
1655     /*
1656      * Definitions for alternative versions of CPU model.
1657      * List is terminated by item with version == 0.
1658      * If NULL, version 1 will be registered automatically.
1659      */
1660     const X86CPUVersionDefinition *versions;
1661     const char *deprecation_note;
1662 } X86CPUDefinition;
1663
1664 /* Reference to a specific CPU model version */
1665 struct X86CPUModel {
1666     /* Base CPU definition */
1667     X86CPUDefinition *cpudef;
1668     /* CPU model version */
1669     X86CPUVersion version;
1670     const char *note;
1671     /*
1672      * If true, this is an alias CPU model.
1673      * This matters only for "-cpu help" and query-cpu-definitions
1674      */
1675     bool is_alias;
1676 };
1677
1678 /* Get full model name for CPU version */
1679 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1680                                           X86CPUVersion version)
1681 {
1682     assert(version > 0);
1683     return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1684 }
1685
1686 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1687 {
1688     /* When X86CPUDefinition::versions is NULL, we register only v1 */
1689     static const X86CPUVersionDefinition default_version_list[] = {
1690         { 1 },
1691         { /* end of list */ }
1692     };
1693
1694     return def->versions ?: default_version_list;
1695 }
1696
1697 static CPUCaches epyc_cache_info = {
1698     .l1d_cache = &(CPUCacheInfo) {
1699         .type = DATA_CACHE,
1700         .level = 1,
1701         .size = 32 * KiB,
1702         .line_size = 64,
1703         .associativity = 8,
1704         .partitions = 1,
1705         .sets = 64,
1706         .lines_per_tag = 1,
1707         .self_init = 1,
1708         .no_invd_sharing = true,
1709     },
1710     .l1i_cache = &(CPUCacheInfo) {
1711         .type = INSTRUCTION_CACHE,
1712         .level = 1,
1713         .size = 64 * KiB,
1714         .line_size = 64,
1715         .associativity = 4,
1716         .partitions = 1,
1717         .sets = 256,
1718         .lines_per_tag = 1,
1719         .self_init = 1,
1720         .no_invd_sharing = true,
1721     },
1722     .l2_cache = &(CPUCacheInfo) {
1723         .type = UNIFIED_CACHE,
1724         .level = 2,
1725         .size = 512 * KiB,
1726         .line_size = 64,
1727         .associativity = 8,
1728         .partitions = 1,
1729         .sets = 1024,
1730         .lines_per_tag = 1,
1731     },
1732     .l3_cache = &(CPUCacheInfo) {
1733         .type = UNIFIED_CACHE,
1734         .level = 3,
1735         .size = 8 * MiB,
1736         .line_size = 64,
1737         .associativity = 16,
1738         .partitions = 1,
1739         .sets = 8192,
1740         .lines_per_tag = 1,
1741         .self_init = true,
1742         .inclusive = true,
1743         .complex_indexing = true,
1744     },
1745 };
1746
1747 static CPUCaches epyc_rome_cache_info = {
1748     .l1d_cache = &(CPUCacheInfo) {
1749         .type = DATA_CACHE,
1750         .level = 1,
1751         .size = 32 * KiB,
1752         .line_size = 64,
1753         .associativity = 8,
1754         .partitions = 1,
1755         .sets = 64,
1756         .lines_per_tag = 1,
1757         .self_init = 1,
1758         .no_invd_sharing = true,
1759     },
1760     .l1i_cache = &(CPUCacheInfo) {
1761         .type = INSTRUCTION_CACHE,
1762         .level = 1,
1763         .size = 32 * KiB,
1764         .line_size = 64,
1765         .associativity = 8,
1766         .partitions = 1,
1767         .sets = 64,
1768         .lines_per_tag = 1,
1769         .self_init = 1,
1770         .no_invd_sharing = true,
1771     },
1772     .l2_cache = &(CPUCacheInfo) {
1773         .type = UNIFIED_CACHE,
1774         .level = 2,
1775         .size = 512 * KiB,
1776         .line_size = 64,
1777         .associativity = 8,
1778         .partitions = 1,
1779         .sets = 1024,
1780         .lines_per_tag = 1,
1781     },
1782     .l3_cache = &(CPUCacheInfo) {
1783         .type = UNIFIED_CACHE,
1784         .level = 3,
1785         .size = 16 * MiB,
1786         .line_size = 64,
1787         .associativity = 16,
1788         .partitions = 1,
1789         .sets = 16384,
1790         .lines_per_tag = 1,
1791         .self_init = true,
1792         .inclusive = true,
1793         .complex_indexing = true,
1794     },
1795 };
1796
1797 /* The following VMX features are not supported by KVM and are left out in the
1798  * CPU definitions:
1799  *
1800  *  Dual-monitor support (all processors)
1801  *  Entry to SMM
1802  *  Deactivate dual-monitor treatment
1803  *  Number of CR3-target values
1804  *  Shutdown activity state
1805  *  Wait-for-SIPI activity state
1806  *  PAUSE-loop exiting (Westmere and newer)
1807  *  EPT-violation #VE (Broadwell and newer)
1808  *  Inject event with insn length=0 (Skylake and newer)
1809  *  Conceal non-root operation from PT
1810  *  Conceal VM exits from PT
1811  *  Conceal VM entries from PT
1812  *  Enable ENCLS exiting
1813  *  Mode-based execute control (XS/XU)
1814  s  TSC scaling (Skylake Server and newer)
1815  *  GPA translation for PT (IceLake and newer)
1816  *  User wait and pause
1817  *  ENCLV exiting
1818  *  Load IA32_RTIT_CTL
1819  *  Clear IA32_RTIT_CTL
1820  *  Advanced VM-exit information for EPT violations
1821  *  Sub-page write permissions
1822  *  PT in VMX operation
1823  */
1824
1825 static X86CPUDefinition builtin_x86_defs[] = {
1826     {
1827         .name = "qemu64",
1828         .level = 0xd,
1829         .vendor = CPUID_VENDOR_AMD,
1830         .family = 6,
1831         .model = 6,
1832         .stepping = 3,
1833         .features[FEAT_1_EDX] =
1834             PPRO_FEATURES |
1835             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1836             CPUID_PSE36,
1837         .features[FEAT_1_ECX] =
1838             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1839         .features[FEAT_8000_0001_EDX] =
1840             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1841         .features[FEAT_8000_0001_ECX] =
1842             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1843         .xlevel = 0x8000000A,
1844         .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1845     },
1846     {
1847         .name = "phenom",
1848         .level = 5,
1849         .vendor = CPUID_VENDOR_AMD,
1850         .family = 16,
1851         .model = 2,
1852         .stepping = 3,
1853         /* Missing: CPUID_HT */
1854         .features[FEAT_1_EDX] =
1855             PPRO_FEATURES |
1856             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1857             CPUID_PSE36 | CPUID_VME,
1858         .features[FEAT_1_ECX] =
1859             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1860             CPUID_EXT_POPCNT,
1861         .features[FEAT_8000_0001_EDX] =
1862             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1863             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1864             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1865         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1866                     CPUID_EXT3_CR8LEG,
1867                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1868                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1869         .features[FEAT_8000_0001_ECX] =
1870             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1871             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1872         /* Missing: CPUID_SVM_LBRV */
1873         .features[FEAT_SVM] =
1874             CPUID_SVM_NPT,
1875         .xlevel = 0x8000001A,
1876         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1877     },
1878     {
1879         .name = "core2duo",
1880         .level = 10,
1881         .vendor = CPUID_VENDOR_INTEL,
1882         .family = 6,
1883         .model = 15,
1884         .stepping = 11,
1885         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1886         .features[FEAT_1_EDX] =
1887             PPRO_FEATURES |
1888             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1889             CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1890         /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1891          * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1892         .features[FEAT_1_ECX] =
1893             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1894             CPUID_EXT_CX16,
1895         .features[FEAT_8000_0001_EDX] =
1896             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1897         .features[FEAT_8000_0001_ECX] =
1898             CPUID_EXT3_LAHF_LM,
1899         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1900         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1901         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1902         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1903         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1904              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1905         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1906              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1907              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1908              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1909              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1910              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1911              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1912              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1913              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1914              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1915         .features[FEAT_VMX_SECONDARY_CTLS] =
1916              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1917         .xlevel = 0x80000008,
1918         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
1919     },
1920     {
1921         .name = "kvm64",
1922         .level = 0xd,
1923         .vendor = CPUID_VENDOR_INTEL,
1924         .family = 15,
1925         .model = 6,
1926         .stepping = 1,
1927         /* Missing: CPUID_HT */
1928         .features[FEAT_1_EDX] =
1929             PPRO_FEATURES | CPUID_VME |
1930             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1931             CPUID_PSE36,
1932         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1933         .features[FEAT_1_ECX] =
1934             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1935         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1936         .features[FEAT_8000_0001_EDX] =
1937             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1938         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1939                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1940                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1941                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1942         .features[FEAT_8000_0001_ECX] =
1943             0,
1944         /* VMX features from Cedar Mill/Prescott */
1945         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1946         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1947         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1948         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1949              VMX_PIN_BASED_NMI_EXITING,
1950         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1951              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1952              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1953              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1954              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1955              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1956              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1957              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1958         .xlevel = 0x80000008,
1959         .model_id = "Common KVM processor"
1960     },
1961     {
1962         .name = "qemu32",
1963         .level = 4,
1964         .vendor = CPUID_VENDOR_INTEL,
1965         .family = 6,
1966         .model = 6,
1967         .stepping = 3,
1968         .features[FEAT_1_EDX] =
1969             PPRO_FEATURES,
1970         .features[FEAT_1_ECX] =
1971             CPUID_EXT_SSE3,
1972         .xlevel = 0x80000004,
1973         .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1974     },
1975     {
1976         .name = "kvm32",
1977         .level = 5,
1978         .vendor = CPUID_VENDOR_INTEL,
1979         .family = 15,
1980         .model = 6,
1981         .stepping = 1,
1982         .features[FEAT_1_EDX] =
1983             PPRO_FEATURES | CPUID_VME |
1984             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
1985         .features[FEAT_1_ECX] =
1986             CPUID_EXT_SSE3,
1987         .features[FEAT_8000_0001_ECX] =
1988             0,
1989         /* VMX features from Yonah */
1990         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1991         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1992         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1993         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1994              VMX_PIN_BASED_NMI_EXITING,
1995         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1996              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1997              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1998              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1999              VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2000              VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2001              VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2002         .xlevel = 0x80000008,
2003         .model_id = "Common 32-bit KVM processor"
2004     },
2005     {
2006         .name = "coreduo",
2007         .level = 10,
2008         .vendor = CPUID_VENDOR_INTEL,
2009         .family = 6,
2010         .model = 14,
2011         .stepping = 8,
2012         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2013         .features[FEAT_1_EDX] =
2014             PPRO_FEATURES | CPUID_VME |
2015             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2016             CPUID_SS,
2017         /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2018          * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2019         .features[FEAT_1_ECX] =
2020             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
2021         .features[FEAT_8000_0001_EDX] =
2022             CPUID_EXT2_NX,
2023         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2024         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2025         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2026         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2027              VMX_PIN_BASED_NMI_EXITING,
2028         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2029              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2030              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2031              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2032              VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2033              VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2034              VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2035         .xlevel = 0x80000008,
2036         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
2037     },
2038     {
2039         .name = "486",
2040         .level = 1,
2041         .vendor = CPUID_VENDOR_INTEL,
2042         .family = 4,
2043         .model = 8,
2044         .stepping = 0,
2045         .features[FEAT_1_EDX] =
2046             I486_FEATURES,
2047         .xlevel = 0,
2048         .model_id = "",
2049     },
2050     {
2051         .name = "pentium",
2052         .level = 1,
2053         .vendor = CPUID_VENDOR_INTEL,
2054         .family = 5,
2055         .model = 4,
2056         .stepping = 3,
2057         .features[FEAT_1_EDX] =
2058             PENTIUM_FEATURES,
2059         .xlevel = 0,
2060         .model_id = "",
2061     },
2062     {
2063         .name = "pentium2",
2064         .level = 2,
2065         .vendor = CPUID_VENDOR_INTEL,
2066         .family = 6,
2067         .model = 5,
2068         .stepping = 2,
2069         .features[FEAT_1_EDX] =
2070             PENTIUM2_FEATURES,
2071         .xlevel = 0,
2072         .model_id = "",
2073     },
2074     {
2075         .name = "pentium3",
2076         .level = 3,
2077         .vendor = CPUID_VENDOR_INTEL,
2078         .family = 6,
2079         .model = 7,
2080         .stepping = 3,
2081         .features[FEAT_1_EDX] =
2082             PENTIUM3_FEATURES,
2083         .xlevel = 0,
2084         .model_id = "",
2085     },
2086     {
2087         .name = "athlon",
2088         .level = 2,
2089         .vendor = CPUID_VENDOR_AMD,
2090         .family = 6,
2091         .model = 2,
2092         .stepping = 3,
2093         .features[FEAT_1_EDX] =
2094             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2095             CPUID_MCA,
2096         .features[FEAT_8000_0001_EDX] =
2097             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2098         .xlevel = 0x80000008,
2099         .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2100     },
2101     {
2102         .name = "n270",
2103         .level = 10,
2104         .vendor = CPUID_VENDOR_INTEL,
2105         .family = 6,
2106         .model = 28,
2107         .stepping = 2,
2108         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2109         .features[FEAT_1_EDX] =
2110             PPRO_FEATURES |
2111             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2112             CPUID_ACPI | CPUID_SS,
2113             /* Some CPUs got no CPUID_SEP */
2114         /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2115          * CPUID_EXT_XTPR */
2116         .features[FEAT_1_ECX] =
2117             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2118             CPUID_EXT_MOVBE,
2119         .features[FEAT_8000_0001_EDX] =
2120             CPUID_EXT2_NX,
2121         .features[FEAT_8000_0001_ECX] =
2122             CPUID_EXT3_LAHF_LM,
2123         .xlevel = 0x80000008,
2124         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
2125     },
2126     {
2127         .name = "Conroe",
2128         .level = 10,
2129         .vendor = CPUID_VENDOR_INTEL,
2130         .family = 6,
2131         .model = 15,
2132         .stepping = 3,
2133         .features[FEAT_1_EDX] =
2134             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2135             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2136             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2137             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2138             CPUID_DE | CPUID_FP87,
2139         .features[FEAT_1_ECX] =
2140             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2141         .features[FEAT_8000_0001_EDX] =
2142             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2143         .features[FEAT_8000_0001_ECX] =
2144             CPUID_EXT3_LAHF_LM,
2145         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2146         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2147         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2148         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2149         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2150              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2151         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2152              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2153              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2154              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2155              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2156              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2157              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2158              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2159              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2160              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2161         .features[FEAT_VMX_SECONDARY_CTLS] =
2162              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2163         .xlevel = 0x80000008,
2164         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2165     },
2166     {
2167         .name = "Penryn",
2168         .level = 10,
2169         .vendor = CPUID_VENDOR_INTEL,
2170         .family = 6,
2171         .model = 23,
2172         .stepping = 3,
2173         .features[FEAT_1_EDX] =
2174             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2175             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2176             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2177             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2178             CPUID_DE | CPUID_FP87,
2179         .features[FEAT_1_ECX] =
2180             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2181             CPUID_EXT_SSE3,
2182         .features[FEAT_8000_0001_EDX] =
2183             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2184         .features[FEAT_8000_0001_ECX] =
2185             CPUID_EXT3_LAHF_LM,
2186         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2187         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2188              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2189         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2190              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2191         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2192         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2193              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2194         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2195              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2196              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2197              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2198              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2199              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2200              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2201              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2202              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2203              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2204         .features[FEAT_VMX_SECONDARY_CTLS] =
2205              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2206              VMX_SECONDARY_EXEC_WBINVD_EXITING,
2207         .xlevel = 0x80000008,
2208         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2209     },
2210     {
2211         .name = "Nehalem",
2212         .level = 11,
2213         .vendor = CPUID_VENDOR_INTEL,
2214         .family = 6,
2215         .model = 26,
2216         .stepping = 3,
2217         .features[FEAT_1_EDX] =
2218             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2219             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2220             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2221             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2222             CPUID_DE | CPUID_FP87,
2223         .features[FEAT_1_ECX] =
2224             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2225             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2226         .features[FEAT_8000_0001_EDX] =
2227             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2228         .features[FEAT_8000_0001_ECX] =
2229             CPUID_EXT3_LAHF_LM,
2230         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2231              MSR_VMX_BASIC_TRUE_CTLS,
2232         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2233              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2234              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2235         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2236              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2237              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2238              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2239              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2240              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2241              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2242         .features[FEAT_VMX_EXIT_CTLS] =
2243              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2244              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2245              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2246              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2247              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2248         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2249         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2250              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2251              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2252         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2253              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2254              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2255              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2256              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2257              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2258              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2259              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2260              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2261              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2262              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2263              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2264         .features[FEAT_VMX_SECONDARY_CTLS] =
2265              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2266              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2267              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2268              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2269              VMX_SECONDARY_EXEC_ENABLE_VPID,
2270         .xlevel = 0x80000008,
2271         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2272         .versions = (X86CPUVersionDefinition[]) {
2273             { .version = 1 },
2274             {
2275                 .version = 2,
2276                 .alias = "Nehalem-IBRS",
2277                 .props = (PropValue[]) {
2278                     { "spec-ctrl", "on" },
2279                     { "model-id",
2280                       "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2281                     { /* end of list */ }
2282                 }
2283             },
2284             { /* end of list */ }
2285         }
2286     },
2287     {
2288         .name = "Westmere",
2289         .level = 11,
2290         .vendor = CPUID_VENDOR_INTEL,
2291         .family = 6,
2292         .model = 44,
2293         .stepping = 1,
2294         .features[FEAT_1_EDX] =
2295             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2296             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2297             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2298             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2299             CPUID_DE | CPUID_FP87,
2300         .features[FEAT_1_ECX] =
2301             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2302             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2303             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2304         .features[FEAT_8000_0001_EDX] =
2305             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2306         .features[FEAT_8000_0001_ECX] =
2307             CPUID_EXT3_LAHF_LM,
2308         .features[FEAT_6_EAX] =
2309             CPUID_6_EAX_ARAT,
2310         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2311              MSR_VMX_BASIC_TRUE_CTLS,
2312         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2313              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2314              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2315         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2316              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2317              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2318              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2319              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2320              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2321              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2322         .features[FEAT_VMX_EXIT_CTLS] =
2323              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2324              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2325              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2326              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2327              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2328         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2329              MSR_VMX_MISC_STORE_LMA,
2330         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2331              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2332              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2333         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2334              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2335              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2336              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2337              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2338              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2339              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2340              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2341              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2342              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2343              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2344              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2345         .features[FEAT_VMX_SECONDARY_CTLS] =
2346              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2347              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2348              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2349              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2350              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2351         .xlevel = 0x80000008,
2352         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2353         .versions = (X86CPUVersionDefinition[]) {
2354             { .version = 1 },
2355             {
2356                 .version = 2,
2357                 .alias = "Westmere-IBRS",
2358                 .props = (PropValue[]) {
2359                     { "spec-ctrl", "on" },
2360                     { "model-id",
2361                       "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2362                     { /* end of list */ }
2363                 }
2364             },
2365             { /* end of list */ }
2366         }
2367     },
2368     {
2369         .name = "SandyBridge",
2370         .level = 0xd,
2371         .vendor = CPUID_VENDOR_INTEL,
2372         .family = 6,
2373         .model = 42,
2374         .stepping = 1,
2375         .features[FEAT_1_EDX] =
2376             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2377             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2378             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2379             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2380             CPUID_DE | CPUID_FP87,
2381         .features[FEAT_1_ECX] =
2382             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2383             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2384             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2385             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2386             CPUID_EXT_SSE3,
2387         .features[FEAT_8000_0001_EDX] =
2388             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2389             CPUID_EXT2_SYSCALL,
2390         .features[FEAT_8000_0001_ECX] =
2391             CPUID_EXT3_LAHF_LM,
2392         .features[FEAT_XSAVE] =
2393             CPUID_XSAVE_XSAVEOPT,
2394         .features[FEAT_6_EAX] =
2395             CPUID_6_EAX_ARAT,
2396         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2397              MSR_VMX_BASIC_TRUE_CTLS,
2398         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2399              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2400              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2401         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2402              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2403              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2404              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2405              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2406              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2407              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2408         .features[FEAT_VMX_EXIT_CTLS] =
2409              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2410              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2411              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2412              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2413              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2414         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2415              MSR_VMX_MISC_STORE_LMA,
2416         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2417              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2418              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2419         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2420              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2421              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2422              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2423              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2424              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2425              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2426              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2427              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2428              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2429              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2430              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2431         .features[FEAT_VMX_SECONDARY_CTLS] =
2432              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2433              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2434              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2435              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2436              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2437         .xlevel = 0x80000008,
2438         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2439         .versions = (X86CPUVersionDefinition[]) {
2440             { .version = 1 },
2441             {
2442                 .version = 2,
2443                 .alias = "SandyBridge-IBRS",
2444                 .props = (PropValue[]) {
2445                     { "spec-ctrl", "on" },
2446                     { "model-id",
2447                       "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2448                     { /* end of list */ }
2449                 }
2450             },
2451             { /* end of list */ }
2452         }
2453     },
2454     {
2455         .name = "IvyBridge",
2456         .level = 0xd,
2457         .vendor = CPUID_VENDOR_INTEL,
2458         .family = 6,
2459         .model = 58,
2460         .stepping = 9,
2461         .features[FEAT_1_EDX] =
2462             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2463             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2464             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2465             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2466             CPUID_DE | CPUID_FP87,
2467         .features[FEAT_1_ECX] =
2468             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2469             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2470             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2471             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2472             CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2473         .features[FEAT_7_0_EBX] =
2474             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2475             CPUID_7_0_EBX_ERMS,
2476         .features[FEAT_8000_0001_EDX] =
2477             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2478             CPUID_EXT2_SYSCALL,
2479         .features[FEAT_8000_0001_ECX] =
2480             CPUID_EXT3_LAHF_LM,
2481         .features[FEAT_XSAVE] =
2482             CPUID_XSAVE_XSAVEOPT,
2483         .features[FEAT_6_EAX] =
2484             CPUID_6_EAX_ARAT,
2485         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2486              MSR_VMX_BASIC_TRUE_CTLS,
2487         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2488              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2489              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2490         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2491              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2492              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2493              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2494              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2495              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2496              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2497         .features[FEAT_VMX_EXIT_CTLS] =
2498              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2499              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2500              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2501              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2502              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2503         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2504              MSR_VMX_MISC_STORE_LMA,
2505         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2506              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2507              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2508         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2509              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2510              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2511              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2512              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2513              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2514              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2515              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2516              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2517              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2518              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2519              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2520         .features[FEAT_VMX_SECONDARY_CTLS] =
2521              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2522              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2523              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2524              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2525              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2526              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2527              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2528              VMX_SECONDARY_EXEC_RDRAND_EXITING,
2529         .xlevel = 0x80000008,
2530         .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2531         .versions = (X86CPUVersionDefinition[]) {
2532             { .version = 1 },
2533             {
2534                 .version = 2,
2535                 .alias = "IvyBridge-IBRS",
2536                 .props = (PropValue[]) {
2537                     { "spec-ctrl", "on" },
2538                     { "model-id",
2539                       "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2540                     { /* end of list */ }
2541                 }
2542             },
2543             { /* end of list */ }
2544         }
2545     },
2546     {
2547         .name = "Haswell",
2548         .level = 0xd,
2549         .vendor = CPUID_VENDOR_INTEL,
2550         .family = 6,
2551         .model = 60,
2552         .stepping = 4,
2553         .features[FEAT_1_EDX] =
2554             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2555             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2556             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2557             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2558             CPUID_DE | CPUID_FP87,
2559         .features[FEAT_1_ECX] =
2560             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2561             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2562             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2563             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2564             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2565             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2566         .features[FEAT_8000_0001_EDX] =
2567             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2568             CPUID_EXT2_SYSCALL,
2569         .features[FEAT_8000_0001_ECX] =
2570             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2571         .features[FEAT_7_0_EBX] =
2572             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2573             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2574             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2575             CPUID_7_0_EBX_RTM,
2576         .features[FEAT_XSAVE] =
2577             CPUID_XSAVE_XSAVEOPT,
2578         .features[FEAT_6_EAX] =
2579             CPUID_6_EAX_ARAT,
2580         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2581              MSR_VMX_BASIC_TRUE_CTLS,
2582         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2583              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2584              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2585         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2586              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2587              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2588              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2589              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2590              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2591              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2592         .features[FEAT_VMX_EXIT_CTLS] =
2593              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2594              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2595              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2596              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2597              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2598         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2599              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2600         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2601              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2602              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2603         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2604              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2605              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2606              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2607              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2608              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2609              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2610              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2611              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2612              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2613              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2614              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2615         .features[FEAT_VMX_SECONDARY_CTLS] =
2616              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2617              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2618              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2619              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2620              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2621              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2622              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2623              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2624              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2625         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2626         .xlevel = 0x80000008,
2627         .model_id = "Intel Core Processor (Haswell)",
2628         .versions = (X86CPUVersionDefinition[]) {
2629             { .version = 1 },
2630             {
2631                 .version = 2,
2632                 .alias = "Haswell-noTSX",
2633                 .props = (PropValue[]) {
2634                     { "hle", "off" },
2635                     { "rtm", "off" },
2636                     { "stepping", "1" },
2637                     { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2638                     { /* end of list */ }
2639                 },
2640             },
2641             {
2642                 .version = 3,
2643                 .alias = "Haswell-IBRS",
2644                 .props = (PropValue[]) {
2645                     /* Restore TSX features removed by -v2 above */
2646                     { "hle", "on" },
2647                     { "rtm", "on" },
2648                     /*
2649                      * Haswell and Haswell-IBRS had stepping=4 in
2650                      * QEMU 4.0 and older
2651                      */
2652                     { "stepping", "4" },
2653                     { "spec-ctrl", "on" },
2654                     { "model-id",
2655                       "Intel Core Processor (Haswell, IBRS)" },
2656                     { /* end of list */ }
2657                 }
2658             },
2659             {
2660                 .version = 4,
2661                 .alias = "Haswell-noTSX-IBRS",
2662                 .props = (PropValue[]) {
2663                     { "hle", "off" },
2664                     { "rtm", "off" },
2665                     /* spec-ctrl was already enabled by -v3 above */
2666                     { "stepping", "1" },
2667                     { "model-id",
2668                       "Intel Core Processor (Haswell, no TSX, IBRS)" },
2669                     { /* end of list */ }
2670                 }
2671             },
2672             { /* end of list */ }
2673         }
2674     },
2675     {
2676         .name = "Broadwell",
2677         .level = 0xd,
2678         .vendor = CPUID_VENDOR_INTEL,
2679         .family = 6,
2680         .model = 61,
2681         .stepping = 2,
2682         .features[FEAT_1_EDX] =
2683             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2684             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2685             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2686             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2687             CPUID_DE | CPUID_FP87,
2688         .features[FEAT_1_ECX] =
2689             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2690             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2691             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2692             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2693             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2694             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2695         .features[FEAT_8000_0001_EDX] =
2696             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2697             CPUID_EXT2_SYSCALL,
2698         .features[FEAT_8000_0001_ECX] =
2699             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2700         .features[FEAT_7_0_EBX] =
2701             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2702             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2703             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2704             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2705             CPUID_7_0_EBX_SMAP,
2706         .features[FEAT_XSAVE] =
2707             CPUID_XSAVE_XSAVEOPT,
2708         .features[FEAT_6_EAX] =
2709             CPUID_6_EAX_ARAT,
2710         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2711              MSR_VMX_BASIC_TRUE_CTLS,
2712         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2713              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2714              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2715         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2716              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2717              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2718              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2719              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2720              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2721              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2722         .features[FEAT_VMX_EXIT_CTLS] =
2723              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2724              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2725              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2726              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2727              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2728         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2729              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2730         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2731              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2732              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2733         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2734              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2735              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2736              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2737              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2738              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2739              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2740              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2741              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2742              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2743              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2744              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2745         .features[FEAT_VMX_SECONDARY_CTLS] =
2746              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2747              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2748              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2749              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2750              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2751              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2752              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2753              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2754              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2755              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2756         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2757         .xlevel = 0x80000008,
2758         .model_id = "Intel Core Processor (Broadwell)",
2759         .versions = (X86CPUVersionDefinition[]) {
2760             { .version = 1 },
2761             {
2762                 .version = 2,
2763                 .alias = "Broadwell-noTSX",
2764                 .props = (PropValue[]) {
2765                     { "hle", "off" },
2766                     { "rtm", "off" },
2767                     { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2768                     { /* end of list */ }
2769                 },
2770             },
2771             {
2772                 .version = 3,
2773                 .alias = "Broadwell-IBRS",
2774                 .props = (PropValue[]) {
2775                     /* Restore TSX features removed by -v2 above */
2776                     { "hle", "on" },
2777                     { "rtm", "on" },
2778                     { "spec-ctrl", "on" },
2779                     { "model-id",
2780                       "Intel Core Processor (Broadwell, IBRS)" },
2781                     { /* end of list */ }
2782                 }
2783             },
2784             {
2785                 .version = 4,
2786                 .alias = "Broadwell-noTSX-IBRS",
2787                 .props = (PropValue[]) {
2788                     { "hle", "off" },
2789                     { "rtm", "off" },
2790                     /* spec-ctrl was already enabled by -v3 above */
2791                     { "model-id",
2792                       "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2793                     { /* end of list */ }
2794                 }
2795             },
2796             { /* end of list */ }
2797         }
2798     },
2799     {
2800         .name = "Skylake-Client",
2801         .level = 0xd,
2802         .vendor = CPUID_VENDOR_INTEL,
2803         .family = 6,
2804         .model = 94,
2805         .stepping = 3,
2806         .features[FEAT_1_EDX] =
2807             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2808             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2809             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2810             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2811             CPUID_DE | CPUID_FP87,
2812         .features[FEAT_1_ECX] =
2813             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2814             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2815             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2816             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2817             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2818             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2819         .features[FEAT_8000_0001_EDX] =
2820             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2821             CPUID_EXT2_SYSCALL,
2822         .features[FEAT_8000_0001_ECX] =
2823             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2824         .features[FEAT_7_0_EBX] =
2825             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2826             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2827             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2828             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2829             CPUID_7_0_EBX_SMAP,
2830         /* Missing: XSAVES (not supported by some Linux versions,
2831          * including v4.1 to v4.12).
2832          * KVM doesn't yet expose any XSAVES state save component,
2833          * and the only one defined in Skylake (processor tracing)
2834          * probably will block migration anyway.
2835          */
2836         .features[FEAT_XSAVE] =
2837             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2838             CPUID_XSAVE_XGETBV1,
2839         .features[FEAT_6_EAX] =
2840             CPUID_6_EAX_ARAT,
2841         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2842         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2843              MSR_VMX_BASIC_TRUE_CTLS,
2844         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2845              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2846              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2847         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2848              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2849              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2850              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2851              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2852              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2853              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2854         .features[FEAT_VMX_EXIT_CTLS] =
2855              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2856              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2857              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2858              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2859              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2860         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2861              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2862         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2863              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2864              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2865         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2866              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2867              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2868              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2869              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2870              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2871              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2872              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2873              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2874              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2875              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2876              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2877         .features[FEAT_VMX_SECONDARY_CTLS] =
2878              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2879              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2880              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2881              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2882              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2883              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2884              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2885         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2886         .xlevel = 0x80000008,
2887         .model_id = "Intel Core Processor (Skylake)",
2888         .versions = (X86CPUVersionDefinition[]) {
2889             { .version = 1 },
2890             {
2891                 .version = 2,
2892                 .alias = "Skylake-Client-IBRS",
2893                 .props = (PropValue[]) {
2894                     { "spec-ctrl", "on" },
2895                     { "model-id",
2896                       "Intel Core Processor (Skylake, IBRS)" },
2897                     { /* end of list */ }
2898                 }
2899             },
2900             {
2901                 .version = 3,
2902                 .alias = "Skylake-Client-noTSX-IBRS",
2903                 .props = (PropValue[]) {
2904                     { "hle", "off" },
2905                     { "rtm", "off" },
2906                     { "model-id",
2907                       "Intel Core Processor (Skylake, IBRS, no TSX)" },
2908                     { /* end of list */ }
2909                 }
2910             },
2911             { /* end of list */ }
2912         }
2913     },
2914     {
2915         .name = "Skylake-Server",
2916         .level = 0xd,
2917         .vendor = CPUID_VENDOR_INTEL,
2918         .family = 6,
2919         .model = 85,
2920         .stepping = 4,
2921         .features[FEAT_1_EDX] =
2922             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2923             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2924             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2925             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2926             CPUID_DE | CPUID_FP87,
2927         .features[FEAT_1_ECX] =
2928             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2929             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2930             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2931             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2932             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2933             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2934         .features[FEAT_8000_0001_EDX] =
2935             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2936             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2937         .features[FEAT_8000_0001_ECX] =
2938             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2939         .features[FEAT_7_0_EBX] =
2940             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2941             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2942             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2943             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2944             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2945             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2946             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2947             CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2948         .features[FEAT_7_0_ECX] =
2949             CPUID_7_0_ECX_PKU,
2950         /* Missing: XSAVES (not supported by some Linux versions,
2951          * including v4.1 to v4.12).
2952          * KVM doesn't yet expose any XSAVES state save component,
2953          * and the only one defined in Skylake (processor tracing)
2954          * probably will block migration anyway.
2955          */
2956         .features[FEAT_XSAVE] =
2957             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2958             CPUID_XSAVE_XGETBV1,
2959         .features[FEAT_6_EAX] =
2960             CPUID_6_EAX_ARAT,
2961         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2962         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2963              MSR_VMX_BASIC_TRUE_CTLS,
2964         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2965              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2966              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2967         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2968              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2969              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2970              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2971              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2972              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2973              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2974         .features[FEAT_VMX_EXIT_CTLS] =
2975              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2976              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2977              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2978              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2979              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2980         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2981              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2982         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2983              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2984              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2985         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2986              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2987              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2988              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2989              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2990              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2991              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2992              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2993              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2994              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2995              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2996              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2997         .features[FEAT_VMX_SECONDARY_CTLS] =
2998              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2999              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3000              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3001              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3002              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3003              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3004              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3005              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3006              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3007              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3008         .xlevel = 0x80000008,
3009         .model_id = "Intel Xeon Processor (Skylake)",
3010         .versions = (X86CPUVersionDefinition[]) {
3011             { .version = 1 },
3012             {
3013                 .version = 2,
3014                 .alias = "Skylake-Server-IBRS",
3015                 .props = (PropValue[]) {
3016                     /* clflushopt was not added to Skylake-Server-IBRS */
3017                     /* TODO: add -v3 including clflushopt */
3018                     { "clflushopt", "off" },
3019                     { "spec-ctrl", "on" },
3020                     { "model-id",
3021                       "Intel Xeon Processor (Skylake, IBRS)" },
3022                     { /* end of list */ }
3023                 }
3024             },
3025             {
3026                 .version = 3,
3027                 .alias = "Skylake-Server-noTSX-IBRS",
3028                 .props = (PropValue[]) {
3029                     { "hle", "off" },
3030                     { "rtm", "off" },
3031                     { "model-id",
3032                       "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3033                     { /* end of list */ }
3034                 }
3035             },
3036             {
3037                 .version = 4,
3038                 .props = (PropValue[]) {
3039                     { "vmx-eptp-switching", "on" },
3040                     { /* end of list */ }
3041                 }
3042             },
3043             { /* end of list */ }
3044         }
3045     },
3046     {
3047         .name = "Cascadelake-Server",
3048         .level = 0xd,
3049         .vendor = CPUID_VENDOR_INTEL,
3050         .family = 6,
3051         .model = 85,
3052         .stepping = 6,
3053         .features[FEAT_1_EDX] =
3054             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3055             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3056             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3057             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3058             CPUID_DE | CPUID_FP87,
3059         .features[FEAT_1_ECX] =
3060             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3061             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3062             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3063             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3064             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3065             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3066         .features[FEAT_8000_0001_EDX] =
3067             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3068             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3069         .features[FEAT_8000_0001_ECX] =
3070             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3071         .features[FEAT_7_0_EBX] =
3072             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3073             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3074             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3075             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3076             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3077             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3078             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3079             CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3080         .features[FEAT_7_0_ECX] =
3081             CPUID_7_0_ECX_PKU |
3082             CPUID_7_0_ECX_AVX512VNNI,
3083         .features[FEAT_7_0_EDX] =
3084             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3085         /* Missing: XSAVES (not supported by some Linux versions,
3086                 * including v4.1 to v4.12).
3087                 * KVM doesn't yet expose any XSAVES state save component,
3088                 * and the only one defined in Skylake (processor tracing)
3089                 * probably will block migration anyway.
3090                 */
3091         .features[FEAT_XSAVE] =
3092             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3093             CPUID_XSAVE_XGETBV1,
3094         .features[FEAT_6_EAX] =
3095             CPUID_6_EAX_ARAT,
3096         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3097         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3098              MSR_VMX_BASIC_TRUE_CTLS,
3099         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3100              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3101              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3102         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3103              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3104              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3105              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3106              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3107              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3108              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3109         .features[FEAT_VMX_EXIT_CTLS] =
3110              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3111              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3112              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3113              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3114              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3115         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3116              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3117         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3118              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3119              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3120         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3121              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3122              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3123              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3124              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3125              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3126              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3127              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3128              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3129              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3130              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3131              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3132         .features[FEAT_VMX_SECONDARY_CTLS] =
3133              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3134              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3135              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3136              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3137              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3138              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3139              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3140              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3141              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3142              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3143         .xlevel = 0x80000008,
3144         .model_id = "Intel Xeon Processor (Cascadelake)",
3145         .versions = (X86CPUVersionDefinition[]) {
3146             { .version = 1 },
3147             { .version = 2,
3148               .note = "ARCH_CAPABILITIES",
3149               .props = (PropValue[]) {
3150                   { "arch-capabilities", "on" },
3151                   { "rdctl-no", "on" },
3152                   { "ibrs-all", "on" },
3153                   { "skip-l1dfl-vmentry", "on" },
3154                   { "mds-no", "on" },
3155                   { /* end of list */ }
3156               },
3157             },
3158             { .version = 3,
3159               .alias = "Cascadelake-Server-noTSX",
3160               .note = "ARCH_CAPABILITIES, no TSX",
3161               .props = (PropValue[]) {
3162                   { "hle", "off" },
3163                   { "rtm", "off" },
3164                   { /* end of list */ }
3165               },
3166             },
3167             { .version = 4,
3168               .note = "ARCH_CAPABILITIES, no TSX",
3169               .props = (PropValue[]) {
3170                   { "vmx-eptp-switching", "on" },
3171                   { /* end of list */ }
3172               },
3173             },
3174             { /* end of list */ }
3175         }
3176     },
3177     {
3178         .name = "Cooperlake",
3179         .level = 0xd,
3180         .vendor = CPUID_VENDOR_INTEL,
3181         .family = 6,
3182         .model = 85,
3183         .stepping = 10,
3184         .features[FEAT_1_EDX] =
3185             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3186             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3187             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3188             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3189             CPUID_DE | CPUID_FP87,
3190         .features[FEAT_1_ECX] =
3191             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3192             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3193             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3194             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3195             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3196             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3197         .features[FEAT_8000_0001_EDX] =
3198             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3199             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3200         .features[FEAT_8000_0001_ECX] =
3201             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3202         .features[FEAT_7_0_EBX] =
3203             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3204             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3205             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3206             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3207             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3208             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3209             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3210             CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3211         .features[FEAT_7_0_ECX] =
3212             CPUID_7_0_ECX_PKU |
3213             CPUID_7_0_ECX_AVX512VNNI,
3214         .features[FEAT_7_0_EDX] =
3215             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3216             CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3217         .features[FEAT_ARCH_CAPABILITIES] =
3218             MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3219             MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3220             MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3221         .features[FEAT_7_1_EAX] =
3222             CPUID_7_1_EAX_AVX512_BF16,
3223         /*
3224          * Missing: XSAVES (not supported by some Linux versions,
3225          * including v4.1 to v4.12).
3226          * KVM doesn't yet expose any XSAVES state save component,
3227          * and the only one defined in Skylake (processor tracing)
3228          * probably will block migration anyway.
3229          */
3230         .features[FEAT_XSAVE] =
3231             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3232             CPUID_XSAVE_XGETBV1,
3233         .features[FEAT_6_EAX] =
3234             CPUID_6_EAX_ARAT,
3235         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3236         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3237              MSR_VMX_BASIC_TRUE_CTLS,
3238         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3239              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3240              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3241         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3242              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3243              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3244              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3245              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3246              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3247              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3248         .features[FEAT_VMX_EXIT_CTLS] =
3249              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3250              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3251              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3252              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3253              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3254         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3255              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3256         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3257              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3258              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3259         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3260              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3261              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3262              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3263              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3264              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3265              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3266              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3267              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3268              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3269              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3270              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3271         .features[FEAT_VMX_SECONDARY_CTLS] =
3272              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3273              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3274              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3275              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3276              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3277              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3278              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3279              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3280              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3281              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3282         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3283         .xlevel = 0x80000008,
3284         .model_id = "Intel Xeon Processor (Cooperlake)",
3285     },
3286     {
3287         .name = "Icelake-Client",
3288         .level = 0xd,
3289         .vendor = CPUID_VENDOR_INTEL,
3290         .family = 6,
3291         .model = 126,
3292         .stepping = 0,
3293         .features[FEAT_1_EDX] =
3294             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3295             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3296             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3297             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3298             CPUID_DE | CPUID_FP87,
3299         .features[FEAT_1_ECX] =
3300             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3301             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3302             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3303             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3304             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3305             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3306         .features[FEAT_8000_0001_EDX] =
3307             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3308             CPUID_EXT2_SYSCALL,
3309         .features[FEAT_8000_0001_ECX] =
3310             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3311         .features[FEAT_8000_0008_EBX] =
3312             CPUID_8000_0008_EBX_WBNOINVD,
3313         .features[FEAT_7_0_EBX] =
3314             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3315             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3316             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3317             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3318             CPUID_7_0_EBX_SMAP,
3319         .features[FEAT_7_0_ECX] =
3320             CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3321             CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3322             CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3323             CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3324             CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3325         .features[FEAT_7_0_EDX] =
3326             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3327         /* Missing: XSAVES (not supported by some Linux versions,
3328                 * including v4.1 to v4.12).
3329                 * KVM doesn't yet expose any XSAVES state save component,
3330                 * and the only one defined in Skylake (processor tracing)
3331                 * probably will block migration anyway.
3332                 */
3333         .features[FEAT_XSAVE] =
3334             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3335             CPUID_XSAVE_XGETBV1,
3336         .features[FEAT_6_EAX] =
3337             CPUID_6_EAX_ARAT,
3338         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3339         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3340              MSR_VMX_BASIC_TRUE_CTLS,
3341         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3342              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3343              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3344         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3345              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3346              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3347              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3348              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3349              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3350              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3351         .features[FEAT_VMX_EXIT_CTLS] =
3352              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3353              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3354              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3355              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3356              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3357         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3358              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3359         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3360              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3361              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3362         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3363              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3364              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3365              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3366              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3367              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3368              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3369              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3370              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3371              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3372              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3373              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3374         .features[FEAT_VMX_SECONDARY_CTLS] =
3375              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3376              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3377              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3378              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3379              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3380              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3381              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3382         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3383         .xlevel = 0x80000008,
3384         .model_id = "Intel Core Processor (Icelake)",
3385         .versions = (X86CPUVersionDefinition[]) {
3386             {
3387                 .version = 1,
3388                 .note = "deprecated"
3389             },
3390             {
3391                 .version = 2,
3392                 .note = "no TSX, deprecated",
3393                 .alias = "Icelake-Client-noTSX",
3394                 .props = (PropValue[]) {
3395                     { "hle", "off" },
3396                     { "rtm", "off" },
3397                     { /* end of list */ }
3398                 },
3399             },
3400             { /* end of list */ }
3401         },
3402         .deprecation_note = "use Icelake-Server instead"
3403     },
3404     {
3405         .name = "Icelake-Server",
3406         .level = 0xd,
3407         .vendor = CPUID_VENDOR_INTEL,
3408         .family = 6,
3409         .model = 134,
3410         .stepping = 0,
3411         .features[FEAT_1_EDX] =
3412             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3413             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3414             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3415             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3416             CPUID_DE | CPUID_FP87,
3417         .features[FEAT_1_ECX] =
3418             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3419             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3420             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3421             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3422             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3423             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3424         .features[FEAT_8000_0001_EDX] =
3425             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3426             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3427         .features[FEAT_8000_0001_ECX] =
3428             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3429         .features[FEAT_8000_0008_EBX] =
3430             CPUID_8000_0008_EBX_WBNOINVD,
3431         .features[FEAT_7_0_EBX] =
3432             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3433             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3434             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3435             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3436             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3437             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3438             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3439             CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3440         .features[FEAT_7_0_ECX] =
3441             CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3442             CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3443             CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3444             CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3445             CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3446         .features[FEAT_7_0_EDX] =
3447             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3448         /* Missing: XSAVES (not supported by some Linux versions,
3449                 * including v4.1 to v4.12).
3450                 * KVM doesn't yet expose any XSAVES state save component,
3451                 * and the only one defined in Skylake (processor tracing)
3452                 * probably will block migration anyway.
3453                 */
3454         .features[FEAT_XSAVE] =
3455             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3456             CPUID_XSAVE_XGETBV1,
3457         .features[FEAT_6_EAX] =
3458             CPUID_6_EAX_ARAT,
3459         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3460         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3461              MSR_VMX_BASIC_TRUE_CTLS,
3462         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3463              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3464              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3465         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3466              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3467              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3468              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3469              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3470              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3471              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3472         .features[FEAT_VMX_EXIT_CTLS] =
3473              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3474              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3475              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3476              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3477              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3478         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3479              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3480         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3481              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3482              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3483         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3484              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3485              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3486              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3487              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3488              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3489              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3490              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3491              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3492              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3493              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3494              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3495         .features[FEAT_VMX_SECONDARY_CTLS] =
3496              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3497              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3498              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3499              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3500              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3501              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3502              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3503              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3504              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3505         .xlevel = 0x80000008,
3506         .model_id = "Intel Xeon Processor (Icelake)",
3507         .versions = (X86CPUVersionDefinition[]) {
3508             { .version = 1 },
3509             {
3510                 .version = 2,
3511                 .note = "no TSX",
3512                 .alias = "Icelake-Server-noTSX",
3513                 .props = (PropValue[]) {
3514                     { "hle", "off" },
3515                     { "rtm", "off" },
3516                     { /* end of list */ }
3517                 },
3518             },
3519             {
3520                 .version = 3,
3521                 .props = (PropValue[]) {
3522                     { "arch-capabilities", "on" },
3523                     { "rdctl-no", "on" },
3524                     { "ibrs-all", "on" },
3525                     { "skip-l1dfl-vmentry", "on" },
3526                     { "mds-no", "on" },
3527                     { "pschange-mc-no", "on" },
3528                     { "taa-no", "on" },
3529                     { /* end of list */ }
3530                 },
3531             },
3532             {
3533                 .version = 4,
3534                 .props = (PropValue[]) {
3535                     { "sha-ni", "on" },
3536                     { "avx512ifma", "on" },
3537                     { "rdpid", "on" },
3538                     { "fsrm", "on" },
3539                     { "vmx-rdseed-exit", "on" },
3540                     { "vmx-pml", "on" },
3541                     { "vmx-eptp-switching", "on" },
3542                     { "model", "106" },
3543                     { /* end of list */ }
3544                 },
3545             },
3546             { /* end of list */ }
3547         }
3548     },
3549     {
3550         .name = "Denverton",
3551         .level = 21,
3552         .vendor = CPUID_VENDOR_INTEL,
3553         .family = 6,
3554         .model = 95,
3555         .stepping = 1,
3556         .features[FEAT_1_EDX] =
3557             CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3558             CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3559             CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3560             CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3561             CPUID_SSE | CPUID_SSE2,
3562         .features[FEAT_1_ECX] =
3563             CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3564             CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3565             CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3566             CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3567             CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3568         .features[FEAT_8000_0001_EDX] =
3569             CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3570             CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3571         .features[FEAT_8000_0001_ECX] =
3572             CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3573         .features[FEAT_7_0_EBX] =
3574             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3575             CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3576             CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3577         .features[FEAT_7_0_EDX] =
3578             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3579             CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3580         /*
3581          * Missing: XSAVES (not supported by some Linux versions,
3582          * including v4.1 to v4.12).
3583          * KVM doesn't yet expose any XSAVES state save component,
3584          * and the only one defined in Skylake (processor tracing)
3585          * probably will block migration anyway.
3586          */
3587         .features[FEAT_XSAVE] =
3588             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3589         .features[FEAT_6_EAX] =
3590             CPUID_6_EAX_ARAT,
3591         .features[FEAT_ARCH_CAPABILITIES] =
3592             MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3593         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3594              MSR_VMX_BASIC_TRUE_CTLS,
3595         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3596              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3597              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3598         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3599              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3600              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3601              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3602              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3603              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3604              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3605         .features[FEAT_VMX_EXIT_CTLS] =
3606              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3607              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3608              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3609              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3610              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3611         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3612              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3613         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3614              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3615              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3616         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3617              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3618              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3619              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3620              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3621              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3622              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3623              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3624              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3625              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3626              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3627              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3628         .features[FEAT_VMX_SECONDARY_CTLS] =
3629              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3630              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3631              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3632              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3633              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3634              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3635              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3636              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3637              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3638              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3639         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3640         .xlevel = 0x80000008,
3641         .model_id = "Intel Atom Processor (Denverton)",
3642         .versions = (X86CPUVersionDefinition[]) {
3643             { .version = 1 },
3644             {
3645                 .version = 2,
3646                 .note = "no MPX, no MONITOR",
3647                 .props = (PropValue[]) {
3648                     { "monitor", "off" },
3649                     { "mpx", "off" },
3650                     { /* end of list */ },
3651                 },
3652             },
3653             { /* end of list */ },
3654         },
3655     },
3656     {
3657         .name = "Snowridge",
3658         .level = 27,
3659         .vendor = CPUID_VENDOR_INTEL,
3660         .family = 6,
3661         .model = 134,
3662         .stepping = 1,
3663         .features[FEAT_1_EDX] =
3664             /* missing: CPUID_PN CPUID_IA64 */
3665             /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3666             CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3667             CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3668             CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3669             CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3670             CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3671             CPUID_MMX |
3672             CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3673         .features[FEAT_1_ECX] =
3674             CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3675             CPUID_EXT_SSSE3 |
3676             CPUID_EXT_CX16 |
3677             CPUID_EXT_SSE41 |
3678             CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3679             CPUID_EXT_POPCNT |
3680             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3681             CPUID_EXT_RDRAND,
3682         .features[FEAT_8000_0001_EDX] =
3683             CPUID_EXT2_SYSCALL |
3684             CPUID_EXT2_NX |
3685             CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3686             CPUID_EXT2_LM,
3687         .features[FEAT_8000_0001_ECX] =
3688             CPUID_EXT3_LAHF_LM |
3689             CPUID_EXT3_3DNOWPREFETCH,
3690         .features[FEAT_7_0_EBX] =
3691             CPUID_7_0_EBX_FSGSBASE |
3692             CPUID_7_0_EBX_SMEP |
3693             CPUID_7_0_EBX_ERMS |
3694             CPUID_7_0_EBX_MPX |  /* missing bits 13, 15 */
3695             CPUID_7_0_EBX_RDSEED |
3696             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3697             CPUID_7_0_EBX_CLWB |
3698             CPUID_7_0_EBX_SHA_NI,
3699         .features[FEAT_7_0_ECX] =
3700             CPUID_7_0_ECX_UMIP |
3701             /* missing bit 5 */
3702             CPUID_7_0_ECX_GFNI |
3703             CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3704             CPUID_7_0_ECX_MOVDIR64B,
3705         .features[FEAT_7_0_EDX] =
3706             CPUID_7_0_EDX_SPEC_CTRL |
3707             CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3708             CPUID_7_0_EDX_CORE_CAPABILITY,
3709         .features[FEAT_CORE_CAPABILITY] =
3710             MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3711         /*
3712          * Missing: XSAVES (not supported by some Linux versions,
3713          * including v4.1 to v4.12).
3714          * KVM doesn't yet expose any XSAVES state save component,
3715          * and the only one defined in Skylake (processor tracing)
3716          * probably will block migration anyway.
3717          */
3718         .features[FEAT_XSAVE] =
3719             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3720             CPUID_XSAVE_XGETBV1,
3721         .features[FEAT_6_EAX] =
3722             CPUID_6_EAX_ARAT,
3723         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3724              MSR_VMX_BASIC_TRUE_CTLS,
3725         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3726              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3727              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3728         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3729              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3730              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3731              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3732              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3733              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3734              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3735         .features[FEAT_VMX_EXIT_CTLS] =
3736              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3737              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3738              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3739              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3740              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3741         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3742              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3743         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3744              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3745              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3746         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3747              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3748              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3749              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3750              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3751              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3752              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3753              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3754              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3755              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3756              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3757              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3758         .features[FEAT_VMX_SECONDARY_CTLS] =
3759              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3760              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3761              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3762              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3763              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3764              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3765              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3766              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3767              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3768              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3769         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3770         .xlevel = 0x80000008,
3771         .model_id = "Intel Atom Processor (SnowRidge)",
3772         .versions = (X86CPUVersionDefinition[]) {
3773             { .version = 1 },
3774             {
3775                 .version = 2,
3776                 .props = (PropValue[]) {
3777                     { "mpx", "off" },
3778                     { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3779                     { /* end of list */ },
3780                 },
3781             },
3782             { /* end of list */ },
3783         },
3784     },
3785     {
3786         .name = "KnightsMill",
3787         .level = 0xd,
3788         .vendor = CPUID_VENDOR_INTEL,
3789         .family = 6,
3790         .model = 133,
3791         .stepping = 0,
3792         .features[FEAT_1_EDX] =
3793             CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3794             CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3795             CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3796             CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3797             CPUID_PSE | CPUID_DE | CPUID_FP87,
3798         .features[FEAT_1_ECX] =
3799             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3800             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3801             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3802             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3803             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3804             CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3805         .features[FEAT_8000_0001_EDX] =
3806             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3807             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3808         .features[FEAT_8000_0001_ECX] =
3809             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3810         .features[FEAT_7_0_EBX] =
3811             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3812             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3813             CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3814             CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3815             CPUID_7_0_EBX_AVX512ER,
3816         .features[FEAT_7_0_ECX] =
3817             CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3818         .features[FEAT_7_0_EDX] =
3819             CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3820         .features[FEAT_XSAVE] =
3821             CPUID_XSAVE_XSAVEOPT,
3822         .features[FEAT_6_EAX] =
3823             CPUID_6_EAX_ARAT,
3824         .xlevel = 0x80000008,
3825         .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3826     },
3827     {
3828         .name = "Opteron_G1",
3829         .level = 5,
3830         .vendor = CPUID_VENDOR_AMD,
3831         .family = 15,
3832         .model = 6,
3833         .stepping = 1,
3834         .features[FEAT_1_EDX] =
3835             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3836             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3837             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3838             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3839             CPUID_DE | CPUID_FP87,
3840         .features[FEAT_1_ECX] =
3841             CPUID_EXT_SSE3,
3842         .features[FEAT_8000_0001_EDX] =
3843             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3844         .xlevel = 0x80000008,
3845         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3846     },
3847     {
3848         .name = "Opteron_G2",
3849         .level = 5,
3850         .vendor = CPUID_VENDOR_AMD,
3851         .family = 15,
3852         .model = 6,
3853         .stepping = 1,
3854         .features[FEAT_1_EDX] =
3855             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3856             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3857             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3858             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3859             CPUID_DE | CPUID_FP87,
3860         .features[FEAT_1_ECX] =
3861             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
3862         .features[FEAT_8000_0001_EDX] =
3863             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3864         .features[FEAT_8000_0001_ECX] =
3865             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3866         .xlevel = 0x80000008,
3867         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3868     },
3869     {
3870         .name = "Opteron_G3",
3871         .level = 5,
3872         .vendor = CPUID_VENDOR_AMD,
3873         .family = 16,
3874         .model = 2,
3875         .stepping = 3,
3876         .features[FEAT_1_EDX] =
3877             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3878             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3879             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3880             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3881             CPUID_DE | CPUID_FP87,
3882         .features[FEAT_1_ECX] =
3883             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3884             CPUID_EXT_SSE3,
3885         .features[FEAT_8000_0001_EDX] =
3886             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3887             CPUID_EXT2_RDTSCP,
3888         .features[FEAT_8000_0001_ECX] =
3889             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3890             CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3891         .xlevel = 0x80000008,
3892         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3893     },
3894     {
3895         .name = "Opteron_G4",
3896         .level = 0xd,
3897         .vendor = CPUID_VENDOR_AMD,
3898         .family = 21,
3899         .model = 1,
3900         .stepping = 2,
3901         .features[FEAT_1_EDX] =
3902             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3903             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3904             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3905             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3906             CPUID_DE | CPUID_FP87,
3907         .features[FEAT_1_ECX] =
3908             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3909             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3910             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3911             CPUID_EXT_SSE3,
3912         .features[FEAT_8000_0001_EDX] =
3913             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3914             CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3915         .features[FEAT_8000_0001_ECX] =
3916             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3917             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3918             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3919             CPUID_EXT3_LAHF_LM,
3920         .features[FEAT_SVM] =
3921             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3922         /* no xsaveopt! */
3923         .xlevel = 0x8000001A,
3924         .model_id = "AMD Opteron 62xx class CPU",
3925     },
3926     {
3927         .name = "Opteron_G5",
3928         .level = 0xd,
3929         .vendor = CPUID_VENDOR_AMD,
3930         .family = 21,
3931         .model = 2,
3932         .stepping = 0,
3933         .features[FEAT_1_EDX] =
3934             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3935             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3936             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3937             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3938             CPUID_DE | CPUID_FP87,
3939         .features[FEAT_1_ECX] =
3940             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
3941             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3942             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3943             CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3944         .features[FEAT_8000_0001_EDX] =
3945             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3946             CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3947         .features[FEAT_8000_0001_ECX] =
3948             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3949             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3950             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3951             CPUID_EXT3_LAHF_LM,
3952         .features[FEAT_SVM] =
3953             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3954         /* no xsaveopt! */
3955         .xlevel = 0x8000001A,
3956         .model_id = "AMD Opteron 63xx class CPU",
3957     },
3958     {
3959         .name = "EPYC",
3960         .level = 0xd,
3961         .vendor = CPUID_VENDOR_AMD,
3962         .family = 23,
3963         .model = 1,
3964         .stepping = 2,
3965         .features[FEAT_1_EDX] =
3966             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3967             CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3968             CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3969             CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3970             CPUID_VME | CPUID_FP87,
3971         .features[FEAT_1_ECX] =
3972             CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3973             CPUID_EXT_XSAVE | CPUID_EXT_AES |  CPUID_EXT_POPCNT |
3974             CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3975             CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3976             CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3977         .features[FEAT_8000_0001_EDX] =
3978             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3979             CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3980             CPUID_EXT2_SYSCALL,
3981         .features[FEAT_8000_0001_ECX] =
3982             CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
3983             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
3984             CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
3985             CPUID_EXT3_TOPOEXT,
3986         .features[FEAT_7_0_EBX] =
3987             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3988             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
3989             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3990             CPUID_7_0_EBX_SHA_NI,
3991         .features[FEAT_XSAVE] =
3992             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3993             CPUID_XSAVE_XGETBV1,
3994         .features[FEAT_6_EAX] =
3995             CPUID_6_EAX_ARAT,
3996         .features[FEAT_SVM] =
3997             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3998         .xlevel = 0x8000001E,
3999         .model_id = "AMD EPYC Processor",
4000         .cache_info = &epyc_cache_info,
4001         .versions = (X86CPUVersionDefinition[]) {
4002             { .version = 1 },
4003             {
4004                 .version = 2,
4005                 .alias = "EPYC-IBPB",
4006                 .props = (PropValue[]) {
4007                     { "ibpb", "on" },
4008                     { "model-id",
4009                       "AMD EPYC Processor (with IBPB)" },
4010                     { /* end of list */ }
4011                 }
4012             },
4013             {
4014                 .version = 3,
4015                 .props = (PropValue[]) {
4016                     { "ibpb", "on" },
4017                     { "perfctr-core", "on" },
4018                     { "clzero", "on" },
4019                     { "xsaveerptr", "on" },
4020                     { "xsaves", "on" },
4021                     { "model-id",
4022                       "AMD EPYC Processor" },
4023                     { /* end of list */ }
4024                 }
4025             },
4026             { /* end of list */ }
4027         }
4028     },
4029     {
4030         .name = "Dhyana",
4031         .level = 0xd,
4032         .vendor = CPUID_VENDOR_HYGON,
4033         .family = 24,
4034         .model = 0,
4035         .stepping = 1,
4036         .features[FEAT_1_EDX] =
4037             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4038             CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4039             CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4040             CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4041             CPUID_VME | CPUID_FP87,
4042         .features[FEAT_1_ECX] =
4043             CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4044             CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4045             CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4046             CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4047             CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4048         .features[FEAT_8000_0001_EDX] =
4049             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4050             CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4051             CPUID_EXT2_SYSCALL,
4052         .features[FEAT_8000_0001_ECX] =
4053             CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4054             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4055             CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4056             CPUID_EXT3_TOPOEXT,
4057         .features[FEAT_8000_0008_EBX] =
4058             CPUID_8000_0008_EBX_IBPB,
4059         .features[FEAT_7_0_EBX] =
4060             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4061             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4062             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
4063         /*
4064          * Missing: XSAVES (not supported by some Linux versions,
4065          * including v4.1 to v4.12).
4066          * KVM doesn't yet expose any XSAVES state save component.
4067          */
4068         .features[FEAT_XSAVE] =
4069             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4070             CPUID_XSAVE_XGETBV1,
4071         .features[FEAT_6_EAX] =
4072             CPUID_6_EAX_ARAT,
4073         .features[FEAT_SVM] =
4074             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4075         .xlevel = 0x8000001E,
4076         .model_id = "Hygon Dhyana Processor",
4077         .cache_info = &epyc_cache_info,
4078     },
4079     {
4080         .name = "EPYC-Rome",
4081         .level = 0xd,
4082         .vendor = CPUID_VENDOR_AMD,
4083         .family = 23,
4084         .model = 49,
4085         .stepping = 0,
4086         .features[FEAT_1_EDX] =
4087             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4088             CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4089             CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4090             CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4091             CPUID_VME | CPUID_FP87,
4092         .features[FEAT_1_ECX] =
4093             CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4094             CPUID_EXT_XSAVE | CPUID_EXT_AES |  CPUID_EXT_POPCNT |
4095             CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4096             CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4097             CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4098         .features[FEAT_8000_0001_EDX] =
4099             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4100             CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4101             CPUID_EXT2_SYSCALL,
4102         .features[FEAT_8000_0001_ECX] =
4103             CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4104             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4105             CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4106             CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4107         .features[FEAT_8000_0008_EBX] =
4108             CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4109             CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4110             CPUID_8000_0008_EBX_STIBP,
4111         .features[FEAT_7_0_EBX] =
4112             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4113             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4114             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4115             CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4116         .features[FEAT_7_0_ECX] =
4117             CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4118         .features[FEAT_XSAVE] =
4119             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4120             CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4121         .features[FEAT_6_EAX] =
4122             CPUID_6_EAX_ARAT,
4123         .features[FEAT_SVM] =
4124             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4125         .xlevel = 0x8000001E,
4126         .model_id = "AMD EPYC-Rome Processor",
4127         .cache_info = &epyc_rome_cache_info,
4128     },
4129 };
4130
4131 /* KVM-specific features that are automatically added/removed
4132  * from all CPU models when KVM is enabled.
4133  */
4134 static PropValue kvm_default_props[] = {
4135     { "kvmclock", "on" },
4136     { "kvm-nopiodelay", "on" },
4137     { "kvm-asyncpf", "on" },
4138     { "kvm-steal-time", "on" },
4139     { "kvm-pv-eoi", "on" },
4140     { "kvmclock-stable-bit", "on" },
4141     { "x2apic", "on" },
4142     { "acpi", "off" },
4143     { "monitor", "off" },
4144     { "svm", "off" },
4145     { NULL, NULL },
4146 };
4147
4148 /* TCG-specific defaults that override all CPU models when using TCG
4149  */
4150 static PropValue tcg_default_props[] = {
4151     { "vme", "off" },
4152     { NULL, NULL },
4153 };
4154
4155
4156 /*
4157  * We resolve CPU model aliases using -v1 when using "-machine
4158  * none", but this is just for compatibility while libvirt isn't
4159  * adapted to resolve CPU model versions before creating VMs.
4160  * See "Runnability guarantee of CPU models" at
4161  * docs/system/deprecated.rst.
4162  */
4163 X86CPUVersion default_cpu_version = 1;
4164
4165 void x86_cpu_set_default_version(X86CPUVersion version)
4166 {
4167     /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4168     assert(version != CPU_VERSION_AUTO);
4169     default_cpu_version = version;
4170 }
4171
4172 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4173 {
4174     int v = 0;
4175     const X86CPUVersionDefinition *vdef =
4176         x86_cpu_def_get_versions(model->cpudef);
4177     while (vdef->version) {
4178         v = vdef->version;
4179         vdef++;
4180     }
4181     return v;
4182 }
4183
4184 /* Return the actual version being used for a specific CPU model */
4185 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4186 {
4187     X86CPUVersion v = model->version;
4188     if (v == CPU_VERSION_AUTO) {
4189         v = default_cpu_version;
4190     }
4191     if (v == CPU_VERSION_LATEST) {
4192         return x86_cpu_model_last_version(model);
4193     }
4194     return v;
4195 }
4196
4197 void x86_cpu_change_kvm_default(const char *prop, const char *value)
4198 {
4199     PropValue *pv;
4200     for (pv = kvm_default_props; pv->prop; pv++) {
4201         if (!strcmp(pv->prop, prop)) {
4202             pv->value = value;
4203             break;
4204         }
4205     }
4206
4207     /* It is valid to call this function only for properties that
4208      * are already present in the kvm_default_props table.
4209      */
4210     assert(pv->prop);
4211 }
4212
4213 static bool lmce_supported(void)
4214 {
4215     uint64_t mce_cap = 0;
4216
4217 #ifdef CONFIG_KVM
4218     if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
4219         return false;
4220     }
4221 #endif
4222
4223     return !!(mce_cap & MCG_LMCE_P);
4224 }
4225
4226 #define CPUID_MODEL_ID_SZ 48
4227
4228 /**
4229  * cpu_x86_fill_model_id:
4230  * Get CPUID model ID string from host CPU.
4231  *
4232  * @str should have at least CPUID_MODEL_ID_SZ bytes
4233  *
4234  * The function does NOT add a null terminator to the string
4235  * automatically.
4236  */
4237 static int cpu_x86_fill_model_id(char *str)
4238 {
4239     uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
4240     int i;
4241
4242     for (i = 0; i < 3; i++) {
4243         host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
4244         memcpy(str + i * 16 +  0, &eax, 4);
4245         memcpy(str + i * 16 +  4, &ebx, 4);
4246         memcpy(str + i * 16 +  8, &ecx, 4);
4247         memcpy(str + i * 16 + 12, &edx, 4);
4248     }
4249     return 0;
4250 }
4251
4252 static Property max_x86_cpu_properties[] = {
4253     DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
4254     DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
4255     DEFINE_PROP_END_OF_LIST()
4256 };
4257
4258 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
4259 {
4260     DeviceClass *dc = DEVICE_CLASS(oc);
4261     X86CPUClass *xcc = X86_CPU_CLASS(oc);
4262
4263     xcc->ordering = 9;
4264
4265     xcc->model_description =
4266         "Enables all features supported by the accelerator in the current host";
4267
4268     device_class_set_props(dc, max_x86_cpu_properties);
4269 }
4270
4271 static void max_x86_cpu_initfn(Object *obj)
4272 {
4273     X86CPU *cpu = X86_CPU(obj);
4274     CPUX86State *env = &cpu->env;
4275     KVMState *s = kvm_state;
4276
4277     /* We can't fill the features array here because we don't know yet if
4278      * "migratable" is true or false.
4279      */
4280     cpu->max_features = true;
4281
4282     if (accel_uses_host_cpuid()) {
4283         char vendor[CPUID_VENDOR_SZ + 1] = { 0 };
4284         char model_id[CPUID_MODEL_ID_SZ + 1] = { 0 };
4285         int family, model, stepping;
4286
4287         host_vendor_fms(vendor, &family, &model, &stepping);
4288         cpu_x86_fill_model_id(model_id);
4289
4290         object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
4291         object_property_set_int(OBJECT(cpu), "family", family, &error_abort);
4292         object_property_set_int(OBJECT(cpu), "model", model, &error_abort);
4293         object_property_set_int(OBJECT(cpu), "stepping", stepping,
4294                                 &error_abort);
4295         object_property_set_str(OBJECT(cpu), "model-id", model_id,
4296                                 &error_abort);
4297
4298         if (kvm_enabled()) {
4299             env->cpuid_min_level =
4300                 kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
4301             env->cpuid_min_xlevel =
4302                 kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
4303             env->cpuid_min_xlevel2 =
4304                 kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
4305         } else {
4306             env->cpuid_min_level =
4307                 hvf_get_supported_cpuid(0x0, 0, R_EAX);
4308             env->cpuid_min_xlevel =
4309                 hvf_get_supported_cpuid(0x80000000, 0, R_EAX);
4310             env->cpuid_min_xlevel2 =
4311                 hvf_get_supported_cpuid(0xC0000000, 0, R_EAX);
4312         }
4313
4314         if (lmce_supported()) {
4315             object_property_set_bool(OBJECT(cpu), "lmce", true, &error_abort);
4316         }
4317     } else {
4318         object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4319                                 &error_abort);
4320         object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4321         object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4322         object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
4323         object_property_set_str(OBJECT(cpu), "model-id",
4324                                 "QEMU TCG CPU version " QEMU_HW_VERSION,
4325                                 &error_abort);
4326     }
4327
4328     object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
4329 }
4330
4331 static const TypeInfo max_x86_cpu_type_info = {
4332     .name = X86_CPU_TYPE_NAME("max"),
4333     .parent = TYPE_X86_CPU,
4334     .instance_init = max_x86_cpu_initfn,
4335     .class_init = max_x86_cpu_class_init,
4336 };
4337
4338 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
4339 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
4340 {
4341     X86CPUClass *xcc = X86_CPU_CLASS(oc);
4342
4343     xcc->host_cpuid_required = true;
4344     xcc->ordering = 8;
4345
4346 #if defined(CONFIG_KVM)
4347     xcc->model_description =
4348         "KVM processor with all supported host features ";
4349 #elif defined(CONFIG_HVF)
4350     xcc->model_description =
4351         "HVF processor with all supported host features ";
4352 #endif
4353 }
4354
4355 static const TypeInfo host_x86_cpu_type_info = {
4356     .name = X86_CPU_TYPE_NAME("host"),
4357     .parent = X86_CPU_TYPE_NAME("max"),
4358     .class_init = host_x86_cpu_class_init,
4359 };
4360
4361 #endif
4362
4363 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4364 {
4365     assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4366
4367     switch (f->type) {
4368     case CPUID_FEATURE_WORD:
4369         {
4370             const char *reg = get_register_name_32(f->cpuid.reg);
4371             assert(reg);
4372             return g_strdup_printf("CPUID.%02XH:%s",
4373                                    f->cpuid.eax, reg);
4374         }
4375     case MSR_FEATURE_WORD:
4376         return g_strdup_printf("MSR(%02XH)",
4377                                f->msr.index);
4378     }
4379
4380     return NULL;
4381 }
4382
4383 static bool x86_cpu_have_filtered_features(X86CPU *cpu)
4384 {
4385     FeatureWord w;
4386
4387     for (w = 0; w < FEATURE_WORDS; w++) {
4388         if (cpu->filtered_features[w]) {
4389             return true;
4390         }
4391     }
4392
4393     return false;
4394 }
4395
4396 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
4397                                       const char *verbose_prefix)
4398 {
4399     CPUX86State *env = &cpu->env;
4400     FeatureWordInfo *f = &feature_word_info[w];
4401     int i;
4402
4403     if (!cpu->force_features) {
4404         env->features[w] &= ~mask;
4405     }
4406     cpu->filtered_features[w] |= mask;
4407
4408     if (!verbose_prefix) {
4409         return;
4410     }
4411
4412     for (i = 0; i < 64; ++i) {
4413         if ((1ULL << i) & mask) {
4414             g_autofree char *feat_word_str = feature_word_description(f, i);
4415             warn_report("%s: %s%s%s [bit %d]",
4416                         verbose_prefix,
4417                         feat_word_str,
4418                         f->feat_names[i] ? "." : "",
4419                         f->feat_names[i] ? f->feat_names[i] : "", i);
4420         }
4421     }
4422 }
4423
4424 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4425                                          const char *name, void *opaque,
4426                                          Error **errp)
4427 {
4428     X86CPU *cpu = X86_CPU(obj);
4429     CPUX86State *env = &cpu->env;
4430     int64_t value;
4431
4432     value = (env->cpuid_version >> 8) & 0xf;
4433     if (value == 0xf) {
4434         value += (env->cpuid_version >> 20) & 0xff;
4435     }
4436     visit_type_int(v, name, &value, errp);
4437 }
4438
4439 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4440                                          const char *name, void *opaque,
4441                                          Error **errp)
4442 {
4443     X86CPU *cpu = X86_CPU(obj);
4444     CPUX86State *env = &cpu->env;
4445     const int64_t min = 0;
4446     const int64_t max = 0xff + 0xf;
4447     int64_t value;
4448
4449     if (!visit_type_int(v, name, &value, errp)) {
4450         return;
4451     }
4452     if (value < min || value > max) {
4453         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4454                    name ? name : "null", value, min, max);
4455         return;
4456     }
4457
4458     env->cpuid_version &= ~0xff00f00;
4459     if (value > 0x0f) {
4460         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
4461     } else {
4462         env->cpuid_version |= value << 8;
4463     }
4464 }
4465
4466 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4467                                         const char *name, void *opaque,
4468                                         Error **errp)
4469 {
4470     X86CPU *cpu = X86_CPU(obj);
4471     CPUX86State *env = &cpu->env;
4472     int64_t value;
4473
4474     value = (env->cpuid_version >> 4) & 0xf;
4475     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
4476     visit_type_int(v, name, &value, errp);
4477 }
4478
4479 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4480                                         const char *name, void *opaque,
4481                                         Error **errp)
4482 {
4483     X86CPU *cpu = X86_CPU(obj);
4484     CPUX86State *env = &cpu->env;
4485     const int64_t min = 0;
4486     const int64_t max = 0xff;
4487     int64_t value;
4488
4489     if (!visit_type_int(v, name, &value, errp)) {
4490         return;
4491     }
4492     if (value < min || value > max) {
4493         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4494                    name ? name : "null", value, min, max);
4495         return;
4496     }
4497
4498     env->cpuid_version &= ~0xf00f0;
4499     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
4500 }
4501
4502 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
4503                                            const char *name, void *opaque,
4504                                            Error **errp)
4505 {
4506     X86CPU *cpu = X86_CPU(obj);
4507     CPUX86State *env = &cpu->env;
4508     int64_t value;
4509
4510     value = env->cpuid_version & 0xf;
4511     visit_type_int(v, name, &value, errp);
4512 }
4513
4514 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
4515                                            const char *name, void *opaque,
4516                                            Error **errp)
4517 {
4518     X86CPU *cpu = X86_CPU(obj);
4519     CPUX86State *env = &cpu->env;
4520     const int64_t min = 0;
4521     const int64_t max = 0xf;
4522     int64_t value;
4523
4524     if (!visit_type_int(v, name, &value, errp)) {
4525         return;
4526     }
4527     if (value < min || value > max) {
4528         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4529                    name ? name : "null", value, min, max);
4530         return;
4531     }
4532
4533     env->cpuid_version &= ~0xf;
4534     env->cpuid_version |= value & 0xf;
4535 }
4536
4537 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4538 {
4539     X86CPU *cpu = X86_CPU(obj);
4540     CPUX86State *env = &cpu->env;
4541     char *value;
4542
4543     value = g_malloc(CPUID_VENDOR_SZ + 1);
4544     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4545                              env->cpuid_vendor3);
4546     return value;
4547 }
4548
4549 static void x86_cpuid_set_vendor(Object *obj, const char *value,
4550                                  Error **errp)
4551 {
4552     X86CPU *cpu = X86_CPU(obj);
4553     CPUX86State *env = &cpu->env;
4554     int i;
4555
4556     if (strlen(value) != CPUID_VENDOR_SZ) {
4557         error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
4558         return;
4559     }
4560
4561     env->cpuid_vendor1 = 0;
4562     env->cpuid_vendor2 = 0;
4563     env->cpuid_vendor3 = 0;
4564     for (i = 0; i < 4; i++) {
4565         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
4566         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4567         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4568     }
4569 }
4570
4571 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4572 {
4573     X86CPU *cpu = X86_CPU(obj);
4574     CPUX86State *env = &cpu->env;
4575     char *value;
4576     int i;
4577
4578     value = g_malloc(48 + 1);
4579     for (i = 0; i < 48; i++) {
4580         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4581     }
4582     value[48] = '\0';
4583     return value;
4584 }
4585
4586 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4587                                    Error **errp)
4588 {
4589     X86CPU *cpu = X86_CPU(obj);
4590     CPUX86State *env = &cpu->env;
4591     int c, len, i;
4592
4593     if (model_id == NULL) {
4594         model_id = "";
4595     }
4596     len = strlen(model_id);
4597     memset(env->cpuid_model, 0, 48);
4598     for (i = 0; i < 48; i++) {
4599         if (i >= len) {
4600             c = '\0';
4601         } else {
4602             c = (uint8_t)model_id[i];
4603         }
4604         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4605     }
4606 }
4607
4608 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4609                                    void *opaque, Error **errp)
4610 {
4611     X86CPU *cpu = X86_CPU(obj);
4612     int64_t value;
4613
4614     value = cpu->env.tsc_khz * 1000;
4615     visit_type_int(v, name, &value, errp);
4616 }
4617
4618 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4619                                    void *opaque, Error **errp)
4620 {
4621     X86CPU *cpu = X86_CPU(obj);
4622     const int64_t min = 0;
4623     const int64_t max = INT64_MAX;
4624     int64_t value;
4625
4626     if (!visit_type_int(v, name, &value, errp)) {
4627         return;
4628     }
4629     if (value < min || value > max) {
4630         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4631                    name ? name : "null", value, min, max);
4632         return;
4633     }
4634
4635     cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
4636 }
4637
4638 /* Generic getter for "feature-words" and "filtered-features" properties */
4639 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4640                                       const char *name, void *opaque,
4641                                       Error **errp)
4642 {
4643     uint64_t *array = (uint64_t *)opaque;
4644     FeatureWord w;
4645     X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4646     X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4647     X86CPUFeatureWordInfoList *list = NULL;
4648
4649     for (w = 0; w < FEATURE_WORDS; w++) {
4650         FeatureWordInfo *wi = &feature_word_info[w];
4651         /*
4652                 * We didn't have MSR features when "feature-words" was
4653                 *  introduced. Therefore skipped other type entries.
4654                 */
4655         if (wi->type != CPUID_FEATURE_WORD) {
4656             continue;
4657         }
4658         X86CPUFeatureWordInfo *qwi = &word_infos[w];
4659         qwi->cpuid_input_eax = wi->cpuid.eax;
4660         qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4661         qwi->cpuid_input_ecx = wi->cpuid.ecx;
4662         qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
4663         qwi->features = array[w];
4664
4665         /* List will be in reverse order, but order shouldn't matter */
4666         list_entries[w].next = list;
4667         list_entries[w].value = &word_infos[w];
4668         list = &list_entries[w];
4669     }
4670
4671     visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
4672 }
4673
4674 /* Convert all '_' in a feature string option name to '-', to make feature
4675  * name conform to QOM property naming rule, which uses '-' instead of '_'.
4676  */
4677 static inline void feat2prop(char *s)
4678 {
4679     while ((s = strchr(s, '_'))) {
4680         *s = '-';
4681     }
4682 }
4683
4684 /* Return the feature property name for a feature flag bit */
4685 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4686 {
4687     const char *name;
4688     /* XSAVE components are automatically enabled by other features,
4689      * so return the original feature name instead
4690      */
4691     if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4692         int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4693
4694         if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4695             x86_ext_save_areas[comp].bits) {
4696             w = x86_ext_save_areas[comp].feature;
4697             bitnr = ctz32(x86_ext_save_areas[comp].bits);
4698         }
4699     }
4700
4701     assert(bitnr < 64);
4702     assert(w < FEATURE_WORDS);
4703     name = feature_word_info[w].feat_names[bitnr];
4704     assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4705     return name;
4706 }
4707
4708 /* Compatibily hack to maintain legacy +-feat semantic,
4709  * where +-feat overwrites any feature set by
4710  * feat=on|feat even if the later is parsed after +-feat
4711  * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4712  */
4713 static GList *plus_features, *minus_features;
4714
4715 static gint compare_string(gconstpointer a, gconstpointer b)
4716 {
4717     return g_strcmp0(a, b);
4718 }
4719
4720 /* Parse "+feature,-feature,feature=foo" CPU feature string
4721  */
4722 static void x86_cpu_parse_featurestr(const char *typename, char *features,
4723                                      Error **errp)
4724 {
4725     char *featurestr; /* Single 'key=value" string being parsed */
4726     static bool cpu_globals_initialized;
4727     bool ambiguous = false;
4728
4729     if (cpu_globals_initialized) {
4730         return;
4731     }
4732     cpu_globals_initialized = true;
4733
4734     if (!features) {
4735         return;
4736     }
4737
4738     for (featurestr = strtok(features, ",");
4739          featurestr;
4740          featurestr = strtok(NULL, ",")) {
4741         const char *name;
4742         const char *val = NULL;
4743         char *eq = NULL;
4744         char num[32];
4745         GlobalProperty *prop;
4746
4747         /* Compatibility syntax: */
4748         if (featurestr[0] == '+') {
4749             plus_features = g_list_append(plus_features,
4750                                           g_strdup(featurestr + 1));
4751             continue;
4752         } else if (featurestr[0] == '-') {
4753             minus_features = g_list_append(minus_features,
4754                                            g_strdup(featurestr + 1));
4755             continue;
4756         }
4757
4758         eq = strchr(featurestr, '=');
4759         if (eq) {
4760             *eq++ = 0;
4761             val = eq;
4762         } else {
4763             val = "on";
4764         }
4765
4766         feat2prop(featurestr);
4767         name = featurestr;
4768
4769         if (g_list_find_custom(plus_features, name, compare_string)) {
4770             warn_report("Ambiguous CPU model string. "
4771                         "Don't mix both \"+%s\" and \"%s=%s\"",
4772                         name, name, val);
4773             ambiguous = true;
4774         }
4775         if (g_list_find_custom(minus_features, name, compare_string)) {
4776             warn_report("Ambiguous CPU model string. "
4777                         "Don't mix both \"-%s\" and \"%s=%s\"",
4778                         name, name, val);
4779             ambiguous = true;
4780         }
4781
4782         /* Special case: */
4783         if (!strcmp(name, "tsc-freq")) {
4784             int ret;
4785             uint64_t tsc_freq;
4786
4787             ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
4788             if (ret < 0 || tsc_freq > INT64_MAX) {
4789                 error_setg(errp, "bad numerical value %s", val);
4790                 return;
4791             }
4792             snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4793             val = num;
4794             name = "tsc-frequency";
4795         }
4796
4797         prop = g_new0(typeof(*prop), 1);
4798         prop->driver = typename;
4799         prop->property = g_strdup(name);
4800         prop->value = g_strdup(val);
4801         qdev_prop_register_global(prop);
4802     }
4803
4804     if (ambiguous) {
4805         warn_report("Compatibility of ambiguous CPU model "
4806                     "strings won't be kept on future QEMU versions");
4807     }
4808 }
4809
4810 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
4811 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
4812
4813 /* Build a list with the name of all features on a feature word array */
4814 static void x86_cpu_list_feature_names(FeatureWordArray features,
4815                                        strList **feat_names)
4816 {
4817     FeatureWord w;
4818     strList **next = feat_names;
4819
4820     for (w = 0; w < FEATURE_WORDS; w++) {
4821         uint64_t filtered = features[w];
4822         int i;
4823         for (i = 0; i < 64; i++) {
4824             if (filtered & (1ULL << i)) {
4825                 strList *new = g_new0(strList, 1);
4826                 new->value = g_strdup(x86_cpu_feature_name(w, i));
4827                 *next = new;
4828                 next = &new->next;
4829             }
4830         }
4831     }
4832 }
4833
4834 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4835                                              const char *name, void *opaque,
4836                                              Error **errp)
4837 {
4838     X86CPU *xc = X86_CPU(obj);
4839     strList *result = NULL;
4840
4841     x86_cpu_list_feature_names(xc->filtered_features, &result);
4842     visit_type_strList(v, "unavailable-features", &result, errp);
4843 }
4844
4845 /* Check for missing features that may prevent the CPU class from
4846  * running using the current machine and accelerator.
4847  */
4848 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4849                                                  strList **missing_feats)
4850 {
4851     X86CPU *xc;
4852     Error *err = NULL;
4853     strList **next = missing_feats;
4854
4855     if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
4856         strList *new = g_new0(strList, 1);
4857         new->value = g_strdup("kvm");
4858         *missing_feats = new;
4859         return;
4860     }
4861
4862     xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
4863
4864     x86_cpu_expand_features(xc, &err);
4865     if (err) {
4866         /* Errors at x86_cpu_expand_features should never happen,
4867          * but in case it does, just report the model as not
4868          * runnable at all using the "type" property.
4869          */
4870         strList *new = g_new0(strList, 1);
4871         new->value = g_strdup("type");
4872         *next = new;
4873         next = &new->next;
4874         error_free(err);
4875     }
4876
4877     x86_cpu_filter_features(xc, false);
4878
4879     x86_cpu_list_feature_names(xc->filtered_features, next);
4880
4881     object_unref(OBJECT(xc));
4882 }
4883
4884 /* Print all cpuid feature names in featureset
4885  */
4886 static void listflags(GList *features)
4887 {
4888     size_t len = 0;
4889     GList *tmp;
4890
4891     for (tmp = features; tmp; tmp = tmp->next) {
4892         const char *name = tmp->data;
4893         if ((len + strlen(name) + 1) >= 75) {
4894             qemu_printf("\n");
4895             len = 0;
4896         }
4897         qemu_printf("%s%s", len == 0 ? "  " : " ", name);
4898         len += strlen(name) + 1;
4899     }
4900     qemu_printf("\n");
4901 }
4902
4903 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
4904 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4905 {
4906     ObjectClass *class_a = (ObjectClass *)a;
4907     ObjectClass *class_b = (ObjectClass *)b;
4908     X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4909     X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
4910     int ret;
4911
4912     if (cc_a->ordering != cc_b->ordering) {
4913         ret = cc_a->ordering - cc_b->ordering;
4914     } else {
4915         g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4916         g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
4917         ret = strcmp(name_a, name_b);
4918     }
4919     return ret;
4920 }
4921
4922 static GSList *get_sorted_cpu_model_list(void)
4923 {
4924     GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4925     list = g_slist_sort(list, x86_cpu_list_compare);
4926     return list;
4927 }
4928
4929 static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4930 {
4931     Object *obj = object_new_with_class(OBJECT_CLASS(xc));
4932     char *r = object_property_get_str(obj, "model-id", &error_abort);
4933     object_unref(obj);
4934     return r;
4935 }
4936
4937 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4938 {
4939     X86CPUVersion version;
4940
4941     if (!cc->model || !cc->model->is_alias) {
4942         return NULL;
4943     }
4944     version = x86_cpu_model_resolve_version(cc->model);
4945     if (version <= 0) {
4946         return NULL;
4947     }
4948     return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4949 }
4950
4951 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4952 {
4953     ObjectClass *oc = data;
4954     X86CPUClass *cc = X86_CPU_CLASS(oc);
4955     g_autofree char *name = x86_cpu_class_get_model_name(cc);
4956     g_autofree char *desc = g_strdup(cc->model_description);
4957     g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
4958     g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
4959
4960     if (!desc && alias_of) {
4961         if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4962             desc = g_strdup("(alias configured by machine type)");
4963         } else {
4964             desc = g_strdup_printf("(alias of %s)", alias_of);
4965         }
4966     }
4967     if (!desc && cc->model && cc->model->note) {
4968         desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4969     }
4970     if (!desc) {
4971         desc = g_strdup_printf("%s", model_id);
4972     }
4973
4974     qemu_printf("x86 %-20s  %-58s\n", name, desc);
4975 }
4976
4977 /* list available CPU models and flags */
4978 void x86_cpu_list(void)
4979 {
4980     int i, j;
4981     GSList *list;
4982     GList *names = NULL;
4983
4984     qemu_printf("Available CPUs:\n");
4985     list = get_sorted_cpu_model_list();
4986     g_slist_foreach(list, x86_cpu_list_entry, NULL);
4987     g_slist_free(list);
4988
4989     names = NULL;
4990     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4991         FeatureWordInfo *fw = &feature_word_info[i];
4992         for (j = 0; j < 64; j++) {
4993             if (fw->feat_names[j]) {
4994                 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4995             }
4996         }
4997     }
4998
4999     names = g_list_sort(names, (GCompareFunc)strcmp);
5000
5001     qemu_printf("\nRecognized CPUID flags:\n");
5002     listflags(names);
5003     qemu_printf("\n");
5004     g_list_free(names);
5005 }
5006
5007 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
5008 {
5009     ObjectClass *oc = data;
5010     X86CPUClass *cc = X86_CPU_CLASS(oc);
5011     CpuDefinitionInfoList **cpu_list = user_data;
5012     CpuDefinitionInfoList *entry;
5013     CpuDefinitionInfo *info;
5014
5015     info = g_malloc0(sizeof(*info));
5016     info->name = x86_cpu_class_get_model_name(cc);
5017     x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
5018     info->has_unavailable_features = true;
5019     info->q_typename = g_strdup(object_class_get_name(oc));
5020     info->migration_safe = cc->migration_safe;
5021     info->has_migration_safe = true;
5022     info->q_static = cc->static_model;
5023     if (cc->model && cc->model->cpudef->deprecation_note) {
5024         info->deprecated = true;
5025     } else {
5026         info->deprecated = false;
5027     }
5028     /*
5029      * Old machine types won't report aliases, so that alias translation
5030      * doesn't break compatibility with previous QEMU versions.
5031      */
5032     if (default_cpu_version != CPU_VERSION_LEGACY) {
5033         info->alias_of = x86_cpu_class_get_alias_of(cc);
5034         info->has_alias_of = !!info->alias_of;
5035     }
5036
5037     entry = g_malloc0(sizeof(*entry));
5038     entry->value = info;
5039     entry->next = *cpu_list;
5040     *cpu_list = entry;
5041 }
5042
5043 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
5044 {
5045     CpuDefinitionInfoList *cpu_list = NULL;
5046     GSList *list = get_sorted_cpu_model_list();
5047     g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
5048     g_slist_free(list);
5049     return cpu_list;
5050 }
5051
5052 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
5053                                                    bool migratable_only)
5054 {
5055     FeatureWordInfo *wi = &feature_word_info[w];
5056     uint64_t r = 0;
5057
5058     if (kvm_enabled()) {
5059         switch (wi->type) {
5060         case CPUID_FEATURE_WORD:
5061             r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
5062                                                         wi->cpuid.ecx,
5063                                                         wi->cpuid.reg);
5064             break;
5065         case MSR_FEATURE_WORD:
5066             r = kvm_arch_get_supported_msr_feature(kvm_state,
5067                         wi->msr.index);
5068             break;
5069         }
5070     } else if (hvf_enabled()) {
5071         if (wi->type != CPUID_FEATURE_WORD) {
5072             return 0;
5073         }
5074         r = hvf_get_supported_cpuid(wi->cpuid.eax,
5075                                     wi->cpuid.ecx,
5076                                     wi->cpuid.reg);
5077     } else if (tcg_enabled()) {
5078         r = wi->tcg_features;
5079     } else {
5080         return ~0;
5081     }
5082     if (migratable_only) {
5083         r &= x86_cpu_get_migratable_flags(w);
5084     }
5085     return r;
5086 }
5087
5088 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5089 {
5090     PropValue *pv;
5091     for (pv = props; pv->prop; pv++) {
5092         if (!pv->value) {
5093             continue;
5094         }
5095         object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5096                               &error_abort);
5097     }
5098 }
5099
5100 /* Apply properties for the CPU model version specified in model */
5101 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5102 {
5103     const X86CPUVersionDefinition *vdef;
5104     X86CPUVersion version = x86_cpu_model_resolve_version(model);
5105
5106     if (version == CPU_VERSION_LEGACY) {
5107         return;
5108     }
5109
5110     for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5111         PropValue *p;
5112
5113         for (p = vdef->props; p && p->prop; p++) {
5114             object_property_parse(OBJECT(cpu), p->prop, p->value,
5115                                   &error_abort);
5116         }
5117
5118         if (vdef->version == version) {
5119             break;
5120         }
5121     }
5122
5123     /*
5124      * If we reached the end of the list, version number was invalid
5125      */
5126     assert(vdef->version == version);
5127 }
5128
5129 /* Load data from X86CPUDefinition into a X86CPU object
5130  */
5131 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
5132 {
5133     X86CPUDefinition *def = model->cpudef;
5134     CPUX86State *env = &cpu->env;
5135     const char *vendor;
5136     char host_vendor[CPUID_VENDOR_SZ + 1];
5137     FeatureWord w;
5138
5139     /*NOTE: any property set by this function should be returned by
5140      * x86_cpu_static_props(), so static expansion of
5141      * query-cpu-model-expansion is always complete.
5142      */
5143
5144     /* CPU models only set _minimum_ values for level/xlevel: */
5145     object_property_set_uint(OBJECT(cpu), "min-level", def->level,
5146                              &error_abort);
5147     object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
5148                              &error_abort);
5149
5150     object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5151     object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5152     object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
5153                             &error_abort);
5154     object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
5155                             &error_abort);
5156     for (w = 0; w < FEATURE_WORDS; w++) {
5157         env->features[w] = def->features[w];
5158     }
5159
5160     /* legacy-cache defaults to 'off' if CPU model provides cache info */
5161     cpu->legacy_cache = !def->cache_info;
5162
5163     /* Special cases not set in the X86CPUDefinition structs: */
5164     /* TODO: in-kernel irqchip for hvf */
5165     if (kvm_enabled()) {
5166         if (!kvm_irqchip_in_kernel()) {
5167             x86_cpu_change_kvm_default("x2apic", "off");
5168         }
5169
5170         x86_cpu_apply_props(cpu, kvm_default_props);
5171     } else if (tcg_enabled()) {
5172         x86_cpu_apply_props(cpu, tcg_default_props);
5173     }
5174
5175     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
5176
5177     /* sysenter isn't supported in compatibility mode on AMD,
5178      * syscall isn't supported in compatibility mode on Intel.
5179      * Normally we advertise the actual CPU vendor, but you can
5180      * override this using the 'vendor' property if you want to use
5181      * KVM's sysenter/syscall emulation in compatibility mode and
5182      * when doing cross vendor migration
5183      */
5184     vendor = def->vendor;
5185     if (accel_uses_host_cpuid()) {
5186         uint32_t  ebx = 0, ecx = 0, edx = 0;
5187         host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
5188         x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
5189         vendor = host_vendor;
5190     }
5191
5192     object_property_set_str(OBJECT(cpu), "vendor", vendor, &error_abort);
5193
5194     x86_cpu_apply_version_props(cpu, model);
5195
5196     /*
5197      * Properties in versioned CPU model are not user specified features.
5198      * We can simply clear env->user_features here since it will be filled later
5199      * in x86_cpu_expand_features() based on plus_features and minus_features.
5200      */
5201     memset(&env->user_features, 0, sizeof(env->user_features));
5202 }
5203
5204 #ifndef CONFIG_USER_ONLY
5205 /* Return a QDict containing keys for all properties that can be included
5206  * in static expansion of CPU models. All properties set by x86_cpu_load_model()
5207  * must be included in the dictionary.
5208  */
5209 static QDict *x86_cpu_static_props(void)
5210 {
5211     FeatureWord w;
5212     int i;
5213     static const char *props[] = {
5214         "min-level",
5215         "min-xlevel",
5216         "family",
5217         "model",
5218         "stepping",
5219         "model-id",
5220         "vendor",
5221         "lmce",
5222         NULL,
5223     };
5224     static QDict *d;
5225
5226     if (d) {
5227         return d;
5228     }
5229
5230     d = qdict_new();
5231     for (i = 0; props[i]; i++) {
5232         qdict_put_null(d, props[i]);
5233     }
5234
5235     for (w = 0; w < FEATURE_WORDS; w++) {
5236         FeatureWordInfo *fi = &feature_word_info[w];
5237         int bit;
5238         for (bit = 0; bit < 64; bit++) {
5239             if (!fi->feat_names[bit]) {
5240                 continue;
5241             }
5242             qdict_put_null(d, fi->feat_names[bit]);
5243         }
5244     }
5245
5246     return d;
5247 }
5248
5249 /* Add an entry to @props dict, with the value for property. */
5250 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5251 {
5252     QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5253                                                  &error_abort);
5254
5255     qdict_put_obj(props, prop, value);
5256 }
5257
5258 /* Convert CPU model data from X86CPU object to a property dictionary
5259  * that can recreate exactly the same CPU model.
5260  */
5261 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5262 {
5263     QDict *sprops = x86_cpu_static_props();
5264     const QDictEntry *e;
5265
5266     for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5267         const char *prop = qdict_entry_key(e);
5268         x86_cpu_expand_prop(cpu, props, prop);
5269     }
5270 }
5271
5272 /* Convert CPU model data from X86CPU object to a property dictionary
5273  * that can recreate exactly the same CPU model, including every
5274  * writeable QOM property.
5275  */
5276 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5277 {
5278     ObjectPropertyIterator iter;
5279     ObjectProperty *prop;
5280
5281     object_property_iter_init(&iter, OBJECT(cpu));
5282     while ((prop = object_property_iter_next(&iter))) {
5283         /* skip read-only or write-only properties */
5284         if (!prop->get || !prop->set) {
5285             continue;
5286         }
5287
5288         /* "hotplugged" is the only property that is configurable
5289          * on the command-line but will be set differently on CPUs
5290          * created using "-cpu ... -smp ..." and by CPUs created
5291          * on the fly by x86_cpu_from_model() for querying. Skip it.
5292          */
5293         if (!strcmp(prop->name, "hotplugged")) {
5294             continue;
5295         }
5296         x86_cpu_expand_prop(cpu, props, prop->name);
5297     }
5298 }
5299
5300 static void object_apply_props(Object *obj, QDict *props, Error **errp)
5301 {
5302     const QDictEntry *prop;
5303
5304     for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
5305         if (!object_property_set_qobject(obj, qdict_entry_key(prop),
5306                                          qdict_entry_value(prop), errp)) {
5307             break;
5308         }
5309     }
5310 }
5311
5312 /* Create X86CPU object according to model+props specification */
5313 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5314 {
5315     X86CPU *xc = NULL;
5316     X86CPUClass *xcc;
5317     Error *err = NULL;
5318
5319     xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5320     if (xcc == NULL) {
5321         error_setg(&err, "CPU model '%s' not found", model);
5322         goto out;
5323     }
5324
5325     xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5326     if (props) {
5327         object_apply_props(OBJECT(xc), props, &err);
5328         if (err) {
5329             goto out;
5330         }
5331     }
5332
5333     x86_cpu_expand_features(xc, &err);
5334     if (err) {
5335         goto out;
5336     }
5337
5338 out:
5339     if (err) {
5340         error_propagate(errp, err);
5341         object_unref(OBJECT(xc));
5342         xc = NULL;
5343     }
5344     return xc;
5345 }
5346
5347 CpuModelExpansionInfo *
5348 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
5349                                                       CpuModelInfo *model,
5350                                                       Error **errp)
5351 {
5352     X86CPU *xc = NULL;
5353     Error *err = NULL;
5354     CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5355     QDict *props = NULL;
5356     const char *base_name;
5357
5358     xc = x86_cpu_from_model(model->name,
5359                             model->has_props ?
5360                                 qobject_to(QDict, model->props) :
5361                                 NULL, &err);
5362     if (err) {
5363         goto out;
5364     }
5365
5366     props = qdict_new();
5367     ret->model = g_new0(CpuModelInfo, 1);
5368     ret->model->props = QOBJECT(props);
5369     ret->model->has_props = true;
5370
5371     switch (type) {
5372     case CPU_MODEL_EXPANSION_TYPE_STATIC:
5373         /* Static expansion will be based on "base" only */
5374         base_name = "base";
5375         x86_cpu_to_dict(xc, props);
5376     break;
5377     case CPU_MODEL_EXPANSION_TYPE_FULL:
5378         /* As we don't return every single property, full expansion needs
5379          * to keep the original model name+props, and add extra
5380          * properties on top of that.
5381          */
5382         base_name = model->name;
5383         x86_cpu_to_dict_full(xc, props);
5384     break;
5385     default:
5386         error_setg(&err, "Unsupported expansion type");
5387         goto out;
5388     }
5389
5390     x86_cpu_to_dict(xc, props);
5391
5392     ret->model->name = g_strdup(base_name);
5393
5394 out:
5395     object_unref(OBJECT(xc));
5396     if (err) {
5397         error_propagate(errp, err);
5398         qapi_free_CpuModelExpansionInfo(ret);
5399         ret = NULL;
5400     }
5401     return ret;
5402 }
5403 #endif  /* !CONFIG_USER_ONLY */
5404
5405 static gchar *x86_gdb_arch_name(CPUState *cs)
5406 {
5407 #ifdef TARGET_X86_64
5408     return g_strdup("i386:x86-64");
5409 #else
5410     return g_strdup("i386");
5411 #endif
5412 }
5413
5414 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5415 {
5416     X86CPUModel *model = data;
5417     X86CPUClass *xcc = X86_CPU_CLASS(oc);
5418     CPUClass *cc = CPU_CLASS(oc);
5419
5420     xcc->model = model;
5421     xcc->migration_safe = true;
5422     cc->deprecation_note = model->cpudef->deprecation_note;
5423 }
5424
5425 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
5426 {
5427     g_autofree char *typename = x86_cpu_type_name(name);
5428     TypeInfo ti = {
5429         .name = typename,
5430         .parent = TYPE_X86_CPU,
5431         .class_init = x86_cpu_cpudef_class_init,
5432         .class_data = model,
5433     };
5434
5435     type_register(&ti);
5436 }
5437
5438 static void x86_register_cpudef_types(X86CPUDefinition *def)
5439 {
5440     X86CPUModel *m;
5441     const X86CPUVersionDefinition *vdef;
5442
5443     /* AMD aliases are handled at runtime based on CPUID vendor, so
5444      * they shouldn't be set on the CPU model table.
5445      */
5446     assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
5447     /* catch mistakes instead of silently truncating model_id when too long */
5448     assert(def->model_id && strlen(def->model_id) <= 48);
5449
5450     /* Unversioned model: */
5451     m = g_new0(X86CPUModel, 1);
5452     m->cpudef = def;
5453     m->version = CPU_VERSION_AUTO;
5454     m->is_alias = true;
5455     x86_register_cpu_model_type(def->name, m);
5456
5457     /* Versioned models: */
5458
5459     for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5460         X86CPUModel *m = g_new0(X86CPUModel, 1);
5461         g_autofree char *name =
5462             x86_cpu_versioned_model_name(def, vdef->version);
5463         m->cpudef = def;
5464         m->version = vdef->version;
5465         m->note = vdef->note;
5466         x86_register_cpu_model_type(name, m);
5467
5468         if (vdef->alias) {
5469             X86CPUModel *am = g_new0(X86CPUModel, 1);
5470             am->cpudef = def;
5471             am->version = vdef->version;
5472             am->is_alias = true;
5473             x86_register_cpu_model_type(vdef->alias, am);
5474         }
5475     }
5476
5477 }
5478
5479 #if !defined(CONFIG_USER_ONLY)
5480
5481 void cpu_clear_apic_feature(CPUX86State *env)
5482 {
5483     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
5484 }
5485
5486 #endif /* !CONFIG_USER_ONLY */
5487
5488 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5489                    uint32_t *eax, uint32_t *ebx,
5490                    uint32_t *ecx, uint32_t *edx)
5491 {
5492     X86CPU *cpu = env_archcpu(env);
5493     CPUState *cs = env_cpu(env);
5494     uint32_t die_offset;
5495     uint32_t limit;
5496     uint32_t signature[3];
5497     X86CPUTopoInfo topo_info;
5498
5499     topo_info.dies_per_pkg = env->nr_dies;
5500     topo_info.cores_per_die = cs->nr_cores;
5501     topo_info.threads_per_core = cs->nr_threads;
5502
5503     /* Calculate & apply limits for different index ranges */
5504     if (index >= 0xC0000000) {
5505         limit = env->cpuid_xlevel2;
5506     } else if (index >= 0x80000000) {
5507         limit = env->cpuid_xlevel;
5508     } else if (index >= 0x40000000) {
5509         limit = 0x40000001;
5510     } else {
5511         limit = env->cpuid_level;
5512     }
5513
5514     if (index > limit) {
5515         /* Intel documentation states that invalid EAX input will
5516          * return the same information as EAX=cpuid_level
5517          * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5518          */
5519         index = env->cpuid_level;
5520     }
5521
5522     switch(index) {
5523     case 0:
5524         *eax = env->cpuid_level;
5525         *ebx = env->cpuid_vendor1;
5526         *edx = env->cpuid_vendor2;
5527         *ecx = env->cpuid_vendor3;
5528         break;
5529     case 1:
5530         *eax = env->cpuid_version;
5531         *ebx = (cpu->apic_id << 24) |
5532                8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5533         *ecx = env->features[FEAT_1_ECX];
5534         if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5535             *ecx |= CPUID_EXT_OSXSAVE;
5536         }
5537         *edx = env->features[FEAT_1_EDX];
5538         if (cs->nr_cores * cs->nr_threads > 1) {
5539             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
5540             *edx |= CPUID_HT;
5541         }
5542         if (!cpu->enable_pmu) {
5543             *ecx &= ~CPUID_EXT_PDCM;
5544         }
5545         break;
5546     case 2:
5547         /* cache info: needed for Pentium Pro compatibility */
5548         if (cpu->cache_info_passthrough) {
5549             host_cpuid(index, 0, eax, ebx, ecx, edx);
5550             break;
5551         }
5552         *eax = 1; /* Number of CPUID[EAX=2] calls required */
5553         *ebx = 0;
5554         if (!cpu->enable_l3_cache) {
5555             *ecx = 0;
5556         } else {
5557             *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
5558         }
5559         *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5560                (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) <<  8) |
5561                (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
5562         break;
5563     case 4:
5564         /* cache info: needed for Core compatibility */
5565         if (cpu->cache_info_passthrough) {
5566             host_cpuid(index, count, eax, ebx, ecx, edx);
5567             /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  */
5568             *eax &= ~0xFC000000;
5569             if ((*eax & 31) && cs->nr_cores > 1) {
5570                 *eax |= (cs->nr_cores - 1) << 26;
5571             }
5572         } else {
5573             *eax = 0;
5574             switch (count) {
5575             case 0: /* L1 dcache info */
5576                 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5577                                     1, cs->nr_cores,
5578                                     eax, ebx, ecx, edx);
5579                 break;
5580             case 1: /* L1 icache info */
5581                 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5582                                     1, cs->nr_cores,
5583                                     eax, ebx, ecx, edx);
5584                 break;
5585             case 2: /* L2 cache info */
5586                 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5587                                     cs->nr_threads, cs->nr_cores,
5588                                     eax, ebx, ecx, edx);
5589                 break;
5590             case 3: /* L3 cache info */
5591                 die_offset = apicid_die_offset(&topo_info);
5592                 if (cpu->enable_l3_cache) {
5593                     encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
5594                                         (1 << die_offset), cs->nr_cores,
5595                                         eax, ebx, ecx, edx);
5596                     break;
5597                 }
5598                 /* fall through */
5599             default: /* end of info */
5600                 *eax = *ebx = *ecx = *edx = 0;
5601                 break;
5602             }
5603         }
5604         break;
5605     case 5:
5606         /* MONITOR/MWAIT Leaf */
5607         *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5608         *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5609         *ecx = cpu->mwait.ecx; /* flags */
5610         *edx = cpu->mwait.edx; /* mwait substates */
5611         break;
5612     case 6:
5613         /* Thermal and Power Leaf */
5614         *eax = env->features[FEAT_6_EAX];
5615         *ebx = 0;
5616         *ecx = 0;
5617         *edx = 0;
5618         break;
5619     case 7:
5620         /* Structured Extended Feature Flags Enumeration Leaf */
5621         if (count == 0) {
5622             /* Maximum ECX value for sub-leaves */
5623             *eax = env->cpuid_level_func7;
5624             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
5625             *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
5626             if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5627                 *ecx |= CPUID_7_0_ECX_OSPKE;
5628             }
5629             *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
5630         } else if (count == 1) {
5631             *eax = env->features[FEAT_7_1_EAX];
5632             *ebx = 0;
5633             *ecx = 0;
5634             *edx = 0;
5635         } else {
5636             *eax = 0;
5637             *ebx = 0;
5638             *ecx = 0;
5639             *edx = 0;
5640         }
5641         break;
5642     case 9:
5643         /* Direct Cache Access Information Leaf */
5644         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5645         *ebx = 0;
5646         *ecx = 0;
5647         *edx = 0;
5648         break;
5649     case 0xA:
5650         /* Architectural Performance Monitoring Leaf */
5651         if (kvm_enabled() && cpu->enable_pmu) {
5652             KVMState *s = cs->kvm_state;
5653
5654             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5655             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5656             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5657             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
5658         } else if (hvf_enabled() && cpu->enable_pmu) {
5659             *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5660             *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5661             *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5662             *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
5663         } else {
5664             *eax = 0;
5665             *ebx = 0;
5666             *ecx = 0;
5667             *edx = 0;
5668         }
5669         break;
5670     case 0xB:
5671         /* Extended Topology Enumeration Leaf */
5672         if (!cpu->enable_cpuid_0xb) {
5673                 *eax = *ebx = *ecx = *edx = 0;
5674                 break;
5675         }
5676
5677         *ecx = count & 0xff;
5678         *edx = cpu->apic_id;
5679
5680         switch (count) {
5681         case 0:
5682             *eax = apicid_core_offset(&topo_info);
5683             *ebx = cs->nr_threads;
5684             *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5685             break;
5686         case 1:
5687             *eax = apicid_pkg_offset(&topo_info);
5688             *ebx = cs->nr_cores * cs->nr_threads;
5689             *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5690             break;
5691         default:
5692             *eax = 0;
5693             *ebx = 0;
5694             *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5695         }
5696
5697         assert(!(*eax & ~0x1f));
5698         *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5699         break;
5700     case 0x1F:
5701         /* V2 Extended Topology Enumeration Leaf */
5702         if (env->nr_dies < 2) {
5703             *eax = *ebx = *ecx = *edx = 0;
5704             break;
5705         }
5706
5707         *ecx = count & 0xff;
5708         *edx = cpu->apic_id;
5709         switch (count) {
5710         case 0:
5711             *eax = apicid_core_offset(&topo_info);
5712             *ebx = cs->nr_threads;
5713             *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5714             break;
5715         case 1:
5716             *eax = apicid_die_offset(&topo_info);
5717             *ebx = cs->nr_cores * cs->nr_threads;
5718             *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5719             break;
5720         case 2:
5721             *eax = apicid_pkg_offset(&topo_info);
5722             *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5723             *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5724             break;
5725         default:
5726             *eax = 0;
5727             *ebx = 0;
5728             *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5729         }
5730         assert(!(*eax & ~0x1f));
5731         *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5732         break;
5733     case 0xD: {
5734         /* Processor Extended State */
5735         *eax = 0;
5736         *ebx = 0;
5737         *ecx = 0;
5738         *edx = 0;
5739         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
5740             break;
5741         }
5742
5743         if (count == 0) {
5744             *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5745             *eax = env->features[FEAT_XSAVE_COMP_LO];
5746             *edx = env->features[FEAT_XSAVE_COMP_HI];
5747             /*
5748              * The initial value of xcr0 and ebx == 0, On host without kvm
5749              * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5750              * even through guest update xcr0, this will crash some legacy guest
5751              * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5752              */
5753             *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
5754         } else if (count == 1) {
5755             *eax = env->features[FEAT_XSAVE];
5756         } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
5757             if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5758                 const ExtSaveArea *esa = &x86_ext_save_areas[count];
5759                 *eax = esa->size;
5760                 *ebx = esa->offset;
5761             }
5762         }
5763         break;
5764     }
5765     case 0x14: {
5766         /* Intel Processor Trace Enumeration */
5767         *eax = 0;
5768         *ebx = 0;
5769         *ecx = 0;
5770         *edx = 0;
5771         if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5772             !kvm_enabled()) {
5773             break;
5774         }
5775
5776         if (count == 0) {
5777             *eax = INTEL_PT_MAX_SUBLEAF;
5778             *ebx = INTEL_PT_MINIMAL_EBX;
5779             *ecx = INTEL_PT_MINIMAL_ECX;
5780             if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
5781                 *ecx |= CPUID_14_0_ECX_LIP;
5782             }
5783         } else if (count == 1) {
5784             *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5785             *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5786         }
5787         break;
5788     }
5789     case 0x40000000:
5790         /*
5791          * CPUID code in kvm_arch_init_vcpu() ignores stuff
5792          * set here, but we restrict to TCG none the less.
5793          */
5794         if (tcg_enabled() && cpu->expose_tcg) {
5795             memcpy(signature, "TCGTCGTCGTCG", 12);
5796             *eax = 0x40000001;
5797             *ebx = signature[0];
5798             *ecx = signature[1];
5799             *edx = signature[2];
5800         } else {
5801             *eax = 0;
5802             *ebx = 0;
5803             *ecx = 0;
5804             *edx = 0;
5805         }
5806         break;
5807     case 0x40000001:
5808         *eax = 0;
5809         *ebx = 0;
5810         *ecx = 0;
5811         *edx = 0;
5812         break;
5813     case 0x80000000:
5814         *eax = env->cpuid_xlevel;
5815         *ebx = env->cpuid_vendor1;
5816         *edx = env->cpuid_vendor2;
5817         *ecx = env->cpuid_vendor3;
5818         break;
5819     case 0x80000001:
5820         *eax = env->cpuid_version;
5821         *ebx = 0;
5822         *ecx = env->features[FEAT_8000_0001_ECX];
5823         *edx = env->features[FEAT_8000_0001_EDX];
5824
5825         /* The Linux kernel checks for the CMPLegacy bit and
5826          * discards multiple thread information if it is set.
5827          * So don't set it here for Intel to make Linux guests happy.
5828          */
5829         if (cs->nr_cores * cs->nr_threads > 1) {
5830             if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5831                 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5832                 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
5833                 *ecx |= 1 << 1;    /* CmpLegacy bit */
5834             }
5835         }
5836         break;
5837     case 0x80000002:
5838     case 0x80000003:
5839     case 0x80000004:
5840         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5841         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5842         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5843         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5844         break;
5845     case 0x80000005:
5846         /* cache info (L1 cache) */
5847         if (cpu->cache_info_passthrough) {
5848             host_cpuid(index, 0, eax, ebx, ecx, edx);
5849             break;
5850         }
5851         *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5852                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
5853         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5854                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
5855         *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5856         *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
5857         break;
5858     case 0x80000006:
5859         /* cache info (L2 cache) */
5860         if (cpu->cache_info_passthrough) {
5861             host_cpuid(index, 0, eax, ebx, ecx, edx);
5862             break;
5863         }
5864         *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5865                (L2_DTLB_2M_ENTRIES << 16) |
5866                (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5867                (L2_ITLB_2M_ENTRIES);
5868         *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5869                (L2_DTLB_4K_ENTRIES << 16) |
5870                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5871                (L2_ITLB_4K_ENTRIES);
5872         encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5873                                    cpu->enable_l3_cache ?
5874                                    env->cache_info_amd.l3_cache : NULL,
5875                                    ecx, edx);
5876         break;
5877     case 0x80000007:
5878         *eax = 0;
5879         *ebx = 0;
5880         *ecx = 0;
5881         *edx = env->features[FEAT_8000_0007_EDX];
5882         break;
5883     case 0x80000008:
5884         /* virtual & phys address size in low 2 bytes. */
5885         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5886             /* 64 bit processor */
5887             *eax = cpu->phys_bits; /* configurable physical bits */
5888             if  (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5889                 *eax |= 0x00003900; /* 57 bits virtual */
5890             } else {
5891                 *eax |= 0x00003000; /* 48 bits virtual */
5892             }
5893         } else {
5894             *eax = cpu->phys_bits;
5895         }
5896         *ebx = env->features[FEAT_8000_0008_EBX];
5897         if (cs->nr_cores * cs->nr_threads > 1) {
5898             /*
5899              * Bits 15:12 is "The number of bits in the initial
5900              * Core::X86::Apic::ApicId[ApicId] value that indicate
5901              * thread ID within a package".
5902              * Bits 7:0 is "The number of threads in the package is NC+1"
5903              */
5904             *ecx = (apicid_pkg_offset(&topo_info) << 12) |
5905                    ((cs->nr_cores * cs->nr_threads) - 1);
5906         } else {
5907             *ecx = 0;
5908         }
5909         *edx = 0;
5910         break;
5911     case 0x8000000A:
5912         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5913             *eax = 0x00000001; /* SVM Revision */
5914             *ebx = 0x00000010; /* nr of ASIDs */
5915             *ecx = 0;
5916             *edx = env->features[FEAT_SVM]; /* optional features */
5917         } else {
5918             *eax = 0;
5919             *ebx = 0;
5920             *ecx = 0;
5921             *edx = 0;
5922         }
5923         break;
5924     case 0x8000001D:
5925         *eax = 0;
5926         if (cpu->cache_info_passthrough) {
5927             host_cpuid(index, count, eax, ebx, ecx, edx);
5928             break;
5929         }
5930         switch (count) {
5931         case 0: /* L1 dcache info */
5932             encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5933                                        &topo_info, eax, ebx, ecx, edx);
5934             break;
5935         case 1: /* L1 icache info */
5936             encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5937                                        &topo_info, eax, ebx, ecx, edx);
5938             break;
5939         case 2: /* L2 cache info */
5940             encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5941                                        &topo_info, eax, ebx, ecx, edx);
5942             break;
5943         case 3: /* L3 cache info */
5944             encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5945                                        &topo_info, eax, ebx, ecx, edx);
5946             break;
5947         default: /* end of info */
5948             *eax = *ebx = *ecx = *edx = 0;
5949             break;
5950         }
5951         break;
5952     case 0x8000001E:
5953         if (cpu->core_id <= 255) {
5954             encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
5955         } else {
5956             *eax = 0;
5957             *ebx = 0;
5958             *ecx = 0;
5959             *edx = 0;
5960         }
5961         break;
5962     case 0xC0000000:
5963         *eax = env->cpuid_xlevel2;
5964         *ebx = 0;
5965         *ecx = 0;
5966         *edx = 0;
5967         break;
5968     case 0xC0000001:
5969         /* Support for VIA CPU's CPUID instruction */
5970         *eax = env->cpuid_version;
5971         *ebx = 0;
5972         *ecx = 0;
5973         *edx = env->features[FEAT_C000_0001_EDX];
5974         break;
5975     case 0xC0000002:
5976     case 0xC0000003:
5977     case 0xC0000004:
5978         /* Reserved for the future, and now filled with zero */
5979         *eax = 0;
5980         *ebx = 0;
5981         *ecx = 0;
5982         *edx = 0;
5983         break;
5984     case 0x8000001F:
5985         *eax = sev_enabled() ? 0x2 : 0;
5986         *ebx = sev_get_cbit_position();
5987         *ebx |= sev_get_reduced_phys_bits() << 6;
5988         *ecx = 0;
5989         *edx = 0;
5990         break;
5991     default:
5992         /* reserved values: zero */
5993         *eax = 0;
5994         *ebx = 0;
5995         *ecx = 0;
5996         *edx = 0;
5997         break;
5998     }
5999 }
6000
6001 static void x86_cpu_reset(DeviceState *dev)
6002 {
6003     CPUState *s = CPU(dev);
6004     X86CPU *cpu = X86_CPU(s);
6005     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
6006     CPUX86State *env = &cpu->env;
6007     target_ulong cr4;
6008     uint64_t xcr0;
6009     int i;
6010
6011     xcc->parent_reset(dev);
6012
6013     memset(env, 0, offsetof(CPUX86State, end_reset_fields));
6014
6015     env->old_exception = -1;
6016
6017     /* init to reset state */
6018
6019     env->hflags2 |= HF2_GIF_MASK;
6020     env->hflags &= ~HF_GUEST_MASK;
6021
6022     cpu_x86_update_cr0(env, 0x60000010);
6023     env->a20_mask = ~0x0;
6024     env->smbase = 0x30000;
6025     env->msr_smi_count = 0;
6026
6027     env->idt.limit = 0xffff;
6028     env->gdt.limit = 0xffff;
6029     env->ldt.limit = 0xffff;
6030     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
6031     env->tr.limit = 0xffff;
6032     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
6033
6034     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
6035                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
6036                            DESC_R_MASK | DESC_A_MASK);
6037     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
6038                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6039                            DESC_A_MASK);
6040     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
6041                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6042                            DESC_A_MASK);
6043     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
6044                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6045                            DESC_A_MASK);
6046     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
6047                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6048                            DESC_A_MASK);
6049     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
6050                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
6051                            DESC_A_MASK);
6052
6053     env->eip = 0xfff0;
6054     env->regs[R_EDX] = env->cpuid_version;
6055
6056     env->eflags = 0x2;
6057
6058     /* FPU init */
6059     for (i = 0; i < 8; i++) {
6060         env->fptags[i] = 1;
6061     }
6062     cpu_set_fpuc(env, 0x37f);
6063
6064     env->mxcsr = 0x1f80;
6065     /* All units are in INIT state.  */
6066     env->xstate_bv = 0;
6067
6068     env->pat = 0x0007040600070406ULL;
6069     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
6070     if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
6071         env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
6072     }
6073
6074     memset(env->dr, 0, sizeof(env->dr));
6075     env->dr[6] = DR6_FIXED_1;
6076     env->dr[7] = DR7_FIXED_1;
6077     cpu_breakpoint_remove_all(s, BP_CPU);
6078     cpu_watchpoint_remove_all(s, BP_CPU);
6079
6080     cr4 = 0;
6081     xcr0 = XSTATE_FP_MASK;
6082
6083 #ifdef CONFIG_USER_ONLY
6084     /* Enable all the features for user-mode.  */
6085     if (env->features[FEAT_1_EDX] & CPUID_SSE) {
6086         xcr0 |= XSTATE_SSE_MASK;
6087     }
6088     for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6089         const ExtSaveArea *esa = &x86_ext_save_areas[i];
6090         if (env->features[esa->feature] & esa->bits) {
6091             xcr0 |= 1ull << i;
6092         }
6093     }
6094
6095     if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6096         cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6097     }
6098     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6099         cr4 |= CR4_FSGSBASE_MASK;
6100     }
6101 #endif
6102
6103     env->xcr0 = xcr0;
6104     cpu_x86_update_cr4(env, cr4);
6105
6106     /*
6107      * SDM 11.11.5 requires:
6108      *  - IA32_MTRR_DEF_TYPE MSR.E = 0
6109      *  - IA32_MTRR_PHYSMASKn.V = 0
6110      * All other bits are undefined.  For simplification, zero it all.
6111      */
6112     env->mtrr_deftype = 0;
6113     memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6114     memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6115
6116     env->interrupt_injected = -1;
6117     env->exception_nr = -1;
6118     env->exception_pending = 0;
6119     env->exception_injected = 0;
6120     env->exception_has_payload = false;
6121     env->exception_payload = 0;
6122     env->nmi_injected = false;
6123 #if !defined(CONFIG_USER_ONLY)
6124     /* We hard-wire the BSP to the first CPU. */
6125     apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
6126
6127     s->halted = !cpu_is_bsp(cpu);
6128
6129     if (kvm_enabled()) {
6130         kvm_arch_reset_vcpu(cpu);
6131     }
6132 #endif
6133 }
6134
6135 #ifndef CONFIG_USER_ONLY
6136 bool cpu_is_bsp(X86CPU *cpu)
6137 {
6138     return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
6139 }
6140
6141 /* TODO: remove me, when reset over QOM tree is implemented */
6142 static void x86_cpu_machine_reset_cb(void *opaque)
6143 {
6144     X86CPU *cpu = opaque;
6145     cpu_reset(CPU(cpu));
6146 }
6147 #endif
6148
6149 static void mce_init(X86CPU *cpu)
6150 {
6151     CPUX86State *cenv = &cpu->env;
6152     unsigned int bank;
6153
6154     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
6155         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
6156             (CPUID_MCE | CPUID_MCA)) {
6157         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6158                         (cpu->enable_lmce ? MCG_LMCE_P : 0);
6159         cenv->mcg_ctl = ~(uint64_t)0;
6160         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6161             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6162         }
6163     }
6164 }
6165
6166 #ifndef CONFIG_USER_ONLY
6167 APICCommonClass *apic_get_class(void)
6168 {
6169     const char *apic_type = "apic";
6170
6171     /* TODO: in-kernel irqchip for hvf */
6172     if (kvm_apic_in_kernel()) {
6173         apic_type = "kvm-apic";
6174     } else if (xen_enabled()) {
6175         apic_type = "xen-apic";
6176     }
6177
6178     return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6179 }
6180
6181 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6182 {
6183     APICCommonState *apic;
6184     ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6185
6186     cpu->apic_state = DEVICE(object_new_with_class(apic_class));
6187
6188     object_property_add_child(OBJECT(cpu), "lapic",
6189                               OBJECT(cpu->apic_state));
6190     object_unref(OBJECT(cpu->apic_state));
6191
6192     qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
6193     /* TODO: convert to link<> */
6194     apic = APIC_COMMON(cpu->apic_state);
6195     apic->cpu = cpu;
6196     apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
6197 }
6198
6199 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6200 {
6201     APICCommonState *apic;
6202     static bool apic_mmio_map_once;
6203
6204     if (cpu->apic_state == NULL) {
6205         return;
6206     }
6207     qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
6208
6209     /* Map APIC MMIO area */
6210     apic = APIC_COMMON(cpu->apic_state);
6211     if (!apic_mmio_map_once) {
6212         memory_region_add_subregion_overlap(get_system_memory(),
6213                                             apic->apicbase &
6214                                             MSR_IA32_APICBASE_BASE,
6215                                             &apic->io_memory,
6216                                             0x1000);
6217         apic_mmio_map_once = true;
6218      }
6219 }
6220
6221 static void x86_cpu_machine_done(Notifier *n, void *unused)
6222 {
6223     X86CPU *cpu = container_of(n, X86CPU, machine_done);
6224     MemoryRegion *smram =
6225         (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
6226
6227     if (smram) {
6228         cpu->smram = g_new(MemoryRegion, 1);
6229         memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
6230                                  smram, 0, 4 * GiB);
6231         memory_region_set_enabled(cpu->smram, true);
6232         memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
6233     }
6234 }
6235 #else
6236 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6237 {
6238 }
6239 #endif
6240
6241 /* Note: Only safe for use on x86(-64) hosts */
6242 static uint32_t x86_host_phys_bits(void)
6243 {
6244     uint32_t eax;
6245     uint32_t host_phys_bits;
6246
6247     host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
6248     if (eax >= 0x80000008) {
6249         host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
6250         /* Note: According to AMD doc 25481 rev 2.34 they have a field
6251          * at 23:16 that can specify a maximum physical address bits for
6252          * the guest that can override this value; but I've not seen
6253          * anything with that set.
6254          */
6255         host_phys_bits = eax & 0xff;
6256     } else {
6257         /* It's an odd 64 bit machine that doesn't have the leaf for
6258          * physical address bits; fall back to 36 that's most older
6259          * Intel.
6260          */
6261         host_phys_bits = 36;
6262     }
6263
6264     return host_phys_bits;
6265 }
6266
6267 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6268 {
6269     if (*min < value) {
6270         *min = value;
6271     }
6272 }
6273
6274 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6275 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6276 {
6277     CPUX86State *env = &cpu->env;
6278     FeatureWordInfo *fi = &feature_word_info[w];
6279     uint32_t eax = fi->cpuid.eax;
6280     uint32_t region = eax & 0xF0000000;
6281
6282     assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
6283     if (!env->features[w]) {
6284         return;
6285     }
6286
6287     switch (region) {
6288     case 0x00000000:
6289         x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6290     break;
6291     case 0x80000000:
6292         x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6293     break;
6294     case 0xC0000000:
6295         x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6296     break;
6297     }
6298
6299     if (eax == 7) {
6300         x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6301                              fi->cpuid.ecx);
6302     }
6303 }
6304
6305 /* Calculate XSAVE components based on the configured CPU feature flags */
6306 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6307 {
6308     CPUX86State *env = &cpu->env;
6309     int i;
6310     uint64_t mask;
6311
6312     if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6313         env->features[FEAT_XSAVE_COMP_LO] = 0;
6314         env->features[FEAT_XSAVE_COMP_HI] = 0;
6315         return;
6316     }
6317
6318     mask = 0;
6319     for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6320         const ExtSaveArea *esa = &x86_ext_save_areas[i];
6321         if (env->features[esa->feature] & esa->bits) {
6322             mask |= (1ULL << i);
6323         }
6324     }
6325
6326     env->features[FEAT_XSAVE_COMP_LO] = mask;
6327     env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
6328 }
6329
6330 /***** Steps involved on loading and filtering CPUID data
6331  *
6332  * When initializing and realizing a CPU object, the steps
6333  * involved in setting up CPUID data are:
6334  *
6335  * 1) Loading CPU model definition (X86CPUDefinition). This is
6336  *    implemented by x86_cpu_load_model() and should be completely
6337  *    transparent, as it is done automatically by instance_init.
6338  *    No code should need to look at X86CPUDefinition structs
6339  *    outside instance_init.
6340  *
6341  * 2) CPU expansion. This is done by realize before CPUID
6342  *    filtering, and will make sure host/accelerator data is
6343  *    loaded for CPU models that depend on host capabilities
6344  *    (e.g. "host"). Done by x86_cpu_expand_features().
6345  *
6346  * 3) CPUID filtering. This initializes extra data related to
6347  *    CPUID, and checks if the host supports all capabilities
6348  *    required by the CPU. Runnability of a CPU model is
6349  *    determined at this step. Done by x86_cpu_filter_features().
6350  *
6351  * Some operations don't require all steps to be performed.
6352  * More precisely:
6353  *
6354  * - CPU instance creation (instance_init) will run only CPU
6355  *   model loading. CPU expansion can't run at instance_init-time
6356  *   because host/accelerator data may be not available yet.
6357  * - CPU realization will perform both CPU model expansion and CPUID
6358  *   filtering, and return an error in case one of them fails.
6359  * - query-cpu-definitions needs to run all 3 steps. It needs
6360  *   to run CPUID filtering, as the 'unavailable-features'
6361  *   field is set based on the filtering results.
6362  * - The query-cpu-model-expansion QMP command only needs to run
6363  *   CPU model loading and CPU expansion. It should not filter
6364  *   any CPUID data based on host capabilities.
6365  */
6366
6367 /* Expand CPU configuration data, based on configured features
6368  * and host/accelerator capabilities when appropriate.
6369  */
6370 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
6371 {
6372     CPUX86State *env = &cpu->env;
6373     FeatureWord w;
6374     int i;
6375     GList *l;
6376
6377     for (l = plus_features; l; l = l->next) {
6378         const char *prop = l->data;
6379         if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6380             return;
6381         }
6382     }
6383
6384     for (l = minus_features; l; l = l->next) {
6385         const char *prop = l->data;
6386         if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6387             return;
6388         }
6389     }
6390
6391     /*TODO: Now cpu->max_features doesn't overwrite features
6392      * set using QOM properties, and we can convert
6393      * plus_features & minus_features to global properties
6394      * inside x86_cpu_parse_featurestr() too.
6395      */
6396     if (cpu->max_features) {
6397         for (w = 0; w < FEATURE_WORDS; w++) {
6398             /* Override only features that weren't set explicitly
6399              * by the user.
6400              */
6401             env->features[w] |=
6402                 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
6403                 ~env->user_features[w] &
6404                 ~feature_word_info[w].no_autoenable_flags;
6405         }
6406     }
6407
6408     for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6409         FeatureDep *d = &feature_dependencies[i];
6410         if (!(env->features[d->from.index] & d->from.mask)) {
6411             uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
6412
6413             /* Not an error unless the dependent feature was added explicitly.  */
6414             mark_unavailable_features(cpu, d->to.index,
6415                                       unavailable_features & env->user_features[d->to.index],
6416                                       "This feature depends on other features that were not requested");
6417
6418             env->features[d->to.index] &= ~unavailable_features;
6419         }
6420     }
6421
6422     if (!kvm_enabled() || !cpu->expose_kvm) {
6423         env->features[FEAT_KVM] = 0;
6424     }
6425
6426     x86_cpu_enable_xsave_components(cpu);
6427
6428     /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6429     x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6430     if (cpu->full_cpuid_auto_level) {
6431         x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6432         x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6433         x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6434         x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
6435         x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
6436         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6437         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6438         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
6439         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
6440         x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6441         x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6442         x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
6443
6444         /* Intel Processor Trace requires CPUID[0x14] */
6445         if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6446             if (cpu->intel_pt_auto_level) {
6447                 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6448             } else if (cpu->env.cpuid_min_level < 0x14) {
6449                 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6450                     CPUID_7_0_EBX_INTEL_PT,
6451                     "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,+intel-pt,min-level=0x14\"");
6452             }
6453         }
6454
6455         /* CPU topology with multi-dies support requires CPUID[0x1F] */
6456         if (env->nr_dies > 1) {
6457             x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6458         }
6459
6460         /* SVM requires CPUID[0x8000000A] */
6461         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6462             x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6463         }
6464
6465         /* SEV requires CPUID[0x8000001F] */
6466         if (sev_enabled()) {
6467             x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6468         }
6469     }
6470
6471     /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6472     if (env->cpuid_level_func7 == UINT32_MAX) {
6473         env->cpuid_level_func7 = env->cpuid_min_level_func7;
6474     }
6475     if (env->cpuid_level == UINT32_MAX) {
6476         env->cpuid_level = env->cpuid_min_level;
6477     }
6478     if (env->cpuid_xlevel == UINT32_MAX) {
6479         env->cpuid_xlevel = env->cpuid_min_xlevel;
6480     }
6481     if (env->cpuid_xlevel2 == UINT32_MAX) {
6482         env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
6483     }
6484 }
6485
6486 /*
6487  * Finishes initialization of CPUID data, filters CPU feature
6488  * words based on host availability of each feature.
6489  *
6490  * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6491  */
6492 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
6493 {
6494     CPUX86State *env = &cpu->env;
6495     FeatureWord w;
6496     const char *prefix = NULL;
6497
6498     if (verbose) {
6499         prefix = accel_uses_host_cpuid()
6500                  ? "host doesn't support requested feature"
6501                  : "TCG doesn't support requested feature";
6502     }
6503
6504     for (w = 0; w < FEATURE_WORDS; w++) {
6505         uint64_t host_feat =
6506             x86_cpu_get_supported_feature_word(w, false);
6507         uint64_t requested_features = env->features[w];
6508         uint64_t unavailable_features = requested_features & ~host_feat;
6509         mark_unavailable_features(cpu, w, unavailable_features, prefix);
6510     }
6511
6512     if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6513         kvm_enabled()) {
6514         KVMState *s = CPU(cpu)->kvm_state;
6515         uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6516         uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6517         uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6518         uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6519         uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6520
6521         if (!eax_0 ||
6522            ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6523            ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6524            ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6525            ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6526                                            INTEL_PT_ADDR_RANGES_NUM) ||
6527            ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
6528                 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6529            ((ecx_0 & CPUID_14_0_ECX_LIP) !=
6530                 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
6531             /*
6532              * Processor Trace capabilities aren't configurable, so if the
6533              * host can't emulate the capabilities we report on
6534              * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6535              */
6536             mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
6537         }
6538     }
6539 }
6540
6541 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6542 {
6543     CPUState *cs = CPU(dev);
6544     X86CPU *cpu = X86_CPU(dev);
6545     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6546     CPUX86State *env = &cpu->env;
6547     Error *local_err = NULL;
6548     static bool ht_warned;
6549
6550     if (xcc->host_cpuid_required) {
6551         if (!accel_uses_host_cpuid()) {
6552             g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6553             error_setg(&local_err, "CPU model '%s' requires KVM", name);
6554             goto out;
6555         }
6556     }
6557
6558     if (cpu->max_features && accel_uses_host_cpuid()) {
6559         if (enable_cpu_pm) {
6560             host_cpuid(5, 0, &cpu->mwait.eax, &cpu->mwait.ebx,
6561                        &cpu->mwait.ecx, &cpu->mwait.edx);
6562             env->features[FEAT_1_ECX] |= CPUID_EXT_MONITOR;
6563             if (kvm_enabled() && kvm_has_waitpkg()) {
6564                 env->features[FEAT_7_0_ECX] |= CPUID_7_0_ECX_WAITPKG;
6565             }
6566         }
6567         if (kvm_enabled() && cpu->ucode_rev == 0) {
6568             cpu->ucode_rev = kvm_arch_get_supported_msr_feature(kvm_state,
6569                                                                 MSR_IA32_UCODE_REV);
6570         }
6571     }
6572
6573     if (cpu->ucode_rev == 0) {
6574         /* The default is the same as KVM's.  */
6575         if (IS_AMD_CPU(env)) {
6576             cpu->ucode_rev = 0x01000065;
6577         } else {
6578             cpu->ucode_rev = 0x100000000ULL;
6579         }
6580     }
6581
6582     /* mwait extended info: needed for Core compatibility */
6583     /* We always wake on interrupt even if host does not have the capability */
6584     cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6585
6586     if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6587         error_setg(errp, "apic-id property was not initialized properly");
6588         return;
6589     }
6590
6591     x86_cpu_expand_features(cpu, &local_err);
6592     if (local_err) {
6593         goto out;
6594     }
6595
6596     x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6597
6598     if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6599         error_setg(&local_err,
6600                    accel_uses_host_cpuid() ?
6601                        "Host doesn't support requested features" :
6602                        "TCG doesn't support requested features");
6603         goto out;
6604     }
6605
6606     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6607      * CPUID[1].EDX.
6608      */
6609     if (IS_AMD_CPU(env)) {
6610         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6611         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
6612            & CPUID_EXT2_AMD_ALIASES);
6613     }
6614
6615     /* For 64bit systems think about the number of physical bits to present.
6616      * ideally this should be the same as the host; anything other than matching
6617      * the host can cause incorrect guest behaviour.
6618      * QEMU used to pick the magic value of 40 bits that corresponds to
6619      * consumer AMD devices but nothing else.
6620      */
6621     if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6622         if (accel_uses_host_cpuid()) {
6623             uint32_t host_phys_bits = x86_host_phys_bits();
6624             static bool warned;
6625
6626             /* Print a warning if the user set it to a value that's not the
6627              * host value.
6628              */
6629             if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
6630                 !warned) {
6631                 warn_report("Host physical bits (%u)"
6632                             " does not match phys-bits property (%u)",
6633                             host_phys_bits, cpu->phys_bits);
6634                 warned = true;
6635             }
6636
6637             if (cpu->host_phys_bits) {
6638                 /* The user asked for us to use the host physical bits */
6639                 cpu->phys_bits = host_phys_bits;
6640                 if (cpu->host_phys_bits_limit &&
6641                     cpu->phys_bits > cpu->host_phys_bits_limit) {
6642                     cpu->phys_bits = cpu->host_phys_bits_limit;
6643                 }
6644             }
6645
6646             if (cpu->phys_bits &&
6647                 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6648                 cpu->phys_bits < 32)) {
6649                 error_setg(errp, "phys-bits should be between 32 and %u "
6650                                  " (but is %u)",
6651                                  TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6652                 return;
6653             }
6654         } else {
6655             if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
6656                 error_setg(errp, "TCG only supports phys-bits=%u",
6657                                   TCG_PHYS_ADDR_BITS);
6658                 return;
6659             }
6660         }
6661         /* 0 means it was not explicitly set by the user (or by machine
6662          * compat_props or by the host code above). In this case, the default
6663          * is the value used by TCG (40).
6664          */
6665         if (cpu->phys_bits == 0) {
6666             cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6667         }
6668     } else {
6669         /* For 32 bit systems don't use the user set value, but keep
6670          * phys_bits consistent with what we tell the guest.
6671          */
6672         if (cpu->phys_bits != 0) {
6673             error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6674             return;
6675         }
6676
6677         if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6678             cpu->phys_bits = 36;
6679         } else {
6680             cpu->phys_bits = 32;
6681         }
6682     }
6683
6684     /* Cache information initialization */
6685     if (!cpu->legacy_cache) {
6686         if (!xcc->model || !xcc->model->cpudef->cache_info) {
6687             g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6688             error_setg(errp,
6689                        "CPU model '%s' doesn't support legacy-cache=off", name);
6690             return;
6691         }
6692         env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
6693             *xcc->model->cpudef->cache_info;
6694     } else {
6695         /* Build legacy cache information */
6696         env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6697         env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6698         env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6699         env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6700
6701         env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6702         env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6703         env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6704         env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6705
6706         env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6707         env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6708         env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6709         env->cache_info_amd.l3_cache = &legacy_l3_cache;
6710     }
6711
6712
6713     cpu_exec_realizefn(cs, &local_err);
6714     if (local_err != NULL) {
6715         error_propagate(errp, local_err);
6716         return;
6717     }
6718
6719 #ifndef CONFIG_USER_ONLY
6720     MachineState *ms = MACHINE(qdev_get_machine());
6721     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
6722
6723     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
6724         x86_cpu_apic_create(cpu, &local_err);
6725         if (local_err != NULL) {
6726             goto out;
6727         }
6728     }
6729 #endif
6730
6731     mce_init(cpu);
6732
6733 #ifndef CONFIG_USER_ONLY
6734     if (tcg_enabled()) {
6735         cpu->cpu_as_mem = g_new(MemoryRegion, 1);
6736         cpu->cpu_as_root = g_new(MemoryRegion, 1);
6737
6738         /* Outer container... */
6739         memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
6740         memory_region_set_enabled(cpu->cpu_as_root, true);
6741
6742         /* ... with two regions inside: normal system memory with low
6743          * priority, and...
6744          */
6745         memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
6746                                  get_system_memory(), 0, ~0ull);
6747         memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
6748         memory_region_set_enabled(cpu->cpu_as_mem, true);
6749
6750         cs->num_ases = 2;
6751         cpu_address_space_init(cs, 0, "cpu-memory", cs->memory);
6752         cpu_address_space_init(cs, 1, "cpu-smm", cpu->cpu_as_root);
6753
6754         /* ... SMRAM with higher priority, linked from /machine/smram.  */
6755         cpu->machine_done.notify = x86_cpu_machine_done;
6756         qemu_add_machine_init_done_notifier(&cpu->machine_done);
6757     }
6758 #endif
6759
6760     qemu_init_vcpu(cs);
6761
6762     /*
6763      * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6764      * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6765      * based on inputs (sockets,cores,threads), it is still better to give
6766      * users a warning.
6767      *
6768      * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6769      * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6770      */
6771     if (IS_AMD_CPU(env) &&
6772         !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6773         cs->nr_threads > 1 && !ht_warned) {
6774             warn_report("This family of AMD CPU doesn't support "
6775                         "hyperthreading(%d)",
6776                         cs->nr_threads);
6777             error_printf("Please configure -smp options properly"
6778                          " or try enabling topoext feature.\n");
6779             ht_warned = true;
6780     }
6781
6782     x86_cpu_apic_realize(cpu, &local_err);
6783     if (local_err != NULL) {
6784         goto out;
6785     }
6786     cpu_reset(cs);
6787
6788     xcc->parent_realize(dev, &local_err);
6789
6790 out:
6791     if (local_err != NULL) {
6792         error_propagate(errp, local_err);
6793         return;
6794     }
6795 }
6796
6797 static void x86_cpu_unrealizefn(DeviceState *dev)
6798 {
6799     X86CPU *cpu = X86_CPU(dev);
6800     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6801
6802 #ifndef CONFIG_USER_ONLY
6803     cpu_remove_sync(CPU(dev));
6804     qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6805 #endif
6806
6807     if (cpu->apic_state) {
6808         object_unparent(OBJECT(cpu->apic_state));
6809         cpu->apic_state = NULL;
6810     }
6811
6812     xcc->parent_unrealize(dev);
6813 }
6814
6815 typedef struct BitProperty {
6816     FeatureWord w;
6817     uint64_t mask;
6818 } BitProperty;
6819
6820 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6821                                  void *opaque, Error **errp)
6822 {
6823     X86CPU *cpu = X86_CPU(obj);
6824     BitProperty *fp = opaque;
6825     uint64_t f = cpu->env.features[fp->w];
6826     bool value = (f & fp->mask) == fp->mask;
6827     visit_type_bool(v, name, &value, errp);
6828 }
6829
6830 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6831                                  void *opaque, Error **errp)
6832 {
6833     DeviceState *dev = DEVICE(obj);
6834     X86CPU *cpu = X86_CPU(obj);
6835     BitProperty *fp = opaque;
6836     bool value;
6837
6838     if (dev->realized) {
6839         qdev_prop_set_after_realize(dev, name, errp);
6840         return;
6841     }
6842
6843     if (!visit_type_bool(v, name, &value, errp)) {
6844         return;
6845     }
6846
6847     if (value) {
6848         cpu->env.features[fp->w] |= fp->mask;
6849     } else {
6850         cpu->env.features[fp->w] &= ~fp->mask;
6851     }
6852     cpu->env.user_features[fp->w] |= fp->mask;
6853 }
6854
6855 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
6856                                      void *opaque)
6857 {
6858     BitProperty *prop = opaque;
6859     g_free(prop);
6860 }
6861
6862 /* Register a boolean property to get/set a single bit in a uint32_t field.
6863  *
6864  * The same property name can be registered multiple times to make it affect
6865  * multiple bits in the same FeatureWord. In that case, the getter will return
6866  * true only if all bits are set.
6867  */
6868 static void x86_cpu_register_bit_prop(X86CPU *cpu,
6869                                       const char *prop_name,
6870                                       FeatureWord w,
6871                                       int bitnr)
6872 {
6873     BitProperty *fp;
6874     ObjectProperty *op;
6875     uint64_t mask = (1ULL << bitnr);
6876
6877     op = object_property_find(OBJECT(cpu), prop_name);
6878     if (op) {
6879         fp = op->opaque;
6880         assert(fp->w == w);
6881         fp->mask |= mask;
6882     } else {
6883         fp = g_new0(BitProperty, 1);
6884         fp->w = w;
6885         fp->mask = mask;
6886         object_property_add(OBJECT(cpu), prop_name, "bool",
6887                             x86_cpu_get_bit_prop,
6888                             x86_cpu_set_bit_prop,
6889                             x86_cpu_release_bit_prop, fp);
6890     }
6891 }
6892
6893 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
6894                                                FeatureWord w,
6895                                                int bitnr)
6896 {
6897     FeatureWordInfo *fi = &feature_word_info[w];
6898     const char *name = fi->feat_names[bitnr];
6899
6900     if (!name) {
6901         return;
6902     }
6903
6904     /* Property names should use "-" instead of "_".
6905      * Old names containing underscores are registered as aliases
6906      * using object_property_add_alias()
6907      */
6908     assert(!strchr(name, '_'));
6909     /* aliases don't use "|" delimiters anymore, they are registered
6910      * manually using object_property_add_alias() */
6911     assert(!strchr(name, '|'));
6912     x86_cpu_register_bit_prop(cpu, name, w, bitnr);
6913 }
6914
6915 #if !defined(CONFIG_USER_ONLY)
6916 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6917 {
6918     X86CPU *cpu = X86_CPU(cs);
6919     CPUX86State *env = &cpu->env;
6920     GuestPanicInformation *panic_info = NULL;
6921
6922     if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
6923         panic_info = g_malloc0(sizeof(GuestPanicInformation));
6924
6925         panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
6926
6927         assert(HV_CRASH_PARAMS >= 5);
6928         panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6929         panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6930         panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6931         panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6932         panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
6933     }
6934
6935     return panic_info;
6936 }
6937 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6938                                        const char *name, void *opaque,
6939                                        Error **errp)
6940 {
6941     CPUState *cs = CPU(obj);
6942     GuestPanicInformation *panic_info;
6943
6944     if (!cs->crash_occurred) {
6945         error_setg(errp, "No crash occured");
6946         return;
6947     }
6948
6949     panic_info = x86_cpu_get_crash_info(cs);
6950     if (panic_info == NULL) {
6951         error_setg(errp, "No crash information");
6952         return;
6953     }
6954
6955     visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6956                                      errp);
6957     qapi_free_GuestPanicInformation(panic_info);
6958 }
6959 #endif /* !CONFIG_USER_ONLY */
6960
6961 static void x86_cpu_initfn(Object *obj)
6962 {
6963     X86CPU *cpu = X86_CPU(obj);
6964     X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
6965     CPUX86State *env = &cpu->env;
6966     FeatureWord w;
6967
6968     env->nr_dies = 1;
6969     cpu_set_cpustate_pointers(cpu);
6970
6971     object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6972                         x86_cpu_get_feature_words,
6973                         NULL, NULL, (void *)env->features);
6974     object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6975                         x86_cpu_get_feature_words,
6976                         NULL, NULL, (void *)cpu->filtered_features);
6977
6978     for (w = 0; w < FEATURE_WORDS; w++) {
6979         int bitnr;
6980
6981         for (bitnr = 0; bitnr < 64; bitnr++) {
6982             x86_cpu_register_feature_bit_props(cpu, w, bitnr);
6983         }
6984     }
6985
6986     object_property_add_alias(obj, "sse3", obj, "pni");
6987     object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6988     object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6989     object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6990     object_property_add_alias(obj, "xd", obj, "nx");
6991     object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6992     object_property_add_alias(obj, "i64", obj, "lm");
6993
6994     object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6995     object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6996     object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6997     object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6998     object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6999     object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
7000     object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
7001     object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
7002     object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
7003     object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
7004     object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
7005     object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
7006     object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
7007     object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
7008     object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
7009     object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
7010     object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
7011     object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
7012     object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
7013     object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
7014     object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
7015     object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
7016     object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
7017
7018     if (xcc->model) {
7019         x86_cpu_load_model(cpu, xcc->model);
7020     }
7021 }
7022
7023 static int64_t x86_cpu_get_arch_id(CPUState *cs)
7024 {
7025     X86CPU *cpu = X86_CPU(cs);
7026
7027     return cpu->apic_id;
7028 }
7029
7030 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
7031 {
7032     X86CPU *cpu = X86_CPU(cs);
7033
7034     return cpu->env.cr[0] & CR0_PG_MASK;
7035 }
7036
7037 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
7038 {
7039     X86CPU *cpu = X86_CPU(cs);
7040
7041     cpu->env.eip = value;
7042 }
7043
7044 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
7045 {
7046     X86CPU *cpu = X86_CPU(cs);
7047
7048     cpu->env.eip = tb->pc - tb->cs_base;
7049 }
7050
7051 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
7052 {
7053     X86CPU *cpu = X86_CPU(cs);
7054     CPUX86State *env = &cpu->env;
7055
7056 #if !defined(CONFIG_USER_ONLY)
7057     if (interrupt_request & CPU_INTERRUPT_POLL) {
7058         return CPU_INTERRUPT_POLL;
7059     }
7060 #endif
7061     if (interrupt_request & CPU_INTERRUPT_SIPI) {
7062         return CPU_INTERRUPT_SIPI;
7063     }
7064
7065     if (env->hflags2 & HF2_GIF_MASK) {
7066         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
7067             !(env->hflags & HF_SMM_MASK)) {
7068             return CPU_INTERRUPT_SMI;
7069         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
7070                    !(env->hflags2 & HF2_NMI_MASK)) {
7071             return CPU_INTERRUPT_NMI;
7072         } else if (interrupt_request & CPU_INTERRUPT_MCE) {
7073             return CPU_INTERRUPT_MCE;
7074         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
7075                    (((env->hflags2 & HF2_VINTR_MASK) &&
7076                      (env->hflags2 & HF2_HIF_MASK)) ||
7077                     (!(env->hflags2 & HF2_VINTR_MASK) &&
7078                      (env->eflags & IF_MASK &&
7079                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
7080             return CPU_INTERRUPT_HARD;
7081 #if !defined(CONFIG_USER_ONLY)
7082         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
7083                    (env->eflags & IF_MASK) &&
7084                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
7085             return CPU_INTERRUPT_VIRQ;
7086 #endif
7087         }
7088     }
7089
7090     return 0;
7091 }
7092
7093 static bool x86_cpu_has_work(CPUState *cs)
7094 {
7095     return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
7096 }
7097
7098 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
7099 {
7100     X86CPU *cpu = X86_CPU(cs);
7101     CPUX86State *env = &cpu->env;
7102
7103     info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
7104                   : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
7105                   : bfd_mach_i386_i8086);
7106     info->print_insn = print_insn_i386;
7107
7108     info->cap_arch = CS_ARCH_X86;
7109     info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
7110                       : env->hflags & HF_CS32_MASK ? CS_MODE_32
7111                       : CS_MODE_16);
7112     info->cap_insn_unit = 1;
7113     info->cap_insn_split = 8;
7114 }
7115
7116 void x86_update_hflags(CPUX86State *env)
7117 {
7118    uint32_t hflags;
7119 #define HFLAG_COPY_MASK \
7120     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
7121        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
7122        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
7123        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
7124
7125     hflags = env->hflags & HFLAG_COPY_MASK;
7126     hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
7127     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
7128     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
7129                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
7130     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
7131
7132     if (env->cr[4] & CR4_OSFXSR_MASK) {
7133         hflags |= HF_OSFXSR_MASK;
7134     }
7135
7136     if (env->efer & MSR_EFER_LMA) {
7137         hflags |= HF_LMA_MASK;
7138     }
7139
7140     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
7141         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
7142     } else {
7143         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
7144                     (DESC_B_SHIFT - HF_CS32_SHIFT);
7145         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
7146                     (DESC_B_SHIFT - HF_SS32_SHIFT);
7147         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
7148             !(hflags & HF_CS32_MASK)) {
7149             hflags |= HF_ADDSEG_MASK;
7150         } else {
7151             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
7152                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
7153         }
7154     }
7155     env->hflags = hflags;
7156 }
7157
7158 static Property x86_cpu_properties[] = {
7159 #ifdef CONFIG_USER_ONLY
7160     /* apic_id = 0 by default for *-user, see commit 9886e834 */
7161     DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
7162     DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
7163     DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
7164     DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
7165     DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
7166 #else
7167     DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
7168     DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
7169     DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
7170     DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
7171     DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
7172 #endif
7173     DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
7174     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
7175
7176     DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7177                        HYPERV_SPINLOCK_NEVER_NOTIFY),
7178     DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7179                       HYPERV_FEAT_RELAXED, 0),
7180     DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7181                       HYPERV_FEAT_VAPIC, 0),
7182     DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7183                       HYPERV_FEAT_TIME, 0),
7184     DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7185                       HYPERV_FEAT_CRASH, 0),
7186     DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7187                       HYPERV_FEAT_RESET, 0),
7188     DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7189                       HYPERV_FEAT_VPINDEX, 0),
7190     DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7191                       HYPERV_FEAT_RUNTIME, 0),
7192     DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7193                       HYPERV_FEAT_SYNIC, 0),
7194     DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7195                       HYPERV_FEAT_STIMER, 0),
7196     DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7197                       HYPERV_FEAT_FREQUENCIES, 0),
7198     DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7199                       HYPERV_FEAT_REENLIGHTENMENT, 0),
7200     DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7201                       HYPERV_FEAT_TLBFLUSH, 0),
7202     DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7203                       HYPERV_FEAT_EVMCS, 0),
7204     DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7205                       HYPERV_FEAT_IPI, 0),
7206     DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7207                       HYPERV_FEAT_STIMER_DIRECT, 0),
7208     DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7209                             hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
7210     DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
7211
7212     DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
7213     DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
7214     DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
7215     DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
7216     DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
7217     DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
7218     DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
7219     DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
7220     DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7221                        UINT32_MAX),
7222     DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7223     DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7224     DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7225     DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7226     DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7227     DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
7228     DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
7229     DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
7230     DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
7231     DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
7232     DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
7233     DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
7234     DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7235                      false),
7236     DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
7237     DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
7238     DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7239                      true),
7240     /*
7241      * lecacy_cache defaults to true unless the CPU model provides its
7242      * own cache information (see x86_cpu_load_def()).
7243      */
7244     DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
7245
7246     /*
7247      * From "Requirements for Implementing the Microsoft
7248      * Hypervisor Interface":
7249      * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7250      *
7251      * "Starting with Windows Server 2012 and Windows 8, if
7252      * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7253      * the hypervisor imposes no specific limit to the number of VPs.
7254      * In this case, Windows Server 2012 guest VMs may use more than
7255      * 64 VPs, up to the maximum supported number of processors applicable
7256      * to the specific Windows version being used."
7257      */
7258     DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
7259     DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7260                      false),
7261     DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7262                      true),
7263     DEFINE_PROP_END_OF_LIST()
7264 };
7265
7266 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7267 {
7268     X86CPUClass *xcc = X86_CPU_CLASS(oc);
7269     CPUClass *cc = CPU_CLASS(oc);
7270     DeviceClass *dc = DEVICE_CLASS(oc);
7271
7272     device_class_set_parent_realize(dc, x86_cpu_realizefn,
7273                                     &xcc->parent_realize);
7274     device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7275                                       &xcc->parent_unrealize);
7276     device_class_set_props(dc, x86_cpu_properties);
7277
7278     device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
7279     cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
7280
7281     cc->class_by_name = x86_cpu_class_by_name;
7282     cc->parse_features = x86_cpu_parse_featurestr;
7283     cc->has_work = x86_cpu_has_work;
7284 #ifdef CONFIG_TCG
7285     cc->do_interrupt = x86_cpu_do_interrupt;
7286     cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
7287 #endif
7288     cc->dump_state = x86_cpu_dump_state;
7289     cc->set_pc = x86_cpu_set_pc;
7290     cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
7291     cc->gdb_read_register = x86_cpu_gdb_read_register;
7292     cc->gdb_write_register = x86_cpu_gdb_write_register;
7293     cc->get_arch_id = x86_cpu_get_arch_id;
7294     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7295 #ifndef CONFIG_USER_ONLY
7296     cc->asidx_from_attrs = x86_asidx_from_attrs;
7297     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
7298     cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
7299     cc->get_crash_info = x86_cpu_get_crash_info;
7300     cc->write_elf64_note = x86_cpu_write_elf64_note;
7301     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7302     cc->write_elf32_note = x86_cpu_write_elf32_note;
7303     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
7304     cc->vmsd = &vmstate_x86_cpu;
7305 #endif
7306     cc->gdb_arch_name = x86_gdb_arch_name;
7307 #ifdef TARGET_X86_64
7308     cc->gdb_core_xml_file = "i386-64bit.xml";
7309     cc->gdb_num_core_regs = 66;
7310 #else
7311     cc->gdb_core_xml_file = "i386-32bit.xml";
7312     cc->gdb_num_core_regs = 50;
7313 #endif
7314 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
7315     cc->debug_excp_handler = breakpoint_handler;
7316 #endif
7317     cc->cpu_exec_enter = x86_cpu_exec_enter;
7318     cc->cpu_exec_exit = x86_cpu_exec_exit;
7319 #ifdef CONFIG_TCG
7320     cc->tcg_initialize = tcg_x86_init;
7321     cc->tlb_fill = x86_cpu_tlb_fill;
7322 #endif
7323     cc->disas_set_info = x86_disas_set_info;
7324
7325     dc->user_creatable = true;
7326
7327     object_class_property_add(oc, "family", "int",
7328                               x86_cpuid_version_get_family,
7329                               x86_cpuid_version_set_family, NULL, NULL);
7330     object_class_property_add(oc, "model", "int",
7331                               x86_cpuid_version_get_model,
7332                               x86_cpuid_version_set_model, NULL, NULL);
7333     object_class_property_add(oc, "stepping", "int",
7334                               x86_cpuid_version_get_stepping,
7335                               x86_cpuid_version_set_stepping, NULL, NULL);
7336     object_class_property_add_str(oc, "vendor",
7337                                   x86_cpuid_get_vendor,
7338                                   x86_cpuid_set_vendor);
7339     object_class_property_add_str(oc, "model-id",
7340                                   x86_cpuid_get_model_id,
7341                                   x86_cpuid_set_model_id);
7342     object_class_property_add(oc, "tsc-frequency", "int",
7343                               x86_cpuid_get_tsc_freq,
7344                               x86_cpuid_set_tsc_freq, NULL, NULL);
7345     /*
7346      * The "unavailable-features" property has the same semantics as
7347      * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
7348      * QMP command: they list the features that would have prevented the
7349      * CPU from running if the "enforce" flag was set.
7350      */
7351     object_class_property_add(oc, "unavailable-features", "strList",
7352                               x86_cpu_get_unavailable_features,
7353                               NULL, NULL, NULL);
7354
7355 #if !defined(CONFIG_USER_ONLY)
7356     object_class_property_add(oc, "crash-information", "GuestPanicInformation",
7357                               x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
7358 #endif
7359
7360 }
7361
7362 static const TypeInfo x86_cpu_type_info = {
7363     .name = TYPE_X86_CPU,
7364     .parent = TYPE_CPU,
7365     .instance_size = sizeof(X86CPU),
7366     .instance_init = x86_cpu_initfn,
7367     .abstract = true,
7368     .class_size = sizeof(X86CPUClass),
7369     .class_init = x86_cpu_common_class_init,
7370 };
7371
7372
7373 /* "base" CPU model, used by query-cpu-model-expansion */
7374 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7375 {
7376     X86CPUClass *xcc = X86_CPU_CLASS(oc);
7377
7378     xcc->static_model = true;
7379     xcc->migration_safe = true;
7380     xcc->model_description = "base CPU model type with no features enabled";
7381     xcc->ordering = 8;
7382 }
7383
7384 static const TypeInfo x86_base_cpu_type_info = {
7385         .name = X86_CPU_TYPE_NAME("base"),
7386         .parent = TYPE_X86_CPU,
7387         .class_init = x86_cpu_base_class_init,
7388 };
7389
7390 static void x86_cpu_register_types(void)
7391 {
7392     int i;
7393
7394     type_register_static(&x86_cpu_type_info);
7395     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
7396         x86_register_cpudef_types(&builtin_x86_defs[i]);
7397     }
7398     type_register_static(&max_x86_cpu_type_info);
7399     type_register_static(&x86_base_cpu_type_info);
7400 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
7401     type_register_static(&host_x86_cpu_type_info);
7402 #endif
7403 }
7404
7405 type_init(x86_cpu_register_types)