target/i386/cpu.c

   1 /*
   2  *  i386 CPUID helper functions
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu/units.h"
  22 #include "qemu/cutils.h"
  23 #include "qemu/bitops.h"
  24 #include "qemu/qemu-print.h"
  25 #include "cpu.h"
  26 #include "tcg/helper-tcg.h"
  27 #include "exec/exec-all.h"
  28 #include "sysemu/kvm.h"
  29 #include "sysemu/reset.h"
  30 #include "sysemu/hvf.h"
  31 #include "hw/core/accel-cpu.h"
  32 #include "sysemu/xen.h"
  33 #include "sysemu/whpx.h"
  34 #include "kvm/kvm_i386.h"
  35 #include "sev_i386.h"
  36 #include "qemu/module.h"
  37 #include "qapi/qapi-visit-machine.h"
  38 #include "qapi/qapi-visit-run-state.h"
  39 #include "qapi/qmp/qdict.h"
  40 #include "qapi/qmp/qerror.h"
  41 #include "qom/qom-qobject.h"
  42 #include "qapi/qapi-commands-machine-target.h"
  43 #include "standard-headers/asm-x86/kvm_para.h"
  44 #include "hw/qdev-properties.h"
  45 #include "hw/i386/topology.h"
  46 #ifndef CONFIG_USER_ONLY
  47 #include "exec/address-spaces.h"
  48 #include "hw/i386/apic_internal.h"
  49 #include "hw/boards.h"
  50 #endif
  51
  52 #include "disas/capstone.h"
  53
  54 /* Helpers for building CPUID[2] descriptors: */
  55
  56 struct CPUID2CacheDescriptorInfo {
  57     enum CacheType type;
  58     int level;
  59     int size;
  60     int line_size;
  61     int associativity;
  62 };
  63
  64 /*
  65  * Known CPUID 2 cache descriptors.
  66  * From Intel SDM Volume 2A, CPUID instruction
  67  */
  68 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
  69     [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size =   8 * KiB,
  70                .associativity = 4,  .line_size = 32, },
  71     [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  16 * KiB,
  72                .associativity = 4,  .line_size = 32, },
  73     [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
  74                .associativity = 4,  .line_size = 64, },
  75     [0x0A] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
  76                .associativity = 2,  .line_size = 32, },
  77     [0x0C] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
  78                .associativity = 4,  .line_size = 32, },
  79     [0x0D] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
  80                .associativity = 4,  .line_size = 64, },
  81     [0x0E] = { .level = 1, .type = DATA_CACHE,        .size =  24 * KiB,
  82                .associativity = 6,  .line_size = 64, },
  83     [0x1D] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
  84                .associativity = 2,  .line_size = 64, },
  85     [0x21] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
  86                .associativity = 8,  .line_size = 64, },
  87     /* lines per sector is not supported cpuid2_cache_descriptor(),
  88     * so descriptors 0x22, 0x23 are not included
  89     */
  90     [0x24] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
  91                .associativity = 16, .line_size = 64, },
  92     /* lines per sector is not supported cpuid2_cache_descriptor(),
  93     * so descriptors 0x25, 0x20 are not included
  94     */
  95     [0x2C] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
  96                .associativity = 8,  .line_size = 64, },
  97     [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
  98                .associativity = 8,  .line_size = 64, },
  99     [0x41] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
 100                .associativity = 4,  .line_size = 32, },
 101     [0x42] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
 102                .associativity = 4,  .line_size = 32, },
 103     [0x43] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 104                .associativity = 4,  .line_size = 32, },
 105     [0x44] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 106                .associativity = 4,  .line_size = 32, },
 107     [0x45] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 108                .associativity = 4,  .line_size = 32, },
 109     [0x46] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
 110                .associativity = 4,  .line_size = 64, },
 111     [0x47] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
 112                .associativity = 8,  .line_size = 64, },
 113     [0x48] = { .level = 2, .type = UNIFIED_CACHE,     .size =   3 * MiB,
 114                .associativity = 12, .line_size = 64, },
 115     /* Descriptor 0x49 depends on CPU family/model, so it is not included */
 116     [0x4A] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
 117                .associativity = 12, .line_size = 64, },
 118     [0x4B] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
 119                .associativity = 16, .line_size = 64, },
 120     [0x4C] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
 121                .associativity = 12, .line_size = 64, },
 122     [0x4D] = { .level = 3, .type = UNIFIED_CACHE,     .size =  16 * MiB,
 123                .associativity = 16, .line_size = 64, },
 124     [0x4E] = { .level = 2, .type = UNIFIED_CACHE,     .size =   6 * MiB,
 125                .associativity = 24, .line_size = 64, },
 126     [0x60] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
 127                .associativity = 8,  .line_size = 64, },
 128     [0x66] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
 129                .associativity = 4,  .line_size = 64, },
 130     [0x67] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
 131                .associativity = 4,  .line_size = 64, },
 132     [0x68] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
 133                .associativity = 4,  .line_size = 64, },
 134     [0x78] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 135                .associativity = 4,  .line_size = 64, },
 136     /* lines per sector is not supported cpuid2_cache_descriptor(),
 137     * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
 138     */
 139     [0x7D] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 140                .associativity = 8,  .line_size = 64, },
 141     [0x7F] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 142                .associativity = 2,  .line_size = 64, },
 143     [0x80] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 144                .associativity = 8,  .line_size = 64, },
 145     [0x82] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
 146                .associativity = 8,  .line_size = 32, },
 147     [0x83] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 148                .associativity = 8,  .line_size = 32, },
 149     [0x84] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 150                .associativity = 8,  .line_size = 32, },
 151     [0x85] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 152                .associativity = 8,  .line_size = 32, },
 153     [0x86] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 154                .associativity = 4,  .line_size = 64, },
 155     [0x87] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 156                .associativity = 8,  .line_size = 64, },
 157     [0xD0] = { .level = 3, .type = UNIFIED_CACHE,     .size = 512 * KiB,
 158                .associativity = 4,  .line_size = 64, },
 159     [0xD1] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 160                .associativity = 4,  .line_size = 64, },
 161     [0xD2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 162                .associativity = 4,  .line_size = 64, },
 163     [0xD6] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
 164                .associativity = 8,  .line_size = 64, },
 165     [0xD7] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 166                .associativity = 8,  .line_size = 64, },
 167     [0xD8] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
 168                .associativity = 8,  .line_size = 64, },
 169     [0xDC] = { .level = 3, .type = UNIFIED_CACHE,     .size = 1.5 * MiB,
 170                .associativity = 12, .line_size = 64, },
 171     [0xDD] = { .level = 3, .type = UNIFIED_CACHE,     .size =   3 * MiB,
 172                .associativity = 12, .line_size = 64, },
 173     [0xDE] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
 174                .associativity = 12, .line_size = 64, },
 175     [0xE2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
 176                .associativity = 16, .line_size = 64, },
 177     [0xE3] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
 178                .associativity = 16, .line_size = 64, },
 179     [0xE4] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
 180                .associativity = 16, .line_size = 64, },
 181     [0xEA] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
 182                .associativity = 24, .line_size = 64, },
 183     [0xEB] = { .level = 3, .type = UNIFIED_CACHE,     .size =  18 * MiB,
 184                .associativity = 24, .line_size = 64, },
 185     [0xEC] = { .level = 3, .type = UNIFIED_CACHE,     .size =  24 * MiB,
 186                .associativity = 24, .line_size = 64, },
 187 };
 188
 189 /*
 190  * "CPUID leaf 2 does not report cache descriptor information,
 191  * use CPUID leaf 4 to query cache parameters"
 192  */
 193 #define CACHE_DESCRIPTOR_UNAVAILABLE 0xFF
 194
 195 /*
 196  * Return a CPUID 2 cache descriptor for a given cache.
 197  * If no known descriptor is found, return CACHE_DESCRIPTOR_UNAVAILABLE
 198  */
 199 static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
 200 {
 201     int i;
 202
 203     assert(cache->size > 0);
 204     assert(cache->level > 0);
 205     assert(cache->line_size > 0);
 206     assert(cache->associativity > 0);
 207     for (i = 0; i < ARRAY_SIZE(cpuid2_cache_descriptors); i++) {
 208         struct CPUID2CacheDescriptorInfo *d = &cpuid2_cache_descriptors[i];
 209         if (d->level == cache->level && d->type == cache->type &&
 210             d->size == cache->size && d->line_size == cache->line_size &&
 211             d->associativity == cache->associativity) {
 212                 return i;
 213             }
 214     }
 215
 216     return CACHE_DESCRIPTOR_UNAVAILABLE;
 217 }
 218
 219 /* CPUID Leaf 4 constants: */
 220
 221 /* EAX: */
 222 #define CACHE_TYPE_D    1
 223 #define CACHE_TYPE_I    2
 224 #define CACHE_TYPE_UNIFIED   3
 225
 226 #define CACHE_LEVEL(l)        (l << 5)
 227
 228 #define CACHE_SELF_INIT_LEVEL (1 << 8)
 229
 230 /* EDX: */
 231 #define CACHE_NO_INVD_SHARING   (1 << 0)
 232 #define CACHE_INCLUSIVE       (1 << 1)
 233 #define CACHE_COMPLEX_IDX     (1 << 2)
 234
 235 /* Encode CacheType for CPUID[4].EAX */
 236 #define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
 237                        ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
 238                        ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
 239                        0 /* Invalid value */)
 240
 241
 242 /* Encode cache info for CPUID[4] */
 243 static void encode_cache_cpuid4(CPUCacheInfo *cache,
 244                                 int num_apic_ids, int num_cores,
 245                                 uint32_t *eax, uint32_t *ebx,
 246                                 uint32_t *ecx, uint32_t *edx)
 247 {
 248     assert(cache->size == cache->line_size * cache->associativity *
 249                           cache->partitions * cache->sets);
 250
 251     assert(num_apic_ids > 0);
 252     *eax = CACHE_TYPE(cache->type) |
 253            CACHE_LEVEL(cache->level) |
 254            (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0) |
 255            ((num_cores - 1) << 26) |
 256            ((num_apic_ids - 1) << 14);
 257
 258     assert(cache->line_size > 0);
 259     assert(cache->partitions > 0);
 260     assert(cache->associativity > 0);
 261     /* We don't implement fully-associative caches */
 262     assert(cache->associativity < cache->sets);
 263     *ebx = (cache->line_size - 1) |
 264            ((cache->partitions - 1) << 12) |
 265            ((cache->associativity - 1) << 22);
 266
 267     assert(cache->sets > 0);
 268     *ecx = cache->sets - 1;
 269
 270     *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
 271            (cache->inclusive ? CACHE_INCLUSIVE : 0) |
 272            (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
 273 }
 274
 275 /* Encode cache info for CPUID[0x80000005].ECX or CPUID[0x80000005].EDX */
 276 static uint32_t encode_cache_cpuid80000005(CPUCacheInfo *cache)
 277 {
 278     assert(cache->size % 1024 == 0);
 279     assert(cache->lines_per_tag > 0);
 280     assert(cache->associativity > 0);
 281     assert(cache->line_size > 0);
 282     return ((cache->size / 1024) << 24) | (cache->associativity << 16) |
 283            (cache->lines_per_tag << 8) | (cache->line_size);
 284 }
 285
 286 #define ASSOC_FULL 0xFF
 287
 288 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
 289 #define AMD_ENC_ASSOC(a) (a <=   1 ? a   : \
 290                           a ==   2 ? 0x2 : \
 291                           a ==   4 ? 0x4 : \
 292                           a ==   8 ? 0x6 : \
 293                           a ==  16 ? 0x8 : \
 294                           a ==  32 ? 0xA : \
 295                           a ==  48 ? 0xB : \
 296                           a ==  64 ? 0xC : \
 297                           a ==  96 ? 0xD : \
 298                           a == 128 ? 0xE : \
 299                           a == ASSOC_FULL ? 0xF : \
 300                           0 /* invalid value */)
 301
 302 /*
 303  * Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
 304  * @l3 can be NULL.
 305  */
 306 static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
 307                                        CPUCacheInfo *l3,
 308                                        uint32_t *ecx, uint32_t *edx)
 309 {
 310     assert(l2->size % 1024 == 0);
 311     assert(l2->associativity > 0);
 312     assert(l2->lines_per_tag > 0);
 313     assert(l2->line_size > 0);
 314     *ecx = ((l2->size / 1024) << 16) |
 315            (AMD_ENC_ASSOC(l2->associativity) << 12) |
 316            (l2->lines_per_tag << 8) | (l2->line_size);
 317
 318     if (l3) {
 319         assert(l3->size % (512 * 1024) == 0);
 320         assert(l3->associativity > 0);
 321         assert(l3->lines_per_tag > 0);
 322         assert(l3->line_size > 0);
 323         *edx = ((l3->size / (512 * 1024)) << 18) |
 324                (AMD_ENC_ASSOC(l3->associativity) << 12) |
 325                (l3->lines_per_tag << 8) | (l3->line_size);
 326     } else {
 327         *edx = 0;
 328     }
 329 }
 330
 331 /* Encode cache info for CPUID[8000001D] */
 332 static void encode_cache_cpuid8000001d(CPUCacheInfo *cache,
 333                                        X86CPUTopoInfo *topo_info,
 334                                        uint32_t *eax, uint32_t *ebx,
 335                                        uint32_t *ecx, uint32_t *edx)
 336 {
 337     uint32_t l3_threads;
 338     assert(cache->size == cache->line_size * cache->associativity *
 339                           cache->partitions * cache->sets);
 340
 341     *eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
 342                (cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
 343
 344     /* L3 is shared among multiple cores */
 345     if (cache->level == 3) {
 346         l3_threads = topo_info->cores_per_die * topo_info->threads_per_core;
 347         *eax |= (l3_threads - 1) << 14;
 348     } else {
 349         *eax |= ((topo_info->threads_per_core - 1) << 14);
 350     }
 351
 352     assert(cache->line_size > 0);
 353     assert(cache->partitions > 0);
 354     assert(cache->associativity > 0);
 355     /* We don't implement fully-associative caches */
 356     assert(cache->associativity < cache->sets);
 357     *ebx = (cache->line_size - 1) |
 358            ((cache->partitions - 1) << 12) |
 359            ((cache->associativity - 1) << 22);
 360
 361     assert(cache->sets > 0);
 362     *ecx = cache->sets - 1;
 363
 364     *edx = (cache->no_invd_sharing ? CACHE_NO_INVD_SHARING : 0) |
 365            (cache->inclusive ? CACHE_INCLUSIVE : 0) |
 366            (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0);
 367 }
 368
 369 /* Encode cache info for CPUID[8000001E] */
 370 static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_info,
 371                                       uint32_t *eax, uint32_t *ebx,
 372                                       uint32_t *ecx, uint32_t *edx)
 373 {
 374     X86CPUTopoIDs topo_ids;
 375
 376     x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids);
 377
 378     *eax = cpu->apic_id;
 379
 380     /*
 381      * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId)
 382      * Read-only. Reset: 0000_XXXXh.
 383      * See Core::X86::Cpuid::ExtApicId.
 384      * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0];
 385      * Bits Description
 386      * 31:16 Reserved.
 387      * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh.
 388      *      The number of threads per core is ThreadsPerCore+1.
 389      *  7:0 CoreId: core ID. Read-only. Reset: XXh.
 390      *
 391      *  NOTE: CoreId is already part of apic_id. Just use it. We can
 392      *  use all the 8 bits to represent the core_id here.
 393      */
 394     *ebx = ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id & 0xFF);
 395
 396     /*
 397      * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId)
 398      * Read-only. Reset: 0000_0XXXh.
 399      * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0];
 400      * Bits Description
 401      * 31:11 Reserved.
 402      * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb.
 403      *      ValidValues:
 404      *      Value Description
 405      *      000b  1 node per processor.
 406      *      001b  2 nodes per processor.
 407      *      010b Reserved.
 408      *      011b 4 nodes per processor.
 409      *      111b-100b Reserved.
 410      *  7:0 NodeId: Node ID. Read-only. Reset: XXh.
 411      *
 412      * NOTE: Hardware reserves 3 bits for number of nodes per processor.
 413      * But users can create more nodes than the actual hardware can
 414      * support. To genaralize we can use all the upper 8 bits for nodes.
 415      * NodeId is combination of node and socket_id which is already decoded
 416      * in apic_id. Just use it by shifting.
 417      */
 418     *ecx = ((topo_info->dies_per_pkg - 1) << 8) |
 419            ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF);
 420
 421     *edx = 0;
 422 }
 423
 424 /*
 425  * Definitions of the hardcoded cache entries we expose:
 426  * These are legacy cache values. If there is a need to change any
 427  * of these values please use builtin_x86_defs
 428  */
 429
 430 /* L1 data cache: */
 431 static CPUCacheInfo legacy_l1d_cache = {
 432     .type = DATA_CACHE,
 433     .level = 1,
 434     .size = 32 * KiB,
 435     .self_init = 1,
 436     .line_size = 64,
 437     .associativity = 8,
 438     .sets = 64,
 439     .partitions = 1,
 440     .no_invd_sharing = true,
 441 };
 442
 443 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 444 static CPUCacheInfo legacy_l1d_cache_amd = {
 445     .type = DATA_CACHE,
 446     .level = 1,
 447     .size = 64 * KiB,
 448     .self_init = 1,
 449     .line_size = 64,
 450     .associativity = 2,
 451     .sets = 512,
 452     .partitions = 1,
 453     .lines_per_tag = 1,
 454     .no_invd_sharing = true,
 455 };
 456
 457 /* L1 instruction cache: */
 458 static CPUCacheInfo legacy_l1i_cache = {
 459     .type = INSTRUCTION_CACHE,
 460     .level = 1,
 461     .size = 32 * KiB,
 462     .self_init = 1,
 463     .line_size = 64,
 464     .associativity = 8,
 465     .sets = 64,
 466     .partitions = 1,
 467     .no_invd_sharing = true,
 468 };
 469
 470 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 471 static CPUCacheInfo legacy_l1i_cache_amd = {
 472     .type = INSTRUCTION_CACHE,
 473     .level = 1,
 474     .size = 64 * KiB,
 475     .self_init = 1,
 476     .line_size = 64,
 477     .associativity = 2,
 478     .sets = 512,
 479     .partitions = 1,
 480     .lines_per_tag = 1,
 481     .no_invd_sharing = true,
 482 };
 483
 484 /* Level 2 unified cache: */
 485 static CPUCacheInfo legacy_l2_cache = {
 486     .type = UNIFIED_CACHE,
 487     .level = 2,
 488     .size = 4 * MiB,
 489     .self_init = 1,
 490     .line_size = 64,
 491     .associativity = 16,
 492     .sets = 4096,
 493     .partitions = 1,
 494     .no_invd_sharing = true,
 495 };
 496
 497 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
 498 static CPUCacheInfo legacy_l2_cache_cpuid2 = {
 499     .type = UNIFIED_CACHE,
 500     .level = 2,
 501     .size = 2 * MiB,
 502     .line_size = 64,
 503     .associativity = 8,
 504 };
 505
 506
 507 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
 508 static CPUCacheInfo legacy_l2_cache_amd = {
 509     .type = UNIFIED_CACHE,
 510     .level = 2,
 511     .size = 512 * KiB,
 512     .line_size = 64,
 513     .lines_per_tag = 1,
 514     .associativity = 16,
 515     .sets = 512,
 516     .partitions = 1,
 517 };
 518
 519 /* Level 3 unified cache: */
 520 static CPUCacheInfo legacy_l3_cache = {
 521     .type = UNIFIED_CACHE,
 522     .level = 3,
 523     .size = 16 * MiB,
 524     .line_size = 64,
 525     .associativity = 16,
 526     .sets = 16384,
 527     .partitions = 1,
 528     .lines_per_tag = 1,
 529     .self_init = true,
 530     .inclusive = true,
 531     .complex_indexing = true,
 532 };
 533
 534 /* TLB definitions: */
 535
 536 #define L1_DTLB_2M_ASSOC       1
 537 #define L1_DTLB_2M_ENTRIES   255
 538 #define L1_DTLB_4K_ASSOC       1
 539 #define L1_DTLB_4K_ENTRIES   255
 540
 541 #define L1_ITLB_2M_ASSOC       1
 542 #define L1_ITLB_2M_ENTRIES   255
 543 #define L1_ITLB_4K_ASSOC       1
 544 #define L1_ITLB_4K_ENTRIES   255
 545
 546 #define L2_DTLB_2M_ASSOC       0 /* disabled */
 547 #define L2_DTLB_2M_ENTRIES     0 /* disabled */
 548 #define L2_DTLB_4K_ASSOC       4
 549 #define L2_DTLB_4K_ENTRIES   512
 550
 551 #define L2_ITLB_2M_ASSOC       0 /* disabled */
 552 #define L2_ITLB_2M_ENTRIES     0 /* disabled */
 553 #define L2_ITLB_4K_ASSOC       4
 554 #define L2_ITLB_4K_ENTRIES   512
 555
 556 /* CPUID Leaf 0x14 constants: */
 557 #define INTEL_PT_MAX_SUBLEAF     0x1
 558 /*
 559  * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MATCH
 560  *          MSR can be accessed;
 561  * bit[01]: Support Configurable PSB and Cycle-Accurate Mode;
 562  * bit[02]: Support IP Filtering, TraceStop filtering, and preservation
 563  *          of Intel PT MSRs across warm reset;
 564  * bit[03]: Support MTC timing packet and suppression of COFI-based packets;
 565  */
 566 #define INTEL_PT_MINIMAL_EBX     0xf
 567 /*
 568  * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1 and
 569  *          IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be
 570  *          accessed;
 571  * bit[01]: ToPA tables can hold any number of output entries, up to the
 572  *          maximum allowed by the MaskOrTableOffset field of
 573  *          IA32_RTIT_OUTPUT_MASK_PTRS;
 574  * bit[02]: Support Single-Range Output scheme;
 575  */
 576 #define INTEL_PT_MINIMAL_ECX     0x7
 577 /* generated packets which contain IP payloads have LIP values */
 578 #define INTEL_PT_IP_LIP          (1 << 31)
 579 #define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ranges */
 580 #define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3
 581 #define INTEL_PT_MTC_BITMAP      (0x0249 << 16) /* Support ART(0,3,6,9) */
 582 #define INTEL_PT_CYCLE_BITMAP    0x1fff         /* Support 0,2^(0~11) */
 583 #define INTEL_PT_PSB_BITMAP      (0x003f << 16) /* Support 2K,4K,8K,16K,32K,64K */
 584
 585 void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
 586                               uint32_t vendor2, uint32_t vendor3)
 587 {
 588     int i;
 589     for (i = 0; i < 4; i++) {
 590         dst[i] = vendor1 >> (8 * i);
 591         dst[i + 4] = vendor2 >> (8 * i);
 592         dst[i + 8] = vendor3 >> (8 * i);
 593     }
 594     dst[CPUID_VENDOR_SZ] = '\0';
 595 }
 596
 597 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
 598 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
 599           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
 600 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
 601           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 602           CPUID_PSE36 | CPUID_FXSR)
 603 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
 604 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
 605           CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
 606           CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
 607           CPUID_PAE | CPUID_SEP | CPUID_APIC)
 608
 609 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
 610           CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
 611           CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
 612           CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
 613           CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
 614           /* partly implemented:
 615           CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
 616           /* missing:
 617           CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
 618 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
 619           CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
 620           CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
 621           CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */   \
 622           CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR | \
 623           CPUID_EXT_RDRAND)
 624           /* missing:
 625           CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
 626           CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
 627           CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
 628           CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
 629           CPUID_EXT_F16C */
 630
 631 #ifdef TARGET_X86_64
 632 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
 633 #else
 634 #define TCG_EXT2_X86_64_FEATURES 0
 635 #endif
 636
 637 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
 638           CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
 639           CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
 640           TCG_EXT2_X86_64_FEATURES)
 641 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
 642           CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
 643 #define TCG_EXT4_FEATURES 0
 644 #define TCG_SVM_FEATURES CPUID_SVM_NPT
 645 #define TCG_KVM_FEATURES 0
 646 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
 647           CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
 648           CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT |            \
 649           CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
 650           CPUID_7_0_EBX_ERMS)
 651           /* missing:
 652           CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
 653           CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
 654           CPUID_7_0_EBX_RDSEED */
 655 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | \
 656           /* CPUID_7_0_ECX_OSPKE is dynamic */ \
 657           CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_PKS)
 658 #define TCG_7_0_EDX_FEATURES 0
 659 #define TCG_7_1_EAX_FEATURES 0
 660 #define TCG_APM_FEATURES 0
 661 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
 662 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
 663           /* missing:
 664           CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
 665 #define TCG_14_0_ECX_FEATURES 0
 666
 667 typedef enum FeatureWordType {
 668    CPUID_FEATURE_WORD,
 669    MSR_FEATURE_WORD,
 670 } FeatureWordType;
 671
 672 typedef struct FeatureWordInfo {
 673     FeatureWordType type;
 674     /* feature flags names are taken from "Intel Processor Identification and
 675      * the CPUID Instruction" and AMD's "CPUID Specification".
 676      * In cases of disagreement between feature naming conventions,
 677      * aliases may be added.
 678      */
 679     const char *feat_names[64];
 680     union {
 681         /* If type==CPUID_FEATURE_WORD */
 682         struct {
 683             uint32_t eax;   /* Input EAX for CPUID */
 684             bool needs_ecx; /* CPUID instruction uses ECX as input */
 685             uint32_t ecx;   /* Input ECX value for CPUID */
 686             int reg;        /* output register (R_* constant) */
 687         } cpuid;
 688         /* If type==MSR_FEATURE_WORD */
 689         struct {
 690             uint32_t index;
 691         } msr;
 692     };
 693     uint64_t tcg_features; /* Feature flags supported by TCG */
 694     uint64_t unmigratable_flags; /* Feature flags known to be unmigratable */
 695     uint64_t migratable_flags; /* Feature flags known to be migratable */
 696     /* Features that shouldn't be auto-enabled by "-cpu host" */
 697     uint64_t no_autoenable_flags;
 698 } FeatureWordInfo;
 699
 700 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
 701     [FEAT_1_EDX] = {
 702         .type = CPUID_FEATURE_WORD,
 703         .feat_names = {
 704             "fpu", "vme", "de", "pse",
 705             "tsc", "msr", "pae", "mce",
 706             "cx8", "apic", NULL, "sep",
 707             "mtrr", "pge", "mca", "cmov",
 708             "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
 709             NULL, "ds" /* Intel dts */, "acpi", "mmx",
 710             "fxsr", "sse", "sse2", "ss",
 711             "ht" /* Intel htt */, "tm", "ia64", "pbe",
 712         },
 713         .cpuid = {.eax = 1, .reg = R_EDX, },
 714         .tcg_features = TCG_FEATURES,
 715     },
 716     [FEAT_1_ECX] = {
 717         .type = CPUID_FEATURE_WORD,
 718         .feat_names = {
 719             "pni" /* Intel,AMD sse3 */, "pclmulqdq", "dtes64", "monitor",
 720             "ds-cpl", "vmx", "smx", "est",
 721             "tm2", "ssse3", "cid", NULL,
 722             "fma", "cx16", "xtpr", "pdcm",
 723             NULL, "pcid", "dca", "sse4.1",
 724             "sse4.2", "x2apic", "movbe", "popcnt",
 725             "tsc-deadline", "aes", "xsave", NULL /* osxsave */,
 726             "avx", "f16c", "rdrand", "hypervisor",
 727         },
 728         .cpuid = { .eax = 1, .reg = R_ECX, },
 729         .tcg_features = TCG_EXT_FEATURES,
 730     },
 731     /* Feature names that are already defined on feature_name[] but
 732      * are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
 733      * names on feat_names below. They are copied automatically
 734      * to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
 735      */
 736     [FEAT_8000_0001_EDX] = {
 737         .type = CPUID_FEATURE_WORD,
 738         .feat_names = {
 739             NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
 740             NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
 741             NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
 742             NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
 743             NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
 744             "nx", NULL, "mmxext", NULL /* mmx */,
 745             NULL /* fxsr */, "fxsr-opt", "pdpe1gb", "rdtscp",
 746             NULL, "lm", "3dnowext", "3dnow",
 747         },
 748         .cpuid = { .eax = 0x80000001, .reg = R_EDX, },
 749         .tcg_features = TCG_EXT2_FEATURES,
 750     },
 751     [FEAT_8000_0001_ECX] = {
 752         .type = CPUID_FEATURE_WORD,
 753         .feat_names = {
 754             "lahf-lm", "cmp-legacy", "svm", "extapic",
 755             "cr8legacy", "abm", "sse4a", "misalignsse",
 756             "3dnowprefetch", "osvw", "ibs", "xop",
 757             "skinit", "wdt", NULL, "lwp",
 758             "fma4", "tce", NULL, "nodeid-msr",
 759             NULL, "tbm", "topoext", "perfctr-core",
 760             "perfctr-nb", NULL, NULL, NULL,
 761             NULL, NULL, NULL, NULL,
 762         },
 763         .cpuid = { .eax = 0x80000001, .reg = R_ECX, },
 764         .tcg_features = TCG_EXT3_FEATURES,
 765         /*
 766          * TOPOEXT is always allowed but can't be enabled blindly by
 767          * "-cpu host", as it requires consistent cache topology info
 768          * to be provided so it doesn't confuse guests.
 769          */
 770         .no_autoenable_flags = CPUID_EXT3_TOPOEXT,
 771     },
 772     [FEAT_C000_0001_EDX] = {
 773         .type = CPUID_FEATURE_WORD,
 774         .feat_names = {
 775             NULL, NULL, "xstore", "xstore-en",
 776             NULL, NULL, "xcrypt", "xcrypt-en",
 777             "ace2", "ace2-en", "phe", "phe-en",
 778             "pmm", "pmm-en", NULL, NULL,
 779             NULL, NULL, NULL, NULL,
 780             NULL, NULL, NULL, NULL,
 781             NULL, NULL, NULL, NULL,
 782             NULL, NULL, NULL, NULL,
 783         },
 784         .cpuid = { .eax = 0xC0000001, .reg = R_EDX, },
 785         .tcg_features = TCG_EXT4_FEATURES,
 786     },
 787     [FEAT_KVM] = {
 788         .type = CPUID_FEATURE_WORD,
 789         .feat_names = {
 790             "kvmclock", "kvm-nopiodelay", "kvm-mmu", "kvmclock",
 791             "kvm-asyncpf", "kvm-steal-time", "kvm-pv-eoi", "kvm-pv-unhalt",
 792             NULL, "kvm-pv-tlb-flush", NULL, "kvm-pv-ipi",
 793             "kvm-poll-control", "kvm-pv-sched-yield", "kvm-asyncpf-int", "kvm-msi-ext-dest-id",
 794             NULL, NULL, NULL, NULL,
 795             NULL, NULL, NULL, NULL,
 796             "kvmclock-stable-bit", NULL, NULL, NULL,
 797             NULL, NULL, NULL, NULL,
 798         },
 799         .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EAX, },
 800         .tcg_features = TCG_KVM_FEATURES,
 801     },
 802     [FEAT_KVM_HINTS] = {
 803         .type = CPUID_FEATURE_WORD,
 804         .feat_names = {
 805             "kvm-hint-dedicated", NULL, NULL, NULL,
 806             NULL, NULL, NULL, NULL,
 807             NULL, NULL, NULL, NULL,
 808             NULL, NULL, NULL, NULL,
 809             NULL, NULL, NULL, NULL,
 810             NULL, NULL, NULL, NULL,
 811             NULL, NULL, NULL, NULL,
 812             NULL, NULL, NULL, NULL,
 813         },
 814         .cpuid = { .eax = KVM_CPUID_FEATURES, .reg = R_EDX, },
 815         .tcg_features = TCG_KVM_FEATURES,
 816         /*
 817          * KVM hints aren't auto-enabled by -cpu host, they need to be
 818          * explicitly enabled in the command-line.
 819          */
 820         .no_autoenable_flags = ~0U,
 821     },
 822     /*
 823      * .feat_names are commented out for Hyper-V enlightenments because we
 824      * don't want to have two different ways for enabling them on QEMU command
 825      * line. Some features (e.g. "hyperv_time", "hyperv_vapic", ...) require
 826      * enabling several feature bits simultaneously, exposing these bits
 827      * individually may just confuse guests.
 828      */
 829     [FEAT_HYPERV_EAX] = {
 830         .type = CPUID_FEATURE_WORD,
 831         .feat_names = {
 832             NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
 833             NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
 834             NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
 835             NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
 836             NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
 837             NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
 838             NULL /* hv_msr_debug_access */, NULL /* hv_msr_reenlightenment_access */,
 839             NULL, NULL,
 840             NULL, NULL, NULL, NULL,
 841             NULL, NULL, NULL, NULL,
 842             NULL, NULL, NULL, NULL,
 843             NULL, NULL, NULL, NULL,
 844         },
 845         .cpuid = { .eax = 0x40000003, .reg = R_EAX, },
 846     },
 847     [FEAT_HYPERV_EBX] = {
 848         .type = CPUID_FEATURE_WORD,
 849         .feat_names = {
 850             NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
 851             NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
 852             NULL /* hv_post_messages */, NULL /* hv_signal_events */,
 853             NULL /* hv_create_port */, NULL /* hv_connect_port */,
 854             NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
 855             NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
 856             NULL, NULL,
 857             NULL, NULL, NULL, NULL,
 858             NULL, NULL, NULL, NULL,
 859             NULL, NULL, NULL, NULL,
 860             NULL, NULL, NULL, NULL,
 861         },
 862         .cpuid = { .eax = 0x40000003, .reg = R_EBX, },
 863     },
 864     [FEAT_HYPERV_EDX] = {
 865         .type = CPUID_FEATURE_WORD,
 866         .feat_names = {
 867             NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
 868             NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
 869             NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
 870             NULL, NULL,
 871             NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
 872             NULL, NULL, NULL, NULL,
 873             NULL, NULL, NULL, NULL,
 874             NULL, NULL, NULL, NULL,
 875             NULL, NULL, NULL, NULL,
 876             NULL, NULL, NULL, NULL,
 877         },
 878         .cpuid = { .eax = 0x40000003, .reg = R_EDX, },
 879     },
 880     [FEAT_HV_RECOMM_EAX] = {
 881         .type = CPUID_FEATURE_WORD,
 882         .feat_names = {
 883             NULL /* hv_recommend_pv_as_switch */,
 884             NULL /* hv_recommend_pv_tlbflush_local */,
 885             NULL /* hv_recommend_pv_tlbflush_remote */,
 886             NULL /* hv_recommend_msr_apic_access */,
 887             NULL /* hv_recommend_msr_reset */,
 888             NULL /* hv_recommend_relaxed_timing */,
 889             NULL /* hv_recommend_dma_remapping */,
 890             NULL /* hv_recommend_int_remapping */,
 891             NULL /* hv_recommend_x2apic_msrs */,
 892             NULL /* hv_recommend_autoeoi_deprecation */,
 893             NULL /* hv_recommend_pv_ipi */,
 894             NULL /* hv_recommend_ex_hypercalls */,
 895             NULL /* hv_hypervisor_is_nested */,
 896             NULL /* hv_recommend_int_mbec */,
 897             NULL /* hv_recommend_evmcs */,
 898             NULL,
 899             NULL, NULL, NULL, NULL,
 900             NULL, NULL, NULL, NULL,
 901             NULL, NULL, NULL, NULL,
 902             NULL, NULL, NULL, NULL,
 903         },
 904         .cpuid = { .eax = 0x40000004, .reg = R_EAX, },
 905     },
 906     [FEAT_HV_NESTED_EAX] = {
 907         .type = CPUID_FEATURE_WORD,
 908         .cpuid = { .eax = 0x4000000A, .reg = R_EAX, },
 909     },
 910     [FEAT_SVM] = {
 911         .type = CPUID_FEATURE_WORD,
 912         .feat_names = {
 913             "npt", "lbrv", "svm-lock", "nrip-save",
 914             "tsc-scale", "vmcb-clean",  "flushbyasid", "decodeassists",
 915             NULL, NULL, "pause-filter", NULL,
 916             "pfthreshold", "avic", NULL, "v-vmsave-vmload",
 917             "vgif", NULL, NULL, NULL,
 918             NULL, NULL, NULL, NULL,
 919             NULL, NULL, NULL, NULL,
 920             "svme-addr-chk", NULL, NULL, NULL,
 921         },
 922         .cpuid = { .eax = 0x8000000A, .reg = R_EDX, },
 923         .tcg_features = TCG_SVM_FEATURES,
 924     },
 925     [FEAT_7_0_EBX] = {
 926         .type = CPUID_FEATURE_WORD,
 927         .feat_names = {
 928             "fsgsbase", "tsc-adjust", NULL, "bmi1",
 929             "hle", "avx2", NULL, "smep",
 930             "bmi2", "erms", "invpcid", "rtm",
 931             NULL, NULL, "mpx", NULL,
 932             "avx512f", "avx512dq", "rdseed", "adx",
 933             "smap", "avx512ifma", "pcommit", "clflushopt",
 934             "clwb", "intel-pt", "avx512pf", "avx512er",
 935             "avx512cd", "sha-ni", "avx512bw", "avx512vl",
 936         },
 937         .cpuid = {
 938             .eax = 7,
 939             .needs_ecx = true, .ecx = 0,
 940             .reg = R_EBX,
 941         },
 942         .tcg_features = TCG_7_0_EBX_FEATURES,
 943     },
 944     [FEAT_7_0_ECX] = {
 945         .type = CPUID_FEATURE_WORD,
 946         .feat_names = {
 947             NULL, "avx512vbmi", "umip", "pku",
 948             NULL /* ospke */, "waitpkg", "avx512vbmi2", NULL,
 949             "gfni", "vaes", "vpclmulqdq", "avx512vnni",
 950             "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
 951             "la57", NULL, NULL, NULL,
 952             NULL, NULL, "rdpid", NULL,
 953             "bus-lock-detect", "cldemote", NULL, "movdiri",
 954             "movdir64b", NULL, NULL, "pks",
 955         },
 956         .cpuid = {
 957             .eax = 7,
 958             .needs_ecx = true, .ecx = 0,
 959             .reg = R_ECX,
 960         },
 961         .tcg_features = TCG_7_0_ECX_FEATURES,
 962     },
 963     [FEAT_7_0_EDX] = {
 964         .type = CPUID_FEATURE_WORD,
 965         .feat_names = {
 966             NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
 967             "fsrm", NULL, NULL, NULL,
 968             "avx512-vp2intersect", NULL, "md-clear", NULL,
 969             NULL, NULL, "serialize", NULL,
 970             "tsx-ldtrk", NULL, NULL /* pconfig */, NULL,
 971             NULL, NULL, NULL, "avx512-fp16",
 972             NULL, NULL, "spec-ctrl", "stibp",
 973             NULL, "arch-capabilities", "core-capability", "ssbd",
 974         },
 975         .cpuid = {
 976             .eax = 7,
 977             .needs_ecx = true, .ecx = 0,
 978             .reg = R_EDX,
 979         },
 980         .tcg_features = TCG_7_0_EDX_FEATURES,
 981     },
 982     [FEAT_7_1_EAX] = {
 983         .type = CPUID_FEATURE_WORD,
 984         .feat_names = {
 985             NULL, NULL, NULL, NULL,
 986             NULL, "avx512-bf16", NULL, NULL,
 987             NULL, NULL, NULL, NULL,
 988             NULL, NULL, NULL, NULL,
 989             NULL, NULL, NULL, NULL,
 990             NULL, NULL, NULL, NULL,
 991             NULL, NULL, NULL, NULL,
 992             NULL, NULL, NULL, NULL,
 993         },
 994         .cpuid = {
 995             .eax = 7,
 996             .needs_ecx = true, .ecx = 1,
 997             .reg = R_EAX,
 998         },
 999         .tcg_features = TCG_7_1_EAX_FEATURES,
1000     },
1001     [FEAT_8000_0007_EDX] = {
1002         .type = CPUID_FEATURE_WORD,
1003         .feat_names = {
1004             NULL, NULL, NULL, NULL,
1005             NULL, NULL, NULL, NULL,
1006             "invtsc", NULL, NULL, NULL,
1007             NULL, NULL, NULL, NULL,
1008             NULL, NULL, NULL, NULL,
1009             NULL, NULL, NULL, NULL,
1010             NULL, NULL, NULL, NULL,
1011             NULL, NULL, NULL, NULL,
1012         },
1013         .cpuid = { .eax = 0x80000007, .reg = R_EDX, },
1014         .tcg_features = TCG_APM_FEATURES,
1015         .unmigratable_flags = CPUID_APM_INVTSC,
1016     },
1017     [FEAT_8000_0008_EBX] = {
1018         .type = CPUID_FEATURE_WORD,
1019         .feat_names = {
1020             "clzero", NULL, "xsaveerptr", NULL,
1021             NULL, NULL, NULL, NULL,
1022             NULL, "wbnoinvd", NULL, NULL,
1023             "ibpb", NULL, "ibrs", "amd-stibp",
1024             NULL, NULL, NULL, NULL,
1025             NULL, NULL, NULL, NULL,
1026             "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
1027             NULL, NULL, NULL, NULL,
1028         },
1029         .cpuid = { .eax = 0x80000008, .reg = R_EBX, },
1030         .tcg_features = 0,
1031         .unmigratable_flags = 0,
1032     },
1033     [FEAT_XSAVE] = {
1034         .type = CPUID_FEATURE_WORD,
1035         .feat_names = {
1036             "xsaveopt", "xsavec", "xgetbv1", "xsaves",
1037             NULL, NULL, NULL, NULL,
1038             NULL, NULL, NULL, NULL,
1039             NULL, NULL, NULL, NULL,
1040             NULL, NULL, NULL, NULL,
1041             NULL, NULL, NULL, NULL,
1042             NULL, NULL, NULL, NULL,
1043             NULL, NULL, NULL, NULL,
1044         },
1045         .cpuid = {
1046             .eax = 0xd,
1047             .needs_ecx = true, .ecx = 1,
1048             .reg = R_EAX,
1049         },
1050         .tcg_features = TCG_XSAVE_FEATURES,
1051     },
1052     [FEAT_6_EAX] = {
1053         .type = CPUID_FEATURE_WORD,
1054         .feat_names = {
1055             NULL, NULL, "arat", NULL,
1056             NULL, NULL, NULL, NULL,
1057             NULL, NULL, NULL, NULL,
1058             NULL, NULL, NULL, NULL,
1059             NULL, NULL, NULL, NULL,
1060             NULL, NULL, NULL, NULL,
1061             NULL, NULL, NULL, NULL,
1062             NULL, NULL, NULL, NULL,
1063         },
1064         .cpuid = { .eax = 6, .reg = R_EAX, },
1065         .tcg_features = TCG_6_EAX_FEATURES,
1066     },
1067     [FEAT_XSAVE_COMP_LO] = {
1068         .type = CPUID_FEATURE_WORD,
1069         .cpuid = {
1070             .eax = 0xD,
1071             .needs_ecx = true, .ecx = 0,
1072             .reg = R_EAX,
1073         },
1074         .tcg_features = ~0U,
1075         .migratable_flags = XSTATE_FP_MASK | XSTATE_SSE_MASK |
1076             XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK |
1077             XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_MASK |
1078             XSTATE_PKRU_MASK,
1079     },
1080     [FEAT_XSAVE_COMP_HI] = {
1081         .type = CPUID_FEATURE_WORD,
1082         .cpuid = {
1083             .eax = 0xD,
1084             .needs_ecx = true, .ecx = 0,
1085             .reg = R_EDX,
1086         },
1087         .tcg_features = ~0U,
1088     },
1089     /*Below are MSR exposed features*/
1090     [FEAT_ARCH_CAPABILITIES] = {
1091         .type = MSR_FEATURE_WORD,
1092         .feat_names = {
1093             "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
1094             "ssb-no", "mds-no", "pschange-mc-no", "tsx-ctrl",
1095             "taa-no", NULL, NULL, NULL,
1096             NULL, NULL, NULL, NULL,
1097             NULL, NULL, NULL, NULL,
1098             NULL, NULL, NULL, NULL,
1099             NULL, NULL, NULL, NULL,
1100             NULL, NULL, NULL, NULL,
1101         },
1102         .msr = {
1103             .index = MSR_IA32_ARCH_CAPABILITIES,
1104         },
1105     },
1106     [FEAT_CORE_CAPABILITY] = {
1107         .type = MSR_FEATURE_WORD,
1108         .feat_names = {
1109             NULL, NULL, NULL, NULL,
1110             NULL, "split-lock-detect", NULL, NULL,
1111             NULL, NULL, NULL, NULL,
1112             NULL, NULL, NULL, NULL,
1113             NULL, NULL, NULL, NULL,
1114             NULL, NULL, NULL, NULL,
1115             NULL, NULL, NULL, NULL,
1116             NULL, NULL, NULL, NULL,
1117         },
1118         .msr = {
1119             .index = MSR_IA32_CORE_CAPABILITY,
1120         },
1121     },
1122     [FEAT_PERF_CAPABILITIES] = {
1123         .type = MSR_FEATURE_WORD,
1124         .feat_names = {
1125             NULL, NULL, NULL, NULL,
1126             NULL, NULL, NULL, NULL,
1127             NULL, NULL, NULL, NULL,
1128             NULL, "full-width-write", NULL, NULL,
1129             NULL, NULL, NULL, NULL,
1130             NULL, NULL, NULL, NULL,
1131             NULL, NULL, NULL, NULL,
1132             NULL, NULL, NULL, NULL,
1133         },
1134         .msr = {
1135             .index = MSR_IA32_PERF_CAPABILITIES,
1136         },
1137     },
1138
1139     [FEAT_VMX_PROCBASED_CTLS] = {
1140         .type = MSR_FEATURE_WORD,
1141         .feat_names = {
1142             NULL, NULL, "vmx-vintr-pending", "vmx-tsc-offset",
1143             NULL, NULL, NULL, "vmx-hlt-exit",
1144             NULL, "vmx-invlpg-exit", "vmx-mwait-exit", "vmx-rdpmc-exit",
1145             "vmx-rdtsc-exit", NULL, NULL, "vmx-cr3-load-noexit",
1146             "vmx-cr3-store-noexit", NULL, NULL, "vmx-cr8-load-exit",
1147             "vmx-cr8-store-exit", "vmx-flexpriority", "vmx-vnmi-pending", "vmx-movdr-exit",
1148             "vmx-io-exit", "vmx-io-bitmap", NULL, "vmx-mtf",
1149             "vmx-msr-bitmap", "vmx-monitor-exit", "vmx-pause-exit", "vmx-secondary-ctls",
1150         },
1151         .msr = {
1152             .index = MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
1153         }
1154     },
1155
1156     [FEAT_VMX_SECONDARY_CTLS] = {
1157         .type = MSR_FEATURE_WORD,
1158         .feat_names = {
1159             "vmx-apicv-xapic", "vmx-ept", "vmx-desc-exit", "vmx-rdtscp-exit",
1160             "vmx-apicv-x2apic", "vmx-vpid", "vmx-wbinvd-exit", "vmx-unrestricted-guest",
1161             "vmx-apicv-register", "vmx-apicv-vid", "vmx-ple", "vmx-rdrand-exit",
1162             "vmx-invpcid-exit", "vmx-vmfunc", "vmx-shadow-vmcs", "vmx-encls-exit",
1163             "vmx-rdseed-exit", "vmx-pml", NULL, NULL,
1164             "vmx-xsaves", NULL, NULL, NULL,
1165             NULL, NULL, NULL, NULL,
1166             NULL, NULL, NULL, NULL,
1167         },
1168         .msr = {
1169             .index = MSR_IA32_VMX_PROCBASED_CTLS2,
1170         }
1171     },
1172
1173     [FEAT_VMX_PINBASED_CTLS] = {
1174         .type = MSR_FEATURE_WORD,
1175         .feat_names = {
1176             "vmx-intr-exit", NULL, NULL, "vmx-nmi-exit",
1177             NULL, "vmx-vnmi", "vmx-preemption-timer", "vmx-posted-intr",
1178             NULL, NULL, NULL, NULL,
1179             NULL, NULL, NULL, NULL,
1180             NULL, NULL, NULL, NULL,
1181             NULL, NULL, NULL, NULL,
1182             NULL, NULL, NULL, NULL,
1183             NULL, NULL, NULL, NULL,
1184         },
1185         .msr = {
1186             .index = MSR_IA32_VMX_TRUE_PINBASED_CTLS,
1187         }
1188     },
1189
1190     [FEAT_VMX_EXIT_CTLS] = {
1191         .type = MSR_FEATURE_WORD,
1192         /*
1193          * VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE is copied from
1194          * the LM CPUID bit.
1195          */
1196         .feat_names = {
1197             NULL, NULL, "vmx-exit-nosave-debugctl", NULL,
1198             NULL, NULL, NULL, NULL,
1199             NULL, NULL /* vmx-exit-host-addr-space-size */, NULL, NULL,
1200             "vmx-exit-load-perf-global-ctrl", NULL, NULL, "vmx-exit-ack-intr",
1201             NULL, NULL, "vmx-exit-save-pat", "vmx-exit-load-pat",
1202             "vmx-exit-save-efer", "vmx-exit-load-efer",
1203                 "vmx-exit-save-preemption-timer", "vmx-exit-clear-bndcfgs",
1204             NULL, "vmx-exit-clear-rtit-ctl", NULL, NULL,
1205             NULL, "vmx-exit-load-pkrs", NULL, NULL,
1206         },
1207         .msr = {
1208             .index = MSR_IA32_VMX_TRUE_EXIT_CTLS,
1209         }
1210     },
1211
1212     [FEAT_VMX_ENTRY_CTLS] = {
1213         .type = MSR_FEATURE_WORD,
1214         .feat_names = {
1215             NULL, NULL, "vmx-entry-noload-debugctl", NULL,
1216             NULL, NULL, NULL, NULL,
1217             NULL, "vmx-entry-ia32e-mode", NULL, NULL,
1218             NULL, "vmx-entry-load-perf-global-ctrl", "vmx-entry-load-pat", "vmx-entry-load-efer",
1219             "vmx-entry-load-bndcfgs", NULL, "vmx-entry-load-rtit-ctl", NULL,
1220             NULL, NULL, "vmx-entry-load-pkrs", NULL,
1221             NULL, NULL, NULL, NULL,
1222             NULL, NULL, NULL, NULL,
1223         },
1224         .msr = {
1225             .index = MSR_IA32_VMX_TRUE_ENTRY_CTLS,
1226         }
1227     },
1228
1229     [FEAT_VMX_MISC] = {
1230         .type = MSR_FEATURE_WORD,
1231         .feat_names = {
1232             NULL, NULL, NULL, NULL,
1233             NULL, "vmx-store-lma", "vmx-activity-hlt", "vmx-activity-shutdown",
1234             "vmx-activity-wait-sipi", NULL, NULL, NULL,
1235             NULL, NULL, NULL, NULL,
1236             NULL, NULL, NULL, NULL,
1237             NULL, NULL, NULL, NULL,
1238             NULL, NULL, NULL, NULL,
1239             NULL, "vmx-vmwrite-vmexit-fields", "vmx-zero-len-inject", NULL,
1240         },
1241         .msr = {
1242             .index = MSR_IA32_VMX_MISC,
1243         }
1244     },
1245
1246     [FEAT_VMX_EPT_VPID_CAPS] = {
1247         .type = MSR_FEATURE_WORD,
1248         .feat_names = {
1249             "vmx-ept-execonly", NULL, NULL, NULL,
1250             NULL, NULL, "vmx-page-walk-4", "vmx-page-walk-5",
1251             NULL, NULL, NULL, NULL,
1252             NULL, NULL, NULL, NULL,
1253             "vmx-ept-2mb", "vmx-ept-1gb", NULL, NULL,
1254             "vmx-invept", "vmx-eptad", "vmx-ept-advanced-exitinfo", NULL,
1255             NULL, "vmx-invept-single-context", "vmx-invept-all-context", NULL,
1256             NULL, NULL, NULL, NULL,
1257             "vmx-invvpid", NULL, NULL, NULL,
1258             NULL, NULL, NULL, NULL,
1259             "vmx-invvpid-single-addr", "vmx-invept-single-context",
1260                 "vmx-invvpid-all-context", "vmx-invept-single-context-noglobals",
1261             NULL, NULL, NULL, NULL,
1262             NULL, NULL, NULL, NULL,
1263             NULL, NULL, NULL, NULL,
1264             NULL, NULL, NULL, NULL,
1265             NULL, NULL, NULL, NULL,
1266         },
1267         .msr = {
1268             .index = MSR_IA32_VMX_EPT_VPID_CAP,
1269         }
1270     },
1271
1272     [FEAT_VMX_BASIC] = {
1273         .type = MSR_FEATURE_WORD,
1274         .feat_names = {
1275             [54] = "vmx-ins-outs",
1276             [55] = "vmx-true-ctls",
1277         },
1278         .msr = {
1279             .index = MSR_IA32_VMX_BASIC,
1280         },
1281         /* Just to be safe - we don't support setting the MSEG version field.  */
1282         .no_autoenable_flags = MSR_VMX_BASIC_DUAL_MONITOR,
1283     },
1284
1285     [FEAT_VMX_VMFUNC] = {
1286         .type = MSR_FEATURE_WORD,
1287         .feat_names = {
1288             [0] = "vmx-eptp-switching",
1289         },
1290         .msr = {
1291             .index = MSR_IA32_VMX_VMFUNC,
1292         }
1293     },
1294
1295     [FEAT_14_0_ECX] = {
1296         .type = CPUID_FEATURE_WORD,
1297         .feat_names = {
1298             NULL, NULL, NULL, NULL,
1299             NULL, NULL, NULL, NULL,
1300             NULL, NULL, NULL, NULL,
1301             NULL, NULL, NULL, NULL,
1302             NULL, NULL, NULL, NULL,
1303             NULL, NULL, NULL, NULL,
1304             NULL, NULL, NULL, NULL,
1305             NULL, NULL, NULL, "intel-pt-lip",
1306         },
1307         .cpuid = {
1308             .eax = 0x14,
1309             .needs_ecx = true, .ecx = 0,
1310             .reg = R_ECX,
1311         },
1312         .tcg_features = TCG_14_0_ECX_FEATURES,
1313      },
1314
1315 };
1316
1317 typedef struct FeatureMask {
1318     FeatureWord index;
1319     uint64_t mask;
1320 } FeatureMask;
1321
1322 typedef struct FeatureDep {
1323     FeatureMask from, to;
1324 } FeatureDep;
1325
1326 static FeatureDep feature_dependencies[] = {
1327     {
1328         .from = { FEAT_7_0_EDX,             CPUID_7_0_EDX_ARCH_CAPABILITIES },
1329         .to = { FEAT_ARCH_CAPABILITIES,     ~0ull },
1330     },
1331     {
1332         .from = { FEAT_7_0_EDX,             CPUID_7_0_EDX_CORE_CAPABILITY },
1333         .to = { FEAT_CORE_CAPABILITY,       ~0ull },
1334     },
1335     {
1336         .from = { FEAT_1_ECX,             CPUID_EXT_PDCM },
1337         .to = { FEAT_PERF_CAPABILITIES,       ~0ull },
1338     },
1339     {
1340         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1341         .to = { FEAT_VMX_PROCBASED_CTLS,    ~0ull },
1342     },
1343     {
1344         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1345         .to = { FEAT_VMX_PINBASED_CTLS,     ~0ull },
1346     },
1347     {
1348         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1349         .to = { FEAT_VMX_EXIT_CTLS,         ~0ull },
1350     },
1351     {
1352         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1353         .to = { FEAT_VMX_ENTRY_CTLS,        ~0ull },
1354     },
1355     {
1356         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1357         .to = { FEAT_VMX_MISC,              ~0ull },
1358     },
1359     {
1360         .from = { FEAT_1_ECX,               CPUID_EXT_VMX },
1361         .to = { FEAT_VMX_BASIC,             ~0ull },
1362     },
1363     {
1364         .from = { FEAT_8000_0001_EDX,       CPUID_EXT2_LM },
1365         .to = { FEAT_VMX_ENTRY_CTLS,        VMX_VM_ENTRY_IA32E_MODE },
1366     },
1367     {
1368         .from = { FEAT_VMX_PROCBASED_CTLS,  VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS },
1369         .to = { FEAT_VMX_SECONDARY_CTLS,    ~0ull },
1370     },
1371     {
1372         .from = { FEAT_XSAVE,               CPUID_XSAVE_XSAVES },
1373         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_XSAVES },
1374     },
1375     {
1376         .from = { FEAT_1_ECX,               CPUID_EXT_RDRAND },
1377         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_RDRAND_EXITING },
1378     },
1379     {
1380         .from = { FEAT_7_0_EBX,             CPUID_7_0_EBX_INVPCID },
1381         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_ENABLE_INVPCID },
1382     },
1383     {
1384         .from = { FEAT_7_0_EBX,             CPUID_7_0_EBX_RDSEED },
1385         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_RDSEED_EXITING },
1386     },
1387     {
1388         .from = { FEAT_7_0_EBX,             CPUID_7_0_EBX_INTEL_PT },
1389         .to = { FEAT_14_0_ECX,              ~0ull },
1390     },
1391     {
1392         .from = { FEAT_8000_0001_EDX,       CPUID_EXT2_RDTSCP },
1393         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_RDTSCP },
1394     },
1395     {
1396         .from = { FEAT_VMX_SECONDARY_CTLS,  VMX_SECONDARY_EXEC_ENABLE_EPT },
1397         .to = { FEAT_VMX_EPT_VPID_CAPS,     0xffffffffull },
1398     },
1399     {
1400         .from = { FEAT_VMX_SECONDARY_CTLS,  VMX_SECONDARY_EXEC_ENABLE_EPT },
1401         .to = { FEAT_VMX_SECONDARY_CTLS,    VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST },
1402     },
1403     {
1404         .from = { FEAT_VMX_SECONDARY_CTLS,  VMX_SECONDARY_EXEC_ENABLE_VPID },
1405         .to = { FEAT_VMX_EPT_VPID_CAPS,     0xffffffffull << 32 },
1406     },
1407     {
1408         .from = { FEAT_VMX_SECONDARY_CTLS,  VMX_SECONDARY_EXEC_ENABLE_VMFUNC },
1409         .to = { FEAT_VMX_VMFUNC,            ~0ull },
1410     },
1411     {
1412         .from = { FEAT_8000_0001_ECX,       CPUID_EXT3_SVM },
1413         .to = { FEAT_SVM,                   ~0ull },
1414     },
1415 };
1416
1417 typedef struct X86RegisterInfo32 {
1418     /* Name of register */
1419     const char *name;
1420     /* QAPI enum value register */
1421     X86CPURegister32 qapi_enum;
1422 } X86RegisterInfo32;
1423
1424 #define REGISTER(reg) \
1425     [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
1426 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
1427     REGISTER(EAX),
1428     REGISTER(ECX),
1429     REGISTER(EDX),
1430     REGISTER(EBX),
1431     REGISTER(ESP),
1432     REGISTER(EBP),
1433     REGISTER(ESI),
1434     REGISTER(EDI),
1435 };
1436 #undef REGISTER
1437
1438 typedef struct ExtSaveArea {
1439     uint32_t feature, bits;
1440     uint32_t offset, size;
1441 } ExtSaveArea;
1442
1443 static const ExtSaveArea x86_ext_save_areas[] = {
1444     [XSTATE_FP_BIT] = {
1445         /* x87 FP state component is always enabled if XSAVE is supported */
1446         .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1447         /* x87 state is in the legacy region of the XSAVE area */
1448         .offset = 0,
1449         .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1450     },
1451     [XSTATE_SSE_BIT] = {
1452         /* SSE state component is always enabled if XSAVE is supported */
1453         .feature = FEAT_1_ECX, .bits = CPUID_EXT_XSAVE,
1454         /* SSE state is in the legacy region of the XSAVE area */
1455         .offset = 0,
1456         .size = sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader),
1457     },
1458     [XSTATE_YMM_BIT] =
1459           { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
1460             .offset = offsetof(X86XSaveArea, avx_state),
1461             .size = sizeof(XSaveAVX) },
1462     [XSTATE_BNDREGS_BIT] =
1463           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1464             .offset = offsetof(X86XSaveArea, bndreg_state),
1465             .size = sizeof(XSaveBNDREG)  },
1466     [XSTATE_BNDCSR_BIT] =
1467           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
1468             .offset = offsetof(X86XSaveArea, bndcsr_state),
1469             .size = sizeof(XSaveBNDCSR)  },
1470     [XSTATE_OPMASK_BIT] =
1471           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1472             .offset = offsetof(X86XSaveArea, opmask_state),
1473             .size = sizeof(XSaveOpmask) },
1474     [XSTATE_ZMM_Hi256_BIT] =
1475           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1476             .offset = offsetof(X86XSaveArea, zmm_hi256_state),
1477             .size = sizeof(XSaveZMM_Hi256) },
1478     [XSTATE_Hi16_ZMM_BIT] =
1479           { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
1480             .offset = offsetof(X86XSaveArea, hi16_zmm_state),
1481             .size = sizeof(XSaveHi16_ZMM) },
1482     [XSTATE_PKRU_BIT] =
1483           { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
1484             .offset = offsetof(X86XSaveArea, pkru_state),
1485             .size = sizeof(XSavePKRU) },
1486 };
1487
1488 static uint32_t xsave_area_size(uint64_t mask)
1489 {
1490     int i;
1491     uint64_t ret = 0;
1492
1493     for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
1494         const ExtSaveArea *esa = &x86_ext_save_areas[i];
1495         if ((mask >> i) & 1) {
1496             ret = MAX(ret, esa->offset + esa->size);
1497         }
1498     }
1499     return ret;
1500 }
1501
1502 static inline bool accel_uses_host_cpuid(void)
1503 {
1504     return kvm_enabled() || hvf_enabled();
1505 }
1506
1507 static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu)
1508 {
1509     return ((uint64_t)cpu->env.features[FEAT_XSAVE_COMP_HI]) << 32 |
1510            cpu->env.features[FEAT_XSAVE_COMP_LO];
1511 }
1512
1513 /* Return name of 32-bit register, from a R_* constant */
1514 static const char *get_register_name_32(unsigned int reg)
1515 {
1516     if (reg >= CPU_NB_REGS32) {
1517         return NULL;
1518     }
1519     return x86_reg_info_32[reg].name;
1520 }
1521
1522 /*
1523  * Returns the set of feature flags that are supported and migratable by
1524  * QEMU, for a given FeatureWord.
1525  */
1526 static uint64_t x86_cpu_get_migratable_flags(FeatureWord w)
1527 {
1528     FeatureWordInfo *wi = &feature_word_info[w];
1529     uint64_t r = 0;
1530     int i;
1531
1532     for (i = 0; i < 64; i++) {
1533         uint64_t f = 1ULL << i;
1534
1535         /* If the feature name is known, it is implicitly considered migratable,
1536          * unless it is explicitly set in unmigratable_flags */
1537         if ((wi->migratable_flags & f) ||
1538             (wi->feat_names[i] && !(wi->unmigratable_flags & f))) {
1539             r |= f;
1540         }
1541     }
1542     return r;
1543 }
1544
1545 void host_cpuid(uint32_t function, uint32_t count,
1546                 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
1547 {
1548     uint32_t vec[4];
1549
1550 #ifdef __x86_64__
1551     asm volatile("cpuid"
1552                  : "=a"(vec[0]), "=b"(vec[1]),
1553                    "=c"(vec[2]), "=d"(vec[3])
1554                  : "0"(function), "c"(count) : "cc");
1555 #elif defined(__i386__)
1556     asm volatile("pusha \n\t"
1557                  "cpuid \n\t"
1558                  "mov %%eax, 0(%2) \n\t"
1559                  "mov %%ebx, 4(%2) \n\t"
1560                  "mov %%ecx, 8(%2) \n\t"
1561                  "mov %%edx, 12(%2) \n\t"
1562                  "popa"
1563                  : : "a"(function), "c"(count), "S"(vec)
1564                  : "memory", "cc");
1565 #else
1566     abort();
1567 #endif
1568
1569     if (eax)
1570         *eax = vec[0];
1571     if (ebx)
1572         *ebx = vec[1];
1573     if (ecx)
1574         *ecx = vec[2];
1575     if (edx)
1576         *edx = vec[3];
1577 }
1578
1579 /* CPU class name definitions: */
1580
1581 /* Return type name for a given CPU model name
1582  * Caller is responsible for freeing the returned string.
1583  */
1584 static char *x86_cpu_type_name(const char *model_name)
1585 {
1586     return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
1587 }
1588
1589 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
1590 {
1591     g_autofree char *typename = x86_cpu_type_name(cpu_model);
1592     return object_class_by_name(typename);
1593 }
1594
1595 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
1596 {
1597     const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
1598     assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
1599     return g_strndup(class_name,
1600                      strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
1601 }
1602
1603 typedef struct X86CPUVersionDefinition {
1604     X86CPUVersion version;
1605     const char *alias;
1606     const char *note;
1607     PropValue *props;
1608 } X86CPUVersionDefinition;
1609
1610 /* Base definition for a CPU model */
1611 typedef struct X86CPUDefinition {
1612     const char *name;
1613     uint32_t level;
1614     uint32_t xlevel;
1615     /* vendor is zero-terminated, 12 character ASCII string */
1616     char vendor[CPUID_VENDOR_SZ + 1];
1617     int family;
1618     int model;
1619     int stepping;
1620     FeatureWordArray features;
1621     const char *model_id;
1622     CPUCaches *cache_info;
1623     /*
1624      * Definitions for alternative versions of CPU model.
1625      * List is terminated by item with version == 0.
1626      * If NULL, version 1 will be registered automatically.
1627      */
1628     const X86CPUVersionDefinition *versions;
1629     const char *deprecation_note;
1630 } X86CPUDefinition;
1631
1632 /* Reference to a specific CPU model version */
1633 struct X86CPUModel {
1634     /* Base CPU definition */
1635     X86CPUDefinition *cpudef;
1636     /* CPU model version */
1637     X86CPUVersion version;
1638     const char *note;
1639     /*
1640      * If true, this is an alias CPU model.
1641      * This matters only for "-cpu help" and query-cpu-definitions
1642      */
1643     bool is_alias;
1644 };
1645
1646 /* Get full model name for CPU version */
1647 static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
1648                                           X86CPUVersion version)
1649 {
1650     assert(version > 0);
1651     return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
1652 }
1653
1654 static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
1655 {
1656     /* When X86CPUDefinition::versions is NULL, we register only v1 */
1657     static const X86CPUVersionDefinition default_version_list[] = {
1658         { 1 },
1659         { /* end of list */ }
1660     };
1661
1662     return def->versions ?: default_version_list;
1663 }
1664
1665 static CPUCaches epyc_cache_info = {
1666     .l1d_cache = &(CPUCacheInfo) {
1667         .type = DATA_CACHE,
1668         .level = 1,
1669         .size = 32 * KiB,
1670         .line_size = 64,
1671         .associativity = 8,
1672         .partitions = 1,
1673         .sets = 64,
1674         .lines_per_tag = 1,
1675         .self_init = 1,
1676         .no_invd_sharing = true,
1677     },
1678     .l1i_cache = &(CPUCacheInfo) {
1679         .type = INSTRUCTION_CACHE,
1680         .level = 1,
1681         .size = 64 * KiB,
1682         .line_size = 64,
1683         .associativity = 4,
1684         .partitions = 1,
1685         .sets = 256,
1686         .lines_per_tag = 1,
1687         .self_init = 1,
1688         .no_invd_sharing = true,
1689     },
1690     .l2_cache = &(CPUCacheInfo) {
1691         .type = UNIFIED_CACHE,
1692         .level = 2,
1693         .size = 512 * KiB,
1694         .line_size = 64,
1695         .associativity = 8,
1696         .partitions = 1,
1697         .sets = 1024,
1698         .lines_per_tag = 1,
1699     },
1700     .l3_cache = &(CPUCacheInfo) {
1701         .type = UNIFIED_CACHE,
1702         .level = 3,
1703         .size = 8 * MiB,
1704         .line_size = 64,
1705         .associativity = 16,
1706         .partitions = 1,
1707         .sets = 8192,
1708         .lines_per_tag = 1,
1709         .self_init = true,
1710         .inclusive = true,
1711         .complex_indexing = true,
1712     },
1713 };
1714
1715 static CPUCaches epyc_rome_cache_info = {
1716     .l1d_cache = &(CPUCacheInfo) {
1717         .type = DATA_CACHE,
1718         .level = 1,
1719         .size = 32 * KiB,
1720         .line_size = 64,
1721         .associativity = 8,
1722         .partitions = 1,
1723         .sets = 64,
1724         .lines_per_tag = 1,
1725         .self_init = 1,
1726         .no_invd_sharing = true,
1727     },
1728     .l1i_cache = &(CPUCacheInfo) {
1729         .type = INSTRUCTION_CACHE,
1730         .level = 1,
1731         .size = 32 * KiB,
1732         .line_size = 64,
1733         .associativity = 8,
1734         .partitions = 1,
1735         .sets = 64,
1736         .lines_per_tag = 1,
1737         .self_init = 1,
1738         .no_invd_sharing = true,
1739     },
1740     .l2_cache = &(CPUCacheInfo) {
1741         .type = UNIFIED_CACHE,
1742         .level = 2,
1743         .size = 512 * KiB,
1744         .line_size = 64,
1745         .associativity = 8,
1746         .partitions = 1,
1747         .sets = 1024,
1748         .lines_per_tag = 1,
1749     },
1750     .l3_cache = &(CPUCacheInfo) {
1751         .type = UNIFIED_CACHE,
1752         .level = 3,
1753         .size = 16 * MiB,
1754         .line_size = 64,
1755         .associativity = 16,
1756         .partitions = 1,
1757         .sets = 16384,
1758         .lines_per_tag = 1,
1759         .self_init = true,
1760         .inclusive = true,
1761         .complex_indexing = true,
1762     },
1763 };
1764
1765 static CPUCaches epyc_milan_cache_info = {
1766     .l1d_cache = &(CPUCacheInfo) {
1767         .type = DATA_CACHE,
1768         .level = 1,
1769         .size = 32 * KiB,
1770         .line_size = 64,
1771         .associativity = 8,
1772         .partitions = 1,
1773         .sets = 64,
1774         .lines_per_tag = 1,
1775         .self_init = 1,
1776         .no_invd_sharing = true,
1777     },
1778     .l1i_cache = &(CPUCacheInfo) {
1779         .type = INSTRUCTION_CACHE,
1780         .level = 1,
1781         .size = 32 * KiB,
1782         .line_size = 64,
1783         .associativity = 8,
1784         .partitions = 1,
1785         .sets = 64,
1786         .lines_per_tag = 1,
1787         .self_init = 1,
1788         .no_invd_sharing = true,
1789     },
1790     .l2_cache = &(CPUCacheInfo) {
1791         .type = UNIFIED_CACHE,
1792         .level = 2,
1793         .size = 512 * KiB,
1794         .line_size = 64,
1795         .associativity = 8,
1796         .partitions = 1,
1797         .sets = 1024,
1798         .lines_per_tag = 1,
1799     },
1800     .l3_cache = &(CPUCacheInfo) {
1801         .type = UNIFIED_CACHE,
1802         .level = 3,
1803         .size = 32 * MiB,
1804         .line_size = 64,
1805         .associativity = 16,
1806         .partitions = 1,
1807         .sets = 32768,
1808         .lines_per_tag = 1,
1809         .self_init = true,
1810         .inclusive = true,
1811         .complex_indexing = true,
1812     },
1813 };
1814
1815 /* The following VMX features are not supported by KVM and are left out in the
1816  * CPU definitions:
1817  *
1818  *  Dual-monitor support (all processors)
1819  *  Entry to SMM
1820  *  Deactivate dual-monitor treatment
1821  *  Number of CR3-target values
1822  *  Shutdown activity state
1823  *  Wait-for-SIPI activity state
1824  *  PAUSE-loop exiting (Westmere and newer)
1825  *  EPT-violation #VE (Broadwell and newer)
1826  *  Inject event with insn length=0 (Skylake and newer)
1827  *  Conceal non-root operation from PT
1828  *  Conceal VM exits from PT
1829  *  Conceal VM entries from PT
1830  *  Enable ENCLS exiting
1831  *  Mode-based execute control (XS/XU)
1832  s  TSC scaling (Skylake Server and newer)
1833  *  GPA translation for PT (IceLake and newer)
1834  *  User wait and pause
1835  *  ENCLV exiting
1836  *  Load IA32_RTIT_CTL
1837  *  Clear IA32_RTIT_CTL
1838  *  Advanced VM-exit information for EPT violations
1839  *  Sub-page write permissions
1840  *  PT in VMX operation
1841  */
1842
1843 static X86CPUDefinition builtin_x86_defs[] = {
1844     {
1845         .name = "qemu64",
1846         .level = 0xd,
1847         .vendor = CPUID_VENDOR_AMD,
1848         .family = 6,
1849         .model = 6,
1850         .stepping = 3,
1851         .features[FEAT_1_EDX] =
1852             PPRO_FEATURES |
1853             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1854             CPUID_PSE36,
1855         .features[FEAT_1_ECX] =
1856             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1857         .features[FEAT_8000_0001_EDX] =
1858             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1859         .features[FEAT_8000_0001_ECX] =
1860             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
1861         .xlevel = 0x8000000A,
1862         .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1863     },
1864     {
1865         .name = "phenom",
1866         .level = 5,
1867         .vendor = CPUID_VENDOR_AMD,
1868         .family = 16,
1869         .model = 2,
1870         .stepping = 3,
1871         /* Missing: CPUID_HT */
1872         .features[FEAT_1_EDX] =
1873             PPRO_FEATURES |
1874             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1875             CPUID_PSE36 | CPUID_VME,
1876         .features[FEAT_1_ECX] =
1877             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
1878             CPUID_EXT_POPCNT,
1879         .features[FEAT_8000_0001_EDX] =
1880             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
1881             CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
1882             CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
1883         /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1884                     CPUID_EXT3_CR8LEG,
1885                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1886                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
1887         .features[FEAT_8000_0001_ECX] =
1888             CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
1889             CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
1890         /* Missing: CPUID_SVM_LBRV */
1891         .features[FEAT_SVM] =
1892             CPUID_SVM_NPT,
1893         .xlevel = 0x8000001A,
1894         .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
1895     },
1896     {
1897         .name = "core2duo",
1898         .level = 10,
1899         .vendor = CPUID_VENDOR_INTEL,
1900         .family = 6,
1901         .model = 15,
1902         .stepping = 11,
1903         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
1904         .features[FEAT_1_EDX] =
1905             PPRO_FEATURES |
1906             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1907             CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
1908         /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
1909          * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
1910         .features[FEAT_1_ECX] =
1911             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1912             CPUID_EXT_CX16,
1913         .features[FEAT_8000_0001_EDX] =
1914             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1915         .features[FEAT_8000_0001_ECX] =
1916             CPUID_EXT3_LAHF_LM,
1917         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
1918         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1919         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1920         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1921         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1922              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
1923         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1924              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1925              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1926              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1927              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1928              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1929              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1930              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
1931              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
1932              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
1933         .features[FEAT_VMX_SECONDARY_CTLS] =
1934              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
1935         .xlevel = 0x80000008,
1936         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
1937     },
1938     {
1939         .name = "kvm64",
1940         .level = 0xd,
1941         .vendor = CPUID_VENDOR_INTEL,
1942         .family = 15,
1943         .model = 6,
1944         .stepping = 1,
1945         /* Missing: CPUID_HT */
1946         .features[FEAT_1_EDX] =
1947             PPRO_FEATURES | CPUID_VME |
1948             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
1949             CPUID_PSE36,
1950         /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
1951         .features[FEAT_1_ECX] =
1952             CPUID_EXT_SSE3 | CPUID_EXT_CX16,
1953         /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
1954         .features[FEAT_8000_0001_EDX] =
1955             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1956         /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
1957                     CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
1958                     CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
1959                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
1960         .features[FEAT_8000_0001_ECX] =
1961             0,
1962         /* VMX features from Cedar Mill/Prescott */
1963         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
1964         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
1965         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
1966         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
1967              VMX_PIN_BASED_NMI_EXITING,
1968         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
1969              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
1970              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
1971              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
1972              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
1973              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
1974              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
1975              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
1976         .xlevel = 0x80000008,
1977         .model_id = "Common KVM processor"
1978     },
1979     {
1980         .name = "qemu32",
1981         .level = 4,
1982         .vendor = CPUID_VENDOR_INTEL,
1983         .family = 6,
1984         .model = 6,
1985         .stepping = 3,
1986         .features[FEAT_1_EDX] =
1987             PPRO_FEATURES,
1988         .features[FEAT_1_ECX] =
1989             CPUID_EXT_SSE3,
1990         .xlevel = 0x80000004,
1991         .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
1992     },
1993     {
1994         .name = "kvm32",
1995         .level = 5,
1996         .vendor = CPUID_VENDOR_INTEL,
1997         .family = 15,
1998         .model = 6,
1999         .stepping = 1,
2000         .features[FEAT_1_EDX] =
2001             PPRO_FEATURES | CPUID_VME |
2002             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
2003         .features[FEAT_1_ECX] =
2004             CPUID_EXT_SSE3,
2005         .features[FEAT_8000_0001_ECX] =
2006             0,
2007         /* VMX features from Yonah */
2008         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2009         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2010         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2011         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2012              VMX_PIN_BASED_NMI_EXITING,
2013         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2014              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2015              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2016              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2017              VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2018              VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2019              VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2020         .xlevel = 0x80000008,
2021         .model_id = "Common 32-bit KVM processor"
2022     },
2023     {
2024         .name = "coreduo",
2025         .level = 10,
2026         .vendor = CPUID_VENDOR_INTEL,
2027         .family = 6,
2028         .model = 14,
2029         .stepping = 8,
2030         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2031         .features[FEAT_1_EDX] =
2032             PPRO_FEATURES | CPUID_VME |
2033             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
2034             CPUID_SS,
2035         /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
2036          * CPUID_EXT_PDCM, CPUID_EXT_VMX */
2037         .features[FEAT_1_ECX] =
2038             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
2039         .features[FEAT_8000_0001_EDX] =
2040             CPUID_EXT2_NX,
2041         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2042         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2043         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2044         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2045              VMX_PIN_BASED_NMI_EXITING,
2046         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2047              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2048              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2049              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2050              VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
2051              VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
2052              VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
2053         .xlevel = 0x80000008,
2054         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
2055     },
2056     {
2057         .name = "486",
2058         .level = 1,
2059         .vendor = CPUID_VENDOR_INTEL,
2060         .family = 4,
2061         .model = 8,
2062         .stepping = 0,
2063         .features[FEAT_1_EDX] =
2064             I486_FEATURES,
2065         .xlevel = 0,
2066         .model_id = "",
2067     },
2068     {
2069         .name = "pentium",
2070         .level = 1,
2071         .vendor = CPUID_VENDOR_INTEL,
2072         .family = 5,
2073         .model = 4,
2074         .stepping = 3,
2075         .features[FEAT_1_EDX] =
2076             PENTIUM_FEATURES,
2077         .xlevel = 0,
2078         .model_id = "",
2079     },
2080     {
2081         .name = "pentium2",
2082         .level = 2,
2083         .vendor = CPUID_VENDOR_INTEL,
2084         .family = 6,
2085         .model = 5,
2086         .stepping = 2,
2087         .features[FEAT_1_EDX] =
2088             PENTIUM2_FEATURES,
2089         .xlevel = 0,
2090         .model_id = "",
2091     },
2092     {
2093         .name = "pentium3",
2094         .level = 3,
2095         .vendor = CPUID_VENDOR_INTEL,
2096         .family = 6,
2097         .model = 7,
2098         .stepping = 3,
2099         .features[FEAT_1_EDX] =
2100             PENTIUM3_FEATURES,
2101         .xlevel = 0,
2102         .model_id = "",
2103     },
2104     {
2105         .name = "athlon",
2106         .level = 2,
2107         .vendor = CPUID_VENDOR_AMD,
2108         .family = 6,
2109         .model = 2,
2110         .stepping = 3,
2111         .features[FEAT_1_EDX] =
2112             PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
2113             CPUID_MCA,
2114         .features[FEAT_8000_0001_EDX] =
2115             CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
2116         .xlevel = 0x80000008,
2117         .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
2118     },
2119     {
2120         .name = "n270",
2121         .level = 10,
2122         .vendor = CPUID_VENDOR_INTEL,
2123         .family = 6,
2124         .model = 28,
2125         .stepping = 2,
2126         /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
2127         .features[FEAT_1_EDX] =
2128             PPRO_FEATURES |
2129             CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
2130             CPUID_ACPI | CPUID_SS,
2131             /* Some CPUs got no CPUID_SEP */
2132         /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
2133          * CPUID_EXT_XTPR */
2134         .features[FEAT_1_ECX] =
2135             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
2136             CPUID_EXT_MOVBE,
2137         .features[FEAT_8000_0001_EDX] =
2138             CPUID_EXT2_NX,
2139         .features[FEAT_8000_0001_ECX] =
2140             CPUID_EXT3_LAHF_LM,
2141         .xlevel = 0x80000008,
2142         .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",
2143     },
2144     {
2145         .name = "Conroe",
2146         .level = 10,
2147         .vendor = CPUID_VENDOR_INTEL,
2148         .family = 6,
2149         .model = 15,
2150         .stepping = 3,
2151         .features[FEAT_1_EDX] =
2152             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2153             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2154             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2155             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2156             CPUID_DE | CPUID_FP87,
2157         .features[FEAT_1_ECX] =
2158             CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2159         .features[FEAT_8000_0001_EDX] =
2160             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2161         .features[FEAT_8000_0001_ECX] =
2162             CPUID_EXT3_LAHF_LM,
2163         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2164         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
2165         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
2166         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2167         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2168              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2169         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2170              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2171              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2172              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2173              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2174              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2175              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2176              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2177              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2178              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2179         .features[FEAT_VMX_SECONDARY_CTLS] =
2180              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
2181         .xlevel = 0x80000008,
2182         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
2183     },
2184     {
2185         .name = "Penryn",
2186         .level = 10,
2187         .vendor = CPUID_VENDOR_INTEL,
2188         .family = 6,
2189         .model = 23,
2190         .stepping = 3,
2191         .features[FEAT_1_EDX] =
2192             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2193             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2194             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2195             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2196             CPUID_DE | CPUID_FP87,
2197         .features[FEAT_1_ECX] =
2198             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2199             CPUID_EXT_SSE3,
2200         .features[FEAT_8000_0001_EDX] =
2201             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2202         .features[FEAT_8000_0001_ECX] =
2203             CPUID_EXT3_LAHF_LM,
2204         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
2205         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2206              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
2207         .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
2208              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
2209         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2210         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2211              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
2212         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2213              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2214              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2215              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2216              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2217              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2218              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2219              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2220              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2221              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2222         .features[FEAT_VMX_SECONDARY_CTLS] =
2223              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2224              VMX_SECONDARY_EXEC_WBINVD_EXITING,
2225         .xlevel = 0x80000008,
2226         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
2227     },
2228     {
2229         .name = "Nehalem",
2230         .level = 11,
2231         .vendor = CPUID_VENDOR_INTEL,
2232         .family = 6,
2233         .model = 26,
2234         .stepping = 3,
2235         .features[FEAT_1_EDX] =
2236             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2237             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2238             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2239             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2240             CPUID_DE | CPUID_FP87,
2241         .features[FEAT_1_ECX] =
2242             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2243             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
2244         .features[FEAT_8000_0001_EDX] =
2245             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2246         .features[FEAT_8000_0001_ECX] =
2247             CPUID_EXT3_LAHF_LM,
2248         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2249              MSR_VMX_BASIC_TRUE_CTLS,
2250         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2251              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2252              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2253         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2254              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2255              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2256              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2257              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2258              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2259              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2260         .features[FEAT_VMX_EXIT_CTLS] =
2261              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2262              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2263              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2264              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2265              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2266         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
2267         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2268              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2269              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2270         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2271              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2272              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2273              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2274              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2275              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2276              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2277              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2278              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2279              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2280              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2281              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2282         .features[FEAT_VMX_SECONDARY_CTLS] =
2283              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2284              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2285              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2286              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2287              VMX_SECONDARY_EXEC_ENABLE_VPID,
2288         .xlevel = 0x80000008,
2289         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
2290         .versions = (X86CPUVersionDefinition[]) {
2291             { .version = 1 },
2292             {
2293                 .version = 2,
2294                 .alias = "Nehalem-IBRS",
2295                 .props = (PropValue[]) {
2296                     { "spec-ctrl", "on" },
2297                     { "model-id",
2298                       "Intel Core i7 9xx (Nehalem Core i7, IBRS update)" },
2299                     { /* end of list */ }
2300                 }
2301             },
2302             { /* end of list */ }
2303         }
2304     },
2305     {
2306         .name = "Westmere",
2307         .level = 11,
2308         .vendor = CPUID_VENDOR_INTEL,
2309         .family = 6,
2310         .model = 44,
2311         .stepping = 1,
2312         .features[FEAT_1_EDX] =
2313             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2314             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2315             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2316             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2317             CPUID_DE | CPUID_FP87,
2318         .features[FEAT_1_ECX] =
2319             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
2320             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2321             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
2322         .features[FEAT_8000_0001_EDX] =
2323             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
2324         .features[FEAT_8000_0001_ECX] =
2325             CPUID_EXT3_LAHF_LM,
2326         .features[FEAT_6_EAX] =
2327             CPUID_6_EAX_ARAT,
2328         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2329              MSR_VMX_BASIC_TRUE_CTLS,
2330         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2331              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2332              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2333         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2334              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2335              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2336              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2337              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2338              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2339              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2340         .features[FEAT_VMX_EXIT_CTLS] =
2341              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2342              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2343              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2344              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2345              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2346         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2347              MSR_VMX_MISC_STORE_LMA,
2348         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2349              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2350              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2351         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2352              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2353              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2354              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2355              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2356              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2357              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2358              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2359              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2360              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2361              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2362              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2363         .features[FEAT_VMX_SECONDARY_CTLS] =
2364              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2365              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2366              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2367              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2368              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2369         .xlevel = 0x80000008,
2370         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
2371         .versions = (X86CPUVersionDefinition[]) {
2372             { .version = 1 },
2373             {
2374                 .version = 2,
2375                 .alias = "Westmere-IBRS",
2376                 .props = (PropValue[]) {
2377                     { "spec-ctrl", "on" },
2378                     { "model-id",
2379                       "Westmere E56xx/L56xx/X56xx (IBRS update)" },
2380                     { /* end of list */ }
2381                 }
2382             },
2383             { /* end of list */ }
2384         }
2385     },
2386     {
2387         .name = "SandyBridge",
2388         .level = 0xd,
2389         .vendor = CPUID_VENDOR_INTEL,
2390         .family = 6,
2391         .model = 42,
2392         .stepping = 1,
2393         .features[FEAT_1_EDX] =
2394             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2395             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2396             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2397             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2398             CPUID_DE | CPUID_FP87,
2399         .features[FEAT_1_ECX] =
2400             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2401             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2402             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2403             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2404             CPUID_EXT_SSE3,
2405         .features[FEAT_8000_0001_EDX] =
2406             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2407             CPUID_EXT2_SYSCALL,
2408         .features[FEAT_8000_0001_ECX] =
2409             CPUID_EXT3_LAHF_LM,
2410         .features[FEAT_XSAVE] =
2411             CPUID_XSAVE_XSAVEOPT,
2412         .features[FEAT_6_EAX] =
2413             CPUID_6_EAX_ARAT,
2414         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2415              MSR_VMX_BASIC_TRUE_CTLS,
2416         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2417              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2418              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2419         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2420              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2421              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2422              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2423              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2424              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2425              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2426         .features[FEAT_VMX_EXIT_CTLS] =
2427              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2428              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2429              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2430              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2431              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2432         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2433              MSR_VMX_MISC_STORE_LMA,
2434         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2435              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2436              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2437         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2438              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2439              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2440              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2441              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2442              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2443              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2444              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2445              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2446              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2447              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2448              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2449         .features[FEAT_VMX_SECONDARY_CTLS] =
2450              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2451              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2452              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2453              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2454              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
2455         .xlevel = 0x80000008,
2456         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
2457         .versions = (X86CPUVersionDefinition[]) {
2458             { .version = 1 },
2459             {
2460                 .version = 2,
2461                 .alias = "SandyBridge-IBRS",
2462                 .props = (PropValue[]) {
2463                     { "spec-ctrl", "on" },
2464                     { "model-id",
2465                       "Intel Xeon E312xx (Sandy Bridge, IBRS update)" },
2466                     { /* end of list */ }
2467                 }
2468             },
2469             { /* end of list */ }
2470         }
2471     },
2472     {
2473         .name = "IvyBridge",
2474         .level = 0xd,
2475         .vendor = CPUID_VENDOR_INTEL,
2476         .family = 6,
2477         .model = 58,
2478         .stepping = 9,
2479         .features[FEAT_1_EDX] =
2480             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2481             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2482             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2483             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2484             CPUID_DE | CPUID_FP87,
2485         .features[FEAT_1_ECX] =
2486             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2487             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
2488             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
2489             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
2490             CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2491         .features[FEAT_7_0_EBX] =
2492             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
2493             CPUID_7_0_EBX_ERMS,
2494         .features[FEAT_8000_0001_EDX] =
2495             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2496             CPUID_EXT2_SYSCALL,
2497         .features[FEAT_8000_0001_ECX] =
2498             CPUID_EXT3_LAHF_LM,
2499         .features[FEAT_XSAVE] =
2500             CPUID_XSAVE_XSAVEOPT,
2501         .features[FEAT_6_EAX] =
2502             CPUID_6_EAX_ARAT,
2503         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2504              MSR_VMX_BASIC_TRUE_CTLS,
2505         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2506              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2507              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2508         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2509              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2510              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2511              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2512              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2513              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2514              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
2515         .features[FEAT_VMX_EXIT_CTLS] =
2516              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2517              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2518              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2519              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2520              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2521         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2522              MSR_VMX_MISC_STORE_LMA,
2523         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2524              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2525              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2526         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2527              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2528              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2529              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2530              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2531              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2532              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2533              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2534              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2535              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2536              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2537              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2538         .features[FEAT_VMX_SECONDARY_CTLS] =
2539              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2540              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2541              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2542              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2543              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2544              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2545              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2546              VMX_SECONDARY_EXEC_RDRAND_EXITING,
2547         .xlevel = 0x80000008,
2548         .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
2549         .versions = (X86CPUVersionDefinition[]) {
2550             { .version = 1 },
2551             {
2552                 .version = 2,
2553                 .alias = "IvyBridge-IBRS",
2554                 .props = (PropValue[]) {
2555                     { "spec-ctrl", "on" },
2556                     { "model-id",
2557                       "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)" },
2558                     { /* end of list */ }
2559                 }
2560             },
2561             { /* end of list */ }
2562         }
2563     },
2564     {
2565         .name = "Haswell",
2566         .level = 0xd,
2567         .vendor = CPUID_VENDOR_INTEL,
2568         .family = 6,
2569         .model = 60,
2570         .stepping = 4,
2571         .features[FEAT_1_EDX] =
2572             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2573             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2574             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2575             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2576             CPUID_DE | CPUID_FP87,
2577         .features[FEAT_1_ECX] =
2578             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2579             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2580             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2581             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2582             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2583             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2584         .features[FEAT_8000_0001_EDX] =
2585             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2586             CPUID_EXT2_SYSCALL,
2587         .features[FEAT_8000_0001_ECX] =
2588             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
2589         .features[FEAT_7_0_EBX] =
2590             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2591             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2592             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2593             CPUID_7_0_EBX_RTM,
2594         .features[FEAT_XSAVE] =
2595             CPUID_XSAVE_XSAVEOPT,
2596         .features[FEAT_6_EAX] =
2597             CPUID_6_EAX_ARAT,
2598         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2599              MSR_VMX_BASIC_TRUE_CTLS,
2600         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2601              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2602              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2603         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2604              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2605              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2606              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2607              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2608              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2609              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2610         .features[FEAT_VMX_EXIT_CTLS] =
2611              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2612              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2613              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2614              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2615              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2616         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2617              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2618         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2619              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2620              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2621         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2622              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2623              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2624              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2625              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2626              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2627              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2628              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2629              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2630              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2631              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2632              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2633         .features[FEAT_VMX_SECONDARY_CTLS] =
2634              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2635              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2636              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2637              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2638              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2639              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2640              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2641              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2642              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
2643         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2644         .xlevel = 0x80000008,
2645         .model_id = "Intel Core Processor (Haswell)",
2646         .versions = (X86CPUVersionDefinition[]) {
2647             { .version = 1 },
2648             {
2649                 .version = 2,
2650                 .alias = "Haswell-noTSX",
2651                 .props = (PropValue[]) {
2652                     { "hle", "off" },
2653                     { "rtm", "off" },
2654                     { "stepping", "1" },
2655                     { "model-id", "Intel Core Processor (Haswell, no TSX)", },
2656                     { /* end of list */ }
2657                 },
2658             },
2659             {
2660                 .version = 3,
2661                 .alias = "Haswell-IBRS",
2662                 .props = (PropValue[]) {
2663                     /* Restore TSX features removed by -v2 above */
2664                     { "hle", "on" },
2665                     { "rtm", "on" },
2666                     /*
2667                      * Haswell and Haswell-IBRS had stepping=4 in
2668                      * QEMU 4.0 and older
2669                      */
2670                     { "stepping", "4" },
2671                     { "spec-ctrl", "on" },
2672                     { "model-id",
2673                       "Intel Core Processor (Haswell, IBRS)" },
2674                     { /* end of list */ }
2675                 }
2676             },
2677             {
2678                 .version = 4,
2679                 .alias = "Haswell-noTSX-IBRS",
2680                 .props = (PropValue[]) {
2681                     { "hle", "off" },
2682                     { "rtm", "off" },
2683                     /* spec-ctrl was already enabled by -v3 above */
2684                     { "stepping", "1" },
2685                     { "model-id",
2686                       "Intel Core Processor (Haswell, no TSX, IBRS)" },
2687                     { /* end of list */ }
2688                 }
2689             },
2690             { /* end of list */ }
2691         }
2692     },
2693     {
2694         .name = "Broadwell",
2695         .level = 0xd,
2696         .vendor = CPUID_VENDOR_INTEL,
2697         .family = 6,
2698         .model = 61,
2699         .stepping = 2,
2700         .features[FEAT_1_EDX] =
2701             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2702             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2703             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2704             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2705             CPUID_DE | CPUID_FP87,
2706         .features[FEAT_1_ECX] =
2707             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2708             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2709             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2710             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2711             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2712             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2713         .features[FEAT_8000_0001_EDX] =
2714             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2715             CPUID_EXT2_SYSCALL,
2716         .features[FEAT_8000_0001_ECX] =
2717             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2718         .features[FEAT_7_0_EBX] =
2719             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2720             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2721             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2722             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2723             CPUID_7_0_EBX_SMAP,
2724         .features[FEAT_XSAVE] =
2725             CPUID_XSAVE_XSAVEOPT,
2726         .features[FEAT_6_EAX] =
2727             CPUID_6_EAX_ARAT,
2728         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2729              MSR_VMX_BASIC_TRUE_CTLS,
2730         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2731              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2732              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2733         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2734              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2735              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2736              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2737              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2738              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2739              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2740         .features[FEAT_VMX_EXIT_CTLS] =
2741              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2742              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2743              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2744              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2745              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2746         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2747              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2748         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2749              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2750              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
2751         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2752              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2753              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2754              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2755              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2756              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2757              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2758              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2759              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2760              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2761              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2762              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2763         .features[FEAT_VMX_SECONDARY_CTLS] =
2764              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2765              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2766              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2767              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2768              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2769              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
2770              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2771              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2772              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2773              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2774         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2775         .xlevel = 0x80000008,
2776         .model_id = "Intel Core Processor (Broadwell)",
2777         .versions = (X86CPUVersionDefinition[]) {
2778             { .version = 1 },
2779             {
2780                 .version = 2,
2781                 .alias = "Broadwell-noTSX",
2782                 .props = (PropValue[]) {
2783                     { "hle", "off" },
2784                     { "rtm", "off" },
2785                     { "model-id", "Intel Core Processor (Broadwell, no TSX)", },
2786                     { /* end of list */ }
2787                 },
2788             },
2789             {
2790                 .version = 3,
2791                 .alias = "Broadwell-IBRS",
2792                 .props = (PropValue[]) {
2793                     /* Restore TSX features removed by -v2 above */
2794                     { "hle", "on" },
2795                     { "rtm", "on" },
2796                     { "spec-ctrl", "on" },
2797                     { "model-id",
2798                       "Intel Core Processor (Broadwell, IBRS)" },
2799                     { /* end of list */ }
2800                 }
2801             },
2802             {
2803                 .version = 4,
2804                 .alias = "Broadwell-noTSX-IBRS",
2805                 .props = (PropValue[]) {
2806                     { "hle", "off" },
2807                     { "rtm", "off" },
2808                     /* spec-ctrl was already enabled by -v3 above */
2809                     { "model-id",
2810                       "Intel Core Processor (Broadwell, no TSX, IBRS)" },
2811                     { /* end of list */ }
2812                 }
2813             },
2814             { /* end of list */ }
2815         }
2816     },
2817     {
2818         .name = "Skylake-Client",
2819         .level = 0xd,
2820         .vendor = CPUID_VENDOR_INTEL,
2821         .family = 6,
2822         .model = 94,
2823         .stepping = 3,
2824         .features[FEAT_1_EDX] =
2825             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2826             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2827             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2828             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2829             CPUID_DE | CPUID_FP87,
2830         .features[FEAT_1_ECX] =
2831             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2832             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2833             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2834             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2835             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2836             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2837         .features[FEAT_8000_0001_EDX] =
2838             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
2839             CPUID_EXT2_SYSCALL,
2840         .features[FEAT_8000_0001_ECX] =
2841             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2842         .features[FEAT_7_0_EBX] =
2843             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2844             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2845             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2846             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2847             CPUID_7_0_EBX_SMAP,
2848         /* Missing: XSAVES (not supported by some Linux versions,
2849          * including v4.1 to v4.12).
2850          * KVM doesn't yet expose any XSAVES state save component,
2851          * and the only one defined in Skylake (processor tracing)
2852          * probably will block migration anyway.
2853          */
2854         .features[FEAT_XSAVE] =
2855             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2856             CPUID_XSAVE_XGETBV1,
2857         .features[FEAT_6_EAX] =
2858             CPUID_6_EAX_ARAT,
2859         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2860         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2861              MSR_VMX_BASIC_TRUE_CTLS,
2862         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2863              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2864              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2865         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2866              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2867              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2868              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2869              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2870              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2871              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2872         .features[FEAT_VMX_EXIT_CTLS] =
2873              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2874              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2875              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2876              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2877              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2878         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2879              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
2880         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
2881              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
2882              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
2883         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
2884              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
2885              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
2886              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
2887              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
2888              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
2889              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
2890              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
2891              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
2892              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
2893              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
2894              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
2895         .features[FEAT_VMX_SECONDARY_CTLS] =
2896              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2897              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
2898              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
2899              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
2900              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
2901              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
2902              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
2903         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
2904         .xlevel = 0x80000008,
2905         .model_id = "Intel Core Processor (Skylake)",
2906         .versions = (X86CPUVersionDefinition[]) {
2907             { .version = 1 },
2908             {
2909                 .version = 2,
2910                 .alias = "Skylake-Client-IBRS",
2911                 .props = (PropValue[]) {
2912                     { "spec-ctrl", "on" },
2913                     { "model-id",
2914                       "Intel Core Processor (Skylake, IBRS)" },
2915                     { /* end of list */ }
2916                 }
2917             },
2918             {
2919                 .version = 3,
2920                 .alias = "Skylake-Client-noTSX-IBRS",
2921                 .props = (PropValue[]) {
2922                     { "hle", "off" },
2923                     { "rtm", "off" },
2924                     { "model-id",
2925                       "Intel Core Processor (Skylake, IBRS, no TSX)" },
2926                     { /* end of list */ }
2927                 }
2928             },
2929             { /* end of list */ }
2930         }
2931     },
2932     {
2933         .name = "Skylake-Server",
2934         .level = 0xd,
2935         .vendor = CPUID_VENDOR_INTEL,
2936         .family = 6,
2937         .model = 85,
2938         .stepping = 4,
2939         .features[FEAT_1_EDX] =
2940             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
2941             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
2942             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
2943             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
2944             CPUID_DE | CPUID_FP87,
2945         .features[FEAT_1_ECX] =
2946             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
2947             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
2948             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
2949             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
2950             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
2951             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
2952         .features[FEAT_8000_0001_EDX] =
2953             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
2954             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
2955         .features[FEAT_8000_0001_ECX] =
2956             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
2957         .features[FEAT_7_0_EBX] =
2958             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
2959             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
2960             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
2961             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
2962             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
2963             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
2964             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
2965             CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
2966         .features[FEAT_7_0_ECX] =
2967             CPUID_7_0_ECX_PKU,
2968         /* Missing: XSAVES (not supported by some Linux versions,
2969          * including v4.1 to v4.12).
2970          * KVM doesn't yet expose any XSAVES state save component,
2971          * and the only one defined in Skylake (processor tracing)
2972          * probably will block migration anyway.
2973          */
2974         .features[FEAT_XSAVE] =
2975             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
2976             CPUID_XSAVE_XGETBV1,
2977         .features[FEAT_6_EAX] =
2978             CPUID_6_EAX_ARAT,
2979         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
2980         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
2981              MSR_VMX_BASIC_TRUE_CTLS,
2982         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
2983              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
2984              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
2985         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
2986              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
2987              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
2988              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
2989              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
2990              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
2991              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
2992         .features[FEAT_VMX_EXIT_CTLS] =
2993              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
2994              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2995              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
2996              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
2997              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
2998         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
2999              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3000         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3001              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3002              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3003         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3004              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3005              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3006              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3007              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3008              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3009              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3010              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3011              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3012              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3013              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3014              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3015         .features[FEAT_VMX_SECONDARY_CTLS] =
3016              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3017              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3018              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3019              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3020              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3021              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3022              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3023              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3024              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3025              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3026         .xlevel = 0x80000008,
3027         .model_id = "Intel Xeon Processor (Skylake)",
3028         .versions = (X86CPUVersionDefinition[]) {
3029             { .version = 1 },
3030             {
3031                 .version = 2,
3032                 .alias = "Skylake-Server-IBRS",
3033                 .props = (PropValue[]) {
3034                     /* clflushopt was not added to Skylake-Server-IBRS */
3035                     /* TODO: add -v3 including clflushopt */
3036                     { "clflushopt", "off" },
3037                     { "spec-ctrl", "on" },
3038                     { "model-id",
3039                       "Intel Xeon Processor (Skylake, IBRS)" },
3040                     { /* end of list */ }
3041                 }
3042             },
3043             {
3044                 .version = 3,
3045                 .alias = "Skylake-Server-noTSX-IBRS",
3046                 .props = (PropValue[]) {
3047                     { "hle", "off" },
3048                     { "rtm", "off" },
3049                     { "model-id",
3050                       "Intel Xeon Processor (Skylake, IBRS, no TSX)" },
3051                     { /* end of list */ }
3052                 }
3053             },
3054             {
3055                 .version = 4,
3056                 .props = (PropValue[]) {
3057                     { "vmx-eptp-switching", "on" },
3058                     { /* end of list */ }
3059                 }
3060             },
3061             { /* end of list */ }
3062         }
3063     },
3064     {
3065         .name = "Cascadelake-Server",
3066         .level = 0xd,
3067         .vendor = CPUID_VENDOR_INTEL,
3068         .family = 6,
3069         .model = 85,
3070         .stepping = 6,
3071         .features[FEAT_1_EDX] =
3072             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3073             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3074             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3075             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3076             CPUID_DE | CPUID_FP87,
3077         .features[FEAT_1_ECX] =
3078             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3079             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3080             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3081             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3082             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3083             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3084         .features[FEAT_8000_0001_EDX] =
3085             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3086             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3087         .features[FEAT_8000_0001_ECX] =
3088             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3089         .features[FEAT_7_0_EBX] =
3090             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3091             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3092             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3093             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3094             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3095             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3096             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3097             CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3098         .features[FEAT_7_0_ECX] =
3099             CPUID_7_0_ECX_PKU |
3100             CPUID_7_0_ECX_AVX512VNNI,
3101         .features[FEAT_7_0_EDX] =
3102             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3103         /* Missing: XSAVES (not supported by some Linux versions,
3104                 * including v4.1 to v4.12).
3105                 * KVM doesn't yet expose any XSAVES state save component,
3106                 * and the only one defined in Skylake (processor tracing)
3107                 * probably will block migration anyway.
3108                 */
3109         .features[FEAT_XSAVE] =
3110             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3111             CPUID_XSAVE_XGETBV1,
3112         .features[FEAT_6_EAX] =
3113             CPUID_6_EAX_ARAT,
3114         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3115         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3116              MSR_VMX_BASIC_TRUE_CTLS,
3117         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3118              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3119              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3120         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3121              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3122              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3123              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3124              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3125              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3126              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3127         .features[FEAT_VMX_EXIT_CTLS] =
3128              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3129              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3130              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3131              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3132              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3133         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3134              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3135         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3136              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3137              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3138         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3139              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3140              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3141              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3142              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3143              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3144              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3145              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3146              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3147              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3148              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3149              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3150         .features[FEAT_VMX_SECONDARY_CTLS] =
3151              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3152              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3153              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3154              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3155              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3156              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3157              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3158              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3159              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3160              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3161         .xlevel = 0x80000008,
3162         .model_id = "Intel Xeon Processor (Cascadelake)",
3163         .versions = (X86CPUVersionDefinition[]) {
3164             { .version = 1 },
3165             { .version = 2,
3166               .note = "ARCH_CAPABILITIES",
3167               .props = (PropValue[]) {
3168                   { "arch-capabilities", "on" },
3169                   { "rdctl-no", "on" },
3170                   { "ibrs-all", "on" },
3171                   { "skip-l1dfl-vmentry", "on" },
3172                   { "mds-no", "on" },
3173                   { /* end of list */ }
3174               },
3175             },
3176             { .version = 3,
3177               .alias = "Cascadelake-Server-noTSX",
3178               .note = "ARCH_CAPABILITIES, no TSX",
3179               .props = (PropValue[]) {
3180                   { "hle", "off" },
3181                   { "rtm", "off" },
3182                   { /* end of list */ }
3183               },
3184             },
3185             { .version = 4,
3186               .note = "ARCH_CAPABILITIES, no TSX",
3187               .props = (PropValue[]) {
3188                   { "vmx-eptp-switching", "on" },
3189                   { /* end of list */ }
3190               },
3191             },
3192             { /* end of list */ }
3193         }
3194     },
3195     {
3196         .name = "Cooperlake",
3197         .level = 0xd,
3198         .vendor = CPUID_VENDOR_INTEL,
3199         .family = 6,
3200         .model = 85,
3201         .stepping = 10,
3202         .features[FEAT_1_EDX] =
3203             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3204             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3205             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3206             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3207             CPUID_DE | CPUID_FP87,
3208         .features[FEAT_1_ECX] =
3209             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3210             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3211             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3212             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3213             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3214             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3215         .features[FEAT_8000_0001_EDX] =
3216             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3217             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3218         .features[FEAT_8000_0001_ECX] =
3219             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3220         .features[FEAT_7_0_EBX] =
3221             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3222             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3223             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3224             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3225             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3226             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3227             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3228             CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3229         .features[FEAT_7_0_ECX] =
3230             CPUID_7_0_ECX_PKU |
3231             CPUID_7_0_ECX_AVX512VNNI,
3232         .features[FEAT_7_0_EDX] =
3233             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
3234             CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
3235         .features[FEAT_ARCH_CAPABILITIES] =
3236             MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
3237             MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
3238             MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
3239         .features[FEAT_7_1_EAX] =
3240             CPUID_7_1_EAX_AVX512_BF16,
3241         /*
3242          * Missing: XSAVES (not supported by some Linux versions,
3243          * including v4.1 to v4.12).
3244          * KVM doesn't yet expose any XSAVES state save component,
3245          * and the only one defined in Skylake (processor tracing)
3246          * probably will block migration anyway.
3247          */
3248         .features[FEAT_XSAVE] =
3249             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3250             CPUID_XSAVE_XGETBV1,
3251         .features[FEAT_6_EAX] =
3252             CPUID_6_EAX_ARAT,
3253         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3254         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3255              MSR_VMX_BASIC_TRUE_CTLS,
3256         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3257              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3258              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3259         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3260              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3261              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3262              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3263              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3264              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3265              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3266         .features[FEAT_VMX_EXIT_CTLS] =
3267              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3268              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3269              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3270              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3271              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3272         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3273              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3274         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3275              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3276              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3277         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3278              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3279              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3280              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3281              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3282              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3283              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3284              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3285              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3286              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3287              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3288              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3289         .features[FEAT_VMX_SECONDARY_CTLS] =
3290              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3291              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3292              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3293              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3294              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3295              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3296              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3297              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3298              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3299              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3300         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3301         .xlevel = 0x80000008,
3302         .model_id = "Intel Xeon Processor (Cooperlake)",
3303     },
3304     {
3305         .name = "Icelake-Client",
3306         .level = 0xd,
3307         .vendor = CPUID_VENDOR_INTEL,
3308         .family = 6,
3309         .model = 126,
3310         .stepping = 0,
3311         .features[FEAT_1_EDX] =
3312             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3313             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3314             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3315             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3316             CPUID_DE | CPUID_FP87,
3317         .features[FEAT_1_ECX] =
3318             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3319             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3320             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3321             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3322             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3323             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3324         .features[FEAT_8000_0001_EDX] =
3325             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
3326             CPUID_EXT2_SYSCALL,
3327         .features[FEAT_8000_0001_ECX] =
3328             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3329         .features[FEAT_8000_0008_EBX] =
3330             CPUID_8000_0008_EBX_WBNOINVD,
3331         .features[FEAT_7_0_EBX] =
3332             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3333             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3334             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3335             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3336             CPUID_7_0_EBX_SMAP,
3337         .features[FEAT_7_0_ECX] =
3338             CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3339             CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3340             CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3341             CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3342             CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3343         .features[FEAT_7_0_EDX] =
3344             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3345         /* Missing: XSAVES (not supported by some Linux versions,
3346                 * including v4.1 to v4.12).
3347                 * KVM doesn't yet expose any XSAVES state save component,
3348                 * and the only one defined in Skylake (processor tracing)
3349                 * probably will block migration anyway.
3350                 */
3351         .features[FEAT_XSAVE] =
3352             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3353             CPUID_XSAVE_XGETBV1,
3354         .features[FEAT_6_EAX] =
3355             CPUID_6_EAX_ARAT,
3356         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3357         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3358              MSR_VMX_BASIC_TRUE_CTLS,
3359         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3360              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3361              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3362         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3363              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3364              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3365              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3366              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3367              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3368              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3369         .features[FEAT_VMX_EXIT_CTLS] =
3370              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3371              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3372              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3373              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3374              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3375         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3376              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3377         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3378              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3379              VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
3380         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3381              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3382              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3383              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3384              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3385              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3386              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3387              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3388              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3389              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3390              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3391              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3392         .features[FEAT_VMX_SECONDARY_CTLS] =
3393              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3394              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3395              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3396              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3397              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3398              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3399              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3400         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3401         .xlevel = 0x80000008,
3402         .model_id = "Intel Core Processor (Icelake)",
3403         .versions = (X86CPUVersionDefinition[]) {
3404             {
3405                 .version = 1,
3406                 .note = "deprecated"
3407             },
3408             {
3409                 .version = 2,
3410                 .note = "no TSX, deprecated",
3411                 .alias = "Icelake-Client-noTSX",
3412                 .props = (PropValue[]) {
3413                     { "hle", "off" },
3414                     { "rtm", "off" },
3415                     { /* end of list */ }
3416                 },
3417             },
3418             { /* end of list */ }
3419         },
3420         .deprecation_note = "use Icelake-Server instead"
3421     },
3422     {
3423         .name = "Icelake-Server",
3424         .level = 0xd,
3425         .vendor = CPUID_VENDOR_INTEL,
3426         .family = 6,
3427         .model = 134,
3428         .stepping = 0,
3429         .features[FEAT_1_EDX] =
3430             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3431             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3432             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3433             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3434             CPUID_DE | CPUID_FP87,
3435         .features[FEAT_1_ECX] =
3436             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3437             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3438             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3439             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3440             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3441             CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3442         .features[FEAT_8000_0001_EDX] =
3443             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3444             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3445         .features[FEAT_8000_0001_ECX] =
3446             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3447         .features[FEAT_8000_0008_EBX] =
3448             CPUID_8000_0008_EBX_WBNOINVD,
3449         .features[FEAT_7_0_EBX] =
3450             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
3451             CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
3452             CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
3453             CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
3454             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
3455             CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
3456             CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
3457             CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
3458         .features[FEAT_7_0_ECX] =
3459             CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
3460             CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
3461             CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
3462             CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
3463             CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57,
3464         .features[FEAT_7_0_EDX] =
3465             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3466         /* Missing: XSAVES (not supported by some Linux versions,
3467                 * including v4.1 to v4.12).
3468                 * KVM doesn't yet expose any XSAVES state save component,
3469                 * and the only one defined in Skylake (processor tracing)
3470                 * probably will block migration anyway.
3471                 */
3472         .features[FEAT_XSAVE] =
3473             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3474             CPUID_XSAVE_XGETBV1,
3475         .features[FEAT_6_EAX] =
3476             CPUID_6_EAX_ARAT,
3477         /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
3478         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3479              MSR_VMX_BASIC_TRUE_CTLS,
3480         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3481              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3482              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3483         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3484              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3485              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3486              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3487              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3488              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3489              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3490         .features[FEAT_VMX_EXIT_CTLS] =
3491              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3492              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3493              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3494              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3495              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3496         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3497              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3498         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3499              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3500              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3501         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3502              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3503              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3504              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3505              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3506              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3507              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3508              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3509              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3510              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3511              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3512              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3513         .features[FEAT_VMX_SECONDARY_CTLS] =
3514              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3515              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3516              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3517              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3518              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3519              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3520              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3521              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3522              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
3523         .xlevel = 0x80000008,
3524         .model_id = "Intel Xeon Processor (Icelake)",
3525         .versions = (X86CPUVersionDefinition[]) {
3526             { .version = 1 },
3527             {
3528                 .version = 2,
3529                 .note = "no TSX",
3530                 .alias = "Icelake-Server-noTSX",
3531                 .props = (PropValue[]) {
3532                     { "hle", "off" },
3533                     { "rtm", "off" },
3534                     { /* end of list */ }
3535                 },
3536             },
3537             {
3538                 .version = 3,
3539                 .props = (PropValue[]) {
3540                     { "arch-capabilities", "on" },
3541                     { "rdctl-no", "on" },
3542                     { "ibrs-all", "on" },
3543                     { "skip-l1dfl-vmentry", "on" },
3544                     { "mds-no", "on" },
3545                     { "pschange-mc-no", "on" },
3546                     { "taa-no", "on" },
3547                     { /* end of list */ }
3548                 },
3549             },
3550             {
3551                 .version = 4,
3552                 .props = (PropValue[]) {
3553                     { "sha-ni", "on" },
3554                     { "avx512ifma", "on" },
3555                     { "rdpid", "on" },
3556                     { "fsrm", "on" },
3557                     { "vmx-rdseed-exit", "on" },
3558                     { "vmx-pml", "on" },
3559                     { "vmx-eptp-switching", "on" },
3560                     { "model", "106" },
3561                     { /* end of list */ }
3562                 },
3563             },
3564             { /* end of list */ }
3565         }
3566     },
3567     {
3568         .name = "Denverton",
3569         .level = 21,
3570         .vendor = CPUID_VENDOR_INTEL,
3571         .family = 6,
3572         .model = 95,
3573         .stepping = 1,
3574         .features[FEAT_1_EDX] =
3575             CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
3576             CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
3577             CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3578             CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
3579             CPUID_SSE | CPUID_SSE2,
3580         .features[FEAT_1_ECX] =
3581             CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3582             CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | CPUID_EXT_SSE41 |
3583             CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3584             CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER |
3585             CPUID_EXT_AES | CPUID_EXT_XSAVE | CPUID_EXT_RDRAND,
3586         .features[FEAT_8000_0001_EDX] =
3587             CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
3588             CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
3589         .features[FEAT_8000_0001_ECX] =
3590             CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3591         .features[FEAT_7_0_EBX] =
3592             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_ERMS |
3593             CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_SMAP |
3594             CPUID_7_0_EBX_CLFLUSHOPT | CPUID_7_0_EBX_SHA_NI,
3595         .features[FEAT_7_0_EDX] =
3596             CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_ARCH_CAPABILITIES |
3597             CPUID_7_0_EDX_SPEC_CTRL_SSBD,
3598         /*
3599          * Missing: XSAVES (not supported by some Linux versions,
3600          * including v4.1 to v4.12).
3601          * KVM doesn't yet expose any XSAVES state save component,
3602          * and the only one defined in Skylake (processor tracing)
3603          * probably will block migration anyway.
3604          */
3605         .features[FEAT_XSAVE] =
3606             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | CPUID_XSAVE_XGETBV1,
3607         .features[FEAT_6_EAX] =
3608             CPUID_6_EAX_ARAT,
3609         .features[FEAT_ARCH_CAPABILITIES] =
3610             MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY,
3611         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3612              MSR_VMX_BASIC_TRUE_CTLS,
3613         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3614              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3615              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3616         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3617              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3618              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3619              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3620              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3621              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3622              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3623         .features[FEAT_VMX_EXIT_CTLS] =
3624              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3625              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3626              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3627              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3628              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3629         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3630              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3631         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3632              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3633              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3634         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3635              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3636              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3637              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3638              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3639              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3640              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3641              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3642              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3643              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3644              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3645              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3646         .features[FEAT_VMX_SECONDARY_CTLS] =
3647              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3648              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3649              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3650              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3651              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3652              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3653              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3654              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3655              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3656              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3657         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3658         .xlevel = 0x80000008,
3659         .model_id = "Intel Atom Processor (Denverton)",
3660         .versions = (X86CPUVersionDefinition[]) {
3661             { .version = 1 },
3662             {
3663                 .version = 2,
3664                 .note = "no MPX, no MONITOR",
3665                 .props = (PropValue[]) {
3666                     { "monitor", "off" },
3667                     { "mpx", "off" },
3668                     { /* end of list */ },
3669                 },
3670             },
3671             { /* end of list */ },
3672         },
3673     },
3674     {
3675         .name = "Snowridge",
3676         .level = 27,
3677         .vendor = CPUID_VENDOR_INTEL,
3678         .family = 6,
3679         .model = 134,
3680         .stepping = 1,
3681         .features[FEAT_1_EDX] =
3682             /* missing: CPUID_PN CPUID_IA64 */
3683             /* missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
3684             CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE |
3685             CPUID_TSC | CPUID_MSR | CPUID_PAE | CPUID_MCE |
3686             CPUID_CX8 | CPUID_APIC | CPUID_SEP |
3687             CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
3688             CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH |
3689             CPUID_MMX |
3690             CPUID_FXSR | CPUID_SSE | CPUID_SSE2,
3691         .features[FEAT_1_ECX] =
3692             CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_MONITOR |
3693             CPUID_EXT_SSSE3 |
3694             CPUID_EXT_CX16 |
3695             CPUID_EXT_SSE41 |
3696             CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
3697             CPUID_EXT_POPCNT |
3698             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES | CPUID_EXT_XSAVE |
3699             CPUID_EXT_RDRAND,
3700         .features[FEAT_8000_0001_EDX] =
3701             CPUID_EXT2_SYSCALL |
3702             CPUID_EXT2_NX |
3703             CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3704             CPUID_EXT2_LM,
3705         .features[FEAT_8000_0001_ECX] =
3706             CPUID_EXT3_LAHF_LM |
3707             CPUID_EXT3_3DNOWPREFETCH,
3708         .features[FEAT_7_0_EBX] =
3709             CPUID_7_0_EBX_FSGSBASE |
3710             CPUID_7_0_EBX_SMEP |
3711             CPUID_7_0_EBX_ERMS |
3712             CPUID_7_0_EBX_MPX |  /* missing bits 13, 15 */
3713             CPUID_7_0_EBX_RDSEED |
3714             CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
3715             CPUID_7_0_EBX_CLWB |
3716             CPUID_7_0_EBX_SHA_NI,
3717         .features[FEAT_7_0_ECX] =
3718             CPUID_7_0_ECX_UMIP |
3719             /* missing bit 5 */
3720             CPUID_7_0_ECX_GFNI |
3721             CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_CLDEMOTE |
3722             CPUID_7_0_ECX_MOVDIR64B,
3723         .features[FEAT_7_0_EDX] =
3724             CPUID_7_0_EDX_SPEC_CTRL |
3725             CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD |
3726             CPUID_7_0_EDX_CORE_CAPABILITY,
3727         .features[FEAT_CORE_CAPABILITY] =
3728             MSR_CORE_CAP_SPLIT_LOCK_DETECT,
3729         /*
3730          * Missing: XSAVES (not supported by some Linux versions,
3731          * including v4.1 to v4.12).
3732          * KVM doesn't yet expose any XSAVES state save component,
3733          * and the only one defined in Skylake (processor tracing)
3734          * probably will block migration anyway.
3735          */
3736         .features[FEAT_XSAVE] =
3737             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
3738             CPUID_XSAVE_XGETBV1,
3739         .features[FEAT_6_EAX] =
3740             CPUID_6_EAX_ARAT,
3741         .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
3742              MSR_VMX_BASIC_TRUE_CTLS,
3743         .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
3744              VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
3745              VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
3746         .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
3747              MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
3748              MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
3749              MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
3750              MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
3751              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
3752              MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
3753         .features[FEAT_VMX_EXIT_CTLS] =
3754              VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
3755              VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
3756              VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
3757              VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
3758              VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
3759         .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
3760              MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
3761         .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
3762              VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
3763              VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
3764         .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
3765              VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
3766              VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
3767              VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
3768              VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
3769              VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
3770              VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
3771              VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
3772              VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
3773              VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
3774              VMX_CPU_BASED_MONITOR_TRAP_FLAG |
3775              VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
3776         .features[FEAT_VMX_SECONDARY_CTLS] =
3777              VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3778              VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
3779              VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
3780              VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3781              VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
3782              VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
3783              VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3784              VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
3785              VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
3786              VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
3787         .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
3788         .xlevel = 0x80000008,
3789         .model_id = "Intel Atom Processor (SnowRidge)",
3790         .versions = (X86CPUVersionDefinition[]) {
3791             { .version = 1 },
3792             {
3793                 .version = 2,
3794                 .props = (PropValue[]) {
3795                     { "mpx", "off" },
3796                     { "model-id", "Intel Atom Processor (Snowridge, no MPX)" },
3797                     { /* end of list */ },
3798                 },
3799             },
3800             { /* end of list */ },
3801         },
3802     },
3803     {
3804         .name = "KnightsMill",
3805         .level = 0xd,
3806         .vendor = CPUID_VENDOR_INTEL,
3807         .family = 6,
3808         .model = 133,
3809         .stepping = 0,
3810         .features[FEAT_1_EDX] =
3811             CPUID_VME | CPUID_SS | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR |
3812             CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV |
3813             CPUID_MCA | CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC |
3814             CPUID_CX8 | CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC |
3815             CPUID_PSE | CPUID_DE | CPUID_FP87,
3816         .features[FEAT_1_ECX] =
3817             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3818             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
3819             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
3820             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
3821             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
3822             CPUID_EXT_F16C | CPUID_EXT_RDRAND,
3823         .features[FEAT_8000_0001_EDX] =
3824             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
3825             CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3826         .features[FEAT_8000_0001_ECX] =
3827             CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
3828         .features[FEAT_7_0_EBX] =
3829             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
3830             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS |
3831             CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_AVX512F |
3832             CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_AVX512PF |
3833             CPUID_7_0_EBX_AVX512ER,
3834         .features[FEAT_7_0_ECX] =
3835             CPUID_7_0_ECX_AVX512_VPOPCNTDQ,
3836         .features[FEAT_7_0_EDX] =
3837             CPUID_7_0_EDX_AVX512_4VNNIW | CPUID_7_0_EDX_AVX512_4FMAPS,
3838         .features[FEAT_XSAVE] =
3839             CPUID_XSAVE_XSAVEOPT,
3840         .features[FEAT_6_EAX] =
3841             CPUID_6_EAX_ARAT,
3842         .xlevel = 0x80000008,
3843         .model_id = "Intel Xeon Phi Processor (Knights Mill)",
3844     },
3845     {
3846         .name = "Opteron_G1",
3847         .level = 5,
3848         .vendor = CPUID_VENDOR_AMD,
3849         .family = 15,
3850         .model = 6,
3851         .stepping = 1,
3852         .features[FEAT_1_EDX] =
3853             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3854             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3855             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3856             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3857             CPUID_DE | CPUID_FP87,
3858         .features[FEAT_1_ECX] =
3859             CPUID_EXT_SSE3,
3860         .features[FEAT_8000_0001_EDX] =
3861             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3862         .xlevel = 0x80000008,
3863         .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
3864     },
3865     {
3866         .name = "Opteron_G2",
3867         .level = 5,
3868         .vendor = CPUID_VENDOR_AMD,
3869         .family = 15,
3870         .model = 6,
3871         .stepping = 1,
3872         .features[FEAT_1_EDX] =
3873             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3874             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3875             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3876             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3877             CPUID_DE | CPUID_FP87,
3878         .features[FEAT_1_ECX] =
3879             CPUID_EXT_CX16 | CPUID_EXT_SSE3,
3880         .features[FEAT_8000_0001_EDX] =
3881             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
3882         .features[FEAT_8000_0001_ECX] =
3883             CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3884         .xlevel = 0x80000008,
3885         .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
3886     },
3887     {
3888         .name = "Opteron_G3",
3889         .level = 5,
3890         .vendor = CPUID_VENDOR_AMD,
3891         .family = 16,
3892         .model = 2,
3893         .stepping = 3,
3894         .features[FEAT_1_EDX] =
3895             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3896             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3897             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3898             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3899             CPUID_DE | CPUID_FP87,
3900         .features[FEAT_1_ECX] =
3901             CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
3902             CPUID_EXT_SSE3,
3903         .features[FEAT_8000_0001_EDX] =
3904             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL |
3905             CPUID_EXT2_RDTSCP,
3906         .features[FEAT_8000_0001_ECX] =
3907             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
3908             CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
3909         .xlevel = 0x80000008,
3910         .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
3911     },
3912     {
3913         .name = "Opteron_G4",
3914         .level = 0xd,
3915         .vendor = CPUID_VENDOR_AMD,
3916         .family = 21,
3917         .model = 1,
3918         .stepping = 2,
3919         .features[FEAT_1_EDX] =
3920             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3921             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3922             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3923             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3924             CPUID_DE | CPUID_FP87,
3925         .features[FEAT_1_ECX] =
3926             CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
3927             CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3928             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
3929             CPUID_EXT_SSE3,
3930         .features[FEAT_8000_0001_EDX] =
3931             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3932             CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3933         .features[FEAT_8000_0001_ECX] =
3934             CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3935             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3936             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3937             CPUID_EXT3_LAHF_LM,
3938         .features[FEAT_SVM] =
3939             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3940         /* no xsaveopt! */
3941         .xlevel = 0x8000001A,
3942         .model_id = "AMD Opteron 62xx class CPU",
3943     },
3944     {
3945         .name = "Opteron_G5",
3946         .level = 0xd,
3947         .vendor = CPUID_VENDOR_AMD,
3948         .family = 21,
3949         .model = 2,
3950         .stepping = 0,
3951         .features[FEAT_1_EDX] =
3952             CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
3953             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
3954             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
3955             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
3956             CPUID_DE | CPUID_FP87,
3957         .features[FEAT_1_ECX] =
3958             CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
3959             CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
3960             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
3961             CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3962         .features[FEAT_8000_0001_EDX] =
3963             CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_NX |
3964             CPUID_EXT2_SYSCALL | CPUID_EXT2_RDTSCP,
3965         .features[FEAT_8000_0001_ECX] =
3966             CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
3967             CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
3968             CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
3969             CPUID_EXT3_LAHF_LM,
3970         .features[FEAT_SVM] =
3971             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
3972         /* no xsaveopt! */
3973         .xlevel = 0x8000001A,
3974         .model_id = "AMD Opteron 63xx class CPU",
3975     },
3976     {
3977         .name = "EPYC",
3978         .level = 0xd,
3979         .vendor = CPUID_VENDOR_AMD,
3980         .family = 23,
3981         .model = 1,
3982         .stepping = 2,
3983         .features[FEAT_1_EDX] =
3984             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
3985             CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
3986             CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
3987             CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
3988             CPUID_VME | CPUID_FP87,
3989         .features[FEAT_1_ECX] =
3990             CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
3991             CPUID_EXT_XSAVE | CPUID_EXT_AES |  CPUID_EXT_POPCNT |
3992             CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
3993             CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
3994             CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
3995         .features[FEAT_8000_0001_EDX] =
3996             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
3997             CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
3998             CPUID_EXT2_SYSCALL,
3999         .features[FEAT_8000_0001_ECX] =
4000             CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4001             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4002             CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4003             CPUID_EXT3_TOPOEXT,
4004         .features[FEAT_7_0_EBX] =
4005             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4006             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4007             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4008             CPUID_7_0_EBX_SHA_NI,
4009         .features[FEAT_XSAVE] =
4010             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4011             CPUID_XSAVE_XGETBV1,
4012         .features[FEAT_6_EAX] =
4013             CPUID_6_EAX_ARAT,
4014         .features[FEAT_SVM] =
4015             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4016         .xlevel = 0x8000001E,
4017         .model_id = "AMD EPYC Processor",
4018         .cache_info = &epyc_cache_info,
4019         .versions = (X86CPUVersionDefinition[]) {
4020             { .version = 1 },
4021             {
4022                 .version = 2,
4023                 .alias = "EPYC-IBPB",
4024                 .props = (PropValue[]) {
4025                     { "ibpb", "on" },
4026                     { "model-id",
4027                       "AMD EPYC Processor (with IBPB)" },
4028                     { /* end of list */ }
4029                 }
4030             },
4031             {
4032                 .version = 3,
4033                 .props = (PropValue[]) {
4034                     { "ibpb", "on" },
4035                     { "perfctr-core", "on" },
4036                     { "clzero", "on" },
4037                     { "xsaveerptr", "on" },
4038                     { "xsaves", "on" },
4039                     { "model-id",
4040                       "AMD EPYC Processor" },
4041                     { /* end of list */ }
4042                 }
4043             },
4044             { /* end of list */ }
4045         }
4046     },
4047     {
4048         .name = "Dhyana",
4049         .level = 0xd,
4050         .vendor = CPUID_VENDOR_HYGON,
4051         .family = 24,
4052         .model = 0,
4053         .stepping = 1,
4054         .features[FEAT_1_EDX] =
4055             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4056             CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4057             CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4058             CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4059             CPUID_VME | CPUID_FP87,
4060         .features[FEAT_1_ECX] =
4061             CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4062             CPUID_EXT_XSAVE | CPUID_EXT_POPCNT |
4063             CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4064             CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4065             CPUID_EXT_MONITOR | CPUID_EXT_SSE3,
4066         .features[FEAT_8000_0001_EDX] =
4067             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4068             CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4069             CPUID_EXT2_SYSCALL,
4070         .features[FEAT_8000_0001_ECX] =
4071             CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4072             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4073             CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4074             CPUID_EXT3_TOPOEXT,
4075         .features[FEAT_8000_0008_EBX] =
4076             CPUID_8000_0008_EBX_IBPB,
4077         .features[FEAT_7_0_EBX] =
4078             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4079             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4080             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT,
4081         /*
4082          * Missing: XSAVES (not supported by some Linux versions,
4083          * including v4.1 to v4.12).
4084          * KVM doesn't yet expose any XSAVES state save component.
4085          */
4086         .features[FEAT_XSAVE] =
4087             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4088             CPUID_XSAVE_XGETBV1,
4089         .features[FEAT_6_EAX] =
4090             CPUID_6_EAX_ARAT,
4091         .features[FEAT_SVM] =
4092             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4093         .xlevel = 0x8000001E,
4094         .model_id = "Hygon Dhyana Processor",
4095         .cache_info = &epyc_cache_info,
4096     },
4097     {
4098         .name = "EPYC-Rome",
4099         .level = 0xd,
4100         .vendor = CPUID_VENDOR_AMD,
4101         .family = 23,
4102         .model = 49,
4103         .stepping = 0,
4104         .features[FEAT_1_EDX] =
4105             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4106             CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4107             CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4108             CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4109             CPUID_VME | CPUID_FP87,
4110         .features[FEAT_1_ECX] =
4111             CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4112             CPUID_EXT_XSAVE | CPUID_EXT_AES |  CPUID_EXT_POPCNT |
4113             CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4114             CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4115             CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
4116         .features[FEAT_8000_0001_EDX] =
4117             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4118             CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4119             CPUID_EXT2_SYSCALL,
4120         .features[FEAT_8000_0001_ECX] =
4121             CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4122             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4123             CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4124             CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4125         .features[FEAT_8000_0008_EBX] =
4126             CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4127             CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4128             CPUID_8000_0008_EBX_STIBP,
4129         .features[FEAT_7_0_EBX] =
4130             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4131             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4132             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4133             CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
4134         .features[FEAT_7_0_ECX] =
4135             CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
4136         .features[FEAT_XSAVE] =
4137             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4138             CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4139         .features[FEAT_6_EAX] =
4140             CPUID_6_EAX_ARAT,
4141         .features[FEAT_SVM] =
4142             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
4143         .xlevel = 0x8000001E,
4144         .model_id = "AMD EPYC-Rome Processor",
4145         .cache_info = &epyc_rome_cache_info,
4146         .versions = (X86CPUVersionDefinition[]) {
4147             { .version = 1 },
4148             {
4149                 .version = 2,
4150                 .props = (PropValue[]) {
4151                     { "ibrs", "on" },
4152                     { "amd-ssbd", "on" },
4153                     { /* end of list */ }
4154                 }
4155             },
4156             { /* end of list */ }
4157         }
4158     },
4159     {
4160         .name = "EPYC-Milan",
4161         .level = 0xd,
4162         .vendor = CPUID_VENDOR_AMD,
4163         .family = 25,
4164         .model = 1,
4165         .stepping = 1,
4166         .features[FEAT_1_EDX] =
4167             CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
4168             CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
4169             CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
4170             CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
4171             CPUID_VME | CPUID_FP87,
4172         .features[FEAT_1_ECX] =
4173             CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
4174             CPUID_EXT_XSAVE | CPUID_EXT_AES |  CPUID_EXT_POPCNT |
4175             CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
4176             CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
4177             CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
4178             CPUID_EXT_PCID,
4179         .features[FEAT_8000_0001_EDX] =
4180             CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
4181             CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
4182             CPUID_EXT2_SYSCALL,
4183         .features[FEAT_8000_0001_ECX] =
4184             CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
4185             CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
4186             CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
4187             CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
4188         .features[FEAT_8000_0008_EBX] =
4189             CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
4190             CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
4191             CPUID_8000_0008_EBX_IBRS | CPUID_8000_0008_EBX_STIBP |
4192             CPUID_8000_0008_EBX_AMD_SSBD,
4193         .features[FEAT_7_0_EBX] =
4194             CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
4195             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
4196             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
4197             CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_ERMS |
4198             CPUID_7_0_EBX_INVPCID,
4199         .features[FEAT_7_0_ECX] =
4200             CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_PKU,
4201         .features[FEAT_7_0_EDX] =
4202             CPUID_7_0_EDX_FSRM,
4203         .features[FEAT_XSAVE] =
4204             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
4205             CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
4206         .features[FEAT_6_EAX] =
4207             CPUID_6_EAX_ARAT,
4208         .features[FEAT_SVM] =
4209             CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE | CPUID_SVM_SVME_ADDR_CHK,
4210         .xlevel = 0x8000001E,
4211         .model_id = "AMD EPYC-Milan Processor",
4212         .cache_info = &epyc_milan_cache_info,
4213     },
4214 };
4215
4216 /*
4217  * We resolve CPU model aliases using -v1 when using "-machine
4218  * none", but this is just for compatibility while libvirt isn't
4219  * adapted to resolve CPU model versions before creating VMs.
4220  * See "Runnability guarantee of CPU models" at
4221  * docs/system/deprecated.rst.
4222  */
4223 X86CPUVersion default_cpu_version = 1;
4224
4225 void x86_cpu_set_default_version(X86CPUVersion version)
4226 {
4227     /* Translating CPU_VERSION_AUTO to CPU_VERSION_AUTO doesn't make sense */
4228     assert(version != CPU_VERSION_AUTO);
4229     default_cpu_version = version;
4230 }
4231
4232 static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
4233 {
4234     int v = 0;
4235     const X86CPUVersionDefinition *vdef =
4236         x86_cpu_def_get_versions(model->cpudef);
4237     while (vdef->version) {
4238         v = vdef->version;
4239         vdef++;
4240     }
4241     return v;
4242 }
4243
4244 /* Return the actual version being used for a specific CPU model */
4245 static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
4246 {
4247     X86CPUVersion v = model->version;
4248     if (v == CPU_VERSION_AUTO) {
4249         v = default_cpu_version;
4250     }
4251     if (v == CPU_VERSION_LATEST) {
4252         return x86_cpu_model_last_version(model);
4253     }
4254     return v;
4255 }
4256
4257 static Property max_x86_cpu_properties[] = {
4258     DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
4259     DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
4260     DEFINE_PROP_END_OF_LIST()
4261 };
4262
4263 static void max_x86_cpu_class_init(ObjectClass *oc, void *data)
4264 {
4265     DeviceClass *dc = DEVICE_CLASS(oc);
4266     X86CPUClass *xcc = X86_CPU_CLASS(oc);
4267
4268     xcc->ordering = 9;
4269
4270     xcc->model_description =
4271         "Enables all features supported by the accelerator in the current host";
4272
4273     device_class_set_props(dc, max_x86_cpu_properties);
4274 }
4275
4276 static void max_x86_cpu_initfn(Object *obj)
4277 {
4278     X86CPU *cpu = X86_CPU(obj);
4279
4280     /* We can't fill the features array here because we don't know yet if
4281      * "migratable" is true or false.
4282      */
4283     cpu->max_features = true;
4284     object_property_set_bool(OBJECT(cpu), "pmu", true, &error_abort);
4285
4286     /*
4287      * these defaults are used for TCG and all other accelerators
4288      * besides KVM and HVF, which overwrite these values
4289      */
4290     object_property_set_str(OBJECT(cpu), "vendor", CPUID_VENDOR_AMD,
4291                             &error_abort);
4292     object_property_set_int(OBJECT(cpu), "family", 6, &error_abort);
4293     object_property_set_int(OBJECT(cpu), "model", 6, &error_abort);
4294     object_property_set_int(OBJECT(cpu), "stepping", 3, &error_abort);
4295     object_property_set_str(OBJECT(cpu), "model-id",
4296                             "QEMU TCG CPU version " QEMU_HW_VERSION,
4297                             &error_abort);
4298 }
4299
4300 static const TypeInfo max_x86_cpu_type_info = {
4301     .name = X86_CPU_TYPE_NAME("max"),
4302     .parent = TYPE_X86_CPU,
4303     .instance_init = max_x86_cpu_initfn,
4304     .class_init = max_x86_cpu_class_init,
4305 };
4306
4307 static char *feature_word_description(FeatureWordInfo *f, uint32_t bit)
4308 {
4309     assert(f->type == CPUID_FEATURE_WORD || f->type == MSR_FEATURE_WORD);
4310
4311     switch (f->type) {
4312     case CPUID_FEATURE_WORD:
4313         {
4314             const char *reg = get_register_name_32(f->cpuid.reg);
4315             assert(reg);
4316             return g_strdup_printf("CPUID.%02XH:%s",
4317                                    f->cpuid.eax, reg);
4318         }
4319     case MSR_FEATURE_WORD:
4320         return g_strdup_printf("MSR(%02XH)",
4321                                f->msr.index);
4322     }
4323
4324     return NULL;
4325 }
4326
4327 static bool x86_cpu_have_filtered_features(X86CPU *cpu)
4328 {
4329     FeatureWord w;
4330
4331     for (w = 0; w < FEATURE_WORDS; w++) {
4332         if (cpu->filtered_features[w]) {
4333             return true;
4334         }
4335     }
4336
4337     return false;
4338 }
4339
4340 static void mark_unavailable_features(X86CPU *cpu, FeatureWord w, uint64_t mask,
4341                                       const char *verbose_prefix)
4342 {
4343     CPUX86State *env = &cpu->env;
4344     FeatureWordInfo *f = &feature_word_info[w];
4345     int i;
4346
4347     if (!cpu->force_features) {
4348         env->features[w] &= ~mask;
4349     }
4350     cpu->filtered_features[w] |= mask;
4351
4352     if (!verbose_prefix) {
4353         return;
4354     }
4355
4356     for (i = 0; i < 64; ++i) {
4357         if ((1ULL << i) & mask) {
4358             g_autofree char *feat_word_str = feature_word_description(f, i);
4359             warn_report("%s: %s%s%s [bit %d]",
4360                         verbose_prefix,
4361                         feat_word_str,
4362                         f->feat_names[i] ? "." : "",
4363                         f->feat_names[i] ? f->feat_names[i] : "", i);
4364         }
4365     }
4366 }
4367
4368 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
4369                                          const char *name, void *opaque,
4370                                          Error **errp)
4371 {
4372     X86CPU *cpu = X86_CPU(obj);
4373     CPUX86State *env = &cpu->env;
4374     int64_t value;
4375
4376     value = (env->cpuid_version >> 8) & 0xf;
4377     if (value == 0xf) {
4378         value += (env->cpuid_version >> 20) & 0xff;
4379     }
4380     visit_type_int(v, name, &value, errp);
4381 }
4382
4383 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
4384                                          const char *name, void *opaque,
4385                                          Error **errp)
4386 {
4387     X86CPU *cpu = X86_CPU(obj);
4388     CPUX86State *env = &cpu->env;
4389     const int64_t min = 0;
4390     const int64_t max = 0xff + 0xf;
4391     int64_t value;
4392
4393     if (!visit_type_int(v, name, &value, errp)) {
4394         return;
4395     }
4396     if (value < min || value > max) {
4397         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4398                    name ? name : "null", value, min, max);
4399         return;
4400     }
4401
4402     env->cpuid_version &= ~0xff00f00;
4403     if (value > 0x0f) {
4404         env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
4405     } else {
4406         env->cpuid_version |= value << 8;
4407     }
4408 }
4409
4410 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
4411                                         const char *name, void *opaque,
4412                                         Error **errp)
4413 {
4414     X86CPU *cpu = X86_CPU(obj);
4415     CPUX86State *env = &cpu->env;
4416     int64_t value;
4417
4418     value = (env->cpuid_version >> 4) & 0xf;
4419     value |= ((env->cpuid_version >> 16) & 0xf) << 4;
4420     visit_type_int(v, name, &value, errp);
4421 }
4422
4423 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
4424                                         const char *name, void *opaque,
4425                                         Error **errp)
4426 {
4427     X86CPU *cpu = X86_CPU(obj);
4428     CPUX86State *env = &cpu->env;
4429     const int64_t min = 0;
4430     const int64_t max = 0xff;
4431     int64_t value;
4432
4433     if (!visit_type_int(v, name, &value, errp)) {
4434         return;
4435     }
4436     if (value < min || value > max) {
4437         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4438                    name ? name : "null", value, min, max);
4439         return;
4440     }
4441
4442     env->cpuid_version &= ~0xf00f0;
4443     env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
4444 }
4445
4446 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
4447                                            const char *name, void *opaque,
4448                                            Error **errp)
4449 {
4450     X86CPU *cpu = X86_CPU(obj);
4451     CPUX86State *env = &cpu->env;
4452     int64_t value;
4453
4454     value = env->cpuid_version & 0xf;
4455     visit_type_int(v, name, &value, errp);
4456 }
4457
4458 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
4459                                            const char *name, void *opaque,
4460                                            Error **errp)
4461 {
4462     X86CPU *cpu = X86_CPU(obj);
4463     CPUX86State *env = &cpu->env;
4464     const int64_t min = 0;
4465     const int64_t max = 0xf;
4466     int64_t value;
4467
4468     if (!visit_type_int(v, name, &value, errp)) {
4469         return;
4470     }
4471     if (value < min || value > max) {
4472         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4473                    name ? name : "null", value, min, max);
4474         return;
4475     }
4476
4477     env->cpuid_version &= ~0xf;
4478     env->cpuid_version |= value & 0xf;
4479 }
4480
4481 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
4482 {
4483     X86CPU *cpu = X86_CPU(obj);
4484     CPUX86State *env = &cpu->env;
4485     char *value;
4486
4487     value = g_malloc(CPUID_VENDOR_SZ + 1);
4488     x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
4489                              env->cpuid_vendor3);
4490     return value;
4491 }
4492
4493 static void x86_cpuid_set_vendor(Object *obj, const char *value,
4494                                  Error **errp)
4495 {
4496     X86CPU *cpu = X86_CPU(obj);
4497     CPUX86State *env = &cpu->env;
4498     int i;
4499
4500     if (strlen(value) != CPUID_VENDOR_SZ) {
4501         error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
4502         return;
4503     }
4504
4505     env->cpuid_vendor1 = 0;
4506     env->cpuid_vendor2 = 0;
4507     env->cpuid_vendor3 = 0;
4508     for (i = 0; i < 4; i++) {
4509         env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);
4510         env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
4511         env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
4512     }
4513 }
4514
4515 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
4516 {
4517     X86CPU *cpu = X86_CPU(obj);
4518     CPUX86State *env = &cpu->env;
4519     char *value;
4520     int i;
4521
4522     value = g_malloc(48 + 1);
4523     for (i = 0; i < 48; i++) {
4524         value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
4525     }
4526     value[48] = '\0';
4527     return value;
4528 }
4529
4530 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
4531                                    Error **errp)
4532 {
4533     X86CPU *cpu = X86_CPU(obj);
4534     CPUX86State *env = &cpu->env;
4535     int c, len, i;
4536
4537     if (model_id == NULL) {
4538         model_id = "";
4539     }
4540     len = strlen(model_id);
4541     memset(env->cpuid_model, 0, 48);
4542     for (i = 0; i < 48; i++) {
4543         if (i >= len) {
4544             c = '\0';
4545         } else {
4546             c = (uint8_t)model_id[i];
4547         }
4548         env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
4549     }
4550 }
4551
4552 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
4553                                    void *opaque, Error **errp)
4554 {
4555     X86CPU *cpu = X86_CPU(obj);
4556     int64_t value;
4557
4558     value = cpu->env.tsc_khz * 1000;
4559     visit_type_int(v, name, &value, errp);
4560 }
4561
4562 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
4563                                    void *opaque, Error **errp)
4564 {
4565     X86CPU *cpu = X86_CPU(obj);
4566     const int64_t min = 0;
4567     const int64_t max = INT64_MAX;
4568     int64_t value;
4569
4570     if (!visit_type_int(v, name, &value, errp)) {
4571         return;
4572     }
4573     if (value < min || value > max) {
4574         error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
4575                    name ? name : "null", value, min, max);
4576         return;
4577     }
4578
4579     cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
4580 }
4581
4582 /* Generic getter for "feature-words" and "filtered-features" properties */
4583 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
4584                                       const char *name, void *opaque,
4585                                       Error **errp)
4586 {
4587     uint64_t *array = (uint64_t *)opaque;
4588     FeatureWord w;
4589     X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
4590     X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
4591     X86CPUFeatureWordInfoList *list = NULL;
4592
4593     for (w = 0; w < FEATURE_WORDS; w++) {
4594         FeatureWordInfo *wi = &feature_word_info[w];
4595         /*
4596                 * We didn't have MSR features when "feature-words" was
4597                 *  introduced. Therefore skipped other type entries.
4598                 */
4599         if (wi->type != CPUID_FEATURE_WORD) {
4600             continue;
4601         }
4602         X86CPUFeatureWordInfo *qwi = &word_infos[w];
4603         qwi->cpuid_input_eax = wi->cpuid.eax;
4604         qwi->has_cpuid_input_ecx = wi->cpuid.needs_ecx;
4605         qwi->cpuid_input_ecx = wi->cpuid.ecx;
4606         qwi->cpuid_register = x86_reg_info_32[wi->cpuid.reg].qapi_enum;
4607         qwi->features = array[w];
4608
4609         /* List will be in reverse order, but order shouldn't matter */
4610         list_entries[w].next = list;
4611         list_entries[w].value = &word_infos[w];
4612         list = &list_entries[w];
4613     }
4614
4615     visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
4616 }
4617
4618 /* Convert all '_' in a feature string option name to '-', to make feature
4619  * name conform to QOM property naming rule, which uses '-' instead of '_'.
4620  */
4621 static inline void feat2prop(char *s)
4622 {
4623     while ((s = strchr(s, '_'))) {
4624         *s = '-';
4625     }
4626 }
4627
4628 /* Return the feature property name for a feature flag bit */
4629 static const char *x86_cpu_feature_name(FeatureWord w, int bitnr)
4630 {
4631     const char *name;
4632     /* XSAVE components are automatically enabled by other features,
4633      * so return the original feature name instead
4634      */
4635     if (w == FEAT_XSAVE_COMP_LO || w == FEAT_XSAVE_COMP_HI) {
4636         int comp = (w == FEAT_XSAVE_COMP_HI) ? bitnr + 32 : bitnr;
4637
4638         if (comp < ARRAY_SIZE(x86_ext_save_areas) &&
4639             x86_ext_save_areas[comp].bits) {
4640             w = x86_ext_save_areas[comp].feature;
4641             bitnr = ctz32(x86_ext_save_areas[comp].bits);
4642         }
4643     }
4644
4645     assert(bitnr < 64);
4646     assert(w < FEATURE_WORDS);
4647     name = feature_word_info[w].feat_names[bitnr];
4648     assert(bitnr < 32 || !(name && feature_word_info[w].type == CPUID_FEATURE_WORD));
4649     return name;
4650 }
4651
4652 /* Compatibily hack to maintain legacy +-feat semantic,
4653  * where +-feat overwrites any feature set by
4654  * feat=on|feat even if the later is parsed after +-feat
4655  * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
4656  */
4657 static GList *plus_features, *minus_features;
4658
4659 static gint compare_string(gconstpointer a, gconstpointer b)
4660 {
4661     return g_strcmp0(a, b);
4662 }
4663
4664 /* Parse "+feature,-feature,feature=foo" CPU feature string
4665  */
4666 static void x86_cpu_parse_featurestr(const char *typename, char *features,
4667                                      Error **errp)
4668 {
4669     char *featurestr; /* Single 'key=value" string being parsed */
4670     static bool cpu_globals_initialized;
4671     bool ambiguous = false;
4672
4673     if (cpu_globals_initialized) {
4674         return;
4675     }
4676     cpu_globals_initialized = true;
4677
4678     if (!features) {
4679         return;
4680     }
4681
4682     for (featurestr = strtok(features, ",");
4683          featurestr;
4684          featurestr = strtok(NULL, ",")) {
4685         const char *name;
4686         const char *val = NULL;
4687         char *eq = NULL;
4688         char num[32];
4689         GlobalProperty *prop;
4690
4691         /* Compatibility syntax: */
4692         if (featurestr[0] == '+') {
4693             plus_features = g_list_append(plus_features,
4694                                           g_strdup(featurestr + 1));
4695             continue;
4696         } else if (featurestr[0] == '-') {
4697             minus_features = g_list_append(minus_features,
4698                                            g_strdup(featurestr + 1));
4699             continue;
4700         }
4701
4702         eq = strchr(featurestr, '=');
4703         if (eq) {
4704             *eq++ = 0;
4705             val = eq;
4706         } else {
4707             val = "on";
4708         }
4709
4710         feat2prop(featurestr);
4711         name = featurestr;
4712
4713         if (g_list_find_custom(plus_features, name, compare_string)) {
4714             warn_report("Ambiguous CPU model string. "
4715                         "Don't mix both \"+%s\" and \"%s=%s\"",
4716                         name, name, val);
4717             ambiguous = true;
4718         }
4719         if (g_list_find_custom(minus_features, name, compare_string)) {
4720             warn_report("Ambiguous CPU model string. "
4721                         "Don't mix both \"-%s\" and \"%s=%s\"",
4722                         name, name, val);
4723             ambiguous = true;
4724         }
4725
4726         /* Special case: */
4727         if (!strcmp(name, "tsc-freq")) {
4728             int ret;
4729             uint64_t tsc_freq;
4730
4731             ret = qemu_strtosz_metric(val, NULL, &tsc_freq);
4732             if (ret < 0 || tsc_freq > INT64_MAX) {
4733                 error_setg(errp, "bad numerical value %s", val);
4734                 return;
4735             }
4736             snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
4737             val = num;
4738             name = "tsc-frequency";
4739         }
4740
4741         prop = g_new0(typeof(*prop), 1);
4742         prop->driver = typename;
4743         prop->property = g_strdup(name);
4744         prop->value = g_strdup(val);
4745         qdev_prop_register_global(prop);
4746     }
4747
4748     if (ambiguous) {
4749         warn_report("Compatibility of ambiguous CPU model "
4750                     "strings won't be kept on future QEMU versions");
4751     }
4752 }
4753
4754 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp);
4755 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose);
4756
4757 /* Build a list with the name of all features on a feature word array */
4758 static void x86_cpu_list_feature_names(FeatureWordArray features,
4759                                        strList **list)
4760 {
4761     strList **tail = list;
4762     FeatureWord w;
4763
4764     for (w = 0; w < FEATURE_WORDS; w++) {
4765         uint64_t filtered = features[w];
4766         int i;
4767         for (i = 0; i < 64; i++) {
4768             if (filtered & (1ULL << i)) {
4769                 QAPI_LIST_APPEND(tail, g_strdup(x86_cpu_feature_name(w, i)));
4770             }
4771         }
4772     }
4773 }
4774
4775 static void x86_cpu_get_unavailable_features(Object *obj, Visitor *v,
4776                                              const char *name, void *opaque,
4777                                              Error **errp)
4778 {
4779     X86CPU *xc = X86_CPU(obj);
4780     strList *result = NULL;
4781
4782     x86_cpu_list_feature_names(xc->filtered_features, &result);
4783     visit_type_strList(v, "unavailable-features", &result, errp);
4784 }
4785
4786 /* Check for missing features that may prevent the CPU class from
4787  * running using the current machine and accelerator.
4788  */
4789 static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
4790                                                  strList **list)
4791 {
4792     strList **tail = list;
4793     X86CPU *xc;
4794     Error *err = NULL;
4795
4796     if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
4797         QAPI_LIST_APPEND(tail, g_strdup("kvm"));
4798         return;
4799     }
4800
4801     xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
4802
4803     x86_cpu_expand_features(xc, &err);
4804     if (err) {
4805         /* Errors at x86_cpu_expand_features should never happen,
4806          * but in case it does, just report the model as not
4807          * runnable at all using the "type" property.
4808          */
4809         QAPI_LIST_APPEND(tail, g_strdup("type"));
4810         error_free(err);
4811     }
4812
4813     x86_cpu_filter_features(xc, false);
4814
4815     x86_cpu_list_feature_names(xc->filtered_features, tail);
4816
4817     object_unref(OBJECT(xc));
4818 }
4819
4820 /* Print all cpuid feature names in featureset
4821  */
4822 static void listflags(GList *features)
4823 {
4824     size_t len = 0;
4825     GList *tmp;
4826
4827     for (tmp = features; tmp; tmp = tmp->next) {
4828         const char *name = tmp->data;
4829         if ((len + strlen(name) + 1) >= 75) {
4830             qemu_printf("\n");
4831             len = 0;
4832         }
4833         qemu_printf("%s%s", len == 0 ? "  " : " ", name);
4834         len += strlen(name) + 1;
4835     }
4836     qemu_printf("\n");
4837 }
4838
4839 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
4840 static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
4841 {
4842     ObjectClass *class_a = (ObjectClass *)a;
4843     ObjectClass *class_b = (ObjectClass *)b;
4844     X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
4845     X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
4846     int ret;
4847
4848     if (cc_a->ordering != cc_b->ordering) {
4849         ret = cc_a->ordering - cc_b->ordering;
4850     } else {
4851         g_autofree char *name_a = x86_cpu_class_get_model_name(cc_a);
4852         g_autofree char *name_b = x86_cpu_class_get_model_name(cc_b);
4853         ret = strcmp(name_a, name_b);
4854     }
4855     return ret;
4856 }
4857
4858 static GSList *get_sorted_cpu_model_list(void)
4859 {
4860     GSList *list = object_class_get_list(TYPE_X86_CPU, false);
4861     list = g_slist_sort(list, x86_cpu_list_compare);
4862     return list;
4863 }
4864
4865 static char *x86_cpu_class_get_model_id(X86CPUClass *xc)
4866 {
4867     Object *obj = object_new_with_class(OBJECT_CLASS(xc));
4868     char *r = object_property_get_str(obj, "model-id", &error_abort);
4869     object_unref(obj);
4870     return r;
4871 }
4872
4873 static char *x86_cpu_class_get_alias_of(X86CPUClass *cc)
4874 {
4875     X86CPUVersion version;
4876
4877     if (!cc->model || !cc->model->is_alias) {
4878         return NULL;
4879     }
4880     version = x86_cpu_model_resolve_version(cc->model);
4881     if (version <= 0) {
4882         return NULL;
4883     }
4884     return x86_cpu_versioned_model_name(cc->model->cpudef, version);
4885 }
4886
4887 static void x86_cpu_list_entry(gpointer data, gpointer user_data)
4888 {
4889     ObjectClass *oc = data;
4890     X86CPUClass *cc = X86_CPU_CLASS(oc);
4891     g_autofree char *name = x86_cpu_class_get_model_name(cc);
4892     g_autofree char *desc = g_strdup(cc->model_description);
4893     g_autofree char *alias_of = x86_cpu_class_get_alias_of(cc);
4894     g_autofree char *model_id = x86_cpu_class_get_model_id(cc);
4895
4896     if (!desc && alias_of) {
4897         if (cc->model && cc->model->version == CPU_VERSION_AUTO) {
4898             desc = g_strdup("(alias configured by machine type)");
4899         } else {
4900             desc = g_strdup_printf("(alias of %s)", alias_of);
4901         }
4902     }
4903     if (!desc && cc->model && cc->model->note) {
4904         desc = g_strdup_printf("%s [%s]", model_id, cc->model->note);
4905     }
4906     if (!desc) {
4907         desc = g_strdup_printf("%s", model_id);
4908     }
4909
4910     qemu_printf("x86 %-20s  %-58s\n", name, desc);
4911 }
4912
4913 /* list available CPU models and flags */
4914 void x86_cpu_list(void)
4915 {
4916     int i, j;
4917     GSList *list;
4918     GList *names = NULL;
4919
4920     qemu_printf("Available CPUs:\n");
4921     list = get_sorted_cpu_model_list();
4922     g_slist_foreach(list, x86_cpu_list_entry, NULL);
4923     g_slist_free(list);
4924
4925     names = NULL;
4926     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
4927         FeatureWordInfo *fw = &feature_word_info[i];
4928         for (j = 0; j < 64; j++) {
4929             if (fw->feat_names[j]) {
4930                 names = g_list_append(names, (gpointer)fw->feat_names[j]);
4931             }
4932         }
4933     }
4934
4935     names = g_list_sort(names, (GCompareFunc)strcmp);
4936
4937     qemu_printf("\nRecognized CPUID flags:\n");
4938     listflags(names);
4939     qemu_printf("\n");
4940     g_list_free(names);
4941 }
4942
4943 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
4944 {
4945     ObjectClass *oc = data;
4946     X86CPUClass *cc = X86_CPU_CLASS(oc);
4947     CpuDefinitionInfoList **cpu_list = user_data;
4948     CpuDefinitionInfo *info;
4949
4950     info = g_malloc0(sizeof(*info));
4951     info->name = x86_cpu_class_get_model_name(cc);
4952     x86_cpu_class_check_missing_features(cc, &info->unavailable_features);
4953     info->has_unavailable_features = true;
4954     info->q_typename = g_strdup(object_class_get_name(oc));
4955     info->migration_safe = cc->migration_safe;
4956     info->has_migration_safe = true;
4957     info->q_static = cc->static_model;
4958     if (cc->model && cc->model->cpudef->deprecation_note) {
4959         info->deprecated = true;
4960     } else {
4961         info->deprecated = false;
4962     }
4963     /*
4964      * Old machine types won't report aliases, so that alias translation
4965      * doesn't break compatibility with previous QEMU versions.
4966      */
4967     if (default_cpu_version != CPU_VERSION_LEGACY) {
4968         info->alias_of = x86_cpu_class_get_alias_of(cc);
4969         info->has_alias_of = !!info->alias_of;
4970     }
4971
4972     QAPI_LIST_PREPEND(*cpu_list, info);
4973 }
4974
4975 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
4976 {
4977     CpuDefinitionInfoList *cpu_list = NULL;
4978     GSList *list = get_sorted_cpu_model_list();
4979     g_slist_foreach(list, x86_cpu_definition_entry, &cpu_list);
4980     g_slist_free(list);
4981     return cpu_list;
4982 }
4983
4984 static uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
4985                                                    bool migratable_only)
4986 {
4987     FeatureWordInfo *wi = &feature_word_info[w];
4988     uint64_t r = 0;
4989
4990     if (kvm_enabled()) {
4991         switch (wi->type) {
4992         case CPUID_FEATURE_WORD:
4993             r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid.eax,
4994                                                         wi->cpuid.ecx,
4995                                                         wi->cpuid.reg);
4996             break;
4997         case MSR_FEATURE_WORD:
4998             r = kvm_arch_get_supported_msr_feature(kvm_state,
4999                         wi->msr.index);
5000             break;
5001         }
5002     } else if (hvf_enabled()) {
5003         if (wi->type != CPUID_FEATURE_WORD) {
5004             return 0;
5005         }
5006         r = hvf_get_supported_cpuid(wi->cpuid.eax,
5007                                     wi->cpuid.ecx,
5008                                     wi->cpuid.reg);
5009     } else if (tcg_enabled()) {
5010         r = wi->tcg_features;
5011     } else {
5012         return ~0;
5013     }
5014 #ifndef TARGET_X86_64
5015     if (w == FEAT_8000_0001_EDX) {
5016         r &= ~CPUID_EXT2_LM;
5017     }
5018 #endif
5019     if (migratable_only) {
5020         r &= x86_cpu_get_migratable_flags(w);
5021     }
5022     return r;
5023 }
5024
5025 void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
5026 {
5027     PropValue *pv;
5028     for (pv = props; pv->prop; pv++) {
5029         if (!pv->value) {
5030             continue;
5031         }
5032         object_property_parse(OBJECT(cpu), pv->prop, pv->value,
5033                               &error_abort);
5034     }
5035 }
5036
5037 /* Apply properties for the CPU model version specified in model */
5038 static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
5039 {
5040     const X86CPUVersionDefinition *vdef;
5041     X86CPUVersion version = x86_cpu_model_resolve_version(model);
5042
5043     if (version == CPU_VERSION_LEGACY) {
5044         return;
5045     }
5046
5047     for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
5048         PropValue *p;
5049
5050         for (p = vdef->props; p && p->prop; p++) {
5051             object_property_parse(OBJECT(cpu), p->prop, p->value,
5052                                   &error_abort);
5053         }
5054
5055         if (vdef->version == version) {
5056             break;
5057         }
5058     }
5059
5060     /*
5061      * If we reached the end of the list, version number was invalid
5062      */
5063     assert(vdef->version == version);
5064 }
5065
5066 /* Load data from X86CPUDefinition into a X86CPU object
5067  */
5068 static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model)
5069 {
5070     X86CPUDefinition *def = model->cpudef;
5071     CPUX86State *env = &cpu->env;
5072     FeatureWord w;
5073
5074     /*NOTE: any property set by this function should be returned by
5075      * x86_cpu_static_props(), so static expansion of
5076      * query-cpu-model-expansion is always complete.
5077      */
5078
5079     /* CPU models only set _minimum_ values for level/xlevel: */
5080     object_property_set_uint(OBJECT(cpu), "min-level", def->level,
5081                              &error_abort);
5082     object_property_set_uint(OBJECT(cpu), "min-xlevel", def->xlevel,
5083                              &error_abort);
5084
5085     object_property_set_int(OBJECT(cpu), "family", def->family, &error_abort);
5086     object_property_set_int(OBJECT(cpu), "model", def->model, &error_abort);
5087     object_property_set_int(OBJECT(cpu), "stepping", def->stepping,
5088                             &error_abort);
5089     object_property_set_str(OBJECT(cpu), "model-id", def->model_id,
5090                             &error_abort);
5091     for (w = 0; w < FEATURE_WORDS; w++) {
5092         env->features[w] = def->features[w];
5093     }
5094
5095     /* legacy-cache defaults to 'off' if CPU model provides cache info */
5096     cpu->legacy_cache = !def->cache_info;
5097
5098     env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
5099
5100     /* sysenter isn't supported in compatibility mode on AMD,
5101      * syscall isn't supported in compatibility mode on Intel.
5102      * Normally we advertise the actual CPU vendor, but you can
5103      * override this using the 'vendor' property if you want to use
5104      * KVM's sysenter/syscall emulation in compatibility mode and
5105      * when doing cross vendor migration
5106      */
5107
5108     /*
5109      * vendor property is set here but then overloaded with the
5110      * host cpu vendor for KVM and HVF.
5111      */
5112     object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abort);
5113
5114     x86_cpu_apply_version_props(cpu, model);
5115
5116     /*
5117      * Properties in versioned CPU model are not user specified features.
5118      * We can simply clear env->user_features here since it will be filled later
5119      * in x86_cpu_expand_features() based on plus_features and minus_features.
5120      */
5121     memset(&env->user_features, 0, sizeof(env->user_features));
5122 }
5123
5124 #ifndef CONFIG_USER_ONLY
5125 /* Return a QDict containing keys for all properties that can be included
5126  * in static expansion of CPU models. All properties set by x86_cpu_load_model()
5127  * must be included in the dictionary.
5128  */
5129 static QDict *x86_cpu_static_props(void)
5130 {
5131     FeatureWord w;
5132     int i;
5133     static const char *props[] = {
5134         "min-level",
5135         "min-xlevel",
5136         "family",
5137         "model",
5138         "stepping",
5139         "model-id",
5140         "vendor",
5141         "lmce",
5142         NULL,
5143     };
5144     static QDict *d;
5145
5146     if (d) {
5147         return d;
5148     }
5149
5150     d = qdict_new();
5151     for (i = 0; props[i]; i++) {
5152         qdict_put_null(d, props[i]);
5153     }
5154
5155     for (w = 0; w < FEATURE_WORDS; w++) {
5156         FeatureWordInfo *fi = &feature_word_info[w];
5157         int bit;
5158         for (bit = 0; bit < 64; bit++) {
5159             if (!fi->feat_names[bit]) {
5160                 continue;
5161             }
5162             qdict_put_null(d, fi->feat_names[bit]);
5163         }
5164     }
5165
5166     return d;
5167 }
5168
5169 /* Add an entry to @props dict, with the value for property. */
5170 static void x86_cpu_expand_prop(X86CPU *cpu, QDict *props, const char *prop)
5171 {
5172     QObject *value = object_property_get_qobject(OBJECT(cpu), prop,
5173                                                  &error_abort);
5174
5175     qdict_put_obj(props, prop, value);
5176 }
5177
5178 /* Convert CPU model data from X86CPU object to a property dictionary
5179  * that can recreate exactly the same CPU model.
5180  */
5181 static void x86_cpu_to_dict(X86CPU *cpu, QDict *props)
5182 {
5183     QDict *sprops = x86_cpu_static_props();
5184     const QDictEntry *e;
5185
5186     for (e = qdict_first(sprops); e; e = qdict_next(sprops, e)) {
5187         const char *prop = qdict_entry_key(e);
5188         x86_cpu_expand_prop(cpu, props, prop);
5189     }
5190 }
5191
5192 /* Convert CPU model data from X86CPU object to a property dictionary
5193  * that can recreate exactly the same CPU model, including every
5194  * writeable QOM property.
5195  */
5196 static void x86_cpu_to_dict_full(X86CPU *cpu, QDict *props)
5197 {
5198     ObjectPropertyIterator iter;
5199     ObjectProperty *prop;
5200
5201     object_property_iter_init(&iter, OBJECT(cpu));
5202     while ((prop = object_property_iter_next(&iter))) {
5203         /* skip read-only or write-only properties */
5204         if (!prop->get || !prop->set) {
5205             continue;
5206         }
5207
5208         /* "hotplugged" is the only property that is configurable
5209          * on the command-line but will be set differently on CPUs
5210          * created using "-cpu ... -smp ..." and by CPUs created
5211          * on the fly by x86_cpu_from_model() for querying. Skip it.
5212          */
5213         if (!strcmp(prop->name, "hotplugged")) {
5214             continue;
5215         }
5216         x86_cpu_expand_prop(cpu, props, prop->name);
5217     }
5218 }
5219
5220 static void object_apply_props(Object *obj, QDict *props, Error **errp)
5221 {
5222     const QDictEntry *prop;
5223
5224     for (prop = qdict_first(props); prop; prop = qdict_next(props, prop)) {
5225         if (!object_property_set_qobject(obj, qdict_entry_key(prop),
5226                                          qdict_entry_value(prop), errp)) {
5227             break;
5228         }
5229     }
5230 }
5231
5232 /* Create X86CPU object according to model+props specification */
5233 static X86CPU *x86_cpu_from_model(const char *model, QDict *props, Error **errp)
5234 {
5235     X86CPU *xc = NULL;
5236     X86CPUClass *xcc;
5237     Error *err = NULL;
5238
5239     xcc = X86_CPU_CLASS(cpu_class_by_name(TYPE_X86_CPU, model));
5240     if (xcc == NULL) {
5241         error_setg(&err, "CPU model '%s' not found", model);
5242         goto out;
5243     }
5244
5245     xc = X86_CPU(object_new_with_class(OBJECT_CLASS(xcc)));
5246     if (props) {
5247         object_apply_props(OBJECT(xc), props, &err);
5248         if (err) {
5249             goto out;
5250         }
5251     }
5252
5253     x86_cpu_expand_features(xc, &err);
5254     if (err) {
5255         goto out;
5256     }
5257
5258 out:
5259     if (err) {
5260         error_propagate(errp, err);
5261         object_unref(OBJECT(xc));
5262         xc = NULL;
5263     }
5264     return xc;
5265 }
5266
5267 CpuModelExpansionInfo *
5268 qmp_query_cpu_model_expansion(CpuModelExpansionType type,
5269                                                       CpuModelInfo *model,
5270                                                       Error **errp)
5271 {
5272     X86CPU *xc = NULL;
5273     Error *err = NULL;
5274     CpuModelExpansionInfo *ret = g_new0(CpuModelExpansionInfo, 1);
5275     QDict *props = NULL;
5276     const char *base_name;
5277
5278     xc = x86_cpu_from_model(model->name,
5279                             model->has_props ?
5280                                 qobject_to(QDict, model->props) :
5281                                 NULL, &err);
5282     if (err) {
5283         goto out;
5284     }
5285
5286     props = qdict_new();
5287     ret->model = g_new0(CpuModelInfo, 1);
5288     ret->model->props = QOBJECT(props);
5289     ret->model->has_props = true;
5290
5291     switch (type) {
5292     case CPU_MODEL_EXPANSION_TYPE_STATIC:
5293         /* Static expansion will be based on "base" only */
5294         base_name = "base";
5295         x86_cpu_to_dict(xc, props);
5296     break;
5297     case CPU_MODEL_EXPANSION_TYPE_FULL:
5298         /* As we don't return every single property, full expansion needs
5299          * to keep the original model name+props, and add extra
5300          * properties on top of that.
5301          */
5302         base_name = model->name;
5303         x86_cpu_to_dict_full(xc, props);
5304     break;
5305     default:
5306         error_setg(&err, "Unsupported expansion type");
5307         goto out;
5308     }
5309
5310     x86_cpu_to_dict(xc, props);
5311
5312     ret->model->name = g_strdup(base_name);
5313
5314 out:
5315     object_unref(OBJECT(xc));
5316     if (err) {
5317         error_propagate(errp, err);
5318         qapi_free_CpuModelExpansionInfo(ret);
5319         ret = NULL;
5320     }
5321     return ret;
5322 }
5323 #endif  /* !CONFIG_USER_ONLY */
5324
5325 static gchar *x86_gdb_arch_name(CPUState *cs)
5326 {
5327 #ifdef TARGET_X86_64
5328     return g_strdup("i386:x86-64");
5329 #else
5330     return g_strdup("i386");
5331 #endif
5332 }
5333
5334 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
5335 {
5336     X86CPUModel *model = data;
5337     X86CPUClass *xcc = X86_CPU_CLASS(oc);
5338     CPUClass *cc = CPU_CLASS(oc);
5339
5340     xcc->model = model;
5341     xcc->migration_safe = true;
5342     cc->deprecation_note = model->cpudef->deprecation_note;
5343 }
5344
5345 static void x86_register_cpu_model_type(const char *name, X86CPUModel *model)
5346 {
5347     g_autofree char *typename = x86_cpu_type_name(name);
5348     TypeInfo ti = {
5349         .name = typename,
5350         .parent = TYPE_X86_CPU,
5351         .class_init = x86_cpu_cpudef_class_init,
5352         .class_data = model,
5353     };
5354
5355     type_register(&ti);
5356 }
5357
5358 static void x86_register_cpudef_types(X86CPUDefinition *def)
5359 {
5360     X86CPUModel *m;
5361     const X86CPUVersionDefinition *vdef;
5362
5363     /* AMD aliases are handled at runtime based on CPUID vendor, so
5364      * they shouldn't be set on the CPU model table.
5365      */
5366     assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
5367     /* catch mistakes instead of silently truncating model_id when too long */
5368     assert(def->model_id && strlen(def->model_id) <= 48);
5369
5370     /* Unversioned model: */
5371     m = g_new0(X86CPUModel, 1);
5372     m->cpudef = def;
5373     m->version = CPU_VERSION_AUTO;
5374     m->is_alias = true;
5375     x86_register_cpu_model_type(def->name, m);
5376
5377     /* Versioned models: */
5378
5379     for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
5380         X86CPUModel *m = g_new0(X86CPUModel, 1);
5381         g_autofree char *name =
5382             x86_cpu_versioned_model_name(def, vdef->version);
5383         m->cpudef = def;
5384         m->version = vdef->version;
5385         m->note = vdef->note;
5386         x86_register_cpu_model_type(name, m);
5387
5388         if (vdef->alias) {
5389             X86CPUModel *am = g_new0(X86CPUModel, 1);
5390             am->cpudef = def;
5391             am->version = vdef->version;
5392             am->is_alias = true;
5393             x86_register_cpu_model_type(vdef->alias, am);
5394         }
5395     }
5396
5397 }
5398
5399 #if !defined(CONFIG_USER_ONLY)
5400
5401 void cpu_clear_apic_feature(CPUX86State *env)
5402 {
5403     env->features[FEAT_1_EDX] &= ~CPUID_APIC;
5404 }
5405
5406 #endif /* !CONFIG_USER_ONLY */
5407
5408 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
5409                    uint32_t *eax, uint32_t *ebx,
5410                    uint32_t *ecx, uint32_t *edx)
5411 {
5412     X86CPU *cpu = env_archcpu(env);
5413     CPUState *cs = env_cpu(env);
5414     uint32_t die_offset;
5415     uint32_t limit;
5416     uint32_t signature[3];
5417     X86CPUTopoInfo topo_info;
5418
5419     topo_info.dies_per_pkg = env->nr_dies;
5420     topo_info.cores_per_die = cs->nr_cores;
5421     topo_info.threads_per_core = cs->nr_threads;
5422
5423     /* Calculate & apply limits for different index ranges */
5424     if (index >= 0xC0000000) {
5425         limit = env->cpuid_xlevel2;
5426     } else if (index >= 0x80000000) {
5427         limit = env->cpuid_xlevel;
5428     } else if (index >= 0x40000000) {
5429         limit = 0x40000001;
5430     } else {
5431         limit = env->cpuid_level;
5432     }
5433
5434     if (index > limit) {
5435         /* Intel documentation states that invalid EAX input will
5436          * return the same information as EAX=cpuid_level
5437          * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
5438          */
5439         index = env->cpuid_level;
5440     }
5441
5442     switch(index) {
5443     case 0:
5444         *eax = env->cpuid_level;
5445         *ebx = env->cpuid_vendor1;
5446         *edx = env->cpuid_vendor2;
5447         *ecx = env->cpuid_vendor3;
5448         break;
5449     case 1:
5450         *eax = env->cpuid_version;
5451         *ebx = (cpu->apic_id << 24) |
5452                8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
5453         *ecx = env->features[FEAT_1_ECX];
5454         if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
5455             *ecx |= CPUID_EXT_OSXSAVE;
5456         }
5457         *edx = env->features[FEAT_1_EDX];
5458         if (cs->nr_cores * cs->nr_threads > 1) {
5459             *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
5460             *edx |= CPUID_HT;
5461         }
5462         if (!cpu->enable_pmu) {
5463             *ecx &= ~CPUID_EXT_PDCM;
5464         }
5465         break;
5466     case 2:
5467         /* cache info: needed for Pentium Pro compatibility */
5468         if (cpu->cache_info_passthrough) {
5469             host_cpuid(index, 0, eax, ebx, ecx, edx);
5470             break;
5471         }
5472         *eax = 1; /* Number of CPUID[EAX=2] calls required */
5473         *ebx = 0;
5474         if (!cpu->enable_l3_cache) {
5475             *ecx = 0;
5476         } else {
5477             *ecx = cpuid2_cache_descriptor(env->cache_info_cpuid2.l3_cache);
5478         }
5479         *edx = (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1d_cache) << 16) |
5480                (cpuid2_cache_descriptor(env->cache_info_cpuid2.l1i_cache) <<  8) |
5481                (cpuid2_cache_descriptor(env->cache_info_cpuid2.l2_cache));
5482         break;
5483     case 4:
5484         /* cache info: needed for Core compatibility */
5485         if (cpu->cache_info_passthrough) {
5486             host_cpuid(index, count, eax, ebx, ecx, edx);
5487             /* QEMU gives out its own APIC IDs, never pass down bits 31..26.  */
5488             *eax &= ~0xFC000000;
5489             if ((*eax & 31) && cs->nr_cores > 1) {
5490                 *eax |= (cs->nr_cores - 1) << 26;
5491             }
5492         } else {
5493             *eax = 0;
5494             switch (count) {
5495             case 0: /* L1 dcache info */
5496                 encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache,
5497                                     1, cs->nr_cores,
5498                                     eax, ebx, ecx, edx);
5499                 break;
5500             case 1: /* L1 icache info */
5501                 encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache,
5502                                     1, cs->nr_cores,
5503                                     eax, ebx, ecx, edx);
5504                 break;
5505             case 2: /* L2 cache info */
5506                 encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache,
5507                                     cs->nr_threads, cs->nr_cores,
5508                                     eax, ebx, ecx, edx);
5509                 break;
5510             case 3: /* L3 cache info */
5511                 die_offset = apicid_die_offset(&topo_info);
5512                 if (cpu->enable_l3_cache) {
5513                     encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache,
5514                                         (1 << die_offset), cs->nr_cores,
5515                                         eax, ebx, ecx, edx);
5516                     break;
5517                 }
5518                 /* fall through */
5519             default: /* end of info */
5520                 *eax = *ebx = *ecx = *edx = 0;
5521                 break;
5522             }
5523         }
5524         break;
5525     case 5:
5526         /* MONITOR/MWAIT Leaf */
5527         *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */
5528         *ebx = cpu->mwait.ebx; /* Largest monitor-line size in bytes */
5529         *ecx = cpu->mwait.ecx; /* flags */
5530         *edx = cpu->mwait.edx; /* mwait substates */
5531         break;
5532     case 6:
5533         /* Thermal and Power Leaf */
5534         *eax = env->features[FEAT_6_EAX];
5535         *ebx = 0;
5536         *ecx = 0;
5537         *edx = 0;
5538         break;
5539     case 7:
5540         /* Structured Extended Feature Flags Enumeration Leaf */
5541         if (count == 0) {
5542             /* Maximum ECX value for sub-leaves */
5543             *eax = env->cpuid_level_func7;
5544             *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
5545             *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
5546             if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
5547                 *ecx |= CPUID_7_0_ECX_OSPKE;
5548             }
5549             *edx = env->features[FEAT_7_0_EDX]; /* Feature flags */
5550         } else if (count == 1) {
5551             *eax = env->features[FEAT_7_1_EAX];
5552             *ebx = 0;
5553             *ecx = 0;
5554             *edx = 0;
5555         } else {
5556             *eax = 0;
5557             *ebx = 0;
5558             *ecx = 0;
5559             *edx = 0;
5560         }
5561         break;
5562     case 9:
5563         /* Direct Cache Access Information Leaf */
5564         *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
5565         *ebx = 0;
5566         *ecx = 0;
5567         *edx = 0;
5568         break;
5569     case 0xA:
5570         /* Architectural Performance Monitoring Leaf */
5571         if (kvm_enabled() && cpu->enable_pmu) {
5572             KVMState *s = cs->kvm_state;
5573
5574             *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
5575             *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
5576             *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
5577             *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
5578         } else if (hvf_enabled() && cpu->enable_pmu) {
5579             *eax = hvf_get_supported_cpuid(0xA, count, R_EAX);
5580             *ebx = hvf_get_supported_cpuid(0xA, count, R_EBX);
5581             *ecx = hvf_get_supported_cpuid(0xA, count, R_ECX);
5582             *edx = hvf_get_supported_cpuid(0xA, count, R_EDX);
5583         } else {
5584             *eax = 0;
5585             *ebx = 0;
5586             *ecx = 0;
5587             *edx = 0;
5588         }
5589         break;
5590     case 0xB:
5591         /* Extended Topology Enumeration Leaf */
5592         if (!cpu->enable_cpuid_0xb) {
5593                 *eax = *ebx = *ecx = *edx = 0;
5594                 break;
5595         }
5596
5597         *ecx = count & 0xff;
5598         *edx = cpu->apic_id;
5599
5600         switch (count) {
5601         case 0:
5602             *eax = apicid_core_offset(&topo_info);
5603             *ebx = cs->nr_threads;
5604             *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5605             break;
5606         case 1:
5607             *eax = apicid_pkg_offset(&topo_info);
5608             *ebx = cs->nr_cores * cs->nr_threads;
5609             *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5610             break;
5611         default:
5612             *eax = 0;
5613             *ebx = 0;
5614             *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5615         }
5616
5617         assert(!(*eax & ~0x1f));
5618         *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5619         break;
5620     case 0x1F:
5621         /* V2 Extended Topology Enumeration Leaf */
5622         if (env->nr_dies < 2) {
5623             *eax = *ebx = *ecx = *edx = 0;
5624             break;
5625         }
5626
5627         *ecx = count & 0xff;
5628         *edx = cpu->apic_id;
5629         switch (count) {
5630         case 0:
5631             *eax = apicid_core_offset(&topo_info);
5632             *ebx = cs->nr_threads;
5633             *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
5634             break;
5635         case 1:
5636             *eax = apicid_die_offset(&topo_info);
5637             *ebx = cs->nr_cores * cs->nr_threads;
5638             *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
5639             break;
5640         case 2:
5641             *eax = apicid_pkg_offset(&topo_info);
5642             *ebx = env->nr_dies * cs->nr_cores * cs->nr_threads;
5643             *ecx |= CPUID_TOPOLOGY_LEVEL_DIE;
5644             break;
5645         default:
5646             *eax = 0;
5647             *ebx = 0;
5648             *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
5649         }
5650         assert(!(*eax & ~0x1f));
5651         *ebx &= 0xffff; /* The count doesn't need to be reliable. */
5652         break;
5653     case 0xD: {
5654         /* Processor Extended State */
5655         *eax = 0;
5656         *ebx = 0;
5657         *ecx = 0;
5658         *edx = 0;
5659         if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
5660             break;
5661         }
5662
5663         if (count == 0) {
5664             *ecx = xsave_area_size(x86_cpu_xsave_components(cpu));
5665             *eax = env->features[FEAT_XSAVE_COMP_LO];
5666             *edx = env->features[FEAT_XSAVE_COMP_HI];
5667             /*
5668              * The initial value of xcr0 and ebx == 0, On host without kvm
5669              * commit 412a3c41(e.g., CentOS 6), the ebx's value always == 0
5670              * even through guest update xcr0, this will crash some legacy guest
5671              * (e.g., CentOS 6), So set ebx == ecx to workaroud it.
5672              */
5673             *ebx = kvm_enabled() ? *ecx : xsave_area_size(env->xcr0);
5674         } else if (count == 1) {
5675             *eax = env->features[FEAT_XSAVE];
5676         } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
5677             if ((x86_cpu_xsave_components(cpu) >> count) & 1) {
5678                 const ExtSaveArea *esa = &x86_ext_save_areas[count];
5679                 *eax = esa->size;
5680                 *ebx = esa->offset;
5681             }
5682         }
5683         break;
5684     }
5685     case 0x14: {
5686         /* Intel Processor Trace Enumeration */
5687         *eax = 0;
5688         *ebx = 0;
5689         *ecx = 0;
5690         *edx = 0;
5691         if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) ||
5692             !kvm_enabled()) {
5693             break;
5694         }
5695
5696         if (count == 0) {
5697             *eax = INTEL_PT_MAX_SUBLEAF;
5698             *ebx = INTEL_PT_MINIMAL_EBX;
5699             *ecx = INTEL_PT_MINIMAL_ECX;
5700             if (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP) {
5701                 *ecx |= CPUID_14_0_ECX_LIP;
5702             }
5703         } else if (count == 1) {
5704             *eax = INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM;
5705             *ebx = INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP;
5706         }
5707         break;
5708     }
5709     case 0x40000000:
5710         /*
5711          * CPUID code in kvm_arch_init_vcpu() ignores stuff
5712          * set here, but we restrict to TCG none the less.
5713          */
5714         if (tcg_enabled() && cpu->expose_tcg) {
5715             memcpy(signature, "TCGTCGTCGTCG", 12);
5716             *eax = 0x40000001;
5717             *ebx = signature[0];
5718             *ecx = signature[1];
5719             *edx = signature[2];
5720         } else {
5721             *eax = 0;
5722             *ebx = 0;
5723             *ecx = 0;
5724             *edx = 0;
5725         }
5726         break;
5727     case 0x40000001:
5728         *eax = 0;
5729         *ebx = 0;
5730         *ecx = 0;
5731         *edx = 0;
5732         break;
5733     case 0x80000000:
5734         *eax = env->cpuid_xlevel;
5735         *ebx = env->cpuid_vendor1;
5736         *edx = env->cpuid_vendor2;
5737         *ecx = env->cpuid_vendor3;
5738         break;
5739     case 0x80000001:
5740         *eax = env->cpuid_version;
5741         *ebx = 0;
5742         *ecx = env->features[FEAT_8000_0001_ECX];
5743         *edx = env->features[FEAT_8000_0001_EDX];
5744
5745         /* The Linux kernel checks for the CMPLegacy bit and
5746          * discards multiple thread information if it is set.
5747          * So don't set it here for Intel to make Linux guests happy.
5748          */
5749         if (cs->nr_cores * cs->nr_threads > 1) {
5750             if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
5751                 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
5752                 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
5753                 *ecx |= 1 << 1;    /* CmpLegacy bit */
5754             }
5755         }
5756         break;
5757     case 0x80000002:
5758     case 0x80000003:
5759     case 0x80000004:
5760         *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
5761         *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
5762         *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
5763         *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
5764         break;
5765     case 0x80000005:
5766         /* cache info (L1 cache) */
5767         if (cpu->cache_info_passthrough) {
5768             host_cpuid(index, 0, eax, ebx, ecx, edx);
5769             break;
5770         }
5771         *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) |
5772                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
5773         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) |
5774                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
5775         *ecx = encode_cache_cpuid80000005(env->cache_info_amd.l1d_cache);
5776         *edx = encode_cache_cpuid80000005(env->cache_info_amd.l1i_cache);
5777         break;
5778     case 0x80000006:
5779         /* cache info (L2 cache) */
5780         if (cpu->cache_info_passthrough) {
5781             host_cpuid(index, 0, eax, ebx, ecx, edx);
5782             break;
5783         }
5784         *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) |
5785                (L2_DTLB_2M_ENTRIES << 16) |
5786                (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) |
5787                (L2_ITLB_2M_ENTRIES);
5788         *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) |
5789                (L2_DTLB_4K_ENTRIES << 16) |
5790                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) |
5791                (L2_ITLB_4K_ENTRIES);
5792         encode_cache_cpuid80000006(env->cache_info_amd.l2_cache,
5793                                    cpu->enable_l3_cache ?
5794                                    env->cache_info_amd.l3_cache : NULL,
5795                                    ecx, edx);
5796         break;
5797     case 0x80000007:
5798         *eax = 0;
5799         *ebx = 0;
5800         *ecx = 0;
5801         *edx = env->features[FEAT_8000_0007_EDX];
5802         break;
5803     case 0x80000008:
5804         /* virtual & phys address size in low 2 bytes. */
5805         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
5806             /* 64 bit processor */
5807             *eax = cpu->phys_bits; /* configurable physical bits */
5808             if  (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_LA57) {
5809                 *eax |= 0x00003900; /* 57 bits virtual */
5810             } else {
5811                 *eax |= 0x00003000; /* 48 bits virtual */
5812             }
5813         } else {
5814             *eax = cpu->phys_bits;
5815         }
5816         *ebx = env->features[FEAT_8000_0008_EBX];
5817         if (cs->nr_cores * cs->nr_threads > 1) {
5818             /*
5819              * Bits 15:12 is "The number of bits in the initial
5820              * Core::X86::Apic::ApicId[ApicId] value that indicate
5821              * thread ID within a package".
5822              * Bits 7:0 is "The number of threads in the package is NC+1"
5823              */
5824             *ecx = (apicid_pkg_offset(&topo_info) << 12) |
5825                    ((cs->nr_cores * cs->nr_threads) - 1);
5826         } else {
5827             *ecx = 0;
5828         }
5829         *edx = 0;
5830         break;
5831     case 0x8000000A:
5832         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
5833             *eax = 0x00000001; /* SVM Revision */
5834             *ebx = 0x00000010; /* nr of ASIDs */
5835             *ecx = 0;
5836             *edx = env->features[FEAT_SVM]; /* optional features */
5837         } else {
5838             *eax = 0;
5839             *ebx = 0;
5840             *ecx = 0;
5841             *edx = 0;
5842         }
5843         break;
5844     case 0x8000001D:
5845         *eax = 0;
5846         if (cpu->cache_info_passthrough) {
5847             host_cpuid(index, count, eax, ebx, ecx, edx);
5848             break;
5849         }
5850         switch (count) {
5851         case 0: /* L1 dcache info */
5852             encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache,
5853                                        &topo_info, eax, ebx, ecx, edx);
5854             break;
5855         case 1: /* L1 icache info */
5856             encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache,
5857                                        &topo_info, eax, ebx, ecx, edx);
5858             break;
5859         case 2: /* L2 cache info */
5860             encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache,
5861                                        &topo_info, eax, ebx, ecx, edx);
5862             break;
5863         case 3: /* L3 cache info */
5864             encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache,
5865                                        &topo_info, eax, ebx, ecx, edx);
5866             break;
5867         default: /* end of info */
5868             *eax = *ebx = *ecx = *edx = 0;
5869             break;
5870         }
5871         break;
5872     case 0x8000001E:
5873         if (cpu->core_id <= 255) {
5874             encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx);
5875         } else {
5876             *eax = 0;
5877             *ebx = 0;
5878             *ecx = 0;
5879             *edx = 0;
5880         }
5881         break;
5882     case 0xC0000000:
5883         *eax = env->cpuid_xlevel2;
5884         *ebx = 0;
5885         *ecx = 0;
5886         *edx = 0;
5887         break;
5888     case 0xC0000001:
5889         /* Support for VIA CPU's CPUID instruction */
5890         *eax = env->cpuid_version;
5891         *ebx = 0;
5892         *ecx = 0;
5893         *edx = env->features[FEAT_C000_0001_EDX];
5894         break;
5895     case 0xC0000002:
5896     case 0xC0000003:
5897     case 0xC0000004:
5898         /* Reserved for the future, and now filled with zero */
5899         *eax = 0;
5900         *ebx = 0;
5901         *ecx = 0;
5902         *edx = 0;
5903         break;
5904     case 0x8000001F:
5905         *eax = sev_enabled() ? 0x2 : 0;
5906         *eax |= sev_es_enabled() ? 0x8 : 0;
5907         *ebx = sev_get_cbit_position();
5908         *ebx |= sev_get_reduced_phys_bits() << 6;
5909         *ecx = 0;
5910         *edx = 0;
5911         break;
5912     default:
5913         /* reserved values: zero */
5914         *eax = 0;
5915         *ebx = 0;
5916         *ecx = 0;
5917         *edx = 0;
5918         break;
5919     }
5920 }
5921
5922 static void x86_cpu_reset(DeviceState *dev)
5923 {
5924     CPUState *s = CPU(dev);
5925     X86CPU *cpu = X86_CPU(s);
5926     X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
5927     CPUX86State *env = &cpu->env;
5928     target_ulong cr4;
5929     uint64_t xcr0;
5930     int i;
5931
5932     xcc->parent_reset(dev);
5933
5934     memset(env, 0, offsetof(CPUX86State, end_reset_fields));
5935
5936     env->old_exception = -1;
5937
5938     /* init to reset state */
5939
5940     env->hflags2 |= HF2_GIF_MASK;
5941     env->hflags &= ~HF_GUEST_MASK;
5942
5943     cpu_x86_update_cr0(env, 0x60000010);
5944     env->a20_mask = ~0x0;
5945     env->smbase = 0x30000;
5946     env->msr_smi_count = 0;
5947
5948     env->idt.limit = 0xffff;
5949     env->gdt.limit = 0xffff;
5950     env->ldt.limit = 0xffff;
5951     env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
5952     env->tr.limit = 0xffff;
5953     env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
5954
5955     cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
5956                            DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
5957                            DESC_R_MASK | DESC_A_MASK);
5958     cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
5959                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5960                            DESC_A_MASK);
5961     cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
5962                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5963                            DESC_A_MASK);
5964     cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
5965                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5966                            DESC_A_MASK);
5967     cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
5968                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5969                            DESC_A_MASK);
5970     cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
5971                            DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
5972                            DESC_A_MASK);
5973
5974     env->eip = 0xfff0;
5975     env->regs[R_EDX] = env->cpuid_version;
5976
5977     env->eflags = 0x2;
5978
5979     /* FPU init */
5980     for (i = 0; i < 8; i++) {
5981         env->fptags[i] = 1;
5982     }
5983     cpu_set_fpuc(env, 0x37f);
5984
5985     env->mxcsr = 0x1f80;
5986     /* All units are in INIT state.  */
5987     env->xstate_bv = 0;
5988
5989     env->pat = 0x0007040600070406ULL;
5990     env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
5991     if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
5992         env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
5993     }
5994
5995     memset(env->dr, 0, sizeof(env->dr));
5996     env->dr[6] = DR6_FIXED_1;
5997     env->dr[7] = DR7_FIXED_1;
5998     cpu_breakpoint_remove_all(s, BP_CPU);
5999     cpu_watchpoint_remove_all(s, BP_CPU);
6000
6001     cr4 = 0;
6002     xcr0 = XSTATE_FP_MASK;
6003
6004 #ifdef CONFIG_USER_ONLY
6005     /* Enable all the features for user-mode.  */
6006     if (env->features[FEAT_1_EDX] & CPUID_SSE) {
6007         xcr0 |= XSTATE_SSE_MASK;
6008     }
6009     for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6010         const ExtSaveArea *esa = &x86_ext_save_areas[i];
6011         if (env->features[esa->feature] & esa->bits) {
6012             xcr0 |= 1ull << i;
6013         }
6014     }
6015
6016     if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
6017         cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
6018     }
6019     if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
6020         cr4 |= CR4_FSGSBASE_MASK;
6021     }
6022 #endif
6023
6024     env->xcr0 = xcr0;
6025     cpu_x86_update_cr4(env, cr4);
6026
6027     /*
6028      * SDM 11.11.5 requires:
6029      *  - IA32_MTRR_DEF_TYPE MSR.E = 0
6030      *  - IA32_MTRR_PHYSMASKn.V = 0
6031      * All other bits are undefined.  For simplification, zero it all.
6032      */
6033     env->mtrr_deftype = 0;
6034     memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
6035     memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
6036
6037     env->interrupt_injected = -1;
6038     env->exception_nr = -1;
6039     env->exception_pending = 0;
6040     env->exception_injected = 0;
6041     env->exception_has_payload = false;
6042     env->exception_payload = 0;
6043     env->nmi_injected = false;
6044 #if !defined(CONFIG_USER_ONLY)
6045     /* We hard-wire the BSP to the first CPU. */
6046     apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
6047
6048     s->halted = !cpu_is_bsp(cpu);
6049
6050     if (kvm_enabled()) {
6051         kvm_arch_reset_vcpu(cpu);
6052     }
6053 #endif
6054 }
6055
6056 #ifndef CONFIG_USER_ONLY
6057 bool cpu_is_bsp(X86CPU *cpu)
6058 {
6059     return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
6060 }
6061
6062 /* TODO: remove me, when reset over QOM tree is implemented */
6063 static void x86_cpu_machine_reset_cb(void *opaque)
6064 {
6065     X86CPU *cpu = opaque;
6066     cpu_reset(CPU(cpu));
6067 }
6068 #endif
6069
6070 static void mce_init(X86CPU *cpu)
6071 {
6072     CPUX86State *cenv = &cpu->env;
6073     unsigned int bank;
6074
6075     if (((cenv->cpuid_version >> 8) & 0xf) >= 6
6076         && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
6077             (CPUID_MCE | CPUID_MCA)) {
6078         cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
6079                         (cpu->enable_lmce ? MCG_LMCE_P : 0);
6080         cenv->mcg_ctl = ~(uint64_t)0;
6081         for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
6082             cenv->mce_banks[bank * 4] = ~(uint64_t)0;
6083         }
6084     }
6085 }
6086
6087 #ifndef CONFIG_USER_ONLY
6088 APICCommonClass *apic_get_class(void)
6089 {
6090     const char *apic_type = "apic";
6091
6092     /* TODO: in-kernel irqchip for hvf */
6093     if (kvm_apic_in_kernel()) {
6094         apic_type = "kvm-apic";
6095     } else if (xen_enabled()) {
6096         apic_type = "xen-apic";
6097     } else if (whpx_apic_in_platform()) {
6098         apic_type = "whpx-apic";
6099     }
6100
6101     return APIC_COMMON_CLASS(object_class_by_name(apic_type));
6102 }
6103
6104 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
6105 {
6106     APICCommonState *apic;
6107     ObjectClass *apic_class = OBJECT_CLASS(apic_get_class());
6108
6109     cpu->apic_state = DEVICE(object_new_with_class(apic_class));
6110
6111     object_property_add_child(OBJECT(cpu), "lapic",
6112                               OBJECT(cpu->apic_state));
6113     object_unref(OBJECT(cpu->apic_state));
6114
6115     qdev_prop_set_uint32(cpu->apic_state, "id", cpu->apic_id);
6116     /* TODO: convert to link<> */
6117     apic = APIC_COMMON(cpu->apic_state);
6118     apic->cpu = cpu;
6119     apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
6120 }
6121
6122 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6123 {
6124     APICCommonState *apic;
6125     static bool apic_mmio_map_once;
6126
6127     if (cpu->apic_state == NULL) {
6128         return;
6129     }
6130     qdev_realize(DEVICE(cpu->apic_state), NULL, errp);
6131
6132     /* Map APIC MMIO area */
6133     apic = APIC_COMMON(cpu->apic_state);
6134     if (!apic_mmio_map_once) {
6135         memory_region_add_subregion_overlap(get_system_memory(),
6136                                             apic->apicbase &
6137                                             MSR_IA32_APICBASE_BASE,
6138                                             &apic->io_memory,
6139                                             0x1000);
6140         apic_mmio_map_once = true;
6141      }
6142 }
6143 #else
6144 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
6145 {
6146 }
6147 #endif
6148
6149 static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
6150 {
6151     if (*min < value) {
6152         *min = value;
6153     }
6154 }
6155
6156 /* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
6157 static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
6158 {
6159     CPUX86State *env = &cpu->env;
6160     FeatureWordInfo *fi = &feature_word_info[w];
6161     uint32_t eax = fi->cpuid.eax;
6162     uint32_t region = eax & 0xF0000000;
6163
6164     assert(feature_word_info[w].type == CPUID_FEATURE_WORD);
6165     if (!env->features[w]) {
6166         return;
6167     }
6168
6169     switch (region) {
6170     case 0x00000000:
6171         x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
6172     break;
6173     case 0x80000000:
6174         x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
6175     break;
6176     case 0xC0000000:
6177         x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
6178     break;
6179     }
6180
6181     if (eax == 7) {
6182         x86_cpu_adjust_level(cpu, &env->cpuid_min_level_func7,
6183                              fi->cpuid.ecx);
6184     }
6185 }
6186
6187 /* Calculate XSAVE components based on the configured CPU feature flags */
6188 static void x86_cpu_enable_xsave_components(X86CPU *cpu)
6189 {
6190     CPUX86State *env = &cpu->env;
6191     int i;
6192     uint64_t mask;
6193
6194     if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
6195         env->features[FEAT_XSAVE_COMP_LO] = 0;
6196         env->features[FEAT_XSAVE_COMP_HI] = 0;
6197         return;
6198     }
6199
6200     mask = 0;
6201     for (i = 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
6202         const ExtSaveArea *esa = &x86_ext_save_areas[i];
6203         if (env->features[esa->feature] & esa->bits) {
6204             mask |= (1ULL << i);
6205         }
6206     }
6207
6208     env->features[FEAT_XSAVE_COMP_LO] = mask;
6209     env->features[FEAT_XSAVE_COMP_HI] = mask >> 32;
6210 }
6211
6212 /***** Steps involved on loading and filtering CPUID data
6213  *
6214  * When initializing and realizing a CPU object, the steps
6215  * involved in setting up CPUID data are:
6216  *
6217  * 1) Loading CPU model definition (X86CPUDefinition). This is
6218  *    implemented by x86_cpu_load_model() and should be completely
6219  *    transparent, as it is done automatically by instance_init.
6220  *    No code should need to look at X86CPUDefinition structs
6221  *    outside instance_init.
6222  *
6223  * 2) CPU expansion. This is done by realize before CPUID
6224  *    filtering, and will make sure host/accelerator data is
6225  *    loaded for CPU models that depend on host capabilities
6226  *    (e.g. "host"). Done by x86_cpu_expand_features().
6227  *
6228  * 3) CPUID filtering. This initializes extra data related to
6229  *    CPUID, and checks if the host supports all capabilities
6230  *    required by the CPU. Runnability of a CPU model is
6231  *    determined at this step. Done by x86_cpu_filter_features().
6232  *
6233  * Some operations don't require all steps to be performed.
6234  * More precisely:
6235  *
6236  * - CPU instance creation (instance_init) will run only CPU
6237  *   model loading. CPU expansion can't run at instance_init-time
6238  *   because host/accelerator data may be not available yet.
6239  * - CPU realization will perform both CPU model expansion and CPUID
6240  *   filtering, and return an error in case one of them fails.
6241  * - query-cpu-definitions needs to run all 3 steps. It needs
6242  *   to run CPUID filtering, as the 'unavailable-features'
6243  *   field is set based on the filtering results.
6244  * - The query-cpu-model-expansion QMP command only needs to run
6245  *   CPU model loading and CPU expansion. It should not filter
6246  *   any CPUID data based on host capabilities.
6247  */
6248
6249 /* Expand CPU configuration data, based on configured features
6250  * and host/accelerator capabilities when appropriate.
6251  */
6252 static void x86_cpu_expand_features(X86CPU *cpu, Error **errp)
6253 {
6254     CPUX86State *env = &cpu->env;
6255     FeatureWord w;
6256     int i;
6257     GList *l;
6258
6259     for (l = plus_features; l; l = l->next) {
6260         const char *prop = l->data;
6261         if (!object_property_set_bool(OBJECT(cpu), prop, true, errp)) {
6262             return;
6263         }
6264     }
6265
6266     for (l = minus_features; l; l = l->next) {
6267         const char *prop = l->data;
6268         if (!object_property_set_bool(OBJECT(cpu), prop, false, errp)) {
6269             return;
6270         }
6271     }
6272
6273     /*TODO: Now cpu->max_features doesn't overwrite features
6274      * set using QOM properties, and we can convert
6275      * plus_features & minus_features to global properties
6276      * inside x86_cpu_parse_featurestr() too.
6277      */
6278     if (cpu->max_features) {
6279         for (w = 0; w < FEATURE_WORDS; w++) {
6280             /* Override only features that weren't set explicitly
6281              * by the user.
6282              */
6283             env->features[w] |=
6284                 x86_cpu_get_supported_feature_word(w, cpu->migratable) &
6285                 ~env->user_features[w] &
6286                 ~feature_word_info[w].no_autoenable_flags;
6287         }
6288     }
6289
6290     for (i = 0; i < ARRAY_SIZE(feature_dependencies); i++) {
6291         FeatureDep *d = &feature_dependencies[i];
6292         if (!(env->features[d->from.index] & d->from.mask)) {
6293             uint64_t unavailable_features = env->features[d->to.index] & d->to.mask;
6294
6295             /* Not an error unless the dependent feature was added explicitly.  */
6296             mark_unavailable_features(cpu, d->to.index,
6297                                       unavailable_features & env->user_features[d->to.index],
6298                                       "This feature depends on other features that were not requested");
6299
6300             env->features[d->to.index] &= ~unavailable_features;
6301         }
6302     }
6303
6304     if (!kvm_enabled() || !cpu->expose_kvm) {
6305         env->features[FEAT_KVM] = 0;
6306     }
6307
6308     x86_cpu_enable_xsave_components(cpu);
6309
6310     /* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
6311     x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
6312     if (cpu->full_cpuid_auto_level) {
6313         x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
6314         x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
6315         x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
6316         x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
6317         x86_cpu_adjust_feat_level(cpu, FEAT_7_1_EAX);
6318         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
6319         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
6320         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
6321         x86_cpu_adjust_feat_level(cpu, FEAT_8000_0008_EBX);
6322         x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
6323         x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
6324         x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
6325
6326         /* Intel Processor Trace requires CPUID[0x14] */
6327         if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) {
6328             if (cpu->intel_pt_auto_level) {
6329                 x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14);
6330             } else if (cpu->env.cpuid_min_level < 0x14) {
6331                 mark_unavailable_features(cpu, FEAT_7_0_EBX,
6332                     CPUID_7_0_EBX_INTEL_PT,
6333                     "Intel PT need CPUID leaf 0x14, please set by \"-cpu ...,intel-pt=on,min-level=0x14\"");
6334             }
6335         }
6336
6337         /* CPU topology with multi-dies support requires CPUID[0x1F] */
6338         if (env->nr_dies > 1) {
6339             x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x1F);
6340         }
6341
6342         /* SVM requires CPUID[0x8000000A] */
6343         if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
6344             x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
6345         }
6346
6347         /* SEV requires CPUID[0x8000001F] */
6348         if (sev_enabled()) {
6349             x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000001F);
6350         }
6351     }
6352
6353     /* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
6354     if (env->cpuid_level_func7 == UINT32_MAX) {
6355         env->cpuid_level_func7 = env->cpuid_min_level_func7;
6356     }
6357     if (env->cpuid_level == UINT32_MAX) {
6358         env->cpuid_level = env->cpuid_min_level;
6359     }
6360     if (env->cpuid_xlevel == UINT32_MAX) {
6361         env->cpuid_xlevel = env->cpuid_min_xlevel;
6362     }
6363     if (env->cpuid_xlevel2 == UINT32_MAX) {
6364         env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
6365     }
6366 }
6367
6368 /*
6369  * Finishes initialization of CPUID data, filters CPU feature
6370  * words based on host availability of each feature.
6371  *
6372  * Returns: 0 if all flags are supported by the host, non-zero otherwise.
6373  */
6374 static void x86_cpu_filter_features(X86CPU *cpu, bool verbose)
6375 {
6376     CPUX86State *env = &cpu->env;
6377     FeatureWord w;
6378     const char *prefix = NULL;
6379
6380     if (verbose) {
6381         prefix = accel_uses_host_cpuid()
6382                  ? "host doesn't support requested feature"
6383                  : "TCG doesn't support requested feature";
6384     }
6385
6386     for (w = 0; w < FEATURE_WORDS; w++) {
6387         uint64_t host_feat =
6388             x86_cpu_get_supported_feature_word(w, false);
6389         uint64_t requested_features = env->features[w];
6390         uint64_t unavailable_features = requested_features & ~host_feat;
6391         mark_unavailable_features(cpu, w, unavailable_features, prefix);
6392     }
6393
6394     if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) &&
6395         kvm_enabled()) {
6396         KVMState *s = CPU(cpu)->kvm_state;
6397         uint32_t eax_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX);
6398         uint32_t ebx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX);
6399         uint32_t ecx_0 = kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX);
6400         uint32_t eax_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX);
6401         uint32_t ebx_1 = kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX);
6402
6403         if (!eax_0 ||
6404            ((ebx_0 & INTEL_PT_MINIMAL_EBX) != INTEL_PT_MINIMAL_EBX) ||
6405            ((ecx_0 & INTEL_PT_MINIMAL_ECX) != INTEL_PT_MINIMAL_ECX) ||
6406            ((eax_1 & INTEL_PT_MTC_BITMAP) != INTEL_PT_MTC_BITMAP) ||
6407            ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) <
6408                                            INTEL_PT_ADDR_RANGES_NUM) ||
6409            ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=
6410                 (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) ||
6411            ((ecx_0 & CPUID_14_0_ECX_LIP) !=
6412                 (env->features[FEAT_14_0_ECX] & CPUID_14_0_ECX_LIP))) {
6413             /*
6414              * Processor Trace capabilities aren't configurable, so if the
6415              * host can't emulate the capabilities we report on
6416              * cpu_x86_cpuid(), intel-pt can't be enabled on the current host.
6417              */
6418             mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT, prefix);
6419         }
6420     }
6421 }
6422
6423 static void x86_cpu_hyperv_realize(X86CPU *cpu)
6424 {
6425     size_t len;
6426
6427     /* Hyper-V vendor id */
6428     if (!cpu->hyperv_vendor) {
6429         memcpy(cpu->hyperv_vendor_id, "Microsoft Hv", 12);
6430     } else {
6431         len = strlen(cpu->hyperv_vendor);
6432
6433         if (len > 12) {
6434             warn_report("hv-vendor-id truncated to 12 characters");
6435             len = 12;
6436         }
6437         memset(cpu->hyperv_vendor_id, 0, 12);
6438         memcpy(cpu->hyperv_vendor_id, cpu->hyperv_vendor, len);
6439     }
6440
6441     /* 'Hv#1' interface identification*/
6442     cpu->hyperv_interface_id[0] = 0x31237648;
6443     cpu->hyperv_interface_id[1] = 0;
6444     cpu->hyperv_interface_id[2] = 0;
6445     cpu->hyperv_interface_id[3] = 0;
6446
6447     /* Hypervisor system identity */
6448     cpu->hyperv_version_id[0] = 0x00001bbc;
6449     cpu->hyperv_version_id[1] = 0x00060001;
6450
6451     /* Hypervisor implementation limits */
6452     cpu->hyperv_limits[0] = 64;
6453     cpu->hyperv_limits[1] = 0;
6454     cpu->hyperv_limits[2] = 0;
6455 }
6456
6457 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
6458 {
6459     CPUState *cs = CPU(dev);
6460     X86CPU *cpu = X86_CPU(dev);
6461     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6462     CPUX86State *env = &cpu->env;
6463     Error *local_err = NULL;
6464     static bool ht_warned;
6465
6466     /* Process Hyper-V enlightenments */
6467     x86_cpu_hyperv_realize(cpu);
6468
6469     cpu_exec_realizefn(cs, &local_err);
6470     if (local_err != NULL) {
6471         error_propagate(errp, local_err);
6472         return;
6473     }
6474
6475     if (xcc->host_cpuid_required && !accel_uses_host_cpuid()) {
6476         g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6477         error_setg(&local_err, "CPU model '%s' requires KVM or HVF", name);
6478         goto out;
6479     }
6480
6481     if (cpu->ucode_rev == 0) {
6482         /* The default is the same as KVM's.  */
6483         if (IS_AMD_CPU(env)) {
6484             cpu->ucode_rev = 0x01000065;
6485         } else {
6486             cpu->ucode_rev = 0x100000000ULL;
6487         }
6488     }
6489
6490     /* mwait extended info: needed for Core compatibility */
6491     /* We always wake on interrupt even if host does not have the capability */
6492     cpu->mwait.ecx |= CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
6493
6494     if (cpu->apic_id == UNASSIGNED_APIC_ID) {
6495         error_setg(errp, "apic-id property was not initialized properly");
6496         return;
6497     }
6498
6499     x86_cpu_expand_features(cpu, &local_err);
6500     if (local_err) {
6501         goto out;
6502     }
6503
6504     x86_cpu_filter_features(cpu, cpu->check_cpuid || cpu->enforce_cpuid);
6505
6506     if (cpu->enforce_cpuid && x86_cpu_have_filtered_features(cpu)) {
6507         error_setg(&local_err,
6508                    accel_uses_host_cpuid() ?
6509                        "Host doesn't support requested features" :
6510                        "TCG doesn't support requested features");
6511         goto out;
6512     }
6513
6514     /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
6515      * CPUID[1].EDX.
6516      */
6517     if (IS_AMD_CPU(env)) {
6518         env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
6519         env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
6520            & CPUID_EXT2_AMD_ALIASES);
6521     }
6522
6523     /* For 64bit systems think about the number of physical bits to present.
6524      * ideally this should be the same as the host; anything other than matching
6525      * the host can cause incorrect guest behaviour.
6526      * QEMU used to pick the magic value of 40 bits that corresponds to
6527      * consumer AMD devices but nothing else.
6528      */
6529     if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
6530         if (cpu->phys_bits &&
6531             (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
6532             cpu->phys_bits < 32)) {
6533             error_setg(errp, "phys-bits should be between 32 and %u "
6534                              " (but is %u)",
6535                              TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
6536             return;
6537         }
6538         /*
6539          * 0 means it was not explicitly set by the user (or by machine
6540          * compat_props or by the host code in host-cpu.c).
6541          * In this case, the default is the value used by TCG (40).
6542          */
6543         if (cpu->phys_bits == 0) {
6544             cpu->phys_bits = TCG_PHYS_ADDR_BITS;
6545         }
6546     } else {
6547         /* For 32 bit systems don't use the user set value, but keep
6548          * phys_bits consistent with what we tell the guest.
6549          */
6550         if (cpu->phys_bits != 0) {
6551             error_setg(errp, "phys-bits is not user-configurable in 32 bit");
6552             return;
6553         }
6554
6555         if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
6556             cpu->phys_bits = 36;
6557         } else {
6558             cpu->phys_bits = 32;
6559         }
6560     }
6561
6562     /* Cache information initialization */
6563     if (!cpu->legacy_cache) {
6564         if (!xcc->model || !xcc->model->cpudef->cache_info) {
6565             g_autofree char *name = x86_cpu_class_get_model_name(xcc);
6566             error_setg(errp,
6567                        "CPU model '%s' doesn't support legacy-cache=off", name);
6568             return;
6569         }
6570         env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
6571             *xcc->model->cpudef->cache_info;
6572     } else {
6573         /* Build legacy cache information */
6574         env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
6575         env->cache_info_cpuid2.l1i_cache = &legacy_l1i_cache;
6576         env->cache_info_cpuid2.l2_cache = &legacy_l2_cache_cpuid2;
6577         env->cache_info_cpuid2.l3_cache = &legacy_l3_cache;
6578
6579         env->cache_info_cpuid4.l1d_cache = &legacy_l1d_cache;
6580         env->cache_info_cpuid4.l1i_cache = &legacy_l1i_cache;
6581         env->cache_info_cpuid4.l2_cache = &legacy_l2_cache;
6582         env->cache_info_cpuid4.l3_cache = &legacy_l3_cache;
6583
6584         env->cache_info_amd.l1d_cache = &legacy_l1d_cache_amd;
6585         env->cache_info_amd.l1i_cache = &legacy_l1i_cache_amd;
6586         env->cache_info_amd.l2_cache = &legacy_l2_cache_amd;
6587         env->cache_info_amd.l3_cache = &legacy_l3_cache;
6588     }
6589
6590 #ifndef CONFIG_USER_ONLY
6591     MachineState *ms = MACHINE(qdev_get_machine());
6592     qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
6593
6594     if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || ms->smp.cpus > 1) {
6595         x86_cpu_apic_create(cpu, &local_err);
6596         if (local_err != NULL) {
6597             goto out;
6598         }
6599     }
6600 #endif
6601
6602     mce_init(cpu);
6603
6604     qemu_init_vcpu(cs);
6605
6606     /*
6607      * Most Intel and certain AMD CPUs support hyperthreading. Even though QEMU
6608      * fixes this issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
6609      * based on inputs (sockets,cores,threads), it is still better to give
6610      * users a warning.
6611      *
6612      * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
6613      * cs->nr_threads hasn't be populated yet and the checking is incorrect.
6614      */
6615     if (IS_AMD_CPU(env) &&
6616         !(env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_TOPOEXT) &&
6617         cs->nr_threads > 1 && !ht_warned) {
6618             warn_report("This family of AMD CPU doesn't support "
6619                         "hyperthreading(%d)",
6620                         cs->nr_threads);
6621             error_printf("Please configure -smp options properly"
6622                          " or try enabling topoext feature.\n");
6623             ht_warned = true;
6624     }
6625
6626     x86_cpu_apic_realize(cpu, &local_err);
6627     if (local_err != NULL) {
6628         goto out;
6629     }
6630     cpu_reset(cs);
6631
6632     xcc->parent_realize(dev, &local_err);
6633
6634 out:
6635     if (local_err != NULL) {
6636         error_propagate(errp, local_err);
6637         return;
6638     }
6639 }
6640
6641 static void x86_cpu_unrealizefn(DeviceState *dev)
6642 {
6643     X86CPU *cpu = X86_CPU(dev);
6644     X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
6645
6646 #ifndef CONFIG_USER_ONLY
6647     cpu_remove_sync(CPU(dev));
6648     qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
6649 #endif
6650
6651     if (cpu->apic_state) {
6652         object_unparent(OBJECT(cpu->apic_state));
6653         cpu->apic_state = NULL;
6654     }
6655
6656     xcc->parent_unrealize(dev);
6657 }
6658
6659 typedef struct BitProperty {
6660     FeatureWord w;
6661     uint64_t mask;
6662 } BitProperty;
6663
6664 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
6665                                  void *opaque, Error **errp)
6666 {
6667     X86CPU *cpu = X86_CPU(obj);
6668     BitProperty *fp = opaque;
6669     uint64_t f = cpu->env.features[fp->w];
6670     bool value = (f & fp->mask) == fp->mask;
6671     visit_type_bool(v, name, &value, errp);
6672 }
6673
6674 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
6675                                  void *opaque, Error **errp)
6676 {
6677     DeviceState *dev = DEVICE(obj);
6678     X86CPU *cpu = X86_CPU(obj);
6679     BitProperty *fp = opaque;
6680     bool value;
6681
6682     if (dev->realized) {
6683         qdev_prop_set_after_realize(dev, name, errp);
6684         return;
6685     }
6686
6687     if (!visit_type_bool(v, name, &value, errp)) {
6688         return;
6689     }
6690
6691     if (value) {
6692         cpu->env.features[fp->w] |= fp->mask;
6693     } else {
6694         cpu->env.features[fp->w] &= ~fp->mask;
6695     }
6696     cpu->env.user_features[fp->w] |= fp->mask;
6697 }
6698
6699 /* Register a boolean property to get/set a single bit in a uint32_t field.
6700  *
6701  * The same property name can be registered multiple times to make it affect
6702  * multiple bits in the same FeatureWord. In that case, the getter will return
6703  * true only if all bits are set.
6704  */
6705 static void x86_cpu_register_bit_prop(X86CPUClass *xcc,
6706                                       const char *prop_name,
6707                                       FeatureWord w,
6708                                       int bitnr)
6709 {
6710     ObjectClass *oc = OBJECT_CLASS(xcc);
6711     BitProperty *fp;
6712     ObjectProperty *op;
6713     uint64_t mask = (1ULL << bitnr);
6714
6715     op = object_class_property_find(oc, prop_name);
6716     if (op) {
6717         fp = op->opaque;
6718         assert(fp->w == w);
6719         fp->mask |= mask;
6720     } else {
6721         fp = g_new0(BitProperty, 1);
6722         fp->w = w;
6723         fp->mask = mask;
6724         object_class_property_add(oc, prop_name, "bool",
6725                                   x86_cpu_get_bit_prop,
6726                                   x86_cpu_set_bit_prop,
6727                                   NULL, fp);
6728     }
6729 }
6730
6731 static void x86_cpu_register_feature_bit_props(X86CPUClass *xcc,
6732                                                FeatureWord w,
6733                                                int bitnr)
6734 {
6735     FeatureWordInfo *fi = &feature_word_info[w];
6736     const char *name = fi->feat_names[bitnr];
6737
6738     if (!name) {
6739         return;
6740     }
6741
6742     /* Property names should use "-" instead of "_".
6743      * Old names containing underscores are registered as aliases
6744      * using object_property_add_alias()
6745      */
6746     assert(!strchr(name, '_'));
6747     /* aliases don't use "|" delimiters anymore, they are registered
6748      * manually using object_property_add_alias() */
6749     assert(!strchr(name, '|'));
6750     x86_cpu_register_bit_prop(xcc, name, w, bitnr);
6751 }
6752
6753 #if !defined(CONFIG_USER_ONLY)
6754 static GuestPanicInformation *x86_cpu_get_crash_info(CPUState *cs)
6755 {
6756     X86CPU *cpu = X86_CPU(cs);
6757     CPUX86State *env = &cpu->env;
6758     GuestPanicInformation *panic_info = NULL;
6759
6760     if (env->features[FEAT_HYPERV_EDX] & HV_GUEST_CRASH_MSR_AVAILABLE) {
6761         panic_info = g_malloc0(sizeof(GuestPanicInformation));
6762
6763         panic_info->type = GUEST_PANIC_INFORMATION_TYPE_HYPER_V;
6764
6765         assert(HV_CRASH_PARAMS >= 5);
6766         panic_info->u.hyper_v.arg1 = env->msr_hv_crash_params[0];
6767         panic_info->u.hyper_v.arg2 = env->msr_hv_crash_params[1];
6768         panic_info->u.hyper_v.arg3 = env->msr_hv_crash_params[2];
6769         panic_info->u.hyper_v.arg4 = env->msr_hv_crash_params[3];
6770         panic_info->u.hyper_v.arg5 = env->msr_hv_crash_params[4];
6771     }
6772
6773     return panic_info;
6774 }
6775 static void x86_cpu_get_crash_info_qom(Object *obj, Visitor *v,
6776                                        const char *name, void *opaque,
6777                                        Error **errp)
6778 {
6779     CPUState *cs = CPU(obj);
6780     GuestPanicInformation *panic_info;
6781
6782     if (!cs->crash_occurred) {
6783         error_setg(errp, "No crash occurred");
6784         return;
6785     }
6786
6787     panic_info = x86_cpu_get_crash_info(cs);
6788     if (panic_info == NULL) {
6789         error_setg(errp, "No crash information");
6790         return;
6791     }
6792
6793     visit_type_GuestPanicInformation(v, "crash-information", &panic_info,
6794                                      errp);
6795     qapi_free_GuestPanicInformation(panic_info);
6796 }
6797 #endif /* !CONFIG_USER_ONLY */
6798
6799 static void x86_cpu_initfn(Object *obj)
6800 {
6801     X86CPU *cpu = X86_CPU(obj);
6802     X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
6803     CPUClass *cc = CPU_CLASS(xcc);
6804
6805     CPUX86State *env = &cpu->env;
6806
6807     env->nr_dies = 1;
6808     cpu_set_cpustate_pointers(cpu);
6809
6810     object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
6811                         x86_cpu_get_feature_words,
6812                         NULL, NULL, (void *)env->features);
6813     object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
6814                         x86_cpu_get_feature_words,
6815                         NULL, NULL, (void *)cpu->filtered_features);
6816
6817     object_property_add_alias(obj, "sse3", obj, "pni");
6818     object_property_add_alias(obj, "pclmuldq", obj, "pclmulqdq");
6819     object_property_add_alias(obj, "sse4-1", obj, "sse4.1");
6820     object_property_add_alias(obj, "sse4-2", obj, "sse4.2");
6821     object_property_add_alias(obj, "xd", obj, "nx");
6822     object_property_add_alias(obj, "ffxsr", obj, "fxsr-opt");
6823     object_property_add_alias(obj, "i64", obj, "lm");
6824
6825     object_property_add_alias(obj, "ds_cpl", obj, "ds-cpl");
6826     object_property_add_alias(obj, "tsc_adjust", obj, "tsc-adjust");
6827     object_property_add_alias(obj, "fxsr_opt", obj, "fxsr-opt");
6828     object_property_add_alias(obj, "lahf_lm", obj, "lahf-lm");
6829     object_property_add_alias(obj, "cmp_legacy", obj, "cmp-legacy");
6830     object_property_add_alias(obj, "nodeid_msr", obj, "nodeid-msr");
6831     object_property_add_alias(obj, "perfctr_core", obj, "perfctr-core");
6832     object_property_add_alias(obj, "perfctr_nb", obj, "perfctr-nb");
6833     object_property_add_alias(obj, "kvm_nopiodelay", obj, "kvm-nopiodelay");
6834     object_property_add_alias(obj, "kvm_mmu", obj, "kvm-mmu");
6835     object_property_add_alias(obj, "kvm_asyncpf", obj, "kvm-asyncpf");
6836     object_property_add_alias(obj, "kvm_asyncpf_int", obj, "kvm-asyncpf-int");
6837     object_property_add_alias(obj, "kvm_steal_time", obj, "kvm-steal-time");
6838     object_property_add_alias(obj, "kvm_pv_eoi", obj, "kvm-pv-eoi");
6839     object_property_add_alias(obj, "kvm_pv_unhalt", obj, "kvm-pv-unhalt");
6840     object_property_add_alias(obj, "kvm_poll_control", obj, "kvm-poll-control");
6841     object_property_add_alias(obj, "svm_lock", obj, "svm-lock");
6842     object_property_add_alias(obj, "nrip_save", obj, "nrip-save");
6843     object_property_add_alias(obj, "tsc_scale", obj, "tsc-scale");
6844     object_property_add_alias(obj, "vmcb_clean", obj, "vmcb-clean");
6845     object_property_add_alias(obj, "pause_filter", obj, "pause-filter");
6846     object_property_add_alias(obj, "sse4_1", obj, "sse4.1");
6847     object_property_add_alias(obj, "sse4_2", obj, "sse4.2");
6848
6849     if (xcc->model) {
6850         x86_cpu_load_model(cpu, xcc->model);
6851     }
6852
6853     /* if required, do the accelerator-specific cpu initialization */
6854     if (cc->accel_cpu) {
6855         cc->accel_cpu->cpu_instance_init(CPU(obj));
6856     }
6857 }
6858
6859 static int64_t x86_cpu_get_arch_id(CPUState *cs)
6860 {
6861     X86CPU *cpu = X86_CPU(cs);
6862
6863     return cpu->apic_id;
6864 }
6865
6866 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
6867 {
6868     X86CPU *cpu = X86_CPU(cs);
6869
6870     return cpu->env.cr[0] & CR0_PG_MASK;
6871 }
6872
6873 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
6874 {
6875     X86CPU *cpu = X86_CPU(cs);
6876
6877     cpu->env.eip = value;
6878 }
6879
6880 int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
6881 {
6882     X86CPU *cpu = X86_CPU(cs);
6883     CPUX86State *env = &cpu->env;
6884
6885 #if !defined(CONFIG_USER_ONLY)
6886     if (interrupt_request & CPU_INTERRUPT_POLL) {
6887         return CPU_INTERRUPT_POLL;
6888     }
6889 #endif
6890     if (interrupt_request & CPU_INTERRUPT_SIPI) {
6891         return CPU_INTERRUPT_SIPI;
6892     }
6893
6894     if (env->hflags2 & HF2_GIF_MASK) {
6895         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
6896             !(env->hflags & HF_SMM_MASK)) {
6897             return CPU_INTERRUPT_SMI;
6898         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
6899                    !(env->hflags2 & HF2_NMI_MASK)) {
6900             return CPU_INTERRUPT_NMI;
6901         } else if (interrupt_request & CPU_INTERRUPT_MCE) {
6902             return CPU_INTERRUPT_MCE;
6903         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
6904                    (((env->hflags2 & HF2_VINTR_MASK) &&
6905                      (env->hflags2 & HF2_HIF_MASK)) ||
6906                     (!(env->hflags2 & HF2_VINTR_MASK) &&
6907                      (env->eflags & IF_MASK &&
6908                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
6909             return CPU_INTERRUPT_HARD;
6910 #if !defined(CONFIG_USER_ONLY)
6911         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
6912                    (env->eflags & IF_MASK) &&
6913                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
6914             return CPU_INTERRUPT_VIRQ;
6915 #endif
6916         }
6917     }
6918
6919     return 0;
6920 }
6921
6922 static bool x86_cpu_has_work(CPUState *cs)
6923 {
6924     return x86_cpu_pending_interrupt(cs, cs->interrupt_request) != 0;
6925 }
6926
6927 static void x86_disas_set_info(CPUState *cs, disassemble_info *info)
6928 {
6929     X86CPU *cpu = X86_CPU(cs);
6930     CPUX86State *env = &cpu->env;
6931
6932     info->mach = (env->hflags & HF_CS64_MASK ? bfd_mach_x86_64
6933                   : env->hflags & HF_CS32_MASK ? bfd_mach_i386_i386
6934                   : bfd_mach_i386_i8086);
6935     info->print_insn = print_insn_i386;
6936
6937     info->cap_arch = CS_ARCH_X86;
6938     info->cap_mode = (env->hflags & HF_CS64_MASK ? CS_MODE_64
6939                       : env->hflags & HF_CS32_MASK ? CS_MODE_32
6940                       : CS_MODE_16);
6941     info->cap_insn_unit = 1;
6942     info->cap_insn_split = 8;
6943 }
6944
6945 void x86_update_hflags(CPUX86State *env)
6946 {
6947    uint32_t hflags;
6948 #define HFLAG_COPY_MASK \
6949     ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
6950        HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
6951        HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
6952        HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
6953
6954     hflags = env->hflags & HFLAG_COPY_MASK;
6955     hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
6956     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
6957     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
6958                 (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
6959     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
6960
6961     if (env->cr[4] & CR4_OSFXSR_MASK) {
6962         hflags |= HF_OSFXSR_MASK;
6963     }
6964
6965     if (env->efer & MSR_EFER_LMA) {
6966         hflags |= HF_LMA_MASK;
6967     }
6968
6969     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
6970         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
6971     } else {
6972         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
6973                     (DESC_B_SHIFT - HF_CS32_SHIFT);
6974         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
6975                     (DESC_B_SHIFT - HF_SS32_SHIFT);
6976         if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK) ||
6977             !(hflags & HF_CS32_MASK)) {
6978             hflags |= HF_ADDSEG_MASK;
6979         } else {
6980             hflags |= ((env->segs[R_DS].base | env->segs[R_ES].base |
6981                         env->segs[R_SS].base) != 0) << HF_ADDSEG_SHIFT;
6982         }
6983     }
6984     env->hflags = hflags;
6985 }
6986
6987 static Property x86_cpu_properties[] = {
6988 #ifdef CONFIG_USER_ONLY
6989     /* apic_id = 0 by default for *-user, see commit 9886e834 */
6990     DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
6991     DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
6992     DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
6993     DEFINE_PROP_INT32("die-id", X86CPU, die_id, 0),
6994     DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
6995 #else
6996     DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
6997     DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
6998     DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
6999     DEFINE_PROP_INT32("die-id", X86CPU, die_id, -1),
7000     DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
7001 #endif
7002     DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
7003     DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
7004
7005     DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
7006                        HYPERV_SPINLOCK_NEVER_NOTIFY),
7007     DEFINE_PROP_BIT64("hv-relaxed", X86CPU, hyperv_features,
7008                       HYPERV_FEAT_RELAXED, 0),
7009     DEFINE_PROP_BIT64("hv-vapic", X86CPU, hyperv_features,
7010                       HYPERV_FEAT_VAPIC, 0),
7011     DEFINE_PROP_BIT64("hv-time", X86CPU, hyperv_features,
7012                       HYPERV_FEAT_TIME, 0),
7013     DEFINE_PROP_BIT64("hv-crash", X86CPU, hyperv_features,
7014                       HYPERV_FEAT_CRASH, 0),
7015     DEFINE_PROP_BIT64("hv-reset", X86CPU, hyperv_features,
7016                       HYPERV_FEAT_RESET, 0),
7017     DEFINE_PROP_BIT64("hv-vpindex", X86CPU, hyperv_features,
7018                       HYPERV_FEAT_VPINDEX, 0),
7019     DEFINE_PROP_BIT64("hv-runtime", X86CPU, hyperv_features,
7020                       HYPERV_FEAT_RUNTIME, 0),
7021     DEFINE_PROP_BIT64("hv-synic", X86CPU, hyperv_features,
7022                       HYPERV_FEAT_SYNIC, 0),
7023     DEFINE_PROP_BIT64("hv-stimer", X86CPU, hyperv_features,
7024                       HYPERV_FEAT_STIMER, 0),
7025     DEFINE_PROP_BIT64("hv-frequencies", X86CPU, hyperv_features,
7026                       HYPERV_FEAT_FREQUENCIES, 0),
7027     DEFINE_PROP_BIT64("hv-reenlightenment", X86CPU, hyperv_features,
7028                       HYPERV_FEAT_REENLIGHTENMENT, 0),
7029     DEFINE_PROP_BIT64("hv-tlbflush", X86CPU, hyperv_features,
7030                       HYPERV_FEAT_TLBFLUSH, 0),
7031     DEFINE_PROP_BIT64("hv-evmcs", X86CPU, hyperv_features,
7032                       HYPERV_FEAT_EVMCS, 0),
7033     DEFINE_PROP_BIT64("hv-ipi", X86CPU, hyperv_features,
7034                       HYPERV_FEAT_IPI, 0),
7035     DEFINE_PROP_BIT64("hv-stimer-direct", X86CPU, hyperv_features,
7036                       HYPERV_FEAT_STIMER_DIRECT, 0),
7037     DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU,
7038                             hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF),
7039     DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false),
7040
7041     DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
7042     DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
7043     DEFINE_PROP_BOOL("x-force-features", X86CPU, force_features, false),
7044     DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
7045     DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
7046     DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
7047     DEFINE_PROP_UINT8("host-phys-bits-limit", X86CPU, host_phys_bits_limit, 0),
7048     DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
7049     DEFINE_PROP_UINT32("level-func7", X86CPU, env.cpuid_level_func7,
7050                        UINT32_MAX),
7051     DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, UINT32_MAX),
7052     DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, UINT32_MAX),
7053     DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, UINT32_MAX),
7054     DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0),
7055     DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0),
7056     DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0),
7057     DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0),
7058     DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_level, true),
7059     DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor),
7060     DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
7061     DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
7062     DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
7063     DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
7064                      false),
7065     DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
7066     DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
7067     DEFINE_PROP_BOOL("x-migrate-smi-count", X86CPU, migrate_smi_count,
7068                      true),
7069     /*
7070      * lecacy_cache defaults to true unless the CPU model provides its
7071      * own cache information (see x86_cpu_load_def()).
7072      */
7073     DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, true),
7074
7075     /*
7076      * From "Requirements for Implementing the Microsoft
7077      * Hypervisor Interface":
7078      * https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
7079      *
7080      * "Starting with Windows Server 2012 and Windows 8, if
7081      * CPUID.40000005.EAX contains a value of -1, Windows assumes that
7082      * the hypervisor imposes no specific limit to the number of VPs.
7083      * In this case, Windows Server 2012 guest VMs may use more than
7084      * 64 VPs, up to the maximum supported number of processors applicable
7085      * to the specific Windows version being used."
7086      */
7087     DEFINE_PROP_INT32("x-hv-max-vps", X86CPU, hv_max_vps, -1),
7088     DEFINE_PROP_BOOL("x-hv-synic-kvm-only", X86CPU, hyperv_synic_kvm_only,
7089                      false),
7090     DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level,
7091                      true),
7092     DEFINE_PROP_END_OF_LIST()
7093 };
7094
7095 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
7096 {
7097     X86CPUClass *xcc = X86_CPU_CLASS(oc);
7098     CPUClass *cc = CPU_CLASS(oc);
7099     DeviceClass *dc = DEVICE_CLASS(oc);
7100     FeatureWord w;
7101
7102     device_class_set_parent_realize(dc, x86_cpu_realizefn,
7103                                     &xcc->parent_realize);
7104     device_class_set_parent_unrealize(dc, x86_cpu_unrealizefn,
7105                                       &xcc->parent_unrealize);
7106     device_class_set_props(dc, x86_cpu_properties);
7107
7108     device_class_set_parent_reset(dc, x86_cpu_reset, &xcc->parent_reset);
7109     cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
7110
7111     cc->class_by_name = x86_cpu_class_by_name;
7112     cc->parse_features = x86_cpu_parse_featurestr;
7113     cc->has_work = x86_cpu_has_work;
7114     cc->dump_state = x86_cpu_dump_state;
7115     cc->set_pc = x86_cpu_set_pc;
7116     cc->gdb_read_register = x86_cpu_gdb_read_register;
7117     cc->gdb_write_register = x86_cpu_gdb_write_register;
7118     cc->get_arch_id = x86_cpu_get_arch_id;
7119     cc->get_paging_enabled = x86_cpu_get_paging_enabled;
7120
7121 #ifndef CONFIG_USER_ONLY
7122     cc->asidx_from_attrs = x86_asidx_from_attrs;
7123     cc->get_memory_mapping = x86_cpu_get_memory_mapping;
7124     cc->get_phys_page_attrs_debug = x86_cpu_get_phys_page_attrs_debug;
7125     cc->get_crash_info = x86_cpu_get_crash_info;
7126     cc->write_elf64_note = x86_cpu_write_elf64_note;
7127     cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
7128     cc->write_elf32_note = x86_cpu_write_elf32_note;
7129     cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
7130     cc->vmsd = &vmstate_x86_cpu;
7131 #endif /* !CONFIG_USER_ONLY */
7132
7133     cc->gdb_arch_name = x86_gdb_arch_name;
7134 #ifdef TARGET_X86_64
7135     cc->gdb_core_xml_file = "i386-64bit.xml";
7136     cc->gdb_num_core_regs = 66;
7137 #else
7138     cc->gdb_core_xml_file = "i386-32bit.xml";
7139     cc->gdb_num_core_regs = 50;
7140 #endif
7141     cc->disas_set_info = x86_disas_set_info;
7142
7143     dc->user_creatable = true;
7144
7145     object_class_property_add(oc, "family", "int",
7146                               x86_cpuid_version_get_family,
7147                               x86_cpuid_version_set_family, NULL, NULL);
7148     object_class_property_add(oc, "model", "int",
7149                               x86_cpuid_version_get_model,
7150                               x86_cpuid_version_set_model, NULL, NULL);
7151     object_class_property_add(oc, "stepping", "int",
7152                               x86_cpuid_version_get_stepping,
7153                               x86_cpuid_version_set_stepping, NULL, NULL);
7154     object_class_property_add_str(oc, "vendor",
7155                                   x86_cpuid_get_vendor,
7156                                   x86_cpuid_set_vendor);
7157     object_class_property_add_str(oc, "model-id",
7158                                   x86_cpuid_get_model_id,
7159                                   x86_cpuid_set_model_id);
7160     object_class_property_add(oc, "tsc-frequency", "int",
7161                               x86_cpuid_get_tsc_freq,
7162                               x86_cpuid_set_tsc_freq, NULL, NULL);
7163     /*
7164      * The "unavailable-features" property has the same semantics as
7165      * CpuDefinitionInfo.unavailable-features on the "query-cpu-definitions"
7166      * QMP command: they list the features that would have prevented the
7167      * CPU from running if the "enforce" flag was set.
7168      */
7169     object_class_property_add(oc, "unavailable-features", "strList",
7170                               x86_cpu_get_unavailable_features,
7171                               NULL, NULL, NULL);
7172
7173 #if !defined(CONFIG_USER_ONLY)
7174     object_class_property_add(oc, "crash-information", "GuestPanicInformation",
7175                               x86_cpu_get_crash_info_qom, NULL, NULL, NULL);
7176 #endif
7177
7178     for (w = 0; w < FEATURE_WORDS; w++) {
7179         int bitnr;
7180         for (bitnr = 0; bitnr < 64; bitnr++) {
7181             x86_cpu_register_feature_bit_props(xcc, w, bitnr);
7182         }
7183     }
7184 }
7185
7186 static const TypeInfo x86_cpu_type_info = {
7187     .name = TYPE_X86_CPU,
7188     .parent = TYPE_CPU,
7189     .instance_size = sizeof(X86CPU),
7190     .instance_init = x86_cpu_initfn,
7191     .abstract = true,
7192     .class_size = sizeof(X86CPUClass),
7193     .class_init = x86_cpu_common_class_init,
7194 };
7195
7196
7197 /* "base" CPU model, used by query-cpu-model-expansion */
7198 static void x86_cpu_base_class_init(ObjectClass *oc, void *data)
7199 {
7200     X86CPUClass *xcc = X86_CPU_CLASS(oc);
7201
7202     xcc->static_model = true;
7203     xcc->migration_safe = true;
7204     xcc->model_description = "base CPU model type with no features enabled";
7205     xcc->ordering = 8;
7206 }
7207
7208 static const TypeInfo x86_base_cpu_type_info = {
7209         .name = X86_CPU_TYPE_NAME("base"),
7210         .parent = TYPE_X86_CPU,
7211         .class_init = x86_cpu_base_class_init,
7212 };
7213
7214 static void x86_cpu_register_types(void)
7215 {
7216     int i;
7217
7218     type_register_static(&x86_cpu_type_info);
7219     for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
7220         x86_register_cpudef_types(&builtin_x86_defs[i]);
7221     }
7222     type_register_static(&max_x86_cpu_type_info);
7223     type_register_static(&x86_base_cpu_type_info);
7224 }
7225
7226 type_init(x86_cpu_register_types)