1 #include "qemu/osdep.h"
2 #include "qapi/error.h"
3 #include "sysemu/hw_accel.h"
4 #include "sysemu/sysemu.h"
6 #include "qemu/error-report.h"
8 #include "exec/exec-all.h"
9 #include "helper_regs.h"
10 #include "hw/ppc/spapr.h"
11 #include "mmu-hash64.h"
12 #include "cpu-models.h"
15 #include "hw/ppc/spapr_ovec.h"
16 #include "mmu-book3s-v3.h"
17 #include "hw/mem/memory-device.h"
19 struct LPCRSyncState {
24 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg)
26 struct LPCRSyncState *s = arg.host_ptr;
27 PowerPCCPU *cpu = POWERPC_CPU(cs);
28 CPUPPCState *env = &cpu->env;
31 cpu_synchronize_state(cs);
32 lpcr = env->spr[SPR_LPCR];
35 ppc_store_lpcr(cpu, lpcr);
38 static void set_all_lpcrs(target_ulong value, target_ulong mask)
41 struct LPCRSyncState s = {
46 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s));
50 static bool has_spr(PowerPCCPU *cpu, int spr)
52 /* We can test whether the SPR is defined by checking for a valid name */
53 return cpu->env.spr_cb[spr].name != NULL;
56 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex)
59 * hash value/pteg group index is normalized by HPT mask
61 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) {
67 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr)
69 MachineState *machine = MACHINE(spapr);
70 MemoryHotplugState *hpms = &spapr->hotplug_memory;
72 if (addr < machine->ram_size) {
75 if ((addr >= hpms->base)
76 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) {
83 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr,
84 target_ulong opcode, target_ulong *args)
86 target_ulong flags = args[0];
87 target_ulong ptex = args[1];
88 target_ulong pteh = args[2];
89 target_ulong ptel = args[3];
93 const ppc_hash_pte64_t *hptes;
95 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel);
97 /* Bad page size encoding */
101 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
103 if (is_ram_address(spapr, raddr)) {
104 /* Regular RAM - should have WIMG=0010 */
105 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) {
109 target_ulong wimg_flags;
110 /* Looks like an IO address */
111 /* FIXME: What WIMG combinations could be sensible for IO?
112 * For now we allow WIMG=010x, but are there others? */
113 /* FIXME: Should we check against registered IO addresses? */
114 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M));
116 if (wimg_flags != HPTE64_R_I &&
117 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) {
124 if (!valid_ptex(cpu, ptex)) {
131 if (likely((flags & H_EXACT) == 0)) {
132 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
133 for (slot = 0; slot < 8; slot++) {
134 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) {
138 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
143 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1);
144 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) {
145 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1);
148 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
151 ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel);
153 args[0] = ptex + slot;
159 REMOVE_NOT_FOUND = 1,
164 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex,
167 target_ulong *vp, target_ulong *rp)
169 const ppc_hash_pte64_t *hptes;
172 if (!valid_ptex(cpu, ptex)) {
176 hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
177 v = ppc_hash64_hpte0(cpu, hptes, 0);
178 r = ppc_hash64_hpte1(cpu, hptes, 0);
179 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
181 if ((v & HPTE64_V_VALID) == 0 ||
182 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
183 ((flags & H_ANDCOND) && (v & avpn) != 0)) {
184 return REMOVE_NOT_FOUND;
188 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0);
189 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
190 return REMOVE_SUCCESS;
193 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
194 target_ulong opcode, target_ulong *args)
196 CPUPPCState *env = &cpu->env;
197 target_ulong flags = args[0];
198 target_ulong ptex = args[1];
199 target_ulong avpn = args[2];
202 ret = remove_hpte(cpu, ptex, avpn, flags,
207 check_tlb_flush(env, true);
210 case REMOVE_NOT_FOUND:
220 g_assert_not_reached();
223 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL
224 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL
225 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL
226 #define H_BULK_REMOVE_END 0xc000000000000000ULL
227 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL
228 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL
229 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL
230 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL
231 #define H_BULK_REMOVE_HW 0x3000000000000000ULL
232 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL
233 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL
234 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL
235 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL
236 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL
237 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL
239 #define H_BULK_REMOVE_MAX_BATCH 4
241 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr,
242 target_ulong opcode, target_ulong *args)
244 CPUPPCState *env = &cpu->env;
246 target_ulong rc = H_SUCCESS;
248 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) {
249 target_ulong *tsh = &args[i*2];
250 target_ulong tsl = args[i*2 + 1];
251 target_ulong v, r, ret;
253 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
255 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) {
259 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS;
260 *tsh |= H_BULK_REMOVE_RESPONSE;
262 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
263 *tsh |= H_BULK_REMOVE_PARM;
267 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl,
268 (*tsh & H_BULK_REMOVE_FLAGS) >> 26,
275 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43;
288 check_tlb_flush(env, true);
293 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr,
294 target_ulong opcode, target_ulong *args)
296 CPUPPCState *env = &cpu->env;
297 target_ulong flags = args[0];
298 target_ulong ptex = args[1];
299 target_ulong avpn = args[2];
300 const ppc_hash_pte64_t *hptes;
303 if (!valid_ptex(cpu, ptex)) {
307 hptes = ppc_hash64_map_hptes(cpu, ptex, 1);
308 v = ppc_hash64_hpte0(cpu, hptes, 0);
309 r = ppc_hash64_hpte1(cpu, hptes, 0);
310 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1);
312 if ((v & HPTE64_V_VALID) == 0 ||
313 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
317 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N |
318 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO);
319 r |= (flags << 55) & HPTE64_R_PP0;
320 r |= (flags << 48) & HPTE64_R_KEY_HI;
321 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO);
322 ppc_hash64_store_hpte(cpu, ptex,
323 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0);
324 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r);
326 check_tlb_flush(env, true);
327 /* Don't need a memory barrier, due to qemu's global lock */
328 ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r);
332 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr,
333 target_ulong opcode, target_ulong *args)
335 target_ulong flags = args[0];
336 target_ulong ptex = args[1];
338 int i, ridx, n_entries = 1;
340 if (!valid_ptex(cpu, ptex)) {
344 if (flags & H_READ_4) {
345 /* Clear the two low order bits */
350 hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64);
352 for (i = 0, ridx = 0; i < n_entries; i++) {
353 args[ridx++] = ldq_p(hpte);
354 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
355 hpte += HASH_PTE_SIZE_64;
361 struct sPAPRPendingHPT {
362 /* These fields are read-only after initialization */
366 /* These fields are protected by the BQL */
369 /* These fields are private to the preparation thread if
370 * !complete, otherwise protected by the BQL */
375 static void free_pending_hpt(sPAPRPendingHPT *pending)
378 qemu_vfree(pending->hpt);
384 static void *hpt_prepare_thread(void *opaque)
386 sPAPRPendingHPT *pending = opaque;
387 size_t size = 1ULL << pending->shift;
389 pending->hpt = qemu_memalign(size, size);
391 memset(pending->hpt, 0, size);
392 pending->ret = H_SUCCESS;
394 pending->ret = H_NO_MEM;
397 qemu_mutex_lock_iothread();
399 if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) {
401 pending->complete = true;
403 /* We've been cancelled, clean ourselves up */
404 free_pending_hpt(pending);
407 qemu_mutex_unlock_iothread();
411 /* Must be called with BQL held */
412 static void cancel_hpt_prepare(sPAPRMachineState *spapr)
414 sPAPRPendingHPT *pending = spapr->pending_hpt;
416 /* Let the thread know it's cancelled */
417 spapr->pending_hpt = NULL;
424 if (!pending->complete) {
425 /* thread will clean itself up */
429 free_pending_hpt(pending);
432 /* Convert a return code from the KVM ioctl()s implementing resize HPT
433 * into a PAPR hypercall return code */
434 static target_ulong resize_hpt_convert_rc(int ret)
437 return H_LONG_BUSY_ORDER_100_SEC;
438 } else if (ret >= 10000) {
439 return H_LONG_BUSY_ORDER_10_SEC;
440 } else if (ret >= 1000) {
441 return H_LONG_BUSY_ORDER_1_SEC;
442 } else if (ret >= 100) {
443 return H_LONG_BUSY_ORDER_100_MSEC;
444 } else if (ret >= 10) {
445 return H_LONG_BUSY_ORDER_10_MSEC;
446 } else if (ret > 0) {
447 return H_LONG_BUSY_ORDER_1_MSEC;
470 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu,
471 sPAPRMachineState *spapr,
475 target_ulong flags = args[0];
477 sPAPRPendingHPT *pending = spapr->pending_hpt;
478 uint64_t current_ram_size;
481 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
485 if (!spapr->htab_shift) {
486 /* Radix guest, no HPT */
487 return H_NOT_AVAILABLE;
490 trace_spapr_h_resize_hpt_prepare(flags, shift);
496 if (shift && ((shift < 18) || (shift > 46))) {
500 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size();
502 /* We only allow the guest to allocate an HPT one order above what
503 * we'd normally give them (to stop a small guest claiming a huge
504 * chunk of resources in the HPT */
505 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) {
509 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift);
511 return resize_hpt_convert_rc(rc);
515 /* something already in progress */
516 if (pending->shift == shift) {
517 /* and it's suitable */
518 if (pending->complete) {
521 return H_LONG_BUSY_ORDER_100_MSEC;
525 /* not suitable, cancel and replace */
526 cancel_hpt_prepare(spapr);
534 /* start new prepare */
536 pending = g_new0(sPAPRPendingHPT, 1);
537 pending->shift = shift;
538 pending->ret = H_HARDWARE;
540 qemu_thread_create(&pending->thread, "sPAPR HPT prepare",
541 hpt_prepare_thread, pending, QEMU_THREAD_DETACHED);
543 spapr->pending_hpt = pending;
545 /* In theory we could estimate the time more accurately based on
546 * the new size, but there's not much point */
547 return H_LONG_BUSY_ORDER_100_MSEC;
550 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot)
552 uint8_t *addr = htab;
554 addr += pteg * HASH_PTEG_SIZE_64;
555 addr += slot * HASH_PTE_SIZE_64;
559 static void new_hpte_store(void *htab, uint64_t pteg, int slot,
560 uint64_t pte0, uint64_t pte1)
562 uint8_t *addr = htab;
564 addr += pteg * HASH_PTEG_SIZE_64;
565 addr += slot * HASH_PTE_SIZE_64;
568 stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1);
571 static int rehash_hpte(PowerPCCPU *cpu,
572 const ppc_hash_pte64_t *hptes,
573 void *old_hpt, uint64_t oldsize,
574 void *new_hpt, uint64_t newsize,
575 uint64_t pteg, int slot)
577 uint64_t old_hash_mask = (oldsize >> 7) - 1;
578 uint64_t new_hash_mask = (newsize >> 7) - 1;
579 target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot);
582 unsigned base_pg_shift;
583 uint64_t hash, new_pteg, replace_pte0;
585 if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) {
589 pte1 = ppc_hash64_hpte1(cpu, hptes, slot);
591 base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1);
592 assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */
593 avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23);
595 if (pte0 & HPTE64_V_SECONDARY) {
599 if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) {
600 uint64_t offset, vsid;
602 /* We only have 28 - 23 bits of offset in avpn */
603 offset = (avpn & 0x1f) << 23;
605 /* We can find more bits from the pteg value */
606 if (base_pg_shift < 23) {
607 offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift;
610 hash = vsid ^ (offset >> base_pg_shift);
611 } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) {
612 uint64_t offset, vsid;
614 /* We only have 40 - 23 bits of seg_off in avpn */
615 offset = (avpn & 0x1ffff) << 23;
617 if (base_pg_shift < 23) {
618 offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask)
622 hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift);
624 error_report("rehash_pte: Bad segment size in HPTE");
628 new_pteg = hash & new_hash_mask;
629 if (pte0 & HPTE64_V_SECONDARY) {
630 assert(~pteg == (hash & old_hash_mask));
631 new_pteg = ~new_pteg;
633 assert(pteg == (hash & old_hash_mask));
635 assert((oldsize != newsize) || (pteg == new_pteg));
636 replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot);
638 * Strictly speaking, we don't need all these tests, since we only
639 * ever rehash bolted HPTEs. We might in future handle non-bolted
640 * HPTEs, though so make the logic correct for those cases as
643 if (replace_pte0 & HPTE64_V_VALID) {
644 assert(newsize < oldsize);
645 if (replace_pte0 & HPTE64_V_BOLTED) {
646 if (pte0 & HPTE64_V_BOLTED) {
647 /* Bolted collision, nothing we can do */
650 /* Discard this hpte */
656 new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1);
660 static int rehash_hpt(PowerPCCPU *cpu,
661 void *old_hpt, uint64_t oldsize,
662 void *new_hpt, uint64_t newsize)
664 uint64_t n_ptegs = oldsize >> 7;
669 for (pteg = 0; pteg < n_ptegs; pteg++) {
670 hwaddr ptex = pteg * HPTES_PER_GROUP;
671 const ppc_hash_pte64_t *hptes
672 = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP);
678 for (slot = 0; slot < HPTES_PER_GROUP; slot++) {
679 rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize,
681 if (rc != H_SUCCESS) {
682 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
686 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP);
692 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data)
696 cpu_synchronize_state(cs);
698 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs));
700 error_report("failed to push sregs to KVM: %s", strerror(-ret));
705 static void push_sregs_to_kvm_pr(sPAPRMachineState *spapr)
710 * This is a hack for the benefit of KVM PR - it abuses the SDR1
711 * slot in kvm_sregs to communicate the userspace address of the
714 if (!kvm_enabled() || !spapr->htab) {
719 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL);
723 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu,
724 sPAPRMachineState *spapr,
728 target_ulong flags = args[0];
729 target_ulong shift = args[1];
730 sPAPRPendingHPT *pending = spapr->pending_hpt;
734 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) {
738 if (!spapr->htab_shift) {
739 /* Radix guest, no HPT */
740 return H_NOT_AVAILABLE;
743 trace_spapr_h_resize_hpt_commit(flags, shift);
745 rc = kvmppc_resize_hpt_commit(cpu, flags, shift);
747 rc = resize_hpt_convert_rc(rc);
748 if (rc == H_SUCCESS) {
749 /* Need to set the new htab_shift in the machine state */
750 spapr->htab_shift = shift;
759 if (!pending || (pending->shift != shift)) {
760 /* no matching prepare */
764 if (!pending->complete) {
765 /* prepare has not completed */
769 /* Shouldn't have got past PREPARE without an HPT */
770 g_assert(spapr->htab_shift);
772 newsize = 1ULL << pending->shift;
773 rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr),
774 pending->hpt, newsize);
775 if (rc == H_SUCCESS) {
776 qemu_vfree(spapr->htab);
777 spapr->htab = pending->hpt;
778 spapr->htab_shift = pending->shift;
780 push_sregs_to_kvm_pr(spapr);
782 pending->hpt = NULL; /* so it's not free()d */
786 spapr->pending_hpt = NULL;
787 free_pending_hpt(pending);
792 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr,
793 target_ulong opcode, target_ulong *args)
795 cpu_synchronize_state(CPU(cpu));
796 cpu->env.spr[SPR_SPRG0] = args[0];
801 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
802 target_ulong opcode, target_ulong *args)
804 if (!has_spr(cpu, SPR_DABR)) {
805 return H_HARDWARE; /* DABR register not available */
807 cpu_synchronize_state(CPU(cpu));
809 if (has_spr(cpu, SPR_DABRX)) {
810 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */
811 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */
812 return H_RESERVED_DABR;
815 cpu->env.spr[SPR_DABR] = args[0];
819 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
820 target_ulong opcode, target_ulong *args)
822 target_ulong dabrx = args[1];
824 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) {
828 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0
829 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) {
833 cpu_synchronize_state(CPU(cpu));
834 cpu->env.spr[SPR_DABRX] = dabrx;
835 cpu->env.spr[SPR_DABR] = args[0];
840 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr,
841 target_ulong opcode, target_ulong *args)
843 target_ulong flags = args[0];
844 hwaddr dst = args[1];
845 hwaddr src = args[2];
846 hwaddr len = TARGET_PAGE_SIZE;
847 uint8_t *pdst, *psrc;
848 target_long ret = H_SUCCESS;
850 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE
851 | H_COPY_PAGE | H_ZERO_PAGE)) {
852 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n",
857 /* Map-in destination */
858 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) {
861 pdst = cpu_physical_memory_map(dst, &len, 1);
862 if (!pdst || len != TARGET_PAGE_SIZE) {
866 if (flags & H_COPY_PAGE) {
867 /* Map-in source, copy to destination, and unmap source again */
868 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) {
872 psrc = cpu_physical_memory_map(src, &len, 0);
873 if (!psrc || len != TARGET_PAGE_SIZE) {
877 memcpy(pdst, psrc, len);
878 cpu_physical_memory_unmap(psrc, len, 0, len);
879 } else if (flags & H_ZERO_PAGE) {
880 memset(pdst, 0, len); /* Just clear the destination page */
883 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) {
884 kvmppc_dcbst_range(cpu, pdst, len);
886 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) {
888 kvmppc_icbi_range(cpu, pdst, len);
895 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len);
899 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL
900 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL
901 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL
902 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL
903 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL
904 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL
906 #define VPA_MIN_SIZE 640
907 #define VPA_SIZE_OFFSET 0x4
908 #define VPA_SHARED_PROC_OFFSET 0x9
909 #define VPA_SHARED_PROC_VAL 0x2
911 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa)
913 CPUState *cs = CPU(ppc_env_get_cpu(env));
918 hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
922 if (vpa % env->dcache_line_size) {
925 /* FIXME: bounds check the address */
927 size = lduw_be_phys(cs->as, vpa + 0x4);
929 if (size < VPA_MIN_SIZE) {
933 /* VPA is not allowed to cross a page boundary */
934 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) {
940 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET);
941 tmp |= VPA_SHARED_PROC_VAL;
942 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp);
947 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa)
949 if (env->slb_shadow_addr) {
961 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr)
963 CPUState *cs = CPU(ppc_env_get_cpu(env));
967 hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
971 size = ldl_be_phys(cs->as, addr + 0x4);
976 if ((addr / 4096) != ((addr + size - 1) / 4096)) {
980 if (!env->vpa_addr) {
984 env->slb_shadow_addr = addr;
985 env->slb_shadow_size = size;
990 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr)
992 env->slb_shadow_addr = 0;
993 env->slb_shadow_size = 0;
997 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr)
999 CPUState *cs = CPU(ppc_env_get_cpu(env));
1003 hcall_dprintf("Can't cope with DTL at logical 0\n");
1007 size = ldl_be_phys(cs->as, addr + 0x4);
1013 if (!env->vpa_addr) {
1017 env->dtl_addr = addr;
1018 env->dtl_size = size;
1023 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr)
1031 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1032 target_ulong opcode, target_ulong *args)
1034 target_ulong flags = args[0];
1035 target_ulong procno = args[1];
1036 target_ulong vpa = args[2];
1037 target_ulong ret = H_PARAMETER;
1041 tcpu = spapr_find_cpu(procno);
1048 case FLAGS_REGISTER_VPA:
1049 ret = register_vpa(tenv, vpa);
1052 case FLAGS_DEREGISTER_VPA:
1053 ret = deregister_vpa(tenv, vpa);
1056 case FLAGS_REGISTER_SLBSHADOW:
1057 ret = register_slb_shadow(tenv, vpa);
1060 case FLAGS_DEREGISTER_SLBSHADOW:
1061 ret = deregister_slb_shadow(tenv, vpa);
1064 case FLAGS_REGISTER_DTL:
1065 ret = register_dtl(tenv, vpa);
1068 case FLAGS_DEREGISTER_DTL:
1069 ret = deregister_dtl(tenv, vpa);
1076 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1077 target_ulong opcode, target_ulong *args)
1079 CPUPPCState *env = &cpu->env;
1080 CPUState *cs = CPU(cpu);
1082 env->msr |= (1ULL << MSR_EE);
1083 hreg_compute_hflags(env);
1084 if (!cpu_has_work(cs)) {
1086 cs->exception_index = EXCP_HLT;
1087 cs->exit_request = 1;
1092 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1093 target_ulong opcode, target_ulong *args)
1095 target_ulong rtas_r3 = args[0];
1096 uint32_t token = rtas_ld(rtas_r3, 0);
1097 uint32_t nargs = rtas_ld(rtas_r3, 1);
1098 uint32_t nret = rtas_ld(rtas_r3, 2);
1100 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12,
1101 nret, rtas_r3 + 12 + 4*nargs);
1104 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1105 target_ulong opcode, target_ulong *args)
1107 CPUState *cs = CPU(cpu);
1108 target_ulong size = args[0];
1109 target_ulong addr = args[1];
1113 args[0] = ldub_phys(cs->as, addr);
1116 args[0] = lduw_phys(cs->as, addr);
1119 args[0] = ldl_phys(cs->as, addr);
1122 args[0] = ldq_phys(cs->as, addr);
1128 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1129 target_ulong opcode, target_ulong *args)
1131 CPUState *cs = CPU(cpu);
1133 target_ulong size = args[0];
1134 target_ulong addr = args[1];
1135 target_ulong val = args[2];
1139 stb_phys(cs->as, addr, val);
1142 stw_phys(cs->as, addr, val);
1145 stl_phys(cs->as, addr, val);
1148 stq_phys(cs->as, addr, val);
1154 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1155 target_ulong opcode, target_ulong *args)
1157 CPUState *cs = CPU(cpu);
1159 target_ulong dst = args[0]; /* Destination address */
1160 target_ulong src = args[1]; /* Source address */
1161 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */
1162 target_ulong count = args[3]; /* Element count */
1163 target_ulong op = args[4]; /* 0 = copy, 1 = invert */
1165 unsigned int mask = (1 << esize) - 1;
1166 int step = 1 << esize;
1168 if (count > 0x80000000) {
1172 if ((dst & mask) || (src & mask) || (op > 1)) {
1176 if (dst >= src && dst < (src + (count << esize))) {
1177 dst = dst + ((count - 1) << esize);
1178 src = src + ((count - 1) << esize);
1185 tmp = ldub_phys(cs->as, src);
1188 tmp = lduw_phys(cs->as, src);
1191 tmp = ldl_phys(cs->as, src);
1194 tmp = ldq_phys(cs->as, src);
1204 stb_phys(cs->as, dst, tmp);
1207 stw_phys(cs->as, dst, tmp);
1210 stl_phys(cs->as, dst, tmp);
1213 stq_phys(cs->as, dst, tmp);
1223 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1224 target_ulong opcode, target_ulong *args)
1226 /* Nothing to do on emulation, KVM will trap this in the kernel */
1230 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1231 target_ulong opcode, target_ulong *args)
1233 /* Nothing to do on emulation, KVM will trap this in the kernel */
1237 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu,
1238 target_ulong mflags,
1239 target_ulong value1,
1240 target_ulong value2)
1250 case H_SET_MODE_ENDIAN_BIG:
1251 set_all_lpcrs(0, LPCR_ILE);
1252 spapr_pci_switch_vga(true);
1255 case H_SET_MODE_ENDIAN_LITTLE:
1256 set_all_lpcrs(LPCR_ILE, LPCR_ILE);
1257 spapr_pci_switch_vga(false);
1261 return H_UNSUPPORTED_FLAG;
1264 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu,
1265 target_ulong mflags,
1266 target_ulong value1,
1267 target_ulong value2)
1269 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
1271 if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
1281 if (mflags == AIL_RESERVED) {
1282 return H_UNSUPPORTED_FLAG;
1285 set_all_lpcrs(mflags << LPCR_AIL_SHIFT, LPCR_AIL);
1290 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1291 target_ulong opcode, target_ulong *args)
1293 target_ulong resource = args[1];
1294 target_ulong ret = H_P2;
1297 case H_SET_MODE_RESOURCE_LE:
1298 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]);
1300 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE:
1301 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0],
1309 static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1310 target_ulong opcode, target_ulong *args)
1312 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
1313 opcode, " (H_CLEAN_SLB)");
1317 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr,
1318 target_ulong opcode, target_ulong *args)
1320 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n",
1321 opcode, " (H_INVALIDATE_PID)");
1325 static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr,
1326 uint64_t patbe_old, uint64_t patbe_new)
1329 * We have 4 Options:
1330 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing
1331 * HASH->RADIX : Free HPT
1332 * RADIX->HASH : Allocate HPT
1333 * NOTHING->HASH : Allocate HPT
1334 * Note: NOTHING implies the case where we said the guest could choose
1335 * later and so assumed radix and now it's called H_REG_PROC_TBL
1338 if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) {
1339 /* We assume RADIX, so this catches all the "Do Nothing" cases */
1340 } else if (!(patbe_old & PATBE1_GR)) {
1341 /* HASH->RADIX : Free HPT */
1342 spapr_free_hpt(spapr);
1343 } else if (!(patbe_new & PATBE1_GR)) {
1344 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */
1345 spapr_setup_hpt_and_vrma(spapr);
1350 #define FLAGS_MASK 0x01FULL
1351 #define FLAG_MODIFY 0x10
1352 #define FLAG_REGISTER 0x08
1353 #define FLAG_RADIX 0x04
1354 #define FLAG_HASH_PROC_TBL 0x02
1355 #define FLAG_GTSE 0x01
1357 static target_ulong h_register_process_table(PowerPCCPU *cpu,
1358 sPAPRMachineState *spapr,
1359 target_ulong opcode,
1362 target_ulong flags = args[0];
1363 target_ulong proc_tbl = args[1];
1364 target_ulong page_size = args[2];
1365 target_ulong table_size = args[3];
1368 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */
1371 if (flags & FLAG_MODIFY) {
1372 if (flags & FLAG_REGISTER) {
1373 if (flags & FLAG_RADIX) { /* Register new RADIX process table */
1374 if (proc_tbl & 0xfff || proc_tbl >> 60) {
1376 } else if (page_size) {
1378 } else if (table_size > 24) {
1381 cproc = PATBE1_GR | proc_tbl | table_size;
1382 } else { /* Register new HPT process table */
1383 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */
1384 /* TODO - Not Supported */
1385 /* Technically caused by flag bits => H_PARAMETER */
1387 } else { /* Hash with SLB */
1388 if (proc_tbl >> 38) {
1390 } else if (page_size & ~0x7) {
1392 } else if (table_size > 24) {
1396 cproc = (proc_tbl << 25) | page_size << 5 | table_size;
1399 } else { /* Deregister current process table */
1400 /* Set to benign value: (current GR) | 0. This allows
1401 * deregistration in KVM to succeed even if the radix bit in flags
1402 * doesn't match the radix bit in the old PATB. */
1403 cproc = spapr->patb_entry & PATBE1_GR;
1405 } else { /* Maintain current registration */
1406 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) {
1407 /* Technically caused by flag bits => H_PARAMETER */
1408 return H_PARAMETER; /* Existing Process Table Mismatch */
1410 cproc = spapr->patb_entry;
1413 /* Check if we need to setup OR free the hpt */
1414 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc);
1416 spapr->patb_entry = cproc; /* Save new process table */
1418 /* Update the UPRT and GTSE bits in the LPCR for all cpus */
1419 set_all_lpcrs(((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) |
1420 ((flags & FLAG_GTSE) ? LPCR_GTSE : 0),
1421 LPCR_UPRT | LPCR_GTSE);
1423 if (kvm_enabled()) {
1424 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX,
1425 flags & FLAG_GTSE, cproc);
1430 #define H_SIGNAL_SYS_RESET_ALL -1
1431 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2
1433 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
1434 sPAPRMachineState *spapr,
1435 target_ulong opcode, target_ulong *args)
1437 target_long target = args[0];
1442 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1447 PowerPCCPU *c = POWERPC_CPU(cs);
1449 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) {
1454 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1460 cs = CPU(spapr_find_cpu(target));
1462 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
1469 static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu,
1470 target_ulong *addr, bool *raw_mode_supported,
1473 bool explicit_match = false; /* Matched the CPU's real PVR */
1474 uint32_t max_compat = spapr->max_compat_pvr;
1475 uint32_t best_compat = 0;
1479 * We scan the supplied table of PVRs looking for two things
1480 * 1. Is our real CPU PVR in the list?
1481 * 2. What's the "best" listed logical PVR
1483 for (i = 0; i < 512; ++i) {
1484 uint32_t pvr, pvr_mask;
1486 pvr_mask = ldl_be_phys(&address_space_memory, *addr);
1487 pvr = ldl_be_phys(&address_space_memory, *addr + 4);
1490 if (~pvr_mask & pvr) {
1491 break; /* Terminator record */
1494 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) {
1495 explicit_match = true;
1497 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) {
1503 if ((best_compat == 0) && (!explicit_match || max_compat)) {
1504 /* We couldn't find a suitable compatibility mode, and either
1505 * the guest doesn't support "raw" mode for this CPU, or raw
1506 * mode is disabled because a maximum compat mode is set */
1507 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS");
1511 *raw_mode_supported = explicit_match;
1513 /* Parsing finished */
1514 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat);
1519 static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
1520 sPAPRMachineState *spapr,
1521 target_ulong opcode,
1524 /* Working address in data buffer */
1525 target_ulong addr = ppc64_phys_to_real(args[0]);
1526 target_ulong ov_table;
1528 sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates;
1530 Error *local_err = NULL;
1531 bool raw_mode_supported = false;
1533 cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err);
1535 error_report_err(local_err);
1540 if (cpu->compat_pvr != cas_pvr) {
1541 ppc_set_compat_all(cas_pvr, &local_err);
1543 /* We fail to set compat mode (likely because running with KVM PR),
1544 * but maybe we can fallback to raw mode if the guest supports it.
1546 if (!raw_mode_supported) {
1547 error_report_err(local_err);
1554 /* For the future use: here @ov_table points to the first option vector */
1557 ov1_guest = spapr_ovec_parse_vector(ov_table, 1);
1558 ov5_guest = spapr_ovec_parse_vector(ov_table, 5);
1559 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) {
1560 error_report("guest requested hash and radix MMU, which is invalid.");
1563 /* The radix/hash bit in byte 24 requires special handling: */
1564 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300);
1565 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300);
1568 * HPT resizing is a bit of a special case, because when enabled
1569 * we assume an HPT guest will support it until it says it
1570 * doesn't, instead of assuming it won't support it until it says
1571 * it does. Strictly speaking that approach could break for
1572 * guests which don't make a CAS call, but those are so old we
1573 * don't care about them. Without that assumption we'd have to
1574 * make at least a temporary allocation of an HPT sized for max
1575 * memory, which could be impossibly difficult under KVM HV if
1578 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) {
1579 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size);
1581 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) {
1583 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required");
1587 if (spapr->htab_shift < maxshift) {
1588 /* Guest doesn't know about HPT resizing, so we
1589 * pre-emptively resize for the maximum permitted RAM. At
1590 * the point this is called, nothing should have been
1591 * entered into the existing HPT */
1592 spapr_reallocate_hpt(spapr, maxshift, &error_fatal);
1593 push_sregs_to_kvm_pr(spapr);
1597 /* NOTE: there are actually a number of ov5 bits where input from the
1598 * guest is always zero, and the platform/QEMU enables them independently
1599 * of guest input. To model these properly we'd want some sort of mask,
1600 * but since they only currently apply to memory migration as defined
1601 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need
1602 * to worry about this for now.
1604 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas);
1606 /* also clear the radix/hash bit from the current ov5_cas bits to
1607 * be in sync with the newly ov5 bits. Else the radix bit will be
1608 * seen as being removed and this will generate a reset loop
1610 spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300);
1612 /* full range of negotiated ov5 capabilities */
1613 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest);
1614 spapr_ovec_cleanup(ov5_guest);
1615 /* capabilities that have been added since CAS-generated guest reset.
1616 * if capabilities have since been removed, generate another reset
1618 ov5_updates = spapr_ovec_new();
1619 spapr->cas_reboot = spapr_ovec_diff(ov5_updates,
1620 ov5_cas_old, spapr->ov5_cas);
1621 /* Now that processing is finished, set the radix/hash bit for the
1622 * guest if it requested a valid mode; otherwise terminate the boot. */
1624 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) {
1625 error_report("Guest requested unavailable MMU mode (radix).");
1628 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300);
1630 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()
1631 && !kvmppc_has_cap_mmu_hash_v3()) {
1632 error_report("Guest requested unavailable MMU mode (hash).");
1636 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest,
1638 if (!spapr->cas_reboot) {
1639 /* If spapr_machine_reset() did not set up a HPT but one is necessary
1640 * (because the guest isn't going to use radix) then set it up here. */
1641 if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) {
1642 /* legacy hash or new hash: */
1643 spapr_setup_hpt_and_vrma(spapr);
1646 (spapr_h_cas_compose_response(spapr, args[1], args[2],
1649 spapr_ovec_cleanup(ov5_updates);
1651 if (spapr->cas_reboot) {
1652 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
1658 static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu,
1659 sPAPRMachineState *spapr,
1660 target_ulong opcode,
1663 uint64_t characteristics = H_CPU_CHAR_HON_BRANCH_HINTS &
1664 ~H_CPU_CHAR_THR_RECONF_TRIG;
1665 uint64_t behaviour = H_CPU_BEHAV_FAVOUR_SECURITY;
1666 uint8_t safe_cache = spapr_get_cap(spapr, SPAPR_CAP_CFPC);
1667 uint8_t safe_bounds_check = spapr_get_cap(spapr, SPAPR_CAP_SBBC);
1668 uint8_t safe_indirect_branch = spapr_get_cap(spapr, SPAPR_CAP_IBS);
1670 switch (safe_cache) {
1671 case SPAPR_CAP_WORKAROUND:
1672 characteristics |= H_CPU_CHAR_L1D_FLUSH_ORI30;
1673 characteristics |= H_CPU_CHAR_L1D_FLUSH_TRIG2;
1674 characteristics |= H_CPU_CHAR_L1D_THREAD_PRIV;
1675 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
1677 case SPAPR_CAP_FIXED:
1679 default: /* broken */
1680 assert(safe_cache == SPAPR_CAP_BROKEN);
1681 behaviour |= H_CPU_BEHAV_L1D_FLUSH_PR;
1685 switch (safe_bounds_check) {
1686 case SPAPR_CAP_WORKAROUND:
1687 characteristics |= H_CPU_CHAR_SPEC_BAR_ORI31;
1688 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR;
1690 case SPAPR_CAP_FIXED:
1692 default: /* broken */
1693 assert(safe_bounds_check == SPAPR_CAP_BROKEN);
1694 behaviour |= H_CPU_BEHAV_BNDS_CHK_SPEC_BAR;
1698 switch (safe_indirect_branch) {
1699 case SPAPR_CAP_FIXED_CCD:
1700 characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS;
1702 case SPAPR_CAP_FIXED_IBS:
1703 characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED;
1705 default: /* broken */
1706 assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
1710 args[0] = characteristics;
1711 args[1] = behaviour;
1716 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
1717 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1];
1719 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
1721 spapr_hcall_fn *slot;
1723 if (opcode <= MAX_HCALL_OPCODE) {
1724 assert((opcode & 0x3) == 0);
1726 slot = &papr_hypercall_table[opcode / 4];
1728 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX));
1730 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1737 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
1740 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1742 if ((opcode <= MAX_HCALL_OPCODE)
1743 && ((opcode & 0x3) == 0)) {
1744 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
1747 return fn(cpu, spapr, opcode, args);
1749 } else if ((opcode >= KVMPPC_HCALL_BASE) &&
1750 (opcode <= KVMPPC_HCALL_MAX)) {
1751 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE];
1754 return fn(cpu, spapr, opcode, args);
1758 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n",
1763 static void hypercall_register_types(void)
1766 spapr_register_hypercall(H_ENTER, h_enter);
1767 spapr_register_hypercall(H_REMOVE, h_remove);
1768 spapr_register_hypercall(H_PROTECT, h_protect);
1769 spapr_register_hypercall(H_READ, h_read);
1772 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove);
1774 /* hcall-hpt-resize */
1775 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare);
1776 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit);
1779 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
1780 spapr_register_hypercall(H_CEDE, h_cede);
1781 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset);
1783 /* processor register resource access h-calls */
1784 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0);
1785 spapr_register_hypercall(H_SET_DABR, h_set_dabr);
1786 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr);
1787 spapr_register_hypercall(H_PAGE_INIT, h_page_init);
1788 spapr_register_hypercall(H_SET_MODE, h_set_mode);
1790 /* In Memory Table MMU h-calls */
1791 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb);
1792 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid);
1793 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table);
1795 /* hcall-get-cpu-characteristics */
1796 spapr_register_hypercall(H_GET_CPU_CHARACTERISTICS,
1797 h_get_cpu_characteristics);
1799 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
1800 * here between the "CI" and the "CACHE" variants, they will use whatever
1801 * mapping attributes qemu is using. When using KVM, the kernel will
1802 * enforce the attributes more strongly
1804 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load);
1805 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store);
1806 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load);
1807 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store);
1808 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi);
1809 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf);
1810 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop);
1812 /* qemu/KVM-PPC specific hcalls */
1813 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas);
1815 /* ibm,client-architecture-support support */
1816 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
1819 type_init(hypercall_register_types)